KR20200139800A - Process simulation model calibration using CD-SEM - Google Patents

Abstract

Computer-implemented methods are disclosed for optimizing a process simulation model that predicts a result of a semiconductor device manufacturing operation to process process parameter values that characterize a semiconductor device manufacturing operation. The methods include generating cost values using a computer predicted result of a semiconductor device manufacturing operation and, at least in part, a measurement result generated by performing a semiconductor device manufacturing operation in a reaction chamber operating under a set of fixed process parameter values. Entails. Determination of the parameters of the process simulation model may employ pre-process profiles, through optimization of the resulting post-process profiles of the parameters for profile measurement results. For example, cost values for optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide the optimization.

Description

Process simulation model calibration using CD-SEM

Quoted by reference

A PCT application form was filed concurrently with this specification as part of this application. Each of the applications claiming priority or interest as identified in the PCT application form to which this application was filed at the same time is incorporated by reference in its entirety for all purposes.

The performance of semiconductor device manufacturing operations, such as plasma-assisted etching processes, is often essential to the success of a semiconductor device processing workflow. However, optimization or tuning of etch processes and/or tools associated with them (e.g., etch reactors, lithographic masks, etc.) often involves etch process parameters or etch process parameters to create a target target feature profile It may turn out to be technically difficult and time consuming, involving the skilled person manually adjusting tool component designs. Currently, there is no automated procedure of sufficient accuracy that may depend to determine the values of the process parameters responsible for the desired etch profile.

Certain models simulate physical and/or chemical processes that occur on a semiconductor substrate during etching processes. Examples of such models are EPMs (etch profile models) implemented as behavioral models (e.g. SEMulator3D available from Coventor (owned by Lam Research) of Cary, NC) or as models of surface reactions. Includes; See, for example, models of M. Kushner and colleagues, as well as models of Cooperberg and colleagues. The former is described in Y. Zhang, "Low Temperature Plasma Etching Control through Ion Energy Angular Distribution and 3-Dimensional Profile Simulation" Chapter 3, dissertation, University of Michigan (2015), and the latter is described in Cooperberg, Vahedi, and Gottscho, "Semiempirical. profile simulation of aluminum etching in a Cl ₂ /BCl ₃ plasma" J. Vac. Sci. Technol. A 20(5), 1536 (2002), all of which are incorporated herein by reference in their entirety. An additional description of the etch profile models of M. Kushner and colleagues can be found in J. Vac. Sci. Technol. A 15(4), 1913 (1997), J. Vac. Sci. Technol. B 16(4), 2102 (1998), J. Vac. Sci. Technol. A 16(6), 3274 (1998), J. Vac. Sci. Technol. A 19(2), 524 (2001), J. Vac. Sci. Technol. A 22(4), 1242 (2004), J. Appl. Phys. 97, 023307 (2005), each of which is also incorporated herein by reference in its entirety. Additional descriptions of Coventor's etch profile models can be found in U.S. Patent No. 9,015,016 to Lorenz et al. filed on November 25, 2008, and U.S. Patent No. 9,659,126 to Greiner et al. filed January 26, 2015, respectively. Is also incorporated herein by reference in its entirety. These disclosed models may benefit from further development to reach the degree of accuracy and reliability desired in the semiconductor processing industry.

Background and contextual descriptions contained herein are for the sole purpose of presenting the context of the present disclosure generally. Much of this disclosure presents the achievements of the inventors, and is not meant to be admitted to be prior art merely because such achievements are described in the background section or presented in context elsewhere in this specification.

One aspect of the present disclosure provides a computer-implemented method for optimizing a process simulation model that predicts a result of a semiconductor device manufacturing operation from process parameter values characterizing a semiconductor device manufacturing operation. The method includes the following steps: (a) receiving current values of one or more plotted process model parameters to be optimized; (b) generating a process simulation model constructed by providing the process simulation model with current values of one or more plotted process model parameters; (c) using the constructed process simulation model, generating a computationally predicted result of the semiconductor device manufacturing operation; (d) comparing, at least in part, measurement results obtained from one or more substrate features generated by performing a semiconductor device manufacturing operation with a computer predicted result, wherein the comparison comprises a semiconductor device manufacturing operation and a computer predicted result. Comparing, generating one or more cost values based on the difference between the measurement results; (e) using one or more cost values and/or a convergence check to generate an update of current values of the one or more plotted process model parameters; (f) performing step (b) using an update of current values of one or more plotted process model parameters; And (g) repeating steps (c) to (f) until current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters that minimize cost values. It can also be characterized.

In certain embodiments, the process simulation model additionally consists of a set of fixed process model parameter values of step (b), and the measurement result is a semiconductor device fabrication in a reaction chamber operating under a fixed set of process parameter values. It is obtained from one or more substrate features created by performing the operation. In certain embodiments, the set of fixed process model parameter value(s) or one or more of the floating process model parameters is one or more temperature values of the reaction chamber, one or more RF conditions of the reaction chamber, one or more process gases of the reaction chamber. S, the pressure of the reaction chamber, or a combination thereof.

In certain embodiments, the semiconductor device manufacturing operation is a subtractive process or a material addition process. In certain embodiments, the semiconductor device manufacturing operation is an etching process, a planarization process, or a deposition process.

In certain embodiments, the one or more plotted process model parameters include a characteristic of a substrate undergoing a semiconductor device manufacturing operation, the characteristic being a reaction rate constant, a reactant and/or product adhesion coefficient, a reactant diffusion constant, Product diffusion constant, and/or optical dispersion properties. In certain embodiments, one or more of the plotted process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, ion incident tilt angle, ion incident twist angle, visibility into feature, angular dispersion, sputtering. The sputter maximum yield angle, and/or the etch rate per crystal direction. In certain embodiments, the one or more plotted process model parameters include a combination of any two or more features of a substrate undergoing a semiconductor device manufacturing operation.

In certain embodiments, generating the process simulation model constructed in (b) additionally comprises providing a process simulation model profile of the substrate before the substrate undergoes a semiconductor device manufacturing operation, wherein the profile of the substrate is semiconductor. It has one or more features to be modified by the device manufacturing operation.

In certain embodiments, the method further comprises, prior to step (c), providing an initial profile of the substrate undergoing the semiconductor device manufacturing operation, the computer predicted result of the semiconductor device manufacturing operation in step (c). The step of creating a uses the initial profile In certain embodiments, the initial profile is computer-generated using information about manufacturing steps that occur prior to a semiconductor device manufacturing operation. In certain embodiments, the initial profile is determined by performing metrology on one or more initial substrate features generated from a manufacturing step that occurs prior to a semiconductor device manufacturing operation.

In certain embodiments, the result of a semiconductor device fabrication operation is a signal generated by the interaction of an etched feature, a deposited feature, or a planarized feature with incident electromagnetic radiation. In certain embodiments, generating a computer-predicted result of a semiconductor device manufacturing operation includes the following steps: (i) Compute etching represented by a series of geometric profile coordinates, using a constructed process simulation model. Creating a profile; And (ii) from the calculated etching profile generated in step (i), generating a calculated reflectance or elliptic spectrum by simulating reflection of the electromagnetic radiation from the calculated etching profile. In some cases, the method additionally includes, prior to step (ii), conditioning the calculated etch profile to smooth out some statistical profile variations in the profile. In certain embodiments, generating the calculated reflectance or elliptic spectrum involves performing a “RCWA” (Rigorous Coupled Wave Analysis) simulation using the calculated etch profile. In certain embodiments, generating the calculated reflectance or elliptic spectrum involves performing a “Finite Difference Time-Domain” (FDTD) simulation using the calculated etch profile. In certain embodiments, the method further includes performing a semiconductor device fabrication operation on a test substrate under a set of process parameter values to produce an additionally etched substrate; And exposing the etched substrate to incident electromagnetic radiation to produce an empirical reflection spectrum containing the measurement results. In certain embodiments, the method further includes generating one or more additional calculated reflectance or elliptical spectra. In certain embodiments, the method additionally comprises reflectometry, dome scatterometry, and angle on a substrate comprising features created by performing a semiconductor device fabrication operation in a reaction chamber operating under a set of process parameter values. -Generating measurement results by performing angle-resolved scatterometry, small-angle X-ray scatterometry and/or ellipsometry.

In certain embodiments, the result of a semiconductor device fabrication operation is a profile of an etched feature, a profile of a deposited feature, and/or a profile of a planarized feature. In certain embodiments, generating the computer-predicted result of the semiconductor device manufacturing operation includes using the constructed process simulation model to generate a calculated etch profile represented by etch profile coordinates. In such embodiments, the method further includes performing a semiconductor device fabrication operation on a test substrate under a set of process parameter values to produce an etched substrate; And measuring the features of the etched substrate to produce experimental etch profile coordinates including the metrology result. In certain embodiments, measuring the features of the etched substrate includes performing microscopy, or optical metrology, of the etched substrate. In some cases, performing microscopy entails performing transmission electron microscopy (TEM) and/or scanning electron microscopy (SEM).

In certain embodiments, the result of the semiconductor device fabrication operation is a set of geometrical profile parameters that characterize the geometry of an etched feature, or a deposited feature, or a planarized feature. Geometric profile parameters are “OCD” (Optical CD) profile parameters. In certain embodiments, generating a computer-predicted result of a semiconductor device manufacturing operation includes: (i) using the constructed process simulation model to generate a calculated etch profile represented by a series of etch profile coordinates; And (ii) converting the calculated etch profile generated in step (i) into a first set of geometric profile parameters that characterize the geometry of the calculated etch profile. In such embodiments, the method further includes performing a semiconductor device fabrication operation on a test substrate under a set of process parameter values to produce an etched substrate; Measuring features of the etched substrate to produce empirical etch profile coordinates including metrology results; And converting the experimental etch profile coordinates to a second set of geometrical profile parameters that characterize the geometry of the etched feature of the etched substrate. In other such embodiments, the one or more cost values may be based on a difference between a computer predicted result using the first set of geometric profile parameters and a metrology result using the second set of geometric profile parameters.

In certain embodiments, the computer-predicted result generated in step (c) is calculated from the constructed process simulation model and the geometric profile of the substrate feature corresponding to a sequence of times representing different durations of the substrate subtraction process or substrate addition process. Or a sequence of profile parameters. In certain embodiments, the measurement result of step (d) comprises a sequence of profile parameters or geometric profiles of the substrate feature obtained from experimental measurements of the substrate at different durations of the substrate subtraction process or the substrate addition process. .

In certain embodiments, the method further comprises: (i) constructing a process simulation model from final values of one or more plotted process model parameters from step (g); And (ii) determining a mask pattern of the lithographic and using the process simulation model consisting of the final values of the one or more plotted process model parameters from step (g) to enable generation of the lithographic mask. . In some cases, creating the lithographic mask includes transferring the pattern of the resist layer. In some such cases, the method additionally includes developing the resist layer and transferring the pattern to the underlying chromium layer.

In certain embodiments, the method further comprises: (i) constructing a process simulation model from final values of one or more plotted process model parameters from step (g); (ii) a process simulation model consisting of the final values of one or more plotted process model parameters from step (g) to identify the design of the semiconductor processing device and enable manufacturing of the semiconductor processing device by using the design of the semiconductor processing device. And using.

In certain embodiments, the method further comprises: (i) constructing a process simulation model from final values of one or more plotted process model parameters from step (g); (ii) a process consisting of the final values of one or more plotted process model parameters from step (g) to identify the operating conditions of the semiconductor processing apparatus and enable fabrication of semiconductor devices by operating the semiconductor processing apparatus under these operating conditions. And using the simulation model.

In some embodiments, repeating steps (c) through (f) includes identifying a substantially local or global minimum in the obtained one or more cost values. In certain embodiments, the method additionally includes obtaining a measurement result by performing an in -situ metrology in the reaction chamber, a non-destructive standalone metrology outside the reaction chamber, and/or a standalone destructive metrology outside the reaction chamber.

In some embodiments, generating a computationally predicted result comprises using a process simulation model configured to calculate local reaction rates in a grid of points representing a feature profile on a semiconductor substrate. Include. In some such embodiments, using the configured process simulation model to calculate local reaction rates calculates the reaction rates as a function of time.

Yet another aspect of the present disclosure is a non-transitory computer-readable, provided with instructions that cause a calculation system to execute an optimized process simulation model that calculates a result of a semiconductor device manufacturing operation from process parameter values characterizing the semiconductor device manufacturing operation It relates to a computer program product comprising a medium. The instructions (a) receive process parameter values as inputs to the optimized process simulation model; (b) run the optimized process simulation model using the process parameter values; And (c) instructions for outputting the calculated result of the semiconductor device manufacturing operation. In certain embodiments, the optimized process simulation model is optimized by one of the described methods. As an example, a process simulation model may include: (i) receiving current values of one or more plotted process model parameters to be optimized; (ii) generating a process simulation model constructed by providing the process simulation model with current values of one or more plotted process model parameters and set value(s) of fixed process model parameter values; (iii) using the constructed process simulation model, generating a computer-predicted result of the semiconductor device manufacturing operation; (iv) at least in part, measurement results obtained from one or more substrate features generated by performing a semiconductor device manufacturing operation in a reaction chamber operating under a set of fixed process parameter values and a computer-predicted result of the semiconductor device manufacturing operation. Comparing, wherein the comparing generates one or more cost values based on a semiconductor device manufacturing operation and a difference between a computer predicted result and a measurement result; (v) using one or more cost values and/or a convergence check to generate an update of the current values of the one or more plotted process model parameters; (vi) performing step (ii) using an update of current values of one or more plotted process model parameters; And (vii) optimization by repeating steps (iii) through (vi) until the current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters that minimize cost values. It could be.

The process simulation model associated with the computer program product may be optimized by any of the described operations of the method for optimizing the process simulation model aspect of the present disclosure. In certain embodiments, the instructions further include, prior to operation (ii), receiving an initial profile of the substrate undergoing a semiconductor device manufacturing operation.

In certain embodiments, one or more of the plotted process model parameters are vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, ion incident tilt angle, ion incident twist angle, visibility into feature, angular dispersion, sputtering. The maximum calculated angle, and/or the etch rate per crystal direction. In certain embodiments, generating the process simulation model constructed in (ii) further comprises providing a process simulation model profile of the substrate before the substrate undergoes a semiconductor device manufacturing operation, the profile of the substrate being semiconductor device manufacturing. It has one or more features to be modified by the operation.

In certain embodiments, the result of a semiconductor device fabrication operation is a signal generated by the interaction of an etched feature, a deposited feature, or a planarized feature with incident electromagnetic radiation. In certain embodiments, generating a computer-predicted result of a semiconductor device manufacturing operation includes: using the constructed process simulation model, generating a calculated etch profile represented by a series of geometric profile coordinates; And from the calculated etching profile, generating a calculated reflectance or elliptic spectrum by simulating reflection of the electromagnetic radiation from the calculated etching profile. In certain embodiments, the optimized process simulation model may further include performing a semiconductor device manufacturing operation on a test substrate under a set of process parameter values to produce an etched substrate; And exposing the etched substrate to incident electromagnetic radiation to produce an empirical reflection spectrum including the measurement results.

In certain embodiments, the optimized process simulation model may additionally be applied to reflectometry, dome scatterometry on a substrate containing features created by performing a semiconductor device fabrication operation in a reaction chamber operating under a set of process parameter values. scatterometry), angle-resolved scatterometry, small-angle X-ray scatterometry, and/or ellipsometry to generate measurement results. Is optimized. In certain embodiments, generating a computer-predicted result of a semiconductor device manufacturing operation includes using the constructed process simulation model to generate a calculated etch profile represented by etch profile coordinates. In some such embodiments, the optimized process simulation model may additionally include performing a semiconductor device fabrication operation on a test substrate under a set of process parameter values to produce an etched substrate; And measuring the features of the etched substrate to generate experimental etch profile coordinates including the metrology result.

In certain embodiments, the result of the semiconductor device fabrication operation is a set of geometrical profile parameters that characterize the geometry of an etched feature, or a deposited feature, or a planarized feature. In some such embodiments, the geometrical profile parameters are “OCD” (Optical CD) profile parameters. In certain embodiments, generating a computer-predicted result of a semiconductor device manufacturing operation includes: generating, using the constructed process simulation model, a calculated etch profile represented by a series of etch profile coordinates; And converting the calculated etch profile into a first set of geometrical profile parameters that characterize the geometry of the calculated etch profile. In some such embodiments, the optimized process simulation model may additionally include performing a semiconductor device fabrication operation on a test substrate under a set of process parameter values to produce an etched substrate; Measuring features of the etched substrate to produce empirical etch profile coordinates including metrology results; And transforming the experimental etch profile coordinates into a second set of geometric profile parameters that characterize the geometry of the etched feature of the etched substrate.

In certain embodiments, the instructions additionally include instructions for using the calculated result to determine the pattern of the lithographic mask. In certain embodiments, the instructions additionally include instructions for using the calculated result to identify the design of the semiconductor processing apparatus. In certain embodiments, the instructions additionally include instructions for using the calculated result to identify operating conditions of the semiconductor processing apparatus to enable fabrication of semiconductor devices by operating the semiconductor processing apparatus under operating conditions. .

Another aspect of the present disclosure relates to a system comprising a computer program product as described and an apparatus for generating a lithographic mask configured to determine a lithographic mask pattern using calculated results of a semiconductor device manufacturing operation. The process simulation model associated with this system may be optimized by any of the described operations of the method of optimizing the process simulation model aspect of the present disclosure.

Another aspect of the present disclosure relates to a system comprising a computer program product as described and a semiconductor processing apparatus configured to operate under process conditions provided in a calculated result of a semiconductor device manufacturing operation. The process simulation model associated with this system may be optimized by any of the described operations of the method of optimizing the process simulation model aspect of the present disclosure.

Another aspect of the present disclosure relates to methods of using a process simulation model to predict the outcome of a semiconductor device manufacturing operation (e.g., material etching, planarization, or deposition) and using the result to improve the operation of a semiconductor device manufacturing operation. About. Such uses include, for example, creating improved mask layouts (which may be implemented in masks), designing improved reactors to perform semiconductor device manufacturing operations, and/or for semiconductor device manufacturing operations. Includes defining the process window. The process simulation model used in this aspect of the present disclosure may be optimized by any of the operations described in the method for optimizing the process simulation model aspect of the present disclosure.

These and other features will be described below with reference to the associated drawings.

Exemplary embodiments will now be described in conjunction with the drawings.
1 shows an example of an etch profile predicted by a computer from an etch profile model of an etch process.
Figure 2 is similar to that shown in Figure 1, but in this figure, shows an example of an etch profile calculated from experimental measurements made with one or more metrology tools.
3 shows a schematic diagram of a process for optimizing a process simulation model according to certain embodiments.
4 shows an embodiment of an optimization system that employs a comparison of simulated and measured reflectance or elliptic values.
5 shows an example of an optimization system that employs a comparison of simulated and measured feature profile values.
6 shows an example of an optimization system that employs a set of “profile parameters” to represent the geometry of a feature profile using, for example, potentially fewer data points or sets thereof.
7 shows an example calculation system that may be used to optimize and/or use process simulation models.
8 shows an exemplary optimization system/flow employing a top down metrology tool such as a CD-SEM.

Introduction

Etch Profile Models (EPMS) referenced above (and/or other similar) so that process simulation models may be used to generate representations of semiconductor feature profiles, resulting from semiconductor device manufacturing operations with a level of accuracy acceptable to the semiconductor processing industry. Models) are disclosed herein for improving the utilization of process simulation models. In general, the disclosed methods improve the predictive capabilities of process simulation models.

Process simulation models can be used to calculate the "evolution" of the substrate surface profile, e.g., the reaction rates or other process parameters associated with the etching process at each of the many spatial locations, thereby allowing time at various spatial locations on the surface of the feature. It may simulate sequential changes to the etch profile of the measured feature or time-dependent changes in the shape of the feature. Variations in reaction rates may arise from the flux of the etchant, characteristics of the selected deposition material, plasma conditions of the reaction chamber, or any number of other factors. In addition, the calculated reaction rates may fluctuate during the simulated etching process. All process simulation models do not simulate progress during semiconductor device manufacturing operations; Some simply predict the final profile (including the duration of the motion) and the initial feature profile, predetermined reaction conditions.

In some embodiments, the output of the simulated etch profile may be represented as a discrete set of data points that spatially define and/or otherwise map the shape of the profile, i.e., profile coordinates, as shown in FIG. have. Further, the simulated profile as shown in FIG. 1 may correspond to an actual measured etch profile as shown in FIG. 2. The evolution of the simulated etch profile that differs in time depends on the modeled, spatially-resolved local etch rates, and in turn depends on the underlying chemistry and physics of the etch process.

Thus, for example, when performed by the EPM, the profile simulation can include, but is not limited to, various physical and/or chemical parameters associated with the chemical reaction mechanisms underlying the device manufacturing processes, and also (but not limited to): temperature, It may be dependent on physical and/or chemical parameters, which may characterize the chamber atmosphere such as pressure, plasma power, reactant flow rate, and the like. These parameters are typically under the control of the process engineer.

Process simulation models that rely on the representation of surface reactions may employ a core set or "fundamental" chemical and/or physical input parameters, examples (but not otherwise limited): reaction probabilities, adhesion coefficient Ions, ionic and neutron fluxes, and the like. The parameters may or may not be controllable independently of each other. Further, in certain process situations and/or configurations, the process engineer managing the manufacturing process may nonetheless be unaware of one or more of the parameters, necessary to run the process simulation model. These parameters may be assumed to have specific values that may be taken from the literature, and their use may include specific simplifications (and/or outlines) of the underlying physical and chemical mechanisms behind the process to be modeled.

The disclosed methods and/or processes combine experimental techniques and data analysis methodologies to improve the practical industrial applicability of process simulation models for semiconductor device manufacturing operations that modify substrates.

In certain embodiments, the techniques disclosed herein optimize the chemical, physical, and/or behavioral input parameter values used by these models, sometimes referred to as “floated” process model parameter values. , Improves the prediction accuracy of models by determining more effective sets of values for the parameters. Optimizing parameters, an environment in which the optimal values determined for the basic parameters may be different from what the literature (or other experiments) determine as "true" or ideal, physical/chemical values for these parameters. They also improve the accuracy of the process simulation models used. The parameters to be optimized need not directly correspond to the specific chemical or physical properties or mechanisms of the etching process. In some cases, they simply represent parameters that allow the model to accurately predict etch results for a predetermined set of inputs such as reactor conditions.

Process simulation models may take into account physical properties and/or measurable values within the process equipment, as well as substrate and/or semiconductor wafer properties at the nanometer level. However, not all wafer properties may be conveniently measured directly, i.e., cutting and/or excluding substrate samples to be observed and/or scanned through a microscope, such as often scanning electron microscopy (SEM) and other metrology techniques. Requires setting.

Definitions

The following terms may be used intermittently throughout the instant specification:

In this specification, the terms “semiconductor wafer”, “wafer”, “substrate”, “wafer substrate”, and “partially fabricated integrated circuit” may be used interchangeably. One of skill in the art understands that the term “partially fabricated integrated circuit” may refer to a semiconductor wafer during any of the many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. This detailed description assumes that the embodiments are implemented on a wafer. However, the present disclosure is not so limited. The workpiece may be of various shapes, sizes, and materials. Besides semiconductor wafers, other workpieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micro-mechanical devices, etc. Include.

As used herein, a "feature" is a non-planar structure on a substrate surface, typically a surface to be modified in a semiconductor device manufacturing operation. Examples of features include trenches, vias, pads, pillars, domes, and the like. Features may be created by photoresist development, mask definition, lithographic etching, lithographic deposition, epitaxial growth, damascene deposition, and the like. Features typically have an aspect ratio (depth or height to width). Examples of feature aspect ratios include aspect ratios of at least about 1:0.5, at least about 1:1, at least about 2:1, at least about 5:1, at least about 10:1, or greater. In certain embodiments, the feature has a width dimension (which may be a critical dimension (CD)) of about 10 nm to 500 nm, such as about 25 nm to about 300 nm. The feature profile may include an overhang in the feature opening and/or may gradually narrow. The re-entrant profile is one that narrows from the inside or the bottom of the feature to the feature opening.

The "initial profile" as used herein is the profile of the geometry of the substrate surface to be processed by a semiconductor device manufacturing operation. The initial profile has one or more features (or may be completely planar) and serves as a starting or input profile for a semiconductor device manufacturing operation that will later modify the initial profile. The initial profile may be computer generated using information about the manufacturing steps preceding the semiconductor device manufacturing operation. Alternatively, the initial profile is created by performing metrology on the substrate surface created from the manufacturing step preceding the semiconductor device manufacturing operation. During a semiconductor device manufacturing operation, the actual or simulated substrate surface is modified from the original profile to the final profile.

As used herein, a "semiconductor device manufacturing operation" is a unit operation performed during manufacturing of semiconductor devices. Typically, the overall manufacturing process includes a plurality of semiconductor device manufacturing operations, each performed in a unique semiconductor manufacturing tool such as a plasma reactor, electroplating cell, chemical mechanical planarization tool, wet etch tool, and the like. Categories of semiconductor device manufacturing operations include subtraction processes, such as etching processes and planarization processes, and material addition processes, such as deposition processes. In the context of etching processes, a substrate etching process includes processes that etch a mask layer, more generally processes that etch any layer of material previously deposited and/or otherwise present on the substrate surface. This etching process may etch the stack of layers of the substrate.

As used herein, "the result of a semiconductor device manufacturing operation" is a characteristic of a substrate undergoing a semiconductor manufacturing operation. An example of this result is the geometric profile of the substrate after the semiconductor manufacturing operation. A profile is a group of features or a set of points in space that represent locations of features. As examples, the profile may be a profile of an etched feature, a profile of a deposited feature, a profile of a planarized feature, and the like. In another example, the result of a semiconductor manufacturing operation is a signal generated by the interaction of incident electromagnetic radiation with one or more substrate features, such as etched features, deposited features, or planarized features. In such examples, the result may be a reflectance signal, for example, that may include the reflectance magnitude as a function of wavelength and/or polarization state. The result may also be an elliptic signal. In another example, the result of a semiconductor fabrication operation is a set of profile parameters, such as "OCD" (Optical CD) profile parameters that characterize the geometry of the feature, such as an etched feature, a deposited feature, or a planarized feature. to be. These profile parameters may characterize overall features of the feature, such as the average CD of the feature, sidewall angles of the feature, depth of the feature, and the like.

The result of the semiconductor manufacturing operation may be obtained over a plurality of time points or at one time point during the semiconductor manufacturing operation. If the result is provided only at one point in time, it may be the point at which the semiconductor manufacturing operation is completed.

As used herein, the "computer predicted result of semiconductor device manufacturing operation" is a calculated model for the device manufacturing operation under consideration, for example, a predicted result of a computer-generated semiconductor device manufacturing operation, such as a process simulation model. . In certain embodiments, the calculation process calculates a predicted feature profile represented by geometric profile coordinates. In other cases, the calculation process calculates a predicted optical response produced by electromagnetic radiation interacting with the predicted feature profile. In still other cases, the calculation process calculates the predicted geometrical profile parameters of the feature profile produced by the semiconductor device manufacturing operation (e.g., a set of OCD profile parameters that characterize the geometry of the calculated etch profile). do. In some embodiments, feature profiles, optical responses, and/or profile parameters are calculated as a function of time (a semiconductor device manufacturing operation occurs). In certain embodiments, to predict the outcome of a semiconductor device manufacturing operation, the calculation process predicts local reaction rates in a grid of points representing a feature profile on a semiconductor substrate. This generates a substrate/feature profile that is derived from the initial profile used at the beginning of the calculation.

Once the calculation process calculates the predicted optical response, it is also possible to calculate the reflection spectrum or elliptic response by simulating the reflection of electromagnetic radiation from the calculated etching profile. The reflection spectrum or elliptic response may be generated using, for example, a “RCWA” (Rigorous Coupled Wave Analysis) simulation or a “FDTD” (Finite Difference Time-Domai) simulation.

In certain embodiments, the calculation process generates geometric profiles of a substrate feature or a time sequence of profile parameters. In certain embodiments, the calculation process produces a time sequence of elliptic response or a calculated reflection spectrum generated by simulating reflection of electromagnetic radiation from a calculated substrate feature profile at different times. The time sequence may be created at different durations of a semiconductor device manufacturing operation. Computer-predicted results of a semiconductor device manufacturing operation may be provided for substrate subtraction processes and/or substrate addition processes.

The term “profile conditioning” as used herein refers to the smoothing of the calculated etch profile to smooth out some statistical profile variations. Profile conditioning may be applied to the computer predicted results of the semiconductor device manufacturing operation before another computational process, such as simulating the reflection of electromagnetic radiation from the computed etch profile.

"Measurement result" as used herein refers to a result produced, at least in part, by measuring features of a processed substrate. Measurements may be made during or after performing a semiconductor device manufacturing operation in a reaction chamber operating under a fixed set of process parameter values. In certain embodiments, measuring the features of the processed substrate creates profile coordinates. In these embodiments, measuring the features of the processed substrate may be performed using microscopy (e.g., CD-SEM, SEM, TEM, STEM, REM, AFM), or optical metrology on the etched substrate. It includes performing steps. When using optical metrology, the system may obtain profile coordinates by calculating them from the measured optical metrology signals. In certain embodiments, the metrology result is by converting the measured feature profile coordinates to a set of geometric profile parameters (e.g., CD, sidewall angles, depth, etc.) that characterize the geometry of the feature of the processed substrate. Is created. In certain embodiments, measurement results are generated by performing reflectometry, dome scattering, angle-resolved scattering, small-angle X-ray scattering, and/or elliptical polarization on the processed substrate. In certain embodiments, the measurement result is endpoint detection for a particular process. Endpoint detection, which may be determined in situ , may be measured by various optical techniques.

In certain embodiments, the measurement result is provided as a temporal sequence of measured geometrical profiles, reflectance or elliptic data, or as profile parameters of a substrate feature. These measured metrology results are produced at different durations of the semiconductor device manufacturing operation.

As used herein, the "process simulation model" is a calculation model that predicts the result of a semiconductor device manufacturing operation. In other words, it prints the result. As described, examples of results include feature profiles (e.g., detailed Cartesian coordinates of the feature), profile parameters characterizing the feature (e.g., CD, sidewall angles, depth, etc.), and /Or if optical metrology is used to probe the features, include the generated reflectance/ellipse data. Results are based on features created or modified during a simulated semiconductor device manufacturing operation. Results may be predicted more than once during a semiconductor device manufacturing operation.

Inputs to the process simulation model include one or more process parameter values that characterize the semiconductor device manufacturing operation. Process parameters used as inputs are often temperature (pedestal, showerhead, etc.), plasma conditions (density, potential, power, etc.), process gas conditions (composition, e.g. partial pressures of components, flow rate, pressure, etc.) ), and the like. Typically, the process simulation model also receives an initial profile substrate, representing the profile of the substrate surface immediately before being processed through the modeled semiconductor device manufacturing operation. In the simple case, the initial profile is simply a planar surface. More typically, the initial profile has features such as mask or photoresist features.

Sometimes, the process simulation model simulates a subtraction process such as a substrate etching process or a planarization process. In various embodiments, the process simulation model is an etch profile model as described herein. Sometimes, process simulation models simulate additional processes such as substrate deposition processes (eg, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.).

"Constructed process simulation model" as used herein describes a process simulation model composed of one or the plotted process model parameters. When so configured, and after receiving the input process parameters and the substrate initial profile, the process simulation model can be executed to predict the outcome of the semiconductor device manufacturing operation.

As used herein, a “process parameter” is a parameter that characterizes a process occurring within a reaction chamber during a semiconductor device manufacturing operation, often on a substrate surface to be modified by operation. Typically, many of these process parameters are needed to uniquely characterize the process. Some process parameters characterize aspects of the process that are relatively easy to control and/or measure. Examples of such process parameters include temperature (pedestal, showerhead, etc.), plasma conditions (plasma density, plasma potential, applied power, etc.), process gas conditions (composition, e.g. partial pressures of components, flow rate, etc.) Pressure, etc.), and adjustable chamber geometry parameters such as separation between the pedestal and the showerhead. Other process parameters characterize aspects of the process that are not directly controllable and/or are not easily measured. Examples of these process parameters include local conditions such as plasma density, direction, or energy at a location on the substrate surface, and reaction rate constant, reactant and/or product adhesion coefficient, reactant diffusion constant, product diffusion constant, optical dispersion. Mechanical properties such as properties, and combinations thereof. The values of the process parameters are used as inputs or constructs of the process simulation model. This value may be a scalar, vector, matrix, tensor, etc.

The "fixed process model parameter" as used herein is a process parameter required by the process simulation model, but this value is fixed during the optimization process used to improve the performance of the process simulation model. In other words, the value of the fixed process model parameter does not change during the optimization process. This is distinct from the plotted process model parameters whose values change during the optimization activity. In some embodiments, the fixed process model parameter is directly controllable and/or easy to measure. Examples include temperature in the reaction chamber, one or more applied radio frequency (RF) or plasma conditions in the reaction chamber, one or more process gas conditions in the reaction chamber, pressure in the reaction chamber, or any combination thereof. However, the fixed process model parameters may alternatively be local or mechanical parameters. Sometimes, for the convenience of the model optimization process described herein, the value of a fixed process model parameter or group of such values is indicated by the symbol μ.

As used herein, the "floated process model parameter" is a process parameter required by the process simulation model, but this value floats (changes, adjusts, etc.) during the optimization process. Iterative modification of the process model parameter values plotted from the initial or seed value to the final value is the objective of the model optimization process. If the optimization routine is successful, the process simulation model consisting of the final values of the plotted process model parameters provides better prediction capability than the process simulation model consisting of the initial values of the plotted process model parameters. Sometimes for the convenience of the model optimization process described herein, the value of a fixed process model parameter or group of such values is denoted by the symbol α.

In certain embodiments, the plotted process model parameters represent a characteristic of a substrate undergoing a semiconductor device fabrication operation. Typical examples include the difficulty of measuring the mechanical properties of local conditions and/or reactions in the reactor during semiconductor device manufacturing operation. In some examples, the characteristic is a reaction rate constant, reactant and/or product adhesion coefficient, reactant diffusion constant, product diffusion constant, local plasma properties (e.g., ion flux at the substrate surface, ion direction, radical flux, Etc.), optical dispersion properties, or any combination thereof. However, the plotted process model parameters are not limited to these parameters. Parameters, which may be more commonly used as fixed process model parameters, may also be used as or as part of the plotted process model parameter(s). Examples of such non-mechanical parameters include temperature in the reaction chamber, one or more RF conditions in the reaction chamber, one or more process gases in the reaction chamber, pressure in the reaction chamber, applied plasma conditions, or any combination thereof. . In some embodiments, the plotted process model parameters include parameters that are more globally focused for a predetermined process, indicated by the process simulation model. Examples of these plotted process model parameters are all plasma angular dependence of vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, vertical deposition rate, sputtering yield for a predetermined material undergoing a predetermined semiconductor device manufacturing operation. , And the plasma energy dependence of the sputtering yield. Other examples of the plotted process model parameters are, again, for a predetermined material that all undergoes a predetermined semiconductor device fabrication operation, for an ion incident tilt angle, an ion incident twist angle, for etching and/or deposition (e.g., into a feature). Visibility, angular dispersion (sometimes called source sigma), adhesion coefficient (sometimes called isotropic ratio), sputtering maximum calculated angle, sputtering ratio, and etching ratio per crystal direction.

In various embodiments, the plotted process model parameter combines any two or more process model parameters that characterize a substrate undergoing a semiconductor device manufacturing operation. This combination may be a product or sum of individual values of the parameters, which may be weighted based on the relative importance of the individual parameters to the predictive ability of the model or based on other factors. Sometimes, some or all values of the individual parameters are normalized prior to combination. In some embodiments, individual values are provided as separate causes in the form of a vector. In one example, the combination of parameters may be an ion density and a rate of reaction with materials on the surface. Without taking into account any other factors, the probability of removal will be proportional to the product of the ion density, reaction rate, substrate material density, and surface area of the original profile. As a result, the ion density and reaction rate cannot be uniquely determined and there may be a product of them. In some cases, the plotted process model parameter does not have a known connection to the physical and/or chemical processes of the device manufacturing operation. These plotted process model parameters may be appropriate when optimizing behavioral process simulation models.

During the iterative optimization process, at any iteration, the value of the plotted process model parameter is considered the "current value" of the plotted process model parameter. The value of the parameter during the previous iteration may be a previous value of a so-called floating process model parameter, and the value of the parameter during successive iterations may be a continuous value of the so-called floating process model parameter. Modification of the value of a process model parameter plotted from one iteration to the next is sometimes a so-called update of the current value of the process model parameter plotted. At the end of the iterative optimization process, the value of the plotted process model parameter is the final value of the so-called plotted process model parameter.

As used herein, "optimizing" a process simulation model is to improve the ability of the process simulation model to predict the outcome of the semiconductor device manufacturing operation for which the model is designed to simulate. In the discussion herein, an optimization routine often optimizes a process simulation model by iteratively adjusting the current value of one or more plotted process model parameters. During optimization, the computer-predicted result of the process simulation model, using the current value(s) of the plotted process model parameter(s), is the same as the experimentally determined result (e.g., measurement result) and the same semiconductor device manufacturing operation It may be compared with both the experimentally determined results and the predicted results to be generated for. This comparison provides a cost value that reflects the magnitude of the difference (or match) between the predicted/simulated results and the experimentally determined results. The optimization routine at least (i) determines whether the value(s) of the plotted process model parameter value(s) converge, and (ii) if the value(s) do not converge, the plotted process model for the next iteration. The cost value is used to determine how to adjust the current value(s) of the parameter(s). In certain embodiments, the process uses the cost value of the current iteration as well as previous cost values of some or all of the historical iterations to search for global optimization.

As used herein, "comparing" a computer-predicted result of a process simulation model with an experimentally determined result (e.g., a measurement result) means comparing the indices of one or more features or two results. . This comparison gives the cost value or values of the optimization process. Examples of differences (cost values) include the L1 and L2 standards of the multidimensional result space, Euclidean distance, and Mahalanobis distance. As an example of using results with multiple features or indices, this comparison may be made by extracting multiple indices to describe the differences. By way of example, these indices may include critical dimension (CD) differences of a plurality of heights of a feature, process endpoint differences (e.g., differences in endpoints of an etching process), thickness differences for a predetermined material, or full spectrum of It could be cars. These indices constitute a cost function for optimization, which may also be weighting factors and combinations of these for each. The cost function is sometimes referred to herein as a simple mathematical operation-"difference", which is interpreted broader than B.

As used herein, the plotted process model parameter values "converge" when a process simulation model composed of them performs appropriately for a close application. Various convergence criteria may be known and applied in the art. Some of these are described below. In general, cost values are evaluated at each iteration of the optimization routine. The cost value generated during a single iteration may be evaluated independently or together with cost values from other iterations. This evaluation causes the optimization routine to perform a convergence check. Once the cost value or cost values representing the current value of the plotted process model parameter provide a process simulation model that performs acceptable and/or no longer significantly improves, the optimization routine terminates the process and The current value is considered the final value. The optimization routine converges. Thus, in certain embodiments, the convergence method determines when the error of parameter estimation (cost function) can no longer be improved. This allows a Bayesian view of the termination problem. The convergence check may search for a local or global minimum (or maximum depending on the structure of the cost value). The end of optimization may employ, for example, statistical gradient descent, batch gradient descent, Bayesian optimization, and the like.

Optimization process

3 shows a schematic diagram of an optimization process 300 for optimizing a process simulation model according to certain embodiments. A process simulated model is configured to predict the outcome of the semiconductor device manufacturing operation using process parameter values that characterize the semiconductor device manufacturing operation.

The methods may involve receiving, at step 302, current values of one or more plotted process model parameters to be optimized. In a first iteration, these current values may be considered original values. In step 304, a configured process simulation model is then created by providing the set of current values, input profile, and fixed process model parameter value(s) of one or more plotted process model parameters to the process simulation model. In step 306, using the constructed process simulation model, a computer-predicted result of the semiconductor device manufacturing operation is generated. In step 308, the computer-predicted result of the semiconductor device manufacturing operation is compared, at least in part, with the measurement result generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under a set of fixed process parameter values, and manufacturing the semiconductor device. Generate one or more cost values based on the difference between the computer-predicted result of operation and the measurement result. In step 310, a convergence check is used to determine whether the optimization process converges. If so, the process is completed as shown at 311. Otherwise, the optimization process generates an update of the current value(s). See step 312. This update may be generated using the cost value(s), current values of one or more plotted process model parameter values, and one or more previous values of optionally plotted process model parameter values. At this point, process control returns to step 304 with an update of the current values of the one or more plotted process model parameters. Thereafter, steps 304, 306, 308, 310, and 312 are repeated until current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters.

4 shows an embodiment 400 of an optimization process that employs a comparison of simulated and measured reflectance or elliptic values. As shown, optimizing the process simulation model improves the ability of the process simulation model to predict the outcome of a semiconductor device manufacturing operation in which the model is designed to, for example, simulate a computer generated feature profile. The iterative operation of the optimization process 400 involves iteratively adjusting one or more of the plotted process model parameters, a current value of α.

In some embodiments, the initial feature profile along with the initial values of the two types of process model parameters denoted as "α" and "μ" in the figure is entered into a process simulation model, such as the Etch Profile Model (EPM) discussed above. . This input is illustrated at 402 and initiates the reflectance or ellipse comparison optimization process 400. As introduced above, the terms “initial profile” and “initial feature profile” shown as 402 may be used interchangeably and may refer to spatial locations on a substrate surface that may be processed by a semiconductor device manufacturing operation. . For example, the initial profile may have one or more features (or may be completely planar), and serve as a starting or input profile for a semiconductor device manufacturing operation that will later modify the initial profile. Process model parameter α represents one or more plotted process model parameters to be optimized during the optimization process 400 and fixed model parameters [mu] are process model parameters that are required to run the process simulation model but do not change during the optimization procedure. The types of parameters used as the plotted and fixed process model parameters do not need to be set invariant, and local plasma properties, such as, for example, ion flux, may, in some optimization embodiments, constitute the plotted model parameter. Alternatively, fixed model parameters can be configured in other optimization embodiments.

Next, the constructed process simulation model 404 is run after providing the initial profile and the initial values of the parameters α and μ. During execution, the model adjusts the input initial profile to output the profile in a manner intended to predict the outcome of the semiconductor device manufacturing operation modeled by the process simulation model.

The execution of the process simulation model 404, and its accompanying calculations and adjustments, ultimately outputs a computer-generated feature profile illustrated at 406. This profile is a prediction of the model of the outcome of the semiconductor device manufacturing operation under consideration. For the etching process, the input feature profile may be a mask profile on the substrate, and the output computer-generated feature profile may be the etching profile of the substrate under the mask openings. However, in cases where the process simulation model models the planarization process or the addition process, the output computer-generated feature profile may be a profile of the substrate reflecting the planarization or addition process.

In some embodiments, a profile conditioner and/or profile conditioning operation (not shown in FIG. 4) prior to another calculation process using this feature profile; For example, a calculation process simulating reflection of electromagnetic radiation from the calculated etching profile is performed on the computer-predicted results of the semiconductor device manufacturing operation before being performed.

In the embodiments shown in Fig. 4, if employed, the operation of the profile conditioner is performed on the computer-generated feature profile, indicated by 406. The profile conditioner, or profile conditioning operation, smoothes and/or otherwise reduces the effect of the various aperiodic deviations generated by the process simulation model of the predicted feature profile. These variations can also be introduced by the statistical behavior of the process simulation model.

In order to accurately predict the reflectance pattern generated by providing incident electromagnetic radiation to the etching profile, the output 406 of the process simulation model, the optimization process assumes a specific period of etched features, such as features and/or feature regions, and It employs a calculation tool or algorithm such as Rigorous Coupled-Wave Analysis (RCWA) that further assumes the material properties of the substrate material to be processed and the various gaps resulting from the etching. Moreover, RCWA expects a specific transition of a given material, i.e. dielectric solid, to a different material, i.e. air, as a length-wise distance to the next from a similar area of one feature area within the expected period, i . . An alternative to RCWA is the Finite Difference Time Domain (FDTD) technique.

The presence of aperiodic or statistical deviations of features may interfere with the proper operation of the RCWA method, such that the method may not accurately predict the reflectance or elliptic spectrum generated when the deviation is present.

The profile conditioner identifies and removes certain aperiodic structures from the feature. In some embodiments, the profile conditioner may determine whether or not to handle the breakout based on the height of the breakout.

For example, the profile conditioner may be configured to identify and process only deviations that exceed a certain pre-specified height. In some embodiments, "micro-bumps" ie deviations below a predefined height threshold are ignored from the profile conditioner. Similarly, deviations exceeding a predefined height threshold may be averaged or otherwise combined by the profile conditioner to produce an average profile prior to application of RCWA to yield a reflectance/elliptic spectrum.

Referring back to the embodiment of FIG. 4, the computer-generated feature profile is a reflectance/elliptic spectrum generator 408 to output a computer-generated output reflectance/elliptic spectrum exemplified by “R[λ] _calc ” in the drawing. ). The reflectance/elliptic spectrum generator may be, for example, an algorithmic tool that implements RCWA or Finite Difference Time Domain (FDTD), all as described elsewhere herein. The reflectance/elliptic spectrum generator may be a standalone tool or may be implemented as a tool or set of routines. In one example, the reflectance/elliptic spectrum generator is part of a tool such as the YieldStar™ scattering system products available from ASML Netherlands BV of Veldhoven, Netherlands. For example, "High-NA optical CD metrology on small in-cell targets enabling improved higher order dose control and process control for logic," Proceedings of SPIE, 10145, Metrology, such as Cramer, which is incorporated herein by reference in its entirety. See Inspection, and Process Control for Microlithography XXXI, 101451B (28 March 2017).

The accuracy of the computer-generated reflectance/elliptic spectrum depends on the predicted power of the process simulation model when constructed with the current value(s) of α. In the illustrated process, the accuracy of the computer-generated reflectance/elliptic spectrum is experimentally measured, _expressed as R[λ] _exp , generated from feature profiles of real substrates processed according to the semiconductor device manufacturing operation modeled by the process simulation model. It is determined by comparing the resulted results (eg measurement results) with them. Both simulated operations and actual manufacturing operations use the same set of fixed process parameters and an initial feature profile. Actual (non-computer generated) results may be reflectance/elliptic spectra experimentally measured from optical metrology techniques such as scatterometry and elliptic polarization, as illustrated by 414 of optimization system 400. Calculated and experimentally generated results are based on the same detection technique (e.g., the same polarization, wavelength range, angle of incidence and detection, etc. for optical instrumentation) and the same feature characteristics (e.g. CD at a specific depth, endpoint detection , Deposited layer thickness, etc.).

The computer-predicted result R[λ] _calc , and the measurement-generated result R[λ] _exp are, for example, R[λ] _{exp -Compared} by "cost function calculator" 412 to output one or more cost values identified as R[λ] _calc (eg, difference, ratio, or other metric is determined). This comparison is based on the predicted/simulated result, e.g. R[λ] _calc and the experimentally determined result, R[λ] _exp It provides the cost value(s) reflecting the magnitude of the difference (or coincidence) between. The optimization system 400 at least (i) determines whether the value(s) of the plotted process model parameter value(s) have converged, and (ii) if the value(s) have not converged, plotting for the next iteration. The cost value is used to determine how and to what extent to adjust the current value(s) of the processed model parameter(s). As introduced earlier, one example of comparison results (cost values) is simply the Euclidean distance of the multidimensional result space. In certain embodiments, the cost function is determined in a result space associated with a scatter measurement tool, such as YieldStar™ scatterometer products, that provide scatter measurement results in a particular type of image.

Estimator 418 employs a "convergence checker", an algorithm for evaluating the potential convergence of the plotted process model parameter values, α. In some embodiments, execution of the convergence checker or estimator 418 involves identifying a substantially local or global minimum of one or more cost values and/or an amount of change in α over recent iterations. Upon determining the convergence of α, the convergence checker represents it at 420, leading to the output of the final, or optimized value of the plotted process model parameter(s) α. As indicated above, iterative modification of the process model parameter values plotted to the final value, e.g., output at 422, from the initial or seed value provided at 402, for example, is a model performed by the optimization system 400 This is the purpose of the optimization process. In some embodiments, iterative execution of the optimization process will generate a process simulation model consisting of the final values of the plotted process model parameters, which is, for example, a process simulation model consisting of the initial values of the plotted process model parameters. Provides excellent predictive ability.

Often, during one or more iterations of the optimization routine, before meeting the final convergence criterion, execution of convergence checker 418 will indicate that the cost values have not reached the required convergence condition. In these examples, the convergence checker adjusts the current value of α and outputs the adjusted value of α as illustrated at 424. Adjusting α may employ the current value of α and/or the cost value, as well as, optionally, one or more previous values of α and/or previous values of the cost value, as will be appreciated by those skilled in the art. The gradient descent technique may be employed for this purpose. The adjusted α is then re-entered, as illustrated at 426, keeping the fixed process parameters, μ, in the process simulation model 404 constant. In other words, the process simulation model is reconstructed with the adjusted value of α. The process simulation model is then rerun with the same initial profile and the same fixed process model parameters, but with adjusted floating process model parameters. Optimization system 400 then repeats the operations of components 404-418, which may achieve the required convergence condition, or if convergence is not achieved, repeats the operations of components 404-426. However, the measurement results obtained at 414 may be reused with this new cycle. Through this cycle, the optimization system 400 may further adjust α as needed. The optimization process continues with iterations as many times as necessary to output a final value of α, corresponding to satisfying the convergence condition for the cost value.

Referring now to FIG. 5, an example of an optimization routine 500 is shown. In contrast to the optimization system 400 previously shown in FIG. 4 (which employs a comparison of reflectance/ellipse values), the optimization system 500 shown here in FIG. 5 is a computer-generated feature profile (pre- For the determined input α), for example via an energy dissipative “X-SEM” (X-ray Scanning Electron Microscopy), for example, the experimental feature profile to adjust α to converge as illustrated in 520 Compare the measured values derived by. In this case, the process simulation model outputs the feature profile directly, and the process does not include a reflectance/elliptic spectrum generator 408. Of course, if the process simulation model outputs information other than feature profiles, the method will require an appropriate converter to change the output for the profile.

The remaining system components and operations 502, 504, 506, 512, 516, 518, 520, 522, 524, and 526 of the optimization process 500 are the components and operations 402, 404 of the optimization process 400 presented above. , 406, 412, 416, 418, 420, 422, 424, and 426 are identical or otherwise very similar, and thus similarly, one or more plotted, while keeping μ constant, representing one or more fixed process model parameters. It functions to iteratively optimize the process model parameter α representing the process model parameters.

Also, similar to the optimization performed by the system 400, the types of various parameters used as plotted and fixed process model parameters do not need to be set unchanged, e.g., local plasma such as ion flux. Attributes may constitute a plotted model parameter in some optimization embodiments, and may constitute a fixed model parameter in other optimization embodiments.

In detail, the optimization performed by the system 500 (similar to the optimization process of the system 400) is at 502, which entails input to the process simulation model of the initial feature profile, α and μ, such as an etch profile model (EPM). It begins. The process simulation model 504 is substantially the same as that made by the model 404, for example, in a manner intended to predict the outcome of a semiconductor device manufacturing operation modeled by the process simulation model (in this case a feature profile) or It is executed to adjust the input initial profile to output a similar profile. Execution of the process simulation model by model 506, and its accompanying calculations and adjustments, ultimately outputs a computer-generated feature profile illustrated at 506. As discussed above for optimization process 400, this profile is a prediction of a process simulation model of the outcome of the semiconductor device manufacturing operation under consideration.

However, unlike the optimization system 400, the optimization system 500 does not employ a reflectance/elliptic spectrum generator (e.g., shown as 408 of the optimization system 400), and thus computer-generated feature profile 506 Is provided directly to the cost function calculator 512, which also receives an empirically derived measure of the feature profile obtained via X-SEM, for example, as illustrated at 514. Experimentally derived measurements are obtained by using the semiconductor device manufacturing operation simulated by the process simulation model and processing the actual substrate using the same initial substrate profile and fixed parameter values. As previously specified, the geometry of a computer-generated or experimentally derived feature profile is a set of discrete points in space representing various positions of a particular feature, or group of features, or parameters representing these points (e.g. , A series of CD values at different heights). Note that there are many techniques available to experimentally determine the feature profile. Some techniques output profiles directly (eg, SEM technique and AFM technique) and other techniques indirectly output profiles (eg, optical metrology techniques). In the latter case, direct results (eg, reflectance spectrum) must be converted into feature profiles before they can be compared with computer-generated results.

Similar to the execution of the cost function calculator 412 of the optimization system 400, the cost function calculator 512, for example, in the drawing [etch profile] _exp- [etch profile] _calc Compare the computer-generated feature profile with an experimentally derived measure of the feature profile to output one or more cost values identified as (e.g., marked 516). This comparison provides a cost value(s) that reflects the magnitude of the difference (or coincidence) between the predicted/simulated results, eg, [etch profile] _calc and experimentally determined results, [etch profile] _exp . And, the same or similar to the optimization system 400, the optimization system 500 determines at least (i) whether the value(s) of the plotted process model parameter value(s) have converged, and (ii) the value If the (s) have not converged, the cost value is used to determine how and how much to adjust the current value(s) of the plotted process model parameter(s) for the next iteration. Of course, adjustment of the plotted process model parameter(s) may employ other information as current and previous values of the plotted process model parameter(s) and/or previous values of the cost value(s).

The cost value(s) illustrated at 516 are provided to a convergence checker 518, which is an algorithm for evaluating the potential convergence of α as indicated by the cost function calculator 512 as cost values. In some embodiments, and identical or similar to convergence checker 418 in optimization process 400, execution of convergence checker 518 involves identifying a substantially local or global minimum of one or more cost values. . On the indication of convergence α by the convergence checker, the convergence checker determines that convergence has occurred as shown at 520, which leads to the output of the final, or optimized, plotted process model parameter α.

As previously indicated, for example, iterative modification of the process model parameter values plotted from the initial or seed value provided at 502 to the output of the final value, e.g. 522, is the model optimization shown by the optimization process 400. This is the purpose of the process. In some embodiments, iterative execution of the optimization process by the system 400 provides a better predictive ability than a process simulation model consisting of, for example, the initial values of the plotted process model parameters, We will generate a process simulation model consisting of the final values of α.

And, the same or similar to the execution of the convergence checker 418 of the optimization system 400, before the final convergence criterion is satisfied, the execution of the convergence checker 518 indicates that the cost values have not reached the required convergence condition. May indicate that. In these examples, the convergence checker adjusts the current value of α and outputs the adjusted value of α as illustrated at 524. This adjusted α is then re-entered, as illustrated at 526, while keeping the fixed process parameters, μ, into the process simulation model 504 constant. In other words, the process simulation model is reconstructed with the adjusted value of α. The process simulation model is then rerun with the same initial profile and the same fixed process model parameters, but with adjusted floating process model parameters. The optimization system 500 then repeats the operations performed through components 502-526, as before, but the experimentally measured profile obtained at 514 may be reused in this new cycle. Through this cycle optimization, system 500 may further adjust α as needed. Optimization continues as many times as necessary to output the final converged value of α at 522.

Referring now to FIG. 6, an optimization system 600 is shown. In contrast to embodiments employing the system 400 shown in FIG. 4 (which employs a comparison of reflectance/elliptic values), the optimization system 600 shown in FIG. Rather, it is shown to include a profile parameters converter 608. The remaining operating components 602-624 of the optimization process 600 are somewhat similar to the corresponding operations of components 402-424, corresponding to the optimization system 400 shown in FIG. 4. The same excess technique is omitted.

As described above, the result of execution of the process simulation model may be the profile of the substrate after (or during) the semiconductor device manufacturing operation simulated by the model. Such a profile may be represented as a set of discrete points in space representing various locations within and/or near a particular feature or group of features.

In the optimization process of the system 600, and as opposed to using the profile of the substrate defined by the set of points in space, this process can, for example, use potentially fewer data points, or a set thereof. , Employs a set of “profile parameters” to represent the geometry of the feature profile. In other words, the process simulation model 604, e.g., EPM, outputs a computer-generated feature profile that may have many discrete points in space as described above. As illustrated at 610, these points may be referred to as a “parsimonious” profile, e.g., profile parameter(s), these points later to output a profile denoted by P _i "Profile Parameters Converter" ( 608) systematically reduced or at least partially eliminated. Examples of profile parameters include those features of a feature or group of features: CD, sidewall angle, depth, pitch, etc. Techniques for converting a feature profile into a set of profile parameters are known in the art and are commonly used for optical CD methods.

Similar to the optimization processes 400 and 500 described above, the cost function calculator 612 of the optimization system 600 is derived from experimentally generated data such as X-SEM, CD-SEM, or optical metrology. Receive geometric profile parameters P _i . These profile parameters may be derived from data experimentally generated using OCD methods. The result is a geometric characterization of a feature of parameters that characterizes different aspects of the geometric model, such as a trapezoidal model or a corner rounding model. Cost function calculator 612 also receives profile parameters from profile parameters converter 608. Using these inputs, the cost function calculator 612 outputs one or more of their cost values, eg [P _i ] _exp- [P _i ] _calc , 616. These cost values are as discussed above for convergence checkers 418 and/or 518 to ultimately achieve convergence as illustrated at 620, and as required to output a final α as illustrated at 622. It is similarly received and used by convergence checker 618 to iteratively adjust α.

In certain embodiments, simulated and metrology experimentally evaluated systems have multilayer stacks of deposited material, optionally including a mask layer. A process simulation model calibrated using multi-layer stacks comprising varying thicknesses and selectively varying layers of materials can have large real values. Typically etching processes are performed on multilayer stacks of homogeneous materials. However, when calibrating a process simulation model using substrates with multilayer stacks of material to be etched, it is important that the simulation model uses correct thickness values for each of the layers of the stack. To this end, the methods described herein may be performed in such a way that a physical substrate comprising a multilayer stack to be used for calibration is preliminarily evaluated by metrology to determine the thickness of each layer of the stack. These thicknesses are later used in a productive representation of the substrate considered in the process simulation model. In this way, the simulation adequately represents the physical structure that will be used to provide experimental information obtained by metrology to calibrate the process simulation model.

In some embodiments, after the process simulation model has been fully calibrated (e.g., the value of α converges to a point where the model can be used with confidence), the model is put into execution (e.g., lithographic It is used to predict the etching results and all applications associated with defining masks, designing a new etching apparatus, specified in the etching process window, etc.). During practical use of such a process simulation model, if it is found that the model fails to accurately predict the etch profile produced by the actual etching process, this information can be employed to further calibrate or at least improve the calibration of the model. Simulation results for conditions that cause false predictions are provided to the optimization routine along with actual results of the etching process to further optimize the parameter values (α) used in the process simulation model. In this way, the predictive power of the process simulation model may be improved in the area of the physical conditions in which they are used, and/or the area of the model is represented by the etching conditions in which the model incorrectly predicts the etching result. Expands to Of course, over the lifetime of the process simulation model, this recalibration may be employed multiple times, i.e. each time it finds that the predictive ability has failed.

Additional Example-CD-SEM Optimization Data

The etch model may generate three-dimensional profiles including x and y dimensions on the surface of the wafer or in a plane parallel (or above) to the integrated circuit chip when viewed from above. The etch model may also provide z-dimensional information in a direction orthogonal to the surface of the wafer or the integrated circuit. The z-direction value specifies the etch depth. Conversely, a contour is a two-dimensional representation that contains only x and y dimensions. Only the x and y dimensions are used in the design layout provided via tapeout and implemented with a lithographic photomask. In certain embodiments, the etch models described herein generate x-y contours by specifying the z-direction height of the etch profile or by specifying the material of the stack to be etched. And, in some cases, the etch profile is provided only in two dimensions, z-direction and x-direction. Further, the contour may be provided in the x-direction, in one dimension only, or as a feature parameter such as CD or pitch.

CD-SEM (or Critical Dimension-Scanning Electron Microscopy) is an electron microscopy technique that provides a top down view of features (showing the x-y plane) and patterns on a substrate surface, such as an integrated circuit chip or coupon. From this vantage, these features may be viewed as top down contours on the substrate. CD-SEM can provide nanometer scale resolution of contours. In addition to sharp contours, the CD-SEM may provide intensity gradients at the boundaries (contour edges). These slopes may, at least in part, clearly show transition regions on features in which the feature sidewalls are tilted from one height to a different height. A single CD-SEM image may provide sufficient details to distinguish the contours in one or more layers (perhaps individually etched) and the slopes of the sidewall of the single layer. A plurality of CD-SEM images taken at different stages of a multi-step process may be overlaid to show the progression of feature contours from one manufacturing process operation to the next.

An apparatus for performing CD-SEM may include a dedicated system for inspecting patterns on a substrate by measuring dimensions of features of the patterns. Examples of CD-SEM systems include CG6300 and KLA-Tencor 8100XP, and Applied Materials VeritySEM 5i. CD-SEM sometimes:

ADI (After Development Inspection): inspection of the resist pattern after transfer and subsequent development of the pattern by an exposure tool (lithography); And

AEI (After Etch Inspection): Etching using a resist pattern as a mask, followed by measuring the dimensions of the etched pattern, and then used for inspection of the substrate.

In developing the fabrication process, CD-SEM is sometimes used to identify the effect of certain processing conditions of the transferred pattern, particularly the focus and dose effect of the exposure tool. The process window is created using the relationship of exposure conditions (focus and dose) and exposure result.

As described, calibration or optimization of process simulation models, such as etch models, may be performed using a cross-sectional SEM or TEM, which may exhibit destructive and sometimes difficult to interpret line boundaries. Using these techniques is expensive and can result in insufficient samples collected. This negatively affects the turn-around time and result accuracy of the etch model calibration.

Calibration may also be performed using top-down information, such as obtained using CD-SEM, which takes a top-down image and extracts critical dimensions (CDs) of the features. Measuring CDs is highly dependent on the structure profile. The challenge of using a CD-SEM is that there is sometimes an inaccuracy of position in which CDs are determined, especially in the z direction. Associating CDs at the wrong location of the profile of the structures limits the roughness of the calibrated etch model. This is a CDSAXS (critical dimension small angle X-ray scattering), transmission electron microscopy technique (e.g., STEM), a thin film, or a CD along with one or more techniques that provide z-direction decomposition information such as OCD scattering techniques. It can also be solved by using -SEM. Feature representations comprising a z-direction component are sometimes referred to herein as profile-based representations, which produce profile-based metrology techniques such as x-ray scattering, TEM, and OCD metrology.

As explained, in terms of profile progress at the wafer level, the etch results can be simulated through an etch model. The embodiment described herein uses CD-SEM alone or in combination with other metrology methods to calibrate the plotted parameters of the etch model. In certain embodiments, the calibration uses CD-SEM assisted by one or more other metrology methods that provide more detailed profile information, eg, STEM and/or optical scattering. The time progression when measured by CD-SEM with profiling measurements (eg, optical scattering or STEM) can provide boundary conditions (calibration information) that optimize plotted parameters of the etch model. The nanometer resolution of the top down contours generated by the CD-SEM is compensated for by the accuracy of the side profile information collected by CDSAXS, TEM, and/or OCD techniques. The calibration process may employ multiple test patterns/samples at the wafer-level (eg, gauges from the clip design library). Each of the test patterns is transferred to a test substrate on which etching or processing is performed and the resulting substrate features are measured using CD-SEM and optionally one or more other metrology techniques.

Optimization using the CD-SEM output may be performed using any one or more of the procedures shown in FIGS. 4, 5, and 6. A separate process flow specific to processes using CD-SEM is shown in FIG. 8.

As shown in Fig. 8, the process begins with the supply of various parameters necessary to run the process simulation models. The whole process iteratively improves one of these parameters, the plotted parameter(s). Initially, the process simulation model (identified herein as "SEM3D or SKM") is (a) a control parameter (α vector or plotted parameter(s)), (b) a constant parameter (μ vector or a fixed parameter ( S)), (c) lead-in profile (xz representation of resist, mask, or other over-layer design layout) and (d) lead-in pattern (top-down xy representation of pattern resist, mask, or other over-layer design layout). ) As input. Running the process simulation model with these inputs provides as output one or more of a feature profile (x-z), a contour (x-y), and a LER or LWR for one or more features to be modeled.

In the inner optimization loop, cross-section measurement data (e.g., CDSAXS, STEM, X-SEM, etc.) along with top-down metrology data (e.g. CD-SEM) are processed using the incoming profile/pattern and process simulation It is provided from one or more substrates that undergo a device manufacturing operation modeled by the model. The value(s) of the metrology data can be compared to the corresponding output(s) of the process simulation model (A=A'?; B=B'?; And C=C'?) It may be used to generate one or more cost functions as described above.

In the outer optimization loop, the profile, contour, and/or LER/LWR output by the process simulation model are provided to a spectrum generator such as RCWA or FDTD as described above. The resulting results are compared against the experimentally generated spectrum, again as described above, to produce a different cost function (B=B'?). The experimentally generated spectrum may be generated by any number of optical metrology techniques with or without OCD conversion. See discussion of FIGS. 4 and 6. In certain embodiments, the comparison is performed in the space used for a particular scatter measurement tool or technique (eg, YieldStar™ tools described above).

The inner and outer optimization loops may be used alone or together. When used together, a combined cost function is created based on the general parameters B with one or more of A, C, and D. The cost function is then used to adjust the value of the plotted parameter, α, as described elsewhere herein.

The back scattered electron intensity of the CD-SEM enables determination of the CD contour and LWR/LER (line width roughness and/or line edge roughness). This information may be provided as a CD-SEM output to facilitate model calibration. A design layout or mask or part thereof, such as a process simulation model (e.g., an etch profile model such as a kinetic model or behavioral model as described herein) provided by one or more gauges/clips. It is used to simulate modification of the input structure such as. As described elsewhere herein, the difference between simulated results of one or more metrics and experimental results is evaluated by cost functions. The cost function using the CD-SEM output is a CD-SEM (e.g., X-ray scattering, TEM, or OCD) to facilitate optimization through nonlinear regression of, for example, plotted parameter value(s), α. Technique) can be combined with other measurement cost functions of data streams.

As shown, the CD-SEM output may include feature contours and LWR and/or LER. Additionally, through the intensity gradients shown in the CD-SEM images, the CD-SEM outputs a plurality of locations of each of the material of the stack (e.g., spin-on materials, hardmask, lower substrate, etc.), And/or within each of the etching steps, the progress of the etching profiles may be captured. The intensity slope may, at least in part, reflect the transition region of the profile in which the sidewalls have a slope (ie, not purely vertical). Thus, while CD-SEM may excel in determining feature contours (in the x-y plane), it may also provide some z-direction information. This may supplement 1D or 2D structural information.

By using the CD-SEM metrology data along with other metrology data, a multi-feature process simulation model may be created. For example, in addition to feature profiles (calibrated by X-ray scattering, TEM, SEM, AFM, OCD, etc.), a single etch model can also be viewed as a feature or top down (calibrated by CD-SEM). Rated) pattern contours/slopes and/or LER and/or LWR estimates (calibrated by CD-SEM). These predicted results of any manufacturing operation can be expressed in one or multiple time steps. For process simulation models that employ multiple time steps, calibration information may require multiple time snapshots captured via metrology.

In certain embodiments, to optimize the process simulation model, the method may combine cost functions of two or more of the following types of metrology data: TEM/SEM/AFM (difference of xz data) with weighted hybrid metrology. , OCD (differences in spectral) and CD-SEM (typically differences in contour/tilt values viewed from the xy plane dominate). In certain embodiments, the optimization process employs error bars of the measurement of L2-standard cost functions, with chi squared. Of course, as described, other cost functions could also be used. As in conventional machine learning, training, validation, and testing may be used. See other techniques for further explanation of machine learning process flows. The global optimization method may be used to search for the lowest mean square error (MSE) for experimental data.

Related selectable points-CD-SEM

In certain embodiments, the optimized metrology results are (e.g., on different gauges/clips) of the CD-SEM along with one or more other metrology techniques, such as OCD and/or TEM, depending on the profile sensitivity and accuracy requirements. Provided by) multiple sample loading methods.

In cases where metrology uncertainty is high, use two or more of the following in the process simulation model parameter space: calibrating kernel parameters, etch physical parameters, etch behavior parameters, and/or structural parameters.

Iterative optimization of kernel parameters and other profile parameters. Kernel parameters representing profile parameters as a function of local feature density and shape of adjacent structures may be calibrated for 1D and 2D images using a large sample size CD-SEM.

This optimization process flow for using CD-SEM-based hybrid metrology to calibrate the etch model has certain advantages such as:

1. CD-SEM can provide accurate input of two-dimensional contours (x-y information). STEM can provide detailed and accurate profiles (including z-direction information). OCD provides excellent precision profile measurements (including z-direction information). Combining the strengths of these individual techniques can provide good accuracy.

2. The calibration allows direct mapping of the etch profile between the etch model parameters and the top down contours (x-y view), optionally between them. This suggests a direct path for integrating OPC/CD-SEM (industry standard) and etch OPC + profile measurements. OPC and CD-SEM are sometimes used in industry without considering profile contribution. In some implementations herein, the considerations of the etch profile are incorporated into a standard OPC flow. In addition, if the etch model provides a simulated profile compared to the profile measurement, the approach extends the OPC simulation to EtchOPC (using the simulated profile) as well as CD-SEM with CD-SEM + profile measurement after etching. Expand This "etch extension" can be integrated into a standard OPC flow.

3. Profile progress is related to the etch-step change of CD-SEM contours, suggesting a way to compare the consistency and evaluation error of each step.

4. Low cost: OCD (which is a non-destructive technique) costs less than CD-SEM (which is biased due to interaction with the electron beam), and may eventually have less cost than STEM (destructive).

Etch Profile Models

As mentioned, etch profile models (EPMS) are a type of process simulation model. They produce a theoretically determined etch profile from a set of input etch reaction parameters (independent variables), which characterize some characteristics of the etch reaction, such as specific underlying physical and chemical etch processes and reaction mechanisms. These processes may be modeled as a function of time and position of the grid representing the features to be etched and their surroundings. Examples of input parameters include plasma parameters such as ion flux and chemical reaction parameters such as the probability of a particular chemical reaction occurring. Other examples include the characteristics of the substrate to be etched (e.g., a layer-by-layer description of thicknesses and materials), the initial mask layout for one or more features to be etched, process chamber conditions, etc. Include. These parameters include process conditions and general reactor configurations such as pressure, substrate temperature, plasma source parameters (e.g., power provided to the plasma source, frequencies, duty cycles), reactants, and their flow rates. It may be obtained from a variety of sources, including other models that calculate them from. In some embodiments, these models may be part of the EPM.

The EPM takes these parameters as independent variables (which may be fixed and/or plotted in the context of the optimization routines described herein) and functionally generates etch profiles as response variables. In other words, the set of independent variables are the parameters used as input to the model, and the response variables are the etch profiles of features calculated by the model. EPMs may employ one or more relationships between reaction parameters and etch profile. Relationships are related to the etch profiles, coefficients, weights, and/or other model parameters (as well as response parameters and/or other model parameters, applied to the independent variables in a prescribed manner to generate response variables). Linear functions such as quadratic and higher-order polynomial functions, etc.). These weights, coefficients, etc. may represent one or more of the reaction parameters described above. In some embodiments, these model parameters are plotted process model parameter values that are tuned or adjusted during the optimization techniques described herein. In some embodiments, some of the response parameters are model parameters to be optimized, while other parameters are used as fixed process model parameters. For example, in some embodiments, chemical reaction parameters may be optimizable plotted process model parameters, while plasma parameters may be fixed process model parameters.

As explained, some EPMs employ basic reaction mechanical parameters and may be viewed as basic to underlying chemicals and physics, so experimental process engineers generally do not have control over these quantities. In the etch profile model, these variables may be applied at each location of the grid and at a plurality of times separated into defined time steps. In some implementations, the grid resolution may vary from about a few Å to about μm. In some implementations that employ time dependent modeling, the time steps may be 1e-15 to 1e-10 seconds. In certain embodiments, the optimization employs two types of mechanical independent variables: (1) local plasma parameters, and (2) local chemical reaction parameters. These parameters are "local" in the sense, which may lower the resolution of the grid in some cases, which may vary a function of position. Examples of plasma parameters include local plasma properties such as fluxes and energies of particles such as ions, radicals, protons, electrons, excited species, deposition species and their energy and angular dispersions, etc. do. Examples of chemical and physical-chemical reaction parameters include rate constants (e.g., the probabilities of a particular chemical reaction occurring at a particular time), adhesion coefficients, energy threshold for etching, reference energy, sputtering yield. Energy index, angular yield functions and their parameters, and the like. Further, parameterized chemical reactions may include reactions involving the etchant and the material to which the reactants will be etched. It will be appreciated that chemical reaction parameters may include various types of reactions in addition to reactions that directly etch the substrate. Examples of such reactions include side reactions, including parasitic reactions, deposition reactions, reactions of by-products, and the like. Any of these may affect the overall etch rate. It will also be appreciated that the model may require other input parameters in addition to the plasma and chemical reaction input parameters mentioned above. Examples of such parameters include the temperature, partial pressure or reactants of the reaction sites, and the like. In some cases, these and/or other non-mechanical parameters may be input in a module that outputs some of the mechanical parameters. In some embodiments, the models do not employ mechanical parameters, at least directly.

Initial (non-optimized) values for EPM model variables as well as variables that are fixed during optimization (e.g., plasma parameters in some embodiments) can be found in various sources such as literature, other calculation modules or models. May be obtained from calculations by, etc. In some embodiments, independent input variables — such as plasma parameters — may be determined using a model, eg, from an etch chamber plasma model for the case of plasma parameters. These models include input EPM parameters applicable from various process parameters (e.g., by turning a knob) that the process engineer has control over-e.g. chamber atmosphere parameters such as pressure, flow rate, plasma power, wafer temperature. , ICP coil currents, bias voltages/power, pulsing frequency, pulse duty cycle, etc.

EPMs may take any of many different forms. Ultimately, they provide the relationship between the independent variable and the response variable. The relationship may be linear or nonlinear. In certain embodiments, EPM is a model, referred to in the art as a cell-based Monte Carlo surface response model. These models of various forms operate to simulate topographic progression of wafer features over time in the context of semiconductor wafer fabrication. The model launches pseudo-particles with energy and angular dispersions generated by a plasma model or experimental diagnostics for any radial locations on the wafer. The pseudo-particles are statistically weighted to represent fluxes of radicals and ions to the surface. These models address a variety of surface reaction mechanisms that generate on-surface etching, sputtering, and mixed alc deposition to predict profile progression. During Monte Carlo integration, the trajectories of the various ionic and neutral pseudo-particles are tracked within the wafer feature until they react with or leave the resulting domain. EPM has advanced capabilities to predict etching, stripping, ALD, ionized metal PVD, and PECVD for a variety of materials.

In some embodiments, the EPM utilizes a mesh that has a fine enough resolution to properly process/model the dimensions of a straight mesh wafer feature in 2 or 3 dimensions (however, by default, the mesh (whether 2D or 3D) is non-linear). Coordinates can also be used). The mesh may be viewed as an array of grid points in two or three dimensions. It can also be viewed as an array of cells representing a 2D local area or 3D volume associated with each of the grid-points. Each of the cells in the mesh may represent a different solid material or mixture of materials. Whether a 2D or 3D mesh is selected as the criterion for modeling may depend on the class/type of the substrate feature to be modeled. For example, a 2D mesh may be used to model a long trench feature (e.g. on a polysilicon substrate), and a 2D mesh is a response of the geometry of the ends of the trench that occur from the ends down the length of multiple trenches. Describe the cross-sectional shape of the trench under the assumption that it is not too relevant to the processes (i.e., for the purposes of this cross-sectional 2D model, the trench is assumed to be infinite, and again a reasonable assumption for the trench feature from the ends). On the other hand, it may be appropriate to model a circular via feature (through-silicon via (TSV)) using a 3D mesh (since the x,y horizontal dimensions of the feature are equal to each other).

The mesh spacing may, for example, range from a sub-nanometer (eg, from 1 Å) to a few μm (eg 10 μm). Typically, each mesh cell is assigned a material identity (e.g., within a spatial area not occupied by a feature), e.g., photoresists, polysilicon, gaseous etchant or plasma, which during profile progression It can be changed. The solid phase species can be represented by the identity of the material of the calculation cell, and the gas phase species can be represented by the calculated pseudo-particles. In this way, the mesh provides a reasonably detailed representation (e.g., computational objectives) of the substrate feature and the ambient gas atmosphere (e.g., plasma) because the geometry/topology of the wafer feature evolves over time in the reactive etching process. For).

Some of the techniques described above have been focused on process simulation models, such as surface dynamic models, that employ a mechanical representation of semiconductor device manufacturing operation. These models are described in more detail in U.S. Patent Application Publication No. 20170228482, filed on February 8, 2016 and U.S. Patent Application Publication No. 20170363950, filed on June 21, 2016, all of which are incorporated herein by reference in their entirety. Is cited. However, certain embodiments use significantly different models to represent semiconductor device manufacturing operations. In some cases, models do not at least directly employ mechanical parameters that attempt to explain the underlying chemistry or physics of the semiconductor device manufacturing operation. For example, behavioral models may employ concepts of processes to predict structural details of features created by one or more semiconductor device manufacturing operations. An example of a behavioral model is SEMulator3D™ from Coventor, owned by Lam Research. Examples of behavioral models are presented in U.S. Patent No. 9,015,016 and U.S. Patent No. 9,659,126, all of which are previously incorporated by reference.

In various embodiments, the process simulation models described herein model a feature in three dimensions. In some cases, the process simulation models described herein are not just one feature for an area of the design layout (e.g., overly large, multi-device areas), but the impact of semiconductor device manufacturing operations on a group of features. Predict.

While the above technique has focused on etch models, this disclosure also relates to other models as models for predicting the effect of a planarization process or deposition process on a substrate.

Experiments and profile measurements

In order to optimize the process simulation models, various experiments may be performed to determine—accurately—the actual profiles arising from actual processes performed under various process conditions specified by various sets of process parameters. . Thus, for example, specifying a first set of values for a set of process parameters-e.g. etchant flow rate, plasma power, temperature, pressure, etc.-to generate a first profile, and set up the chamber apparatus accordingly. And flowing the etchant into the chamber, striking the plasma, etc., and proceeds to the first semiconductor substrate processing. Then specify a second set of values for the same set of process parameters to create a second profile, process the second substrate, and so on.

Various combinations of process parameters may be used to represent a suitably wide or focused process space to optimize the process simulation model. The same combinations of process parameters are then used by the process simulation model to provide (response variables) profile outputs that can be compared against experimental results, to calculate (independent) input parameters, such as mechanical parameters. As experiments are expensive and time consuming, techniques can be employed to design experiments in a manner that reduces the number of experiments that must be performed to provide a robust training set that optimizes the process simulation model. Techniques such as design of experiments (DOE) may be employed for this purpose. In general, these techniques determine the sets of process parameters to be used in various experiments. They select combinations of process parameters by taking into account statistical interactions, randomization, etc. between the process parameters. As an example, the DOE may identify a small number of experiments covering a limited range of parameters around a completed process center point.

In some approaches, the researcher performs all experiments prior to the model optimization process and uses only these experiments of the optimization routine iterations until convergence. Alternatively, the experimental designer may perform some experiments on previous iterations of the optimization and additional experiments later as the optimization proceeds. The optimization process may inform the experiment designer of specific parameters to be evaluated and thus specific experiments to be run for later iterations.

One or more in-situ or offline metrology tools may be used to measure experimentally generated profiles arising from these experimental process operations. Measurements may be made at the end of the processes, during the processes, or at one or more times during the processes. If measurements are made at the end of the process, the measurement methodology may be destructive, and if it is made at intervals during the etch process, the measurement methodology will generally be non-destructive (and thus does not destroy the etch). Examples of suitable metrology techniques include, but are not limited to, in situ reflectometry, OCD, cross-sectional SEM, CD-SEM, and others mentioned above. As in the case of the SEM (where the experiment basically images the etch profile of the feature), the metrology tool can measure the profile of the feature directly, or for OCD measurements (some post-processing from the actual measured data is the etch of the feature). Note that it is also possible to indirectly determine a feature's etch profile, such as to retract the profile. The metrology techniques may be categorized by where they are performed and what is sampled, and categories include in-situ , offline, non-destructive, and destructive metrology. In-situ measurements include, for example, reflectometry and ellipsometry; Offline non-destructive measurements include, for example, single wavelength and broadband OCD measurements or scatterometry, dome scatterometry, CD-SAXS, and top-down SEM (CD-SEM); And destructive measurements include, for example, X-SEM, STEM, and TEM.

In any case, the result of experiments and metrology procedures is a set of measured profiles, each generally a set of coordinates or a set of values for a set of grid values, representing the shape of the feature's profile as described above. Includes them. The profiles are later used as inputs to train, optimize, and refine computerized etch profile models as described herein.

Reflectometry and Ellipsometry Spectrum Analysis and Modeling Tools

When using a process simulation model to generate feature profile values, optical parameters generated from the geometry may be modeled or predicted using an optical modeling routine such as the RCWA method or similar technique.

RCWA is a second method that can be used to describe the characteristics of radiation reflected (diffracted, scattered) from periodic structures such as a grating, or transmitted through the grating. RCWA was developed widely by Moharam and Gaylord described in the scientific literature. For example, M. G. Moharam and T. K. Gaylord "Rigorous coupled-wave analysis of planar-grating diffraction" J. Opt Soc of America, Vol. 71, Issue 7, pp. See 811-818 (1981). RCWA calculates the intensity and polarization characteristics of various diffracted orders (zero or higher). Other optical modeling methods that can provide results include, but are not limited to, C method, Modal method, Rayleigh approximation, EFIE (e-field integration equation), and Cf-FFT (conjugate gradient-fast fourier transform). do.

RCWA is a semi-analytic method of computational electromagnetism that is often employed to address scattering from periodic dielectric structures. This is a Fourier-space method and thus devices and fields are represented by the sum of spatial harmonics. The method is based on Floquet theory, and the solutions of periodic differential equations can be extended to Floquet functions (or, in particular, sometimes referred to as a block wave in solid state physics). The device is divided into layers, each uniform in the z direction. Stepwise approximation is required for curved devices with properties such as dielectric permittivity degraded along the z-direction. Electromagnetic modes in each layer are calculated and propagated analytically through the layers. The whole problem is solved by matching boundary conditions at each of the interfaces between the layers using a technique such as scattering matrices. In a periodic dielectric medium, to solve the electromagnetic modes, determined by the wave vector of the planar incident waveform, the Maxwell equation (partially in differential form) as well as the boundary conditions are expanded by Floquet functions and transformed into an infinitely large algebraic equation. Depending on the required accuracy and speed of convergence, with the cutoff of higher order Floquet functions, infinitely large algebraic equations become finite and thus solveable by computers.

Another way to computer-generated optical parameters generated (or generateable) by optical beam interaction with substrate features is to use a finite-difference time-domain (FDTD) method. This is a numerical analysis technique for modeling electrodynamics. This is a grid-based finite difference method to find a suitable solution to the time-dependent Maxwell equation in partially differential form. These equations discretize in time and are partial derivatives of space. The resulting finite difference equations are solved in a leaprog manner: the electric field vector components of the volume space are solved at a predetermined moment in time, then the magnetic field vector components of the same spatial volume are solved at the next moment in time, And the process is repeated until the target transient or steady state electromagnetic field is calculated.

Convergence check

, J.J. and D.C. Sorensen, "Computing Trust Region Step," SIAM Journal on Scientific and Statistical Computing, Vol. 3, pp 553-572, (1983); Byrd, R.H., R.B. Schnabel, and G.A. Shultz, "Approximate Solution of Trust Region Problem by Minimization over Two-Dimensional Subspaces," Mathematical Programming, Vol. 40, pp 247-263 (1988); Dennis, J.E., Jr., "Nonlinear least-squares," State of Art in Numerical Analysis ed. D. Jacobs, Academic Press, pp 269-312 (1977); Mor

, J.J., "Levenberg-Marquardt Algorithm: Implementation and Theory," Numerical Analysis, ed. G. A. Watson, Lecture Notes in Mathematics 630, Springer Verlag, pp 105-116 (1977); Powell, M.J.D., "A Fast Algorithm for Nonlinearly Constrained 최적화 Calculations," Numerical Analysis, G.A.Watson ed., Lecture Notes in Mathematics, Springer Verlag, Vol. 630 (1978) 를 참조하라. The plotted process model parameter optimization procedure described above may be an iterative nonlinear optimization procedure-for example, optimizing an error metric or cost value, which is generally a nonlinear function of the input parameters-and, as such, is known in the art. Various known techniques may be employed for nonlinear optimization. For example, each of which is incorporated herein by reference in its entirety: Biggs, MC, “Constrained Minimization Using Recursive Quadratic Programming,” Towards Global Optimization (LCW Dixon and GP Szergo, eds.), North-Holland, pp 341- 349, (1975); Conn, NR, NIM Gould, and Ph.L. Toint, “Trust-Region Methods,” MPS/SIAM Series on Optimization, SIAM and MPS (2000); Mor

, JJ and DC Sorensen, "Computing Trust Region Step," SIAM Journal on Scientific and Statistical Computing, Vol. 3, pp 553-572, (1983); Byrd, RH, RB Schnabel, and GA Shultz, "Approximate Solution of Trust Region Problem by Minimization over Two-Dimensional Subspaces," Mathematical Programming, Vol. 40, pp 247-263 (1988); Dennis, JE, Jr., "Nonlinear least-squares," State of Art in Numerical Analysis ed. D. Jacobs, Academic Press, pp 269-312 (1977); Mor

, JJ, "Levenberg-Marquardt Algorithm: Implementation and Theory," Numerical Analysis, ed. GA Watson, Lecture Notes in Mathematics 630, Springer Verlag, pp 105-116 (1977); Powell, MJD, "A Fast Algorithm for Nonlinearly Constrained Optimization Calculations," Numerical Analysis, GAWatson ed., Lecture Notes in Mathematics, Springer Verlag, Vol. See 630 (1978).

In general, the comparison used to calculate the cost compares a plurality of aspects or indices of computer-predicted measurement results. The differences between the computer-generated and measured values of these indices constitute a cost function for optimization. Examples of indices include critical dimension (CD) differences for a plurality of heights of a material, thickness differences for a given material, and spectral differences in the full spectrum. The cost function may be a combination of these, optionally with weighting factors for each. These differences can also be expressed as L1 or L2 standards, Euclidean distance, Mahalanobis distance, etc. In some embodiments, these techniques optimize an objective function (here a cost function/value) subject to certain constraints, which may be located in the entered parameters and/or error metric. In certain such embodiments, the constraint functions themselves may be nonlinear. For example, in embodiments in which the calculated etch profile is represented by a set of stacked trapezoids output by the process simulation model, the cost value is the area represented by the boundaries of these stacked trapezoids and the area of the measured experimental etch profile. It can also be defined as the difference between. In this case, the error metric is a nonlinear function of the response variables output by the process simulation model, so the constrained optimization technique is chosen from those just described (and/or from the unified criteria), which allows the specification of nonlinear constraints. do. Examples of widely used cost functions are WWW: docs.scipy.org/doc/scipy/reference/generated/scipy.optimize.

Available on SciPy.org as least_squares.html#scipy.optimize.least_squares.

Applications of optimized process simulation models

The optimized calculated etch models disclosed herein may be useful for all semiconductor processing workflows where detailed evaluation and characterization of the etch process is desired. For example, if a new etch process is developed, a model may be used to determine etch profile characteristics for many combinations of process parameters without having to enter a laboratory, and each experiment may be performed individually. In this way, optimized etch profile models may enable faster process development cycles, and in some embodiments may significantly reduce the amount of work required to fine tune the target profile.

Since estimating the edge placement error is typically quite important in a lithographic operation and an accurate calculation of the profile shape provides this information, lithographic operations and masking may also be quite beneficial from accurate etch profile modeling.

US US Patent Application No. 15/367,060, filed Dec. 1, 2016, which is incorporated herein by reference in its entirety, describes edge placement error detection and lithographic mask design. Note that there are at least two levels that may be applicable in this context: design layout correction of lithography and etching. In other words, optical considerations and etch-based considerations may be used to determine the mask layout. Etch-based considerations are determined using a prepared model as described herein.

Fabricating a photolithographic mask using a layout determined as described herein begins with a so-called blank in which the process comprises a glass substrate coated with a layer of chromium and a layer of resist. Sometimes materials in addition to or other than chromium are used. For example, the attenuated phase shifting masks use an additional layer such as a molybdenum silicide layer. The resist may be a positive or negative resist. Upon exposure of the electron beam, a pattern is formed on the resist that can be transferred into the underlying chromium layer through an etching process. Chromium provides opaque areas on the photolithography mask that casts a shadow during the exposure of semiconductor wafers.

The fabrication of photolithographic masks are similar lithographic steps during semiconductor device fabrication. However, exposure of the resist is made by electron beams opposed to light (eg, deep UV). The blank is exposed at least in part to electron beam radiation impinging on the resist at locations specified by the mask design layout, determined using an EPM of the type described herein. Subsequently, the mask is developed to create a pattern of the layout. The resist pattern now formed is later transferred to the lower chromium by an appropriate etching process (eg plasma or wet etching). Thereafter, the resist is removed and the exposed chromium pattern is covered with a pellicle to prevent contamination.

The optimized models disclosed herein may also be useful in solving a reciprocity problem, requiring a specific target etch profile and wanting to find one or more specific combinations of process parameters (or EPM input parameters). Again, this may be done by experimental trial and error, but until accurate modeling of the etch profile arising from a predetermined set of process parameters (or EPM input parameters) and conditions, good candidates are identified for the entire experimental study. It may replace the need to do this in experiments or at least the first phases of exploring the process/input parameter space. In some embodiments, in fact, it may be possible to numerically reverse the model in a fully automated manner—ie, repeatedly positioning a set of parameters that produce a predetermined etch profile. Once again, a reduction in the dimensionality of the etch profile coordinate space (via PCA), projection into this space of the target etch profile, may make this numerical reversal easier.

Based on the disclosure provided herein, EPM may be used to facilitate process window and hardware optimizations. In some embodiments, EPM is used to determine a set of parameters (eg, process window) for an existing reactor or reactor design that is not modified. In some embodiments, the EPM is used to determine a modified reactor design, including, but not limited to, the components of the reactor. For example, the EPM may propose to modify the showerhead design (eg, hole patterns or internal flow lines are converted from the existing design). In another example, the EPM may propose modifications to the plasma generator design (eg, the arrangement and/or configuration of a “CCP” (capacitively coupled plasma) electrode or “ICP” (inductively coupled plasma) coil) is converted from an existing design. do). In one example, the EPM may suggest changes to the design or location of the wafer pedestal. In another example, the EPM may suggest changes to the location or shape of the chamber walls. The general description of CCP reactors and ICP reactors is found in U.S. Patent Application Publication No. 20170363950, filed June 21, 2016, which is incorporated herein by reference in its entirety.

In certain embodiments, the optimized EPM may be integrated into the infrastructure of a semiconductor manufacturing facility that places one or more etcher devices or with an etching device. The optimized EPM may be used to determine appropriate adjustments to the process parameters to provide a desired etch profile or to understand the effect of changes in the process parameters on the etch profile. Thus, for example, a system for processing semiconductor substrates in a manufacturing facility includes an etcher device for etching semiconductor substrates, whose operation is controlled by a set of independent input parameters controlled by a controller implementing an optimized EPM. You may. A controller suitable for controlling the operation of the etcher device typically includes a processor and a memory, the memory stores an optimized EPM, and the processor produces etched feature profiles for a predetermined set of values of the stored set of input process parameters. Use EPM to do it. After calculating the profile, in some embodiments, the controller may adjust the operation of the etcher device by varying one or more values of the set of independent input parameters (in response to the shape of the calculated profile).

In some implementations, a model is used to monitor and process in-situ optical signals in real time to generate geometric etch parameters from in-situ optical information (eg, real-time endpoint or CD monitoring). This in situ monitoring and processing capability may be provided with any of a variety of reactor configurations (eg, CCP reactors and ICP reactors). In certain embodiments, the feature characterization process (eg, endpoint evaluation) completes processing in less than about 100 ms (from the time of receiving input variable values such as optical measurements). In certain embodiments, the feature characterization algorithm completes processing in less than about 20 ms. Such rapid processing may be employed, for example, in applications using critical step change requirements or in high etch rate processes (eg, etch processes that are completed in less than about 1 minute). In processes with many variations induced by a processing regime (e.g. in RF pulsing or gas pulsing) or when the wafer structure itself has a complex structure (e.g. of alternating stacks of materials), each for a plurality of time samples. Data arrays (eg, thousands of) may be required (eg, 100 or more, or 1000 or more). The model's execution time is also dependent on the type of algorithm used. In some implementations, the model processes all or most of the time evolution of the spectral information from the start of the etch process to the current time. This may require, for example, a large number of models generated using multiway principal component analysis (PCA) and multi-directional partial least squares (PLS), each of which is based on the historical trajectories of the corresponding time intervals. Compare the optical measurement trajectories from the start of the etch to the current time step. These models may have elevated productive requirements both during real-time process monitoring and during model calibration as etch times become longer. In such cases, the system may be configured with additional processing capabilities, such as large amounts of buffer space, multithreading, and/or processors with multiple cores.

In certain embodiments, the model uses an optical output signal for only a limited range of wavelengths (or other aspect of the optical signal), which may be selected to determine the geometric parameter of interest. Signals in this range are used as independent variables (or groups of independent variables) for this model. In some such implementations, most of the available optical signals are not used as input. The selected range may represent a small fraction of the total range of values that can be measured by the metrology tool (eg, less than about 10% or even discrete values). Using the selected range as model input, it may require less computation and thus faster computation to determine the geometry of the etched feature. It also allows selected independent variables to be calculated without interfering with the correlated geometric parameters; For example, the etch depth can be calculated without significant interference from input signals that correlate strongly with CD. For example, the first wavelength range may strongly correlate with the etch depth, while a different wavelength range may strongly correlate with the CD, which weakly correlates with the etch depth. The process of focusing on the etch depth uses only optical signals in the first wavelength range, so as not to obscure the signal.

In general, the etched device that may be used with the disclosed optimized EPM may be any kind of semiconductor processing device suitable for etching semiconductor substrates without removing material from their surface. In some embodiments, the etcher device may constitute an ICP reactor; In some embodiments, a CCP reactor may be configured. Accordingly, an etcher apparatus for use with these disclosed optimized EPMs may have a processing chamber, a substrate holder for holding a substrate within the processing chamber, and a plasma generator for generating plasma within the processing chamber. The apparatus further includes one or more valve-controlled process gas inlets for flowing one or more process gases into the processing chamber, one or more gas outlets fluidly connected to one or more vacuum pumps for evacuating gases from the processing chamber, and the like. It can also be included. Further details regarding etching devices (also generally referred to as etch reactors, or plasma etch reactors, etc.).

Initiated output In embodiments About the background

Certain embodiments disclosed herein relate to systems for using and/or generating process simulation models. Certain embodiments herein relate to methods for creating and/or using a process simulation model implemented by such systems. The system for generating the process simulation model may be configured to analyze the data to calibrate or optimize the expressions or relationships used to represent the effects of the semiconductor device manufacturing operation on the substrate. The system for generating the process simulation model may also be configured to receive instructions and data, such as program code, representing physical processes occurring during a semiconductor device manufacturing operation. In this way, a process simulation model is created or programmed on this system. A system programmed to use the process simulation model receives inputs such as (i) process parameters that characterize the semiconductor device manufacturing operation and/or the original design layout or mask to create features on the substrate, and (ii) ) May be configured to execute instructions that determine the effect of the semiconductor device manufacturing operation on the substrate. To this end, the system may calculate a time dependent (or time independent) result of the semiconductor device manufacturing operation.

Many types of computing systems having any of a variety of computer architectures may employ the disclosed systems to implement process simulation models and algorithms for generating and/or optimizing such models. For example, systems may include software components running on one or more general purpose processors or specially designed processors such as programmable logic devices (eg, Field Programmable Gate Arrays (FPGAs)). Further, the systems may be implemented on a single device or may be distributed across multiple devices. The functions of the computational elements may be merged with each other or may be further divided into a plurality of sub-modules.

In some embodiments, the code executed during the generation or execution of a process simulation model in a properly programmed system includes a number of instructions for configuring a computer device (e.g., PC, servers, network equipment, etc.), non-volatile. It can be implemented in the form of software elements that can be stored on a storage medium (eg, optical disk, flash storage device, mobile hard disk, etc.).

At one level, the software element is implemented as a set of instructions prepared by the programmer/developer. However, modular software that can be executed by computer hardware is executable code stored in memory using "machine codes" selected from a particular machine language instruction set or "native instructions" designed within a hardware processor. The machine language instruction set, or native instruction set, is known to and essentially built inside the hardware processor(s). This is the "language" in which system and application software communicate with hardware processors. Each of the native instructions is recognized by the processing architecture and includes operations, addressing, or functions; Specific memory locations or offsets; And discrete code that can be specified in specific registers to control specific addressing modes used to interpret operators. Executed sequentially, or otherwise, more complex operations are built by combining these simple native instructions, as indicated by the control flow instructions.

The interrelationship between executable software instructions and hardware processors is structural. In other words, the instructions themselves are a series of symbols or numerical values. They essentially do not carry any information. It is a processor that is pre-configured to interpret symbols/numeric values by design and conveys meaning to instructions.

Models used herein may be configured to run on a single machine in a single location, on a plurality of machines in a single location, or on a plurality of machines in a plurality of locations. When multiple machines are employed, individual machines may be tailored for specific tasks. For example, large blocks of code and/or operations that require significant processing capacity may be implemented in large and/or fixed machines.

In addition, certain embodiments relate to tangible and/or non-transitory computer-readable media or computer program products containing program instructions and/or data (including data structures) to perform various computer-implemented operations. do. Examples of computer-readable media include, but are not limited to, semiconductor memory devices, phase change devices, magnetic media such as disk drives, magnetic tapes, optical media such as CDs, magneto-optical media, and ROM (read -only memory) devices and hardware devices specifically configured to store and interpret program instructions such as random access memory (RAM). The computer-readable medium may be controlled directly by the end user, or the medium may be controlled indirectly by the end user. Examples of directly controlled media include media located on user equipment and/or media that are not shared with other entities. Examples of indirectly controlled media include media that are indirectly accessible to a user through an external network and/or through a service that provides shared resources such as a “cloud”. Examples of program instructions include both machine code as generated by a compiler, and files containing higher level code that may be executed by a computer using an interpreter.

In various embodiments, data or information employed in the disclosed methods and apparatus is provided in an electronic format. Such data or information may include design layouts, fixed parameter values, plotted parameter values, feature profiles, measurement results, and the like. As used herein, data or other information provided in an electronic format is available for transmission between machines for storage in the machine. Conventional, electronic format data is provided digitally and may be stored in bits and/or bytes in various data structures, lists, databases, etc. The data may be implemented electronically, optically, or the like.

In certain embodiments, the process simulation model may be viewed in the form of application software that interfaces with user and system software, respectively. System software typically interfaces with computer hardware and associated memory. In certain embodiments, the system software includes operating system (OS) software and/or firmware, as well as middleware and drivers installed in the system. The system software provides the basic non-task specific functions of the computer. Conversely, modules and other application software are used to accomplish certain tasks. Each native instruction to the module is stored in a memory device and represented as a numeric value.

An exemplary computer system 800 is shown in FIG. 7. As shown, computer system 800 includes an input/output subsystem 802, which may implement an interface for interacting with human users and/or other computer systems depending on the application. Embodiments of the present invention use an I/O subsystem 802 used to receive input program statements and/or data from a human user (e.g., via a GUI or keyboard) and display them back to the user. Thus, it may be implemented as program code on the system 800. The I/O subsystem 802 may include, for example, a keyboard, mouse, graphical user interface (GUI), a touch screen, or other interfaces for input, and, for example, an LED or other flat screen display, or output. It may include other interfaces for Other elements of the embodiments of the present disclosure, such as order placement engine 208 may be implemented with a computer system such as computer system 800, but perhaps no I/O.

The program code may be stored in a non-transitory medium such as persistent storage 810 or memory 808 or both. By the embodiments of the present specification, in which one or more processors 804 are involved in reading program code from one or more non-transitory media and causing a computer system to generate or use a process simulation model as described herein. Execute the code to achieve the methods performed. Those of skill in the art will understand that the processor may accept source code, such as statements for performing training and/or modeling operations, and interpret or compile the source code into machine code that can be understood at the hardware gate level of the processor. A bus couples I/O subsystem 802, processor 804, peripheral device 806, memory 808, and persistent storage 810.

conclusion

A number of specific details have been mentioned in the art to provide a thorough understanding of the presented embodiments. It will be apparent that the disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that these specific embodiments are not intended to limit the disclosed embodiments.

Claims (70)

A computer-implemented method for optimizing a process simulation model predicting a result of the semiconductor device manufacturing operation from process parameter values characterizing a semiconductor device manufacturing operation, comprising:
(a) receiving current values of one or more plotted process model parameters to be optimized;
(b) generating a process simulation model constructed by providing the process simulation model with the current values of the one or more plotted process model parameters and a set of fixed process model parameter value(s);
(c) using the constructed process simulation model, generating a computer-predicted result of the semiconductor device manufacturing operation;
(d) the computer of the semiconductor device manufacturing operation and measurement results obtained, at least in part, from one or more substrate features generated by performing the semiconductor device manufacturing operation within a reaction chamber operating under the fixed set of process parameter values. Comparing the predicted result with, the comparing generating one or more cost values based on the semiconductor device manufacturing operation and a difference between the computer-predicted result and the measurement result;
(e) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more plotted process model parameters;
(f) performing step (b) using the update of the current values of the one or more plotted process model parameters; And
(g) steps (c) to (f) until the current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters that minimize the cost values. ) A computer-implemented method of optimizing a process simulation model. The method of claim 1,
The computer-implemented method of optimizing a process simulation model, wherein the semiconductor device manufacturing operation is a subtractive process or a material addition process. The method according to claim 1 or 2,
The computer-implemented method of optimizing a process simulation model, wherein the semiconductor device manufacturing operation is an etching process, a planarization process, or a deposition process. The method according to any one of claims 1 to 3,
The set of fixed process model parameter value(s) or the one or more floating process model parameters are one or more temperature values of the reaction chamber, one or more RF conditions of the reaction chamber, one or more process gases of the reaction chamber. , The pressure in the reaction chamber, or a combination thereof, a computer-implemented method of optimizing a process simulation model. The method according to any one of claims 1 to 4,
The one or more plotted process model parameters include a characteristic of the substrate undergoing the semiconductor device manufacturing operation, the characteristic being a reaction rate constant, reactant and/or product adhesion coefficient, reactant diffusion constant, product diffusion constant. , And/or optical dispersion properties, a computer-implemented method of optimizing a process simulation model. The method according to any one of claims 1 to 4,
The one or more plotted process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, ion incident tilt angle, ion incident twist angle, visibility into feature, angular dispersion, sputtering maximum calculated angle (sputter). maximum yield angle), and/or an etch rate per crystal direction. The method according to any one of claims 1 to 6,
The computer-implemented method of optimizing a process simulation model, wherein the one or more plotted process model parameters include a combination of any two or more features of a substrate undergoing the semiconductor device manufacturing operation. The method according to any one of claims 1 to 7,
The step (b) of generating the configured process simulation model further comprises providing the process simulation model profile of the substrate before the substrate undergoes the semiconductor device manufacturing operation, wherein the profile of the substrate is the semiconductor device manufacturing operation. A computer-implemented method of optimizing a process simulation model with one or more features to be modified by operation. The method according to any one of claims 1 to 8,
Prior to the step (c), further comprising the step of providing an initial profile of the substrate undergoing the semiconductor device manufacturing operation, and generating the computer-predicted result of the semiconductor device manufacturing operation in step (c) A computer-implemented method of optimizing a process simulation model using the original profile. The method of claim 9,
The initial profile is computer-generated using information about manufacturing steps that occur prior to the semiconductor device manufacturing operation. A computer-implemented method of optimizing a process simulation model. The method of claim 10,
Wherein the initial profile is determined by performing metrology on one or more original substrate features generated from a manufacturing step that occurs prior to the semiconductor device manufacturing operation. The method according to any one of claims 1 to 11,
The computer-implemented method of optimizing a process simulation model, wherein the result of a semiconductor device manufacturing operation is an etched feature, a deposited feature, or a signal generated by the interaction of a planarized feature with incident electromagnetic radiation. The method according to any one of claims 1 to 12,
Generating a computer predicted result of the semiconductor device manufacturing operation,
(i) using the constructed process simulation model, generating a computed etch profile represented by a series of geometric profile coordinates; And
(ii) generating a calculated reflectance or elliptic spectrum by simulating reflection of electromagnetic radiation from the calculated etching profile from the calculated etching profile generated in step (i). Computer-implemented method of optimizing. The method of claim 13,
Before step (ii), further comprising conditioning the calculated etch profile to smooth out profile partial statistical profile variations. The method of claim 13,
A computer-implemented method of optimizing a process simulation model, wherein generating the calculated reflectance or elliptic spectrum comprises performing a “RCWA” (Rigorous Coupled Wave Analysis) simulation using the calculated etch profile. The method of claim 13,
The step of generating the calculated reflectance or elliptic spectrum comprises performing “FDTD” (Finite Difference Time-Domain) simulation using the calculated etching profile, a computer-implemented method for optimizing a process simulation model . The method of claim 13,
Performing the semiconductor device fabrication operation on a test substrate under the set of process parameter values to produce an etched substrate; And
The computer-implemented method of optimizing a process simulation model, further comprising exposing the etched substrate to incident electromagnetic radiation to generate an empirical reflection spectrum containing the measurement results. The method of claim 13,
A computer-implemented method of optimizing a process simulation model, further comprising generating one or more additional calculated reflectance or elliptic spectra. The method according to any one of claims 1 to 18,
Reflectometry, dome scatterometry, and angle-resolved scatterometry on a substrate containing features created by performing the semiconductor device manufacturing operation in the reaction chamber operating under the set of process parameter values. ), small-angle X-ray scatterometry (small-angle X-ray scatterometry) and / or ellipsometry (ellipsometry) further comprising the step of generating the measurement result, computer-implemented to optimize the process simulation model Way. The method according to any one of claims 1 to 12,
The computer-implemented method of optimizing a process simulation model, wherein the result of the semiconductor device fabrication operation is a profile of an etched feature, a profile of a deposited feature, or a profile of a planarized feature. The method according to any one of claims 1 to 12,
The step of generating the computer-predicted result of the semiconductor device manufacturing operation includes using the constructed process simulation model to generate a calculated etch profile represented by etch profile coordinates. Computer-implemented method. The method of claim 21,
Performing the semiconductor device fabrication operation on a test substrate under the set of process parameter values to produce an etched substrate; And
A computer-implemented method of optimizing a process simulation model, further comprising measuring features of the etched substrate to produce empirical etch profile coordinates containing the metrology result. The method of claim 22,
A computer-implemented method of optimizing a process simulation model, wherein measuring the features of the etched substrate comprises performing microscopy, or optical metrology, of the etched substrate. The method of claim 23,
A computer-implemented method of optimizing a process simulation model, wherein the step of performing microscopy comprises performing transmission electron microscopy (TEM) and/or scanning electron microscopy (SEM). The method according to any one of claims 1 to 12,
A computer-implemented method of optimizing a process simulation model, wherein the result of the semiconductor device fabrication operation is a set of geometric profile parameters that characterize the geometry of an etched feature, or a deposited feature, or a planarized feature. The method of claim 25,
The computer-implemented method of optimizing a process simulation model, wherein the geometrical profile parameters are “OCD” (Optical CD) profile parameters. The method according to any one of claims 1 to 12,
Generating the computer-predicted result of the semiconductor device manufacturing operation,
(i) using the constructed process simulation model, generating a calculated etch profile represented by a series of etch profile coordinates; And
(ii) converting the calculated etch profile generated in step (i) into a first set of geometrical profile parameters characterized by the geometry of the calculated etch profile, optimizing a process simulation model. Computer-implemented method. The method of claim 27,
Performing the semiconductor device fabrication operation on a test substrate under the set of process parameter values to produce an etched substrate;
Measuring features of the etched substrate to produce experimental etch profile coordinates; And
Transforming the empirical etch profile coordinates into a second set of geometrical profile parameters that characterize the geometry of the etched feature of the etched substrate. The method of claim 28,
The one or more cost values are based on the difference between the computer-predicted result using the first set of geometrical profile parameters and the measurement result using the second set of geometrical profile parameters. Computer-implemented method. The method according to any one of claims 1 to 29,
The computer-predicted result generated in step (c) is calculated from the constructed process simulation model and geometrical profiles or profiles of substrate features corresponding to a sequence of times representing different durations of the substrate subtraction process or the substrate addition process. Contains a sequence of parameters; And
The measurement result of step (d) comprises a sequence of profile parameters or geometric profiles of the substrate feature obtained from experimental measurements of a substrate at different durations of the substrate subtraction process or the substrate addition process. Computer-implemented method of optimizing process simulation models. The method according to any one of claims 1 to 30,
(i) constructing the process simulation model with final values of the one or more plotted process model parameters from step (g); And
(ii) determining a pattern of the lithographic mask, and
Optimizing the process simulation model, further comprising using the process simulation model consisting of final values of the one or more plotted process model parameters from the step (g) to enable generating the lithographic mask. Computer-implemented method. The method of claim 31,
A computer-implemented method of optimizing a process simulation model, wherein generating the lithographic mask comprises transferring the pattern of the resist layer. The method of claim 32,
A computer-implemented method of optimizing a process simulation model, further comprising developing the resist layer and transferring the pattern to an underlying chromium layer. The method according to any one of claims 1 to 30,
(i) constructing the process simulation model with final values of the one or more plotted process model parameters from step (g);
(ii) identifying the design of the semiconductor processing device, and
Using the process simulation model consisting of final values of the one or more plotted process model parameters from step (g) to enable manufacturing the semiconductor processing device by using the design of the semiconductor processing device. Further comprising a computer-implemented method of optimizing a process simulation model. The method according to any one of claims 1 to 30,
(i) constructing the process simulation model with final values of the one or more plotted process model parameters from step (g);
(ii) final values of the one or more plotted process model parameters from step (g) to identify the operating conditions of a semiconductor processing apparatus to enable manufacturing of semiconductor devices by operating the semiconductor processing apparatus under operating conditions. A computer-implemented method of optimizing a process simulation model, further comprising the step of using the constructed process simulation model. The method according to any one of claims 1 to 35,
Repeating steps (c) to (f) until the current values of the one or more plotted process model parameters converge to identify a substantially local or global minimum in the obtained one or more cost values. A computer-implemented method of optimizing a process simulation model, comprising the step of: The method according to any one of claims 1 to 36,
Generating the computer-predicted result comprises using the constructed process simulation model to calculate local reaction rates in a grid of points representing a feature profile on a semiconductor substrate. Computer-implemented method of optimizing. The method of claim 37,
A computer-implemented method of optimizing a process simulation model, wherein using the constructed process simulation model to calculate local reaction rates calculates reaction rates as a function of time. The method according to any one of claims 1 to 38,
Optimizing the process simulation model, further comprising obtaining the measurement results by performing in situ measurements in the reaction chamber, non-destructive standalone measurements outside the reaction chamber, and/or standalone destructive measurements outside the reaction chamber. Computer-implemented method. Computer program comprising a non-transitory computer-readable medium provided with instructions for causing a calculation system to execute an optimized process simulation model that calculates a result of a semiconductor device manufacturing operation from process parameter values characterizing the semiconductor device manufacturing operation. In the product,
The above instructions,
(a) instructions for receiving process parameter values as inputs to the optimized process simulation model;
(b) an instruction for executing the optimized process simulation model using the process parameter values,
(i) receive current values of one or more plotted process model parameters to be optimized,
(ii) generating a process simulation model constructed by providing the current values of the one or more plotted process model parameters and a set of fixed process model parameter value(s) to the process simulation model,
(iii) using the constructed process simulation model to generate a computer predicted result of the semiconductor device manufacturing operation,
(iv) obtaining the computer-predicted result of the semiconductor device manufacturing operation, at least in part, from one or more substrate features generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Comparing the result of the measured measurement and generating one or more cost values based on the difference between the measurement result and the computer-predicted result of the semiconductor device manufacturing operation,
(v) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more plotted process model parameters,
(vi) performing the operation (ii) using the update of the current values of the one or more plotted process model parameters, and
(vii) steps (iii) through (vi) until the current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters that minimize the cost values. ) By iterating, the optimized process simulation model is optimized; instructions for executing the optimized process simulation model; And
(c) a computer program product comprising instructions for outputting a calculated result of the semiconductor device manufacturing operation. The method of claim 40,
Before the instruction (b), further comprising instructions for receiving an initial profile of a substrate undergoing the semiconductor device manufacturing operation. The method of claim 40 or 41,
The one or more plotted process model parameters include vertical etch rate, lateral etch rate, nominal etch depth, etch selectivity, ion incidence tilt angle, ion incidence twist angle, visibility into feature, angular dispersion, sputtering maximum calculated angle, and And/or an etch rate per crystal direction. The method according to any one of claims 40 to 42,
Instruction (ii) for generating the configured process simulation model further comprises providing the process simulation model profile of the substrate before the substrate undergoes the semiconductor device manufacturing operation, the profile of the substrate being the semiconductor device A computer program product having one or more features to be modified by a manufacturing operation. The method according to any one of claims 40 to 43,
The result of a semiconductor device manufacturing operation is a signal generated by the interaction of an etched feature, a deposited feature, or a planarized feature with incident electromagnetic radiation. The method according to any one of claims 40 to 44,
The operation of generating the computer-predicted result of the semiconductor device manufacturing operation,
Generating, using the constructed process simulation model, a calculated etch profile represented by a series of geometric profile coordinates; And
And generating a calculated reflectance or elliptic spectrum from the calculated etching profile by simulating reflection of electromagnetic radiation from the calculated etching profile. The method of claim 45,
The optimized process simulation model additionally,
Performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values to produce an etched substrate, and
A computer program product, optimized by exposing the etched substrate to incident electromagnetic radiation to produce an experimental reflection spectrum containing the measurement result. The method of claim 40,
The optimized process simulation model may additionally include reflectometry, dome scattering, angle-resolved on a substrate containing features created by performing the semiconductor device manufacturing operation in the reaction chamber operating under the set of process parameter values. A computer program product, which is optimized by generating the measurement result by performing scatterometry, small angle X-ray scatterometry and/or elliptic polarization. The method of claim 40,
The operation of generating the computer-predicted result of the semiconductor device manufacturing operation includes using the constructed process simulation model to generate the calculated etch profile represented by etch profile coordinates. The method of claim 48,
The optimized process simulation model additionally,
Performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values to produce an etched substrate, and
A computer program product that is optimized by measuring features of the etched substrate to produce experimental etch profile coordinates that contain the metrology result. The method of claim 40,
The result of the semiconductor device fabrication operation is a set of geometric profile parameters that characterize the geometry of an etched feature, a deposited feature, or a planarized feature. The method of claim 50,
The geometrical profile parameters are “OCD” (Optical CD) profile parameters. The method of claim 40,
The operation of generating the computer-predicted result of the semiconductor device manufacturing operation,
Generating, using the constructed process simulation model, a calculated etch profile represented by a series of etch profile coordinates; And
Converting the calculated etch profile into a first set of geometrical profile parameters characterized by a geometry of the calculated etch profile. The method of claim 52,
The optimized process simulation model additionally,
Performing the semiconductor device manufacturing operation on a test substrate under the set of process parameter values to produce an etched substrate,
Measuring features of the etched substrate to produce experimental etch profile coordinates; And
Computer program product, optimized by transforming the experimental etch profile coordinates into a second set of geometrical profile parameters that characterize the geometry of the etched feature of the etched substrate. The method according to any one of claims 40 to 53,
The computer program product further comprising instructions for using the calculated result to determine a pattern of a lithographic mask. The method according to any one of claims 40 to 53,
The computer program product further comprising instructions for using the calculated result to identify a design of a semiconductor processing device. The method according to any one of claims 40 to 53,
The computer program product further comprising instructions for using the calculated result to identify the operating conditions of the semiconductor processing apparatus to enable manufacturing of semiconductor devices by operating the semiconductor processing apparatus under operating conditions. 55. A system comprising a lithographic mask generation apparatus configured to determine a lithographic mask pattern using the computer program product according to any one of claims 40 to 54 and the calculated result of the semiconductor device manufacturing operation. 54. A system comprising a semiconductor processing apparatus configured to operate under process conditions provided in the calculated result of the computer program product and the semiconductor device manufacturing operation according to any one of claims 40 to 53. A computer-implemented method for optimizing a process simulation model for predicting a result of the semiconductor device manufacturing operation from process parameter values characterizing a semiconductor device manufacturing operation, comprising:
(a) receiving current values of one or more plotted process model parameters to be optimized;
(b) generating a process simulation model constructed by providing the process simulation model with the current values of the one or more plotted process model parameters and a set of fixed process model parameter value(s);
(c) using the constructed process simulation model, generating a computer-predicted result of the semiconductor device manufacturing operation;
(d) obtaining the computer-predicted result of the semiconductor device manufacturing operation, at least in part, from one or more substrate features generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Comparing the resulted top down measurement, the method comprising: generating one or more cost values based on a difference between the computer-predicted result of the semiconductor device manufacturing operation and the top down measurement result;
(e) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more plotted process model parameters;
(f) performing step (b) using the update of the current values of the one or more plotted process model parameters; And
(g) steps (c) to (f) until the current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters that minimize the cost values. ) A computer-implemented method of optimizing a process simulation model. The method of claim 59,
The top-down metrology result comprises, at least in part, one or more CD-SEM images of the one or more substrate features generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Computer-implemented method of optimizing process simulation models. The method of claim 59 or 60,
The step (d) generates at least in part the computer-predicted result of the semiconductor device manufacturing operation, generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Further comprising comparing the obtained profile-based metrology result from the substrate features, and
The one or more cost values comprising at least one cost function based on a difference between the profile-based measurement result and the computer predicted result of the semiconductor device manufacturing operation. Way. The method of claim 61,
The computer-implemented method of optimizing a process simulation model, wherein the profile-based metrology results are obtained by a CD-SAXS metrology process. The method of claim 61,
The computer-implemented method of optimizing a process simulation model, wherein the profile-based metrology results are obtained by a TEM metrology process. The method of claim 61,
The computer-implemented method of optimizing a process simulation model, wherein the profile-based metrology results are obtained by an OCD metrology process. Computer program comprising a non-transitory computer-readable medium provided with instructions for causing a calculation system to execute an optimized process simulation model that calculates a result of a semiconductor device manufacturing operation from process parameter values characterizing the semiconductor device manufacturing operation. In the product,
The above instructions,
(a) instructions for receiving process parameter values as inputs to the optimized process simulation model;
(b) an instruction for executing the optimized process simulation model using the process parameter values,
(i) receive current values of one or more plotted process model parameters to be optimized,
(ii) generating a process simulation model constructed by providing the current values of the one or more plotted process model parameters and a set of fixed process model parameter value(s) to the process simulation model,
(iii) using the constructed process simulation model to generate a computer predicted result of the semiconductor device manufacturing operation,
(iv) obtaining the computer-predicted result of the semiconductor device manufacturing operation, at least in part, from one or more substrate features generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Comparing the result of the top-down measurement with the result of the semiconductor device manufacturing operation and generating one or more cost values based on the difference between the result of the top-down measurement and the computer-predicted result of the semiconductor device manufacturing operation,
(v) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more plotted process model parameters,
(vi) performing the operation (ii) using the update of the current values of the one or more plotted process model parameters, and
(vii) steps (iii) through (vi) until the current values of the one or more plotted process model parameters converge to produce final values of the one or more plotted process model parameters that minimize the cost values. ) By iterating, the optimized process simulation model is optimized; instructions for executing the optimized process simulation model; And
(c) a computer program product comprising instructions for outputting a calculated result of the semiconductor device manufacturing operation. The method of claim 65,
The top-down metrology result comprises, at least in part, one or more CD-SEM images of the one or more substrate features generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Computer program product. The method of claim 65 or 66,
The operation (iv) comprises at least in part the computer-predicted result of the semiconductor device manufacturing operation, the at least one substrate generated by performing the semiconductor device manufacturing operation in a reaction chamber operating under the fixed set of process parameter values. Further comprising an operation of comparing the measurement result obtained from the feature, and
The one or more cost values comprising at least one cost function based on a difference between the profile-based measurement result and the computer predicted result of the semiconductor device manufacturing operation. The method of claim 67,
The profile-based measurement result is obtained by a CD-SAXS metrology process. The method of claim 67,
The profile-based metrology results are obtained by a TEM metrology process. The method of claim 67,
The profile-based measurement result is obtained by an OCD measurement process.

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