KR20200137248A - Photomultiplier and method of fabricating the same - Google Patents

Abstract

According to one aspect of the present invention, a photomultiplier capable of suppressing the occurrence of a dark count rate (DCR) due to process induced defects (PIDs) comprises: a substrate; a first well layer of a first conductivity type formed on the substrate and including at least one first epitaxial layer; a second well layer of a second conductivity type including a first electrode connected to the first well layer and at least one second epitaxial layer formed on the first well layer; a quenching resistor connected to the second well layer; and a second electrode connected to the second well layer through the quenching resistor.

Description

Photomultiplier and method of fabricating the same}

The present invention relates to a semiconductor device, and more particularly, to a photomultiplier (PM) and a method of manufacturing the same.

In general, a photomultiplier (PM) is a photodector that absorbs photons and generates a current pulse. For example, a photomultiplier element is an optical sensor used for a gamma ray detector, and uses the effect of generating a number of secondary electrons through reaction with surrounding materials in the process of moving electrons generated by visible light incident from the scintillator. Thus, it can be used as a device that amplifies photocurrent.

Silicon photomultiplier (SiPM) is one of the low-illuminance light detection sensors and can replace the existing vacuum tube-based light multiplier. The silicon photomultiplier device has the same amplification factor as the existing photomultiplier, but has advantages such as low price, low operating voltage, and miniaturization, and is not sensitive to magnetic fields, so it can be applied in various ways.

However, since the incident optical signal is extremely weak in the silicon photomultiplier device, the influence of noise is very high. Accordingly, in a dark state in which photons are not incident, a dark count rate (DCR), which is a rate of occurrence of an event due to unwanted noise, is one of important performance indicators in a silicon photomultiplier.

One of the important causes of DCR occurrence is a phenomenon caused by a process induced defect (PID). During the manufacturing process, as electrons trapped in the unwanted PID defect level are moved from the valence band to the conduction band by heat and electric fields, DCR may occur. For this reason, the amount of PID defects has a significant impact on device performance. Defects made once are not easily removed even if additional processing is performed, so it is the most effective method to reduce the DCR by reducing the occurrence of PID in advance.

1. Korean Patent Application Publication No. 10-2016-0060795 (Publication date: May 31, 2016)

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a photomultiplier device capable of suppressing the occurrence of DCR due to a PID defect and a method of manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A photomultiplier device according to an aspect of the present invention includes a substrate, a first well layer of a first conductivity type formed on the substrate and including at least one first epi layer, a first electrode connected to the first well layer, and , A second well layer of a second conductivity type formed on the first well layer and including at least one second epi layer, a quenching resistor connected to the second well layer through the quenching resistor, and the? And a second electrode connected to the quenching resistor.

In the photomultiplier device, the first well layer and the second well layer are formed using an epitaxial deposition process without using an ion implantation process, and the first well layer and the second well layer do not use a plasma process. It may be formed in a mesa structure on the substrate by using wet etching.

In the photomultiplier device, the first electrode, the quenching resistor, and the second electrode may be patterned using wet etching without using plasma.

In the photomultiplier device, the first electrode may be formed to be jointly connected to the first well layer and the substrate.

In the photomultiplier device, the quenching resistor may be formed to extend from the second well layer onto the substrate, and the second electrode may be formed on a portion of the quenching resistor extending onto the substrate. have.

In the photomultiplier device, the first conductivity type is N-type, the second conductivity type is P-type, the substrate is a P-type substrate, and the first well layer includes an N+ epi layer on the substrate, and the An N- epi layer on the N+ epi layer, and a No epi layer on the N- epi layer; and the second well layer may include a P+ epi layer on the No epi layer.

In the photomultiplication device, the impurity doping concentration of the N+ epi layer may be greater than the impurity doping concentration of the No epi layer, and the impurity doping concentration of the No epi layer may be greater than the impurity doping concentration of the N- epi layer.

In the photomultiplier device, the first conductivity type is P-type, the second conductivity type is N-type, the substrate is an N-type substrate, and the first well layer includes a P+ epi layer on the substrate, and the A P- epi layer on the P+ epi layer and a Po epi layer on the P- epi layer may be included, and the second well layer may include an N+ epi layer on the Po epi layer.

In the photomultiplier device, an impurity doping concentration of the P+ epi layer may be greater than an impurity doping concentration of the Po epi layer, and an impurity doping concentration of the Po epi layer may be greater than an impurity doping concentration of the P- epi layer.

In the photomultiplier device, the substrate may include silicon (Si) or germanium (Ge).

A method of manufacturing a photomultiplier device according to another aspect of the present invention includes forming a first well layer of a first conductivity type including at least one first epi layer on a substrate, and at least one on the first well layer. Forming a second well layer of a second conductivity type including a second epi layer, forming a quenching resistor connected to the second well layer, a first electrode connected to the first well layer, and the ?? It may include forming a second electrode connected to the second well layer through a ching resistance.

In the manufacturing method of the photomultiplier device, in the forming of the first well layer and the forming of the second well layer, the first well layer and the second well layer are formed in a mesa structure on the substrate, and the The first well layer and the second well layer may be formed by using an epitaxial deposition process without using an ion implantation process.

In the method of manufacturing the photomultiplier device, the forming of the first electrode, the forming of the quenching resistance, and the forming of the second electrode may include patterning using wet etching without using plasma. The process can be carried out.

According to an embodiment of the present invention made as described above, it is possible to implement a silicon photomultiplier device capable of reducing PID defects and suppressing DCR generation and a manufacturing method thereof by not using an ion implantation process and a plasma treatment process. Of course, the scope of the present invention is not limited by these effects.

1 is a schematic cross-sectional view of a photomultiplier device according to an embodiment of the present invention.
2 is a schematic cross-sectional view of a photomultiplier device according to another embodiment of the present invention.
3 is a schematic cross-sectional view of a photomultiplier device according to another embodiment of the present invention.
4 is a schematic cross-sectional view of a photomultiplier device according to another embodiment of the present invention.
5 is a flow chart showing a manufacturing process of a photomultiplier device according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the following embodiments make the disclosure of the present invention complete, and the scope of the invention to those of ordinary skill in the art. It is provided to fully inform you. In addition, in the drawings for convenience of description, the size of the components may be exaggerated or reduced.

1 is a schematic cross-sectional view of a photomultiplier device 100 according to an embodiment of the present invention.

Referring to FIG. 1, the photomultiplier device 100 includes a substrate 105, a first well layer 110 of a first conductivity type, a second well layer 120 of a second conductivity type, and a quenching resistor 130, It may include a first electrode 140 and a second electrode 145.

The substrate 105 may include a semiconductor material. For example, the substrate 105 may include a single crystal semiconductor wafer, for example silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In this embodiment, the substrate 105 may function as a single crystal underlying layer for epitaxially depositing the first well layer 110 thereon, rather than being used as an active layer.

The first well layer 110 is formed on the substrate 105 and may include at least one first epitaxial layer. The second well layer 120 is formed on the first well layer 110 and may include at least one second epitaxial layer. Here, the epitaxial layer refers to a layer forming an epitaxy with the substrate 105, and may also be referred to as an epitaxial layer.

The first well layer 110 may have a first conductivity type, and the second well layer 120 may have a second conductivity type. The first conductivity type and the second conductivity type may be of opposite conductivity types. For example, when the first conductivity type is N-type, the second conductivity type is P-type. Conversely, when the first conductivity type is P-type, the second conductivity type may be N-type. Accordingly, the stacked structure of the first well layer 110 and the second well layer 120 may form a P-N junction diode structure. For example, impurities for N-type doping include phosphorus (P), arsenic (As) or antimony (Sb), and impurities for P-type doping include boron (B), aluminum (Al), and gallium (Ga). Or it may contain indium (In).

The first well layer 110 and the second well layer 120 include a semiconductor material, and may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

In this embodiment, the diode junction structure of the first well layer 110 and the second well layer 120 is an Avalanche photodiode operating in a Geiger mode, that is, a Geiger mode Avalanche photodiode. A diode (GAPD) can be configured.

A quenching resistor 130 may be connected to the second well layer 120. Quenching resistance 130 may be provided to control the avalanche breakdown of GAPD.

The first electrode 140 may be connected to the first well layer 110, and the second electrode 145 may be connected to the second well layer 120 through a quenching resistor 130. For example, the first electrode 140 may be referred to as an anode electrode, and the second electrode 145 may be referred to as a cathode electrode. In this case, the first well layer 110 may be referred to as an anode well and the second well layer 120 may be referred to as a cathode well.

In this embodiment, optionally, the first electrode 140 may be formed to be commonly connected on the first well layer 110 and the substrate 105.

In addition, the quenching resistor 130 is formed to extend from the second well layer 120 to the substrate 105, and the second electrode 145 extends on the substrate 105 of the quenching resistor 130 It can be formed on the part. In this case, one end of the quenching resistor 130 is connected to the second well layer 120 and extends along the sidewalls of the first well layer 110 and the second well layer 120 so that the other end thereof is the substrate 105 It can be formed to be located on the top.

The insulating layer 125 may be interposed between the quenching resistor 130 and the first well layer 110 and between the quenching resistor 130 and the second well layer 120. Further, the insulating layer 125 insulates between any two of the first well layer 110, the second well layer 120, the quenching resistor 130, the first electrode 140, and the second electrode 145. Can be formed appropriately for this purpose.

For example, the substrate 105, the first well layer 110, and the second well layer 120 may be formed of silicon, and in this case, the photomultiplier device 100 is a silicon photomultiplier (SIPM). Can be called.

The photomultiplier device 100 according to this embodiment may include a structure in which a plurality of GAPDs are connected in parallel. During the operation of the photomultiplier device 100, a voltage slightly higher than a breakdown voltage is applied to each GAPD, and each GAPD causes an avalanche breakdown by a charge generated by a photon to generate a current. Thereafter, the current is extinguished by the quenching resistor 130 and the breakdown phenomenon is stopped.

The inventors of the present invention point that PID, which is one of the main causes of DCR generation, is used in an ion implantation process using high-energy ions and a dry etching process using plasma. Focusing on, in the manufacture of the photomultiplier device 100 according to this embodiment, the ion implantation process and the plasma dry etching process were excluded as much as possible.

For example, the first well layer 110 and the second well layer 120 may not be formed using an ion implantation process, but may be formed using an epitaxial deposition process. That is, the first well layer 110 is formed as an epitaxial layer on the substrate 105 and is doped with a first conductivity type, and the second well layer 120 is formed as an epitaxial layer on the first well layer 110. It can be doped with a conductivity type.

Further, the first well layer 110 and the second well layer 120 may be formed in a mesa structure on the substrate 105 by using wet etching without using a plasma process. For example, after forming the first well layer 110 and the second well layer 120 as a blanket on the substrate 105 by epitaxial deposition, a photoresist pattern is formed on the stacked structure using photolithography. Then, the photoresist pattern may be used as an etch protective layer to form a mesa structure by wet etching using an etchant.

Furthermore, the first electrode 140, the quenching resistor 130, and the second electrode 145 may also be formed without using a plasma process. For example, even when etching the first electrode 140, the quenching resistor 130, and the second electrode 145, a patterning process may be performed using wet etching. Meanwhile, even when the quenching resistor 130 is formed, the quenching resistor 130 may be connected to the second well layer 120 without a via plug.

As described above, in the manufacture of the photomultiplier device 100, the generation of PID can be minimized by minimizing or almost eliminating the ion implantation process and the plasma dry etching process. Accordingly, the generation of DCR of the photomultiplier device 100 can be greatly reduced.

2 is a schematic cross-sectional view of a photomultiplier device 100a according to another embodiment of the present invention. The photomultiplier device 100a of FIG. 2 is a modified version of the photomultiplier device 100 of FIG. 1, and therefore, a duplicate description in the two embodiments is omitted.

2, in the photomultiplier device 100a, the quenching resistor 130a does not go down from the second well layer 120 to the sidewalls of the second well layer 120 and the first well layer 110, It may be formed on the 2 well layer 120.

For example, the insulating layer 125a may be formed higher than the second well layer 120, and the quenching resistor 130a may extend from the second well layer 120 to the insulating layer 125a. The second electrode 145a may be connected to the quenching resistor 130a on the quenching resistor 130a.

In a modified example of this embodiment, the height of the insulating layer 125a may be variously modified, and in this case, the height of the quenching resistor 130a and the second electrode 145a may be variously modified.

3 is a schematic cross-sectional view of a photomultiplier device 100b according to another embodiment of the present invention. The photomultiplier device 100b of FIG. 3 is a modified version of the photomultiplier device 100 of FIG. 1, and therefore, a duplicate description in the two embodiments is omitted.

Referring to FIG. 3, a first well layer 110b may be doped with an N type, a second well layer 120b may be doped with a P type, and a substrate 105b may be doped with a P type.

For example, the first well layer 110b is an N+ epitaxial layer 112b on the substrate 105b, an N- epitaxial layer 114b on the N+ epitaxial layer 112b, and a No epitaxial layer 114b on the N- epitaxial layer 114b. 116b). The second well layer 120b may include the P+ epitaxial layer 122b on the No epi layer 116b.

In this embodiment, the impurity doping concentration of the N+ epi layer 112b is greater than the impurity doping concentration of the No epi layer 116b, and the impurity doping concentration of the No epi layer 116b is the impurity doping concentration of the N- epi layer 114b. May be greater than the concentration. In this way, the applied bias voltage level can be lowered by increasing the doping concentration of the No epi layer 116b in contact with the P+ epi layer 122b than the N− epi layer 114b.

For example, the impurity doping concentration of the N+ epi layer 112b is about 10 ²⁰ atoms/cm ³ level, the impurity doping concentration of the No epi layer 116b is about 10 ¹⁷ atoms/cm ³ level, and the N- epi layer The impurity doping concentration of 114b may be at a level of about 10 ¹⁵ atoms/cm ³ .

4 is a schematic cross-sectional view of a photomultiplier device 100c according to another embodiment of the present invention. The photomultiplier device 100c of FIG. 4 is partially modified from the photomultiplier device 100 of FIG. 1, and therefore, a duplicate description in the two embodiments is omitted.

Referring to FIG. 4, a first well layer 110c may be doped with a P type, a second well layer 120c may be doped with an N type, and a substrate 105c may be doped with an N type.

For example, the first well layer 110c is a P+ epitaxial layer 112c on the substrate 105c, a P- epitaxial layer 114c on the P+ epitaxial layer 112c, and a Po epitaxial layer 114c on the P- epitaxial layer 114c. 116c) may be included. The second well layer 120c may include an N+ epitaxial layer 122c on the Po epitaxial layer 116c.

In this embodiment, the impurity doping concentration of the P+ epitaxial layer 112c is greater than the impurity doping concentration of the Po epitaxial layer 116c, and the impurity doping concentration of the Po epitaxial layer 116c is impurity doping of the P- epitaxial layer 114c. May be greater than the concentration. As such, the applied bias voltage level can be lowered by increasing the doping concentration of the Po epi layer 116c in contact with the N+ epi layer 122c than the P- epi layer 114c.

For example, the impurity doping concentration of the P+ epitaxial layer 112c is about 10 ²⁰ atoms/cm ³ level, the impurity doping concentration of the Po epi layer 116c is about 10 ¹⁷ atoms/cm ³ level, and the P- epitaxial layer The impurity doping concentration of 114c may be at the level of about 10 ¹⁵ atoms/cm ³ .

5 is a flow chart showing a manufacturing process of the photomultiplier device 100 according to an embodiment of the present invention.

Referring to FIGS. 1 and 5 together, a first well layer 110 of a first conductivity type including at least one first epi layer may be formed on the substrate 105 (S10 ). The first well layer 110 may be formed on the substrate 105 in a mesa structure.

For example, as shown in FIG. 3, an N+ epitaxial layer 112b is formed on the substrate 105b, an N- epitaxial layer 114b is formed on the N+ epitaxial layer 112b, and N- epitaxial The first well layer 110b may be formed by forming a No epi layer 116b on the layer 114b. As another example, as shown in FIG. 4, a P+ epitaxial layer 112c is formed on the substrate 105c, a P- epitaxial layer 114c is formed on the P+ epitaxial layer 112c, and the P- epitaxial layer The Po epitaxial layer 116c may be formed on the 114c to form the first well layer 110c.

The first well layers 110, 110b, and 110c may be formed by simultaneously performing doping and deposition using an epitaxial deposition process without using an ion implantation process.

Subsequently, a second well layer 120 of a second conductivity type including at least one second epi layer may be formed on the first well layer 110 (S20 ). The second well layer 120 may be formed on the substrate 105 in a mesa structure.

For example, as shown in FIG. 3, a P+ epitaxial layer 122b is formed on the No epitaxial layer 116b to form a second well layer 120b, or a Po epitaxial layer ( The second well layer 120c may be formed by forming the N+ epitaxial layer 122c on 116c).

The second well layers 120, 120b, and 120c may be formed by simultaneously performing doping and deposition using an epitaxial deposition process without using an ion implantation process.

Subsequently, a quenching resistor 130 connected to the second well layer 120 may be formed (S30). For example, the quenching resistor 130 may be formed by forming a predetermined resistance layer and then patterning it by wet etching without using plasma.

Subsequently, the first electrode 140 connected to the first well layer 110 and the second electrode 145 connected to the second well layer 120 through the quenching resistor 130 may be formed (S40). For example, the first electrode 140 and the second electrode 145 may be formed by forming a conductive layer and then patterning the conductive layer by wet etching without using plasma.

As described above, in the manufacture of the photomultiplier devices 100, 100a, 100b, and 100c, the generation of PID can be minimized by minimizing or almost eliminating the ion implantation process and the plasma dry etching process. Accordingly, the generation of DCR of the photomultiplier devices 100, 100a, 100b, and 100c can be greatly reduced.

The photomultiplier devices (100, 100a, 100b, 100c) of the present invention are conventional in the field of medical imaging equipment, nuclear power and accelerator particle detection, aerospace field, optical and biofluorescence analysis field, military field such as night vision, measurement field, etc. It is expected that technology replacement and market expansion will be possible in all fields using photomultiplier devices.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those of ordinary skill in the art will appreciate that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: photomultiplier element
105: substrate
110: first well layer
120: second well layer
130: Qing resistance
140: first electrode
150: second electrode

Claims (13)

Board;
A first well layer of a first conductivity type formed on the substrate and including at least one first epi layer;
A first electrode connected to the first well layer;
A second well layer of a second conductivity type formed on the first well layer and including at least one second epi layer;
A quenching resistor connected to the second well layer; And
Including; a second electrode connected to the second well layer through the quenching resistor
Photomultiplier. The method of claim 1,
The first well layer and the second well layer are formed using an epitaxial deposition process without using an ion implantation process,
The first well layer and the second well layer are formed in a mesa structure on the substrate by wet etching without using plasma,
Photomultiplier. The method of claim 2,
The first electrode, the quenching resistor, and the second electrode are patterned using wet etching without using a plasma process,
Photomultiplier. The method of claim 1,
The first electrode is formed to be jointly connected to the first well layer and the substrate,
Photomultiplier. The method of claim 1,
The quenching resistor is formed to extend from the second well layer onto the substrate,
The second electrode is formed on a portion of the quenching resistance extending onto the substrate,
Photomultiplier. The method of claim 1,
The first conductivity type is N-type, the second conductivity type is P-type, and the substrate is a P-type substrate,
The first well layer,
An N+ epitaxial layer on the substrate;
An N- epi layer on the N+ epi layer;
Including; No epi layer on the N- epi layer,
The second well layer comprises a P+ epi layer on the No epi layer,
Photomultiplier. The method of claim 6,
The impurity doping concentration of the N+ epi layer is greater than the impurity doping concentration of the No epi layer,
The impurity doping concentration of the No epi layer is greater than the impurity doping concentration of the N- epi layer,
Photomultiplier. The method of claim 1,
The first conductivity type is a P type, the second conductivity type is an N type, the substrate is an N type substrate,
The first well layer,
A P+ epitaxial layer on the substrate;
A P- epi layer on the P+ epi layer;
Including; Po epi layer on the P- epi layer,
The second well layer comprises an N+ epi layer on the Po epi layer,
Photomultiplier. The method of claim 8,
The impurity doping concentration of the P+ epi layer is greater than the impurity doping concentration of the Po epi layer,
The impurity doping concentration of the Po epi layer is greater than the impurity doping concentration of the P- epi layer,
Photomultiplier. The method of claim 1,
The substrate includes silicon (Si) or germanium (Ge),
Photomultiplier. Forming a first well layer of a first conductivity type including at least one first epitaxial layer on a substrate;
Forming a second well layer of a second conductivity type including at least one second epi layer on the first well layer;
Forming a quenching resistor connected to the second well layer; And
Including; a first electrode connected to the first well layer and a second electrode connected to the second well layer through the quenching resistor;
Manufacturing method of photomultiplier device The method of claim 11,
In the step of forming the first well layer and the step of forming the second well layer,
The first well layer and the second well layer are formed in a mesa structure on the substrate,
The first well layer and the second well layer are formed using an epitaxial deposition process without using an ion implantation process,
Manufacturing method of photomultiplier device The method of claim 12,
The forming of the first electrode, the forming of the quenching resistance, and the forming of the second electrode may include performing a patterning process using wet etching without using plasma,
Method of manufacturing a photomultiplier device.

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