KR20200136339A - Low density parity check encoder with 16200 length and 5/15 rate, and method using the same - Google Patents

Abstract

Disclosed are an LDPC encoder and decoder, and an LDPC encoding method are disclosed. The objective of present invention is to provide a new low density parity check (LDPC) codeword with a length of 16200 and a code rate of 5/15 that can be used universally. According to an embodiment of the present invention, the LDPC encoder comprises: a first memory for storing an LDPC codeword having a length of 16200 and a code rate of 5/15; a second memory initialized to zero; and a processor for generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix.

Description

LDPC encoder with a length of 16200 and a code rate of 5/15 and an LDPC encoding method using it {LOW DENSITY PARITY CHECK ENCODER WITH 16200 LENGTH AND 5/15 RATE, AND METHOD USING THE SAME}

The present invention relates to a LDPC (Low Density Parity Check) code for correcting an error occurring in a radio channel, and in particular, to an LDPC code applicable to a digital broadcasting system.

Since current terrestrial TV broadcasting generates co-channel interference, which is three times the service change, the same frequency cannot be reused in an area within three times the service radius. As such, a region in which the same frequency cannot be reused is called a white space, and the spectral efficiency is very low due to the occurrence of the white space.

Therefore, the necessity of developing a transmission technology that is easy to remove a white space and reuse frequency focusing on reception robustness has emerged in order to improve spectrum efficiency.

Accordingly, in September 2012 IEEE Transactions on Broadcasting, vol. In the academic document "Cloud Transmission: A New Spectrum-Reuse Friendly Digital Terrestrial Broadcasting Transmission System" published through 58, no.3, it is easy to reuse, does not generate white space, and is a terrestrial cloud that is easy to build and operate a single frequency network. Broadcast technology was proposed.

Using such terrestrial cloud broadcasting technology, broadcasters can transmit broadcast content that is the same nationwide or different for each region through one broadcast channel. However, for this, the receiver must be able to receive one or more terrestrial cloud broadcast signals in an area where signals transmitted from different transmitters overlap in a single frequency network, that is, in an overlapping area, and can distinguish and demodulate the received terrestrial cloud broadcast signals. Should be. That is, in a situation where co-channel interference exists and timing and frequency synchronization of each transmission signal is not guaranteed, the receiver must be able to demodulate one or more cloud broadcast signals.

On the other hand, "LDPC Code for Terrestrial Cloud Broadcasting" in Korean Patent Application Laid-Open No. 2013-0135746 discloses an LDPC code that is optimized for terrestrial cloud broadcasting and exhibits excellent performance at a low code rate (<0.5).

However, Korean Patent Application Laid-Open No. 2013-0135746 relates to a code length that is completely different from the LDPC code length used in the DVB broadcasting standard, and is silent about a specific LDPC code method.

An object of the present invention is to provide a new LDPC codeword with a codeword length of 16200 and a code rate of 5/15 that can be used universally.

In addition, an object of the present invention is to efficiently encode LDPC using a sequence having a number of rows corresponding to a value obtained by dividing the sum of the length of the systematic part of the LDPC codeword 5400 and the length of the first parity part 720 by 360. To provide an LDPC coding technique capable of performing

The LDPC encoder according to the present invention for achieving the above object includes: a first memory for storing an LDPC codeword having a length of 16200 and a code rate of 5/15; A second memory initialized to zero; And a processor for generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. do.

In this case, the accumulation may be performed in parity bit addresses updated using a sequence corresponding to a parity check matrix.

At this time, the LDPC codeword is a systematic part corresponding to the information bits and having a length of 5400, a first parity part having a length of 720 and corresponding to a double diagonal matrix included in the parity check matrix, and the parity check matrix. A second parity part corresponding to the identity matrix included in and having a length of 10080 may be included.

In this case, the sequence is equal to a value obtained by dividing the length of the systematic part 5400 by the CPM size corresponding to the parity check matrix 360, and the value obtained by dividing the length of the first parity part 720 by the CPM size. You can have rows.

In this case, the sequence may be expressed in the following table.

[table]

Line 1: 69 244 706 5145 5994 6066 6763 6815 8509

Line 2: 257 541 618 3933 6188 7048 7484 8424 9104

Line 3: 69 500 536 1494 1669 7075 7553 8202 10305

Line 4: 11 189 340 2103 3199 6775 7471 7918 10530

Line 5: 333 400 434 1806 3264 5693 8534 9274 10344

Line 6: 111 129 260 3562 3676 3680 3809 5169 7308 8280

Line 7: 100 303 342 3133 3952 4226 4713 5053 5717 9931

Line 8: 83 87 374 828 2460 4943 6311 8657 9272 9571

Line 9: 114 166 325 2680 4698 7703 7886 8791 9978 10684

Line 10: 281 542 549 1671 3178 3955 7153 7432 9052 10219

Line 11: 202 271 608 3860 4173 4203 5169 6871 8113 9757

Line 12: 16 359 419 3333 4198 4737 6170 7987 9573 10095

Line 13: 235 244 584 4640 5007 5563 6029 6816 7678 9968

Line 14: 123 449 646 2460 3845 4161 6610 7245 7686 8651

Line 15: 136 231 468 835 2622 3292 5158 5294 6584 9926

Line 16: 3085 4683 8191 9027 9922 9928 10550

Line 17: 2462 3185 3976 4091 8089 8772 9342

In this case, the accumulation may be performed by changing the rows of the sequence in units of the CPM size (L) of the parity check matrix.

In addition, the LDPC encoding method according to an embodiment of the present invention includes: initializing a first memory and a second memory for storing the LDPC codeword; And generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. do.

In this case, the accumulation may be performed in parity bit addresses updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword is a systematic part having a length of 5400 corresponding to the information bits, a first parity part having a length of 720 and corresponding to a double diagonal matrix included in the parity check matrix, and the parity check matrix. A second parity part corresponding to the identity matrix included in and having a length of 10080 may be included.

In this case, the sequence is equal to a value obtained by dividing the length of the systematic part 5400 by the CPM size corresponding to the parity check matrix 360, and the value obtained by dividing the length of the first parity part 720 by the CPM size. You can have rows.

In this case, the sequence may be represented by the table.

In addition, the LDPC decoder according to an embodiment of the present invention includes: a receiver configured to receive a Low Density Parity Check (LDPC) codeword corresponding to a parity check matrix and encoded using a sequence represented by the table; And a decoding unit for restoring information bits from the received LDPC codeword by performing decoding corresponding to the parity check matrix.

According to the present invention, a new LDPC codeword with a universally usable codeword length of 16200 and a code rate of 5/15 is provided.

In addition, the present invention efficiently performs LDPC encoding using a sequence having a number of rows corresponding to a value obtained by dividing the sum of the length of the systematic part of the LDPC codeword 5400 and the length of the first parity part 720 by 360. can do.

1 is a block diagram showing a broadcast signal transmission/reception system according to an embodiment of the present invention.
2 is a flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.
3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
4 is a block diagram showing an LDPC encoder according to an embodiment of the present invention.
5 is a block diagram showing an LDPC decoder according to an embodiment of the present invention.
6 is a flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.
7 is a graph showing the performance of a QC-LDPC code having a length of 16200 and a code rate of 5/15 compared to E _b /N _o according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings as follows. Here, repeated descriptions, well-known functions that may unnecessarily obscure the subject matter of the present invention, and detailed descriptions of configurations are omitted. Embodiments of the present invention are provided to more completely explain the present invention to those with average knowledge in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a broadcast signal transmission/reception system according to an embodiment of the present invention.

Referring to FIG. 1, it can be seen that the transmitter 10 and the receiver 30 perform communication via a radio channel 20.

The transmitter 10 encodes k-bit information bits 11 by the LDPC encoder 13 to generate an n-bit codeword. The codeword is modulated by the modulator 15 and transmitted through the antenna 17. The signal transmitted through the radio channel 20 is received through the antenna 31 of the receiver 30, and the receiver 30 goes through the reverse process of the process that occurred in the transmitter 10. That is, the received data is demodulated by the demodulator 33 and decoded by the LDPC decoder 35 to finally recover the information bits.

It is apparent to those skilled in the art that the above-described transmission/reception process is described within the minimum range necessary to describe the features of the present invention, and many processes necessary for data transmission may be added.

Hereinafter, a detailed process of encoding or decoding through the LDPC code in the LDPC encoder 13 or the LDPC decoder 35 and a specific configuration of an encoding or decoding apparatus such as the LDPC encoder 13 or the LDPC decoder 35 Explain about it. The LDPC encoder 13 shown in FIG. 1 may have the structure shown in FIG. 4, and the LDPC decoder 35 may have the structure shown in FIG. 5.

2 is a flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.

Referring to FIG. 2, in the broadcast signal transmission/reception method according to an embodiment of the present invention, first, input bits are LDPC-encoded (S210).

That is, in step S210, k-bit information bits are encoded by the LDPC encoder to generate an n-bit codeword.

In this case, step S210 may be performed in the same manner as the LDPC encoding method illustrated in FIG. 6.

In addition, the broadcast signal transmission/reception method modulates the encoded data (S220).

That is, in step S220, the coded n-bit codeword is modulated by the modulator.

In addition, the broadcast signal transmission/reception method transmits the modulated data (S230).

That is, in step S230, the modulated codeword is transmitted through an antenna through a wireless channel.

In addition, the broadcast signal transmission/reception method demodulates the received data (S240).

That is, in step S240, a signal transmitted through a wireless channel is received through an antenna of the receiver, and the received data is demodulated by a demodulator.

Also, in the broadcast signal transmission/reception method, the demodulated data is LDPC-decoded (S250).

That is, in step S250, LDPC decoding is performed through the demodulator of the receiver to finally restore information bits.

In this case, step S250 corresponds to a reverse process of the LDPC encoding method shown in FIG. 6 and may correspond to the LDPC decoder of FIG. 5.

The LDPC (Low Density Parity Check) code is known as a code that approaches the Shannon limit in the AWGN (Additive White Gaussian Noise) channel, and has asymptotically superior performance than the turbo code, parallel decoding, etc. There is an advantage.

In general, the LDPC code is defined by a randomly generated low density PCM (Parity Check Matrix). However, a randomly generated LDPC code not only requires a lot of memory to store the PCM, but also takes a lot of time to access the memory. In order to solve this problem, a Quasi-cyclic LDPC (QC-LDPC) code was proposed, and the QC-LDPC code composed of a zero matrix or a Circulant Permutation Matrix (CPM) is represented by the following equation. It is defined by the PCM expressed by 1.

[Equation 1]

Here, J is a CPM having a size of L x L and is given by Equation 2 below. Hereinafter, L may be 360.

[Equation 2]

In addition, J ⁱ is an L x L identity matrix I (=J ⁰ ) shifted to the right i (0 = i <L) times, and J ^∞ is an L x L zero matrix. Therefore, in the QC-LDPC code, since only exponent ^{i needs} to be stored to store J ⁱ , the memory required to store the PCM is greatly reduced.

3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of matrices A and C are respectively g x K and (N-K-g) x (K+g), and are composed of a zero matrix and a CPM having a size of L x L. Further, matrix z is a zero matrix of size gx (NKg), matrix D is an identity matrix of size (NKg) x (NKg), and matrix B is a dual diagonal matrix of size gxg. matrix). In this case, the matrix B may be a matrix in which all elements other than the diagonal element and the elements adjacent to the diagonal line are 0, or may be defined as in Equation 3 below.

[Equation 3]

Here, I _LxL is an identity matrix of size L x L.

That is, the matrix B may be a bit-wise double diagonal matrix, or a block-wise double diagonal matrix having an identity matrix as a block as shown in Equation 3 above. A general (bit-wise) double diagonal matrix is disclosed in detail such as Korean Patent Publication No. 2007-0058438.

In particular, when the matrix B is a bit-wise double diagonal matrix, a row permutation or column permutation is applied to the PCM of the structure shown in FIG. 3 including the matrix B. It is obvious to those skilled in the art that it can be converted into quasi cyclic.

In this case, N denotes the length of a codeword, and K denotes the length of information, respectively.

In the present invention, as shown in Table 1 below, a newly designed QC-LDPC code with a code rate of 5/15 and a codeword length of 16200 is proposed. That is, we propose an LDPC code that receives information having a length of 5400 and generates an LDPC codeword having a length of 16200.

Table 1 shows the sizes of the A, B, C, D, and Z matrices of the QC-LDPC code of the present invention.

[Table 1]

The newly designed LDPC code can be displayed in the form of a sequence, the sequence and the matrix (parity bit check matrix) have an equivalent relationship, and the sequence can be expressed as shown in the following table.

[table]

Line 1: 69 244 706 5145 5994 6066 6763 6815 8509

Line 2: 257 541 618 3933 6188 7048 7484 8424 9104

Line 3: 69 500 536 1494 1669 7075 7553 8202 10305

Line 4: 11 189 340 2103 3199 6775 7471 7918 10530

Line 5: 333 400 434 1806 3264 5693 8534 9274 10344

Line 6: 111 129 260 3562 3676 3680 3809 5169 7308 8280

Line 7: 100 303 342 3133 3952 4226 4713 5053 5717 9931

Line 8: 83 87 374 828 2460 4943 6311 8657 9272 9571

Line 9: 114 166 325 2680 4698 7703 7886 8791 9978 10684

Line 10: 281 542 549 1671 3178 3955 7153 7432 9052 10219

Line 11: 202 271 608 3860 4173 4203 5169 6871 8113 9757

Line 12: 16 359 419 3333 4198 4737 6170 7987 9573 10095

Line 13: 235 244 584 4640 5007 5563 6029 6816 7678 9968

Line 14: 123 449 646 2460 3845 4161 6610 7245 7686 8651

Line 15: 136 231 468 835 2622 3292 5158 5294 6584 9926

Line 16: 3085 4683 8191 9027 9922 9928 10550

Line 17: 2462 3185 3976 4091 8089 8772 9342

LDPC codes expressed in sequence form are widely used in DVB standards.

를 생성한다. 여기서, M₁=g, M₂=N-K-g이다. 또한, M₁은 이중 대각행렬(dual diagonal matrix) B에 대응하는 패러티(parity)의 크기이며, M₂는 항등행렬 D에 대응하는 패러티의 크기이다. 부호화 과정은 다음과 같다.According to an embodiment of the present invention, an LDPC code expressed in a sequence format is encoded as follows. Suppose an information block S=(s ₀ , s ₁ , ..., s _K-1 ) with an information size of K. LDPC encoder uses an information block S of size K, and uses a codeword of size N=K+M ₁ +M ₂

Create Here, M ₁ =g, M ₂ =NKg. In addition, M ₁ is the size of a parity corresponding to the dual diagonal matrix B, and M ₂ is the size of the parity corresponding to the identity matrix D. The encoding process is as follows.

-Initialization:

[Equation 4]

를 상기 테이블의 수열의 제1행에 명시된 패러티 비트 주소들(parity bit addresses)에서 누적(accumulate)한다. 예를 들어, 길이가 16200이며, 부호율이 5/15인 LDPC 부호에서의 누적 과정은 다음과 같다.-first

Is accumulated in the parity bit addresses specified in the first row of the sequence of the table. For example, the accumulation process in an LDPC code whose length is 16200 and code rate is 5/15 is as follows.

)은 GF(2)에서 일어난다.Where the addition (

) Occurs in GF(2).

들에 대해서는, 하기 수학식 5에서 계산된 패러티 비트 주소들에서 누적한다.-The next L-1 information bits, namely

For these, they are accumulated in the parity bit addresses calculated in Equation 5 below.

[Equation 5]

에 대응되는 패러티 비트 주소들, 즉 상기 테이블의 수열의 제1행에 표기된 패러티 비트 주소들을 나타내며, Q₁ = M₁/L, Q₂ = M₂/L, L = 360이다. 또한, Q₁과 Q₂는 하기 표 2에 정의된다. 예를 들어, 길이가 16200이며, 부호율이 5/15인 LDPC 부호는 M₁ = 720, Q₁ = 2, M₂ = 10080, Q₂ = 28, L = 360이므로, 두 번째 비트

에 대해서는 상기 수학식 5를 이용하면 다음과 같은 연산이 수행된다.Where x is the first bit

Parity bit addresses corresponding to, that is, parity bit addresses indicated in the first row of the sequence of the table, are Q ₁ = M ₁ /L, Q ₂ = M ₂ /L, L = 360. In addition, Q ₁ and Q ₂ are defined in Table 2 below. For example, an LDPC code with a length of 16200 and a code rate of 5/15 is M ₁ = 720, Q ₁ = 2, M ₂ = 10080, Q ₂ = 28, L = 360, so the second bit

With respect to Equation 5, the following operation is performed.

Table 2 shows the sizes of M ₁ , M ₂ , Q ₁ , and Q ₂ of the designed QC-LDPC code.

[Table 2]

부터

까지의 새로운 360개의 정보비트들은 상기 수열의 제2행을 이용하여, 상기 수학식 5로부터 패러티 비트 누적기들의 주소를 계산하고, 누적한다.-the next

from

By using the second row of the sequence of 360 new information bits, addresses of parity bit accumulators are calculated and accumulated from Equation (5).

-In a similar way, for all groups consisting of new L information bits, the addresses of parity bit accumulators are calculated from Equation 5 and accumulated using the new row of the sequences.

에서

까지의 모든 정보비트들이 사용된 후, i = 1부터 시작하여 하기 수학식 6의 연산을 순차적으로 수행한다.-

in

After all the information bits up to are used, the operation of Equation 6 below is sequentially performed starting from i = 1.

[Equation 6]

-Next, when parity interleaving as shown in Equation 7 below is performed, parity generation corresponding to the double diagonal matrix B is completed.

[Equation 7]

)를 이용하여 이중 대각행렬 B에 대응하는 패러티 생성이 완료되면, M₁개의 생성된 패러티(

)을 이용하여, 항등행렬 D에 대응하는 패러티를 생성한다.K information bits (

When the parity generation corresponding to the double diagonal matrix B is completed using ), M ₁ generated parity (

) To generate a parity corresponding to the identity matrix D.

에서

까지의 L개의 비트들로 구성된 모든 그룹(group)들에 대해서, 상기 수열들의 새로운 행(이중 대각행렬 B에 대응하는 패러티를 생성할 때 이용한 마지막 행의 바로 다음 행부터 시작)과 상기 수학식 5를 이용하여 패러티 비트 누적기들의 주소를 계산하고, 관련 연산을 수행한다.-

in

For all groups consisting of L bits up to, a new row of the sequences (starting from the row immediately following the last row used when generating the parity corresponding to the double diagonal matrix B) and Equation 5 Calculate addresses of parity bit accumulators by using and perform related operations.

에서

까지의 모든 비트들이 사용된 후, 하기 수학식 8과 같은 패러티 인터리빙을 수행하면, 항등행렬 D에 대응하는 패러티 생성이 완료된다.-

in

After all the bits up to are used, parity interleaving as shown in Equation 8 below is performed to complete the generation of parity corresponding to the identity matrix D.

[Equation 8]

4 is a block diagram showing an LDPC encoder according to an embodiment of the present invention.

Referring to FIG. 4, the LDPC encoder according to an embodiment of the present invention includes memories 310 and 320 and a processor 330.

The memory 310 is a memory for storing an LDPC codeword having a length of 16200 and a code rate of 5/15.

The memory 320 is a memory initialized to zero.

The memory 310 and the memory 320 are respectively λ _i (i=0, 1, ..., N-1) and P _j (j=0, 1, ..., M ₁ +M ₂ -1) It may correspond to

The memory 310 and the memory 320 may correspond to various hardware for storing a set of bits, and data structures such as arrays, lists, stacks, and queues ( data structure).

The processor 330 accumulates the memory 320 using a sequence corresponding to a parity check matrix, and calculates the LDPC codeword corresponding to information bits. Generate.

In this case, the accumulation may be performed in parity bit addresses updated using the sequence of the table.

In this case, the LDPC codeword corresponds to the information bits and is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) having a length of 5400 (=K), included in the parity check matrix. The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 720 (=M ₁ =g) and the identity included in the parity check matrix A second parity part corresponding to the matrix and having a length of 10080 (=M ₂ ) (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) may be included.

In this case, the sequence is a value obtained by dividing the length of the systematic part 5400 by 360, which is the CPM size (L) corresponding to the parity check matrix, and the value obtained by dividing 720, which is the length of the first parity part (M ₁ ), by 360. You can have as many rows as the sum (5400/360+720/360=17).

As described above, the sequence may be represented by the table.

In this case, the memory 320 may have a size corresponding to the sum (M ₁ +M ₂ ) of the length M _{1 of} the first parity part and the length M ₂ of the second parity part.

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) shown in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses may be updated by Equation (5). At this time, x is the previous parity bit address, m is an information bit index, which is an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of, Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

In this case, as described above, the accumulation may be performed by changing the rows of the sequence in units of the CPM size L=360 of the parity check matrix.

In this case, the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) uses the memory 310 and the memory 320 as described through Equation 7 above, It may be generated by performing parity interleaving.

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _K) as described through Equation 8 above. , λ _K+1 , ..., λ _K+M1-1 ) after the generation of the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence After the accumulation performed by using is completed, it may be generated by performing parity interleaving using the memory 310 and the memory 320.

5 is a block diagram showing an LDPC decoder according to an embodiment of the present invention.

Referring to FIG. 5, the LDPC decoder according to an embodiment of the present invention includes a receiver 410 and a decoder 420.

The receiving unit 410 receives a Low Density Parity Check (LDPC) codeword corresponding to the parity check matrix and encoded using a sequence represented by the table.

The decoding unit 420 restores information bits from the received LDPC codeword by performing decoding corresponding to the parity check matrix.

In this case, the sequence is used to update parity bit addresses of the memory, and the parity bit addresses may be used for accumulation to generate parity bits corresponding to the LDPC codeword.

In this case, the LDPC codeword is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) corresponding to the information bits, and a first corresponding to the double diagonal matrix included in the parity check matrix. A parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and a second parity part (λ _K+M1 , λ _K+M1+) corresponding to the identity matrix included in the parity check matrix ₁ , ..., λ _K+M1+M2-1 ).

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) shown in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses may be updated by Equation (5). At this time, x is the previous parity bit address, m is an information bit index, which is an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of, Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

6 is a flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.

Referring to FIG. 6, in the LDPC encoding method according to an embodiment of the present invention, a first memory and a second memory for storing an LDPC codeword are initialized (S510).

At this time, step S510 may be performed by Equation 4 above.

In addition, the LDPC encoding method according to an embodiment of the present invention performs accumulation on the second memory by using a sequence corresponding to a parity check matrix, and information bits The LDPC codeword corresponding to is generated (S520).

In this case, the accumulation may be performed in parity bit addresses updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword corresponds to the information bits and is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) having a length of 5400 (=K), included in the parity check matrix. The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 720 (=M ₁ =g) and the identity included in the parity check matrix A second parity part corresponding to the matrix and having a length of 10080 (=M ₂ ) (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) may be included.

In this case, the sequence is a value obtained by dividing the length of the systematic part 5400 by 360, which is the CPM size (L) corresponding to the parity check matrix, and the value obtained by dividing 720, which is the length of the first parity part (M ₁ ), by 360. You can have as many rows as the sum (5400/360+720/360=17).

As described above, the sequence may be represented by the table.

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) shown in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses may be updated by Equation (5). At this time, x is the previous parity bit address, m is an information bit index, which is an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of, Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

In this case, as described above, the accumulation may be performed by changing the rows of the sequence in units of the CPM size L=360 of the parity check matrix.

In this case, the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) is parity interleaving using the first memory and the second memory, as described through Equation 7 above. It can be created by performing (parity interleaving).

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _K) as described through Equation 8 above. , λ _K+1 , ..., λ _K+M1-1 ) after the generation of the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence After the accumulation performed by using is completed, it may be generated by performing parity interleaving using the first memory 310 and the second memory 320.

7 is a graph showing the performance of a QC-LDPC code having a length of 16200 and a code rate of 5/15 compared to E _b /N _o according to an embodiment of the present invention.

The graph shown in FIG. 7 is a result of assuming a sum-product algorithm based on a log-likelihood ratio (LLR) performing BPSK (binary phase shift keying) modulation and 50 iterations of decoding for a computational experiment. As shown in FIG. 7, it can be seen that the designed code is about 1.2 dB away from the Shannon limit at BER=10 ^-6 .

As described above, the LDPC encoder, decoder, and LDPC encoding method according to the present invention are not limited to the configuration and method of the embodiments described as described above, but the embodiments are All or some of the embodiments may be selectively combined and configured.

310, 320: memory
330: processor

Claims (13)

Initializing a first memory and a second memory for storing LDPC codewords having a length of 16200 and a code rate of 5/15; And
Comprising the step of generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. LDPC encoding method, characterized in that. The method according to claim 1,
The LDPC encoding method, characterized in that the sequence is represented by the following table.
[table]
Line 1: 69 244 706 5145 5994 6066 6763 6815 8509
Line 2: 257 541 618 3933 6188 7048 7484 8424 9104
Line 3: 69 500 536 1494 1669 7075 7553 8202 10305
Line 4: 11 189 340 2103 3199 6775 7471 7918 10530
Line 5: 333 400 434 1806 3264 5693 8534 9274 10344
Line 6: 111 129 260 3562 3676 3680 3809 5169 7308 8280
Line 7: 100 303 342 3133 3952 4226 4713 5053 5717 9931
Line 8: 83 87 374 828 2460 4943 6311 8657 9272 9571
Line 9: 114 166 325 2680 4698 7703 7886 8791 9978 10684
Line 10: 281 542 549 1671 3178 3955 7153 7432 9052 10219
Line 11: 202 271 608 3860 4173 4203 5169 6871 8113 9757
Line 12: 16 359 419 3333 4198 4737 6170 7987 9573 10095
Line 13: 235 244 584 4640 5007 5563 6029 6816 7678 9968
Line 14: 123 449 646 2460 3845 4161 6610 7245 7686 8651
Line 15: 136 231 468 835 2622 3292 5158 5294 6584 9926
Line 16: 3085 4683 8191 9027 9922 9928 10550
Line 17: 2462 3185 3976 4091 8089 8772 9342 The method according to claim 2,
The accumulation is the second bit of the information bits

About

(p _x (0≤x≤10799) is the second memory,

Is the addition operator)
LDPC encoding method, characterized in that it is performed using the nine equations of. The method according to claim 2,
The LDPC codeword is
A systematic part corresponding to the information bits and having a length of 5400, a first parity part having a length of 720 and corresponding to a double diagonal matrix included in the parity check matrix, and an identity matrix included in the parity check matrix. LDPC encoding method comprising a second parity part corresponding to and having a length of 10080. The method of claim 4,
The sequence is a value obtained by dividing 5400, which is the length of the systematic part, by 360, which is a circulant permutation matrix (CPM) size corresponding to the parity check matrix, plus a value obtained by dividing 720, which is the length of the first parity part, by the CPM size. LDPC encoding method, characterized in that it has as many rows as the number of rows. The method of claim 5,
The accumulation is,
LDPC encoding method, characterized in that performed on parity bit addresses updated using the sequence. The method of claim 6,
The above accumulation is
The LDPC encoding method, characterized in that it is performed while changing rows of the sequence in units of a CPM size (L) of the parity check matrix. By using a sequence corresponding to the parity check matrix, accumulation is performed on the memory initialized to 0, corresponding to information bits, the length is 16200 and the code rate is 5 Generating an LDPC codeword of /15; And
Including the step of performing modulation corresponding to the LDPC codeword,
The broadcast signal transmission method, characterized in that the sequence is represented by the following table.
[table]
Line 1: 69 244 706 5145 5994 6066 6763 6815 8509
Line 2: 257 541 618 3933 6188 7048 7484 8424 9104
Line 3: 69 500 536 1494 1669 7075 7553 8202 10305
Line 4: 11 189 340 2103 3199 6775 7471 7918 10530
Line 5: 333 400 434 1806 3264 5693 8534 9274 10344
Line 6: 111 129 260 3562 3676 3680 3809 5169 7308 8280
Line 7: 100 303 342 3133 3952 4226 4713 5053 5717 9931
Line 8: 83 87 374 828 2460 4943 6311 8657 9272 9571
Line 9: 114 166 325 2680 4698 7703 7886 8791 9978 10684
Line 10: 281 542 549 1671 3178 3955 7153 7432 9052 10219
Line 11: 202 271 608 3860 4173 4203 5169 6871 8113 9757
Line 12: 16 359 419 3333 4198 4737 6170 7987 9573 10095
Line 13: 235 244 584 4640 5007 5563 6029 6816 7678 9968
Line 14: 123 449 646 2460 3845 4161 6610 7245 7686 8651
Line 15: 136 231 468 835 2622 3292 5158 5294 6584 9926
Line 16: 3085 4683 8191 9027 9922 9928 10550
Line 17: 2462 3185 3976 4091 8089 8772 9342 The method of claim 8,
The accumulation is the second bit of the information bits

About

(p _x (0≤x≤10799) is the memory,

Is the addition operator)
Broadcast signal transmission method, characterized in that performed using the nine equations of. The method of claim 8,
The LDPC codeword is
A systematic part corresponding to the information bits and having a length of 5400, a first parity part having a length of 720 and corresponding to a double diagonal matrix included in the parity check matrix, and an identity matrix included in the parity check matrix. And a second parity part corresponding to and having a length of 10080. The method of claim 10,
The sequence is a value obtained by dividing 5400, which is the length of the systematic part, by 360, which is a circulant permutation matrix (CPM) size corresponding to the parity check matrix, plus a value obtained by dividing 720, which is the length of the first parity part, by the CPM size. Broadcast signal transmission method, characterized in that the number of rows (rows). The method of claim 11,
The accumulation is,
A method for transmitting broadcast signals, characterized in that performed on parity bit addresses updated using the sequence. The method of claim 12,
The above accumulation is
And changing the rows of the sequence in units of a CPM size (L) of the parity check matrix.

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