KR20200135149A - Spin logic device and method of operating the same - Google Patents

Abstract

The present invention relates to a spin logic device and an operation method thereof, and more specifically, to a spin logic device and an operation method thereof, wherein the spin logic device can be operated using a general dielectric capacitor and an additional transistor. According to an embodiment of the present invention, the spin logic device includes: a magnetic layer; a current transfer layer formed on one surface of the magnetic layer; a spin injection layer formed on the one surface of the magnetic layer to be spaced apart from the current transfer layer; and a spin-charge conversion layer formed on the spin injection layer.

Description

Spin logic device and its operation method {SPIN LOGIC DEVICE AND METHOD OF OPERATING THE SAME}

The present invention relates to a spin logic device and a method of operating the same, and more particularly, to a spin logic device capable of operating using a general dielectric capacitor and an additional transistor, and a method of operating the same.

2016 C. Murapaka et. al proposed a method of applying an input signal to a vertical/horizontal nanowire and selecting a logic function using a separate magnetic gate at the top (see Sci. Rep. 6, 20130 (2016)). The input signal is a magnetic signal, not a current signal or a voltage signal, and the magnetic domain wall movement method was used.

2017 M. G. Mankalale et. In al., logic is implemented through voltage-based switching and magnetic domain wall movement (see IEEE J. Explore. Solid-State Comput. Devices Circuits 3, 27 (2017)). It contains a dual-rail CMOS inverter and uses four control signals. Since a CMOS inverter is included in the circuit to perform the function of a simple inverter, it has less advantage than a CMOS inverter, and it is difficult to implement reconfigurable logic.

N. Rangarajan et. In al., a Boolean function was implemented using a unit element and magnetic tunnel junction based on the spin hall effect and magnetic dipole coupling. Although a logic function can be selected using MUX, implementation of a lateral structure and dipolar coupling is not easy in practice.

Research on spin logic devices has been proposed for various structures around the world, but no results have been shown that can exceed the characteristics of CMOS-based devices.

However, the MESO (magnetoelectric spin-orbit) device theoretically proposed by Intel in 2019 is expected to be implemented as a low-power spin logic device that is comparable to CMOS-based devices (see Nature 565, 35 (2019)). .

Conventional reconfigurable spin logic uses a magnetic signal or a multi-ferroic material that is not easy to mass-produce semiconductors due to its high deposition temperature (which has both ferromagnetic + ferroelectric properties). It is based on the effect. In addition, because the unit device remains at the theoretical and conceptual level, the compatibility of the semiconductor mass production process and experimental device verification have not been performed. In order to be used in low-power, high-area-efficiency applications, a circuit capable of real-time reconfiguration of Boolean functions such as inverter/buffer/NAND/NOR using voltage-controlled magnetization switching and spin-charge conversion is required.

The conventional MESO structure switches spins using a multi-ferroic/ferromagnetic magnetic-electric coupling and an exchange coupling between the spins.

Although theoretically a great concept, conventional MESO structures cannot be used in a back-end process in which transistors and ferromagnetic materials are integrated as a result of being made on a single crystal substrate grown at a high temperature of 600 degrees Celsius or higher. In addition, in the conventional MESO structure, fatigue phenomenon occurs due to strain generated during switching, so the endurance of the logic device cannot be guaranteed. In addition, in the conventional MESO structure, since the sign of the spin-charge conversion layer is set to one, it is used only as an inverter and a buffer cannot be made.

A technical problem to be achieved by the present invention is to provide a spin logic device capable of operating using a general dielectric capacitor and an additional transistor, and a method of operating the same.

A spin logic device according to an embodiment of the present invention includes a magnetic material layer, a current transfer layer formed on one surface of the magnetic material layer, a spin injection layer formed on the one surface of the magnetic material layer to be spaced apart from the current transfer layer, and the spin injection layer. And a spin-charge conversion layer formed thereon.

According to an embodiment, the magnetization direction of the magnetic layer may be switched by a current flowing through the current transfer layer.

According to an embodiment, the current is supplied from a current supply unit, and the current supply unit includes a capacitor and a gate electrode connected between an input node and a ground connected to the input node, a first electrode connected to a slave power supply, and a second An electrode may include a transistor connected to one end of the current transfer layer.

According to an embodiment, the dependent power supply may supply power corresponding to the polarity of the voltage across the capacitor.

According to an embodiment, the other end of the current transfer layer may be connected to the ground.

The current transfer layer may include at least one of a heavy metal and a phase insulator.

The spin injection layer may inject a spin current determined according to the magnetization direction of the magnetic material layer into the spin-charge conversion layer as a spin filter.

According to an embodiment, the spin-charge conversion layer may convert the spin current injected from the spin injection layer into a charge current and output it as an output current.

A method of operating a spin logic device according to an embodiment of the present invention includes charging a capacitor by a current supplied through an input node, supplying a current through a current transfer layer in a direction corresponding to the polarity of the voltage across the capacitor. Switching a magnetization direction of the magnetic material layer according to the direction of the current, injecting a spin current determined according to the magnetization direction of the magnetic material layer into the spin-charge conversion layer, and converting the spin current into a charge current Converting and outputting it as an output current.

According to an embodiment, the current transfer layer is formed on one surface of the magnetic material layer, the spin injection layer is formed on the one surface of the magnetic material layer and spaced apart from the current transfer layer, and the spin-charge conversion layer is It may be formed on the spin injection layer.

According to an embodiment, the current transfer layer may include at least one of a heavy metal and a phase insulator.

According to an embodiment, the spin injection layer may operate as a spin filter.

The spin logic device and its operating method according to an embodiment of the present invention may be operated using a general dielectric capacitor and an additional transistor.

The spin logic device according to an embodiment of the present invention may be manufactured using a conventional semiconductor process (silicon-based process).

Conventional devices use a current signal for magnetization switching with a ferromagnetic material, but the spin logic device according to an embodiment of the present invention can be controlled using a voltage signal applied to a dielectric capacitor.

The spin logic device according to an exemplary embodiment of the present invention consumes less power, has high area efficiency, and enables real-time circuit reconfiguration.

A detailed description of each drawing is provided in order to more fully understand the drawings cited in the detailed description of the present invention.
1 is a schematic diagram illustrating a spin logic device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating in detail a connection relationship between the spin logic device and related circuits shown in FIG.
3 is a diagram illustrating an example of a process of switching a magnetization direction of a magnetic layer in response to an input current.
4 is a diagram illustrating an example of a process of generating an output current according to a magnetization direction of a magnetic material.
5 is a diagram illustrating another example of a process in which a magnetization direction of a magnetic layer is switched in response to an input current.
6 is a diagram illustrating another example of a process of generating an output current according to a magnetization direction of a magnetic material.
FIG. 7 is a diagram illustrating a buffer constructed using the spin logic device shown in FIG. 1.
8 is a flow chart illustrating an operation of a spin logic device according to an embodiment of the present invention.
9 is a diagram for describing a majority gate that can be implemented using a spin logic device according to an embodiment of the present invention.
10 is a diagram illustrating an inverted majority gate that can be implemented using a spin logic device according to an embodiment of the present invention.
11 is a diagram illustrating a 1-bit adder that can be implemented using a spin logic device according to an embodiment of the present invention.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present invention. It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of the rights according to the concept of the present invention, the first component may be referred to as the second component, and similarly The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in this specification are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of a set feature, number, step, action, component, part, or combination thereof, but one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, the present invention will be described in detail by describing a preferred embodiment of the present invention with reference to the accompanying drawings.

1 is a schematic diagram illustrating a spin logic device according to an embodiment of the present invention.

Referring to FIG. 1, the spin logic device 100 includes a magnetic layer 110, a current transfer layer 120, a spin injection layer 130, a spin-charge conversion layer 140, and a current output layer 150. .

The magnetic layer 110 may initially have an arbitrary magnetization direction.

The magnetization direction of the magnetic layer 110 may be switched by a current flowing through the current transfer layer 120. Specifically, the magnetization direction of the magnetic layer 110 may be switched by a spin current or spin-orbit torque generated by a current flowing through the current transfer layer 120.

It is preferable that the magnetic layer 110 is formed of a ferromagnet.

The current transfer layer 120 may be formed on one surface of the magnetic layer 110 and may be formed to be spaced apart from the spin injection layer 130.

The current transfer layer 120 allows the current supplied from the current supply unit 200 to flow to the ground. In this case, the current transfer layer 120 may switch the magnetization direction of the magnetic layer 110 by inducing a magnetic field corresponding to the direction of the current supplied from the current supply unit 200.

It is preferable that the current transfer layer 120 is formed of a heavy metal or a phase insulator having a large spin hall angle.

A spin injection layer 130 may be formed on the one surface of the magnetic layer 110 and may be formed to be spaced apart from the current transfer layer 120.

The spin injection layer 130 may receive a spin current from the magnetic layer 110. Specifically, the spin injection layer 130 is a spin filter and passes a spin current having a direction corresponding to the magnetization direction of the magnetic layer 110.

The spin injection layer 130 may be formed of an insulating layer based on MgO.

A spin-charge conversion layer 140 may be formed on the spin injection layer 130.

The spin-charge conversion layer 140 may convert the spin current injected through the spin injection layer 130 into a charge current and output the converted current. Specifically, the spin-charge conversion layer 140 converts the spin current passing through the spin injection layer 120 into a charge current through a spin orbit interaction or the like.

The current output layer 150 may be formed on the spin-charge conversion layer 140.

The current output layer 150 outputs a charge current converted by the spin-charge conversion layer 140.

The current output layer 150 may be formed of a material through which a charge current can flow.

Although not shown in FIG. 1, an artificial antiferromagnetic material may be provided between the magnetic material layer 110 and the spin injection layer 130. When the artificial antiferromagnetic material is provided, the direction of the charge current flowing through the current output layer 150 can be reversed.

That is, the spin logic device 100 may be implemented as an inverter or a buffer depending on whether an artificial antiferromagnetic material is provided.

For example, the artificial antiferromagnetic material may be implemented as an artificial structure in which the magnetization of two magnetic layers is reversely aligned in a magnetic layer/non-magnetic layer/magnetic layer structure by a Ruderman-Kittle-Kasuya-Yosida bond.

FIG. 2 is a diagram illustrating in detail a connection relationship between the spin logic element shown in FIG. 1 and a related circuit.

Referring to FIG. 2, the current transfer layer 120 may be connected to the current supply unit 200 through an electrode 161 and to ground through the electrode 163.

The current supply unit 200 may supply a current corresponding to the input current I _in supplied through the input node IN to the current transfer layer 120 through the electrode 161.

According to an embodiment, the current supply unit 200 may supply a current _{in the} same direction as the input current I _in to the current transfer layer 120.

The current supply unit 200 may include a capacitor C, a dependent power supply DS, and a transfer transistor TM.

The capacitor C charges the input current I _in supplied from the input node IN. That is, the capacitor C stores the voltage Vc corresponding to the input current I _in .

The dependent power supply DS supplies power determined according to the voltage Vc stored in the capacitor C.

For example, when the voltage Vc is charged, that is, when it is positive, the dependent power source DS may operate as a power source having a positive voltage. Conversely, when the voltage Vc is discharged, the dependent power source DS may operate as a power source having a negative voltage.

For another example, when the voltage Vc is greater than or equal to a predetermined reference voltage, the dependent power supply DS operates as a power having a positive voltage, and when the voltage Vc is less than the predetermined reference voltage, the dependent power supply DS is negative. It can be operated with a power supply having a voltage of

The structure of the current supply unit 200 shown in FIG. 2 is only an example, and may be implemented in various forms. In other words, the current supply unit 200 may be implemented in various structures having a function of a bi-directional current amplifier.

The gate electrode of the transfer transistor TM may be connected to the input node IN, the first electrode may be connected to the slave power supply DS, and the second electrode may be connected to the electrode 161.

The transfer transistor TM may supply a current corresponding to the output voltage of the dependent power supply DS to the electrode 161. The current may flow to the ground through the electrode 161, the current transfer layer 120, and the electrode 163.

When a current flows through the current transfer layer 120, a magnetic material is generated by a spin current or spin-orbital torque generated by a spin-hall effect or a Rashba effect in the current transfer layer 120. The magnetization direction of the layer 110 may be switched.

A header transistor TH may be provided between the magnetic layer 110 and the power source V _DD , and a foot transistor TF may be provided between the current output layer 150 and the ground.

The header transistor TH may be connected to the magnetic layer 110 through the electrode layer 171, and the footer transistor TF may be connected to the current output layer 173 through the electrode layer 173.

The header transistor TH is connected between the power source V _DD and the electrode layer 171 and may be turned on in response to the control signal Vsup.

The footer transistor TF is connected between the power source V _DD and the electrode layer 173 and may be turned on in response to the control signal Vsup.

When the control signal Vsup is supplied to the header transistor TH and the footer transistor TF, the vertical current Isup is applied to the magnetic layer 110, the spin injection layer 130, the spin-charge conversion layer 140, and It is preferable that the magnetic material layer 110, the spin injection layer 130, the spin-charge conversion layer 140, and the current output layer 150 be formed in a vertical direction so as to flow through the current output layer 150.

2 illustrates a case in which the header transistor TH and the footer transistor TF are simultaneously provided, but the exemplary embodiment of the present invention is not limited thereto. For example, it is sufficient if only at least one of the header transistor TH and the footer transistor TF is provided.

The operation of the spin logic device 100 according to the direction of the input current I _in supplied from the input node IN will be described in more detail with reference to FIGS. 3 to 6.

3 is a diagram illustrating an example of a process of switching a magnetization direction of a magnetic layer in response to an input current. 3 is a view for explaining a process in which the magnetization direction Ms of the magnetic layer 110 is switched when the input current I _in flows from the input node IN to the current supply unit 200.

Referring to FIG. 3, when the input current I _in is supplied from the input node IN to the current supply unit 200, the capacitor C may be charged. In other words, the voltage Vc at both ends of the capacitor C may be charged to a predetermined reference voltage or more by the input current I _in .

The dependent power supply DS outputs a positive voltage according to the voltage Vc of both ends of the capacitor C.

In this case, the transfer transistor TM is an N-channel MOSFET (NMOS) and may amplify the input current I _in and output it to the spin logic device 100. Specifically, the transfer transistor TM may supply the amplified current Itr through the electrode 161, the current transfer layer 120, and the electrode 163 in the ground direction.

When the amplified current Itr flows, the current transfer layer 120 generates a spin current or a spin-orbital torque in the direction of the amplified current Itr. As a result, the magnetization direction Ms of the magnetic layer 110 can be switched by the induced magnetic field as shown in FIG. 3.

4 is a diagram illustrating an example of a process of generating an output current according to a magnetization direction of a magnetic material. 4 is a view for explaining a process in which the direction of the output current Iout is determined when the magnetization direction Ms of the magnetic layer 110 is switched as illustrated in FIG. 3.

Referring to FIG. 4, after the magnetization direction Ms of the magnetic layer 110 is switched, a vertical current Isup is applied to the magnetic layer 110, the spin injection layer 130, the spin-charge conversion layer 140, and the current. When flowing through the output layer 150, an output current Iout may be generated.

The spin injection layer 130 may receive a spin current in a direction corresponding to the magnetization direction of the magnetic layer 110. Specifically, as a spin filter, the spin injection layer 130 may pass a spin current having a direction corresponding to the magnetization direction of the magnetic layer 110.

The spin-charge conversion layer 140 converts the spin current passing through the spin injection layer 130 into a charge current and outputs the converted current. In this case, the charge current output from the spin-charge conversion layer 140 flows through the current output layer 150 and serves as an output current Iout.

It can be understood that the spin logic element 100 operates as an inverter since the direction of the input current I _in and the direction of the output current Iout shown _in FIG. 3 are opposite.

5 is a diagram illustrating another example of a process in which a magnetization direction of a magnetic layer is switched in response to an input current. Figure 5 "when the flow to the input node (IN) from the current supply section 200, that is, to the input node (IN) input current (I _in input current (I _in), when the sink (sink)) magnetic layers A diagram for explaining a process in which the magnetization direction Ms of (110) is switched.

Referring to FIG. 5, when the input current I _in ′ is supplied from the input node IN to the current supply unit 200, the capacitor C may be discharged.

Referring to FIG. 3, when the input current I _in' is supplied from the input node IN to the current supply unit 200, the capacitor C may be discharged. In other words, the voltage Vc at both ends of the capacitor C may be discharged to less than a predetermined reference voltage by the input current I _in ′.

The dependent power supply DS outputs a negative voltage according to the voltage Vc of both ends of the capacitor C.

In this case, the transfer transistor TM may amplify the input current I _in ′ as an NMOS and output it to the spin logic device 100. Specifically, the transfer transistor TM may supply the amplified current Itr' from ground to the transfer transistor TM through the electrode 163, the current transfer layer 120 and the electrode 161. That is, the transfer transistor TM may sink the current Itr' from the ground through the current transfer layer 120.

The current transfer layer 120 may generate a spin current or spin-orbit torque corresponding to a direction of the amplified current Itr' when the amplified current Itr' flows. As a result, the magnetization direction Ms of the magnetic layer 110 may be switched as shown in FIG. 5.

6 is a diagram illustrating another example of a process of generating an output current according to a magnetization direction of a magnetic material. 6 is a view for explaining a process in which the direction of the output current Iout' is determined when the magnetization direction Ms of the magnetic layer 110 is switched as shown in FIG. 5.

Referring to FIG. 6, after the magnetization direction Ms of the magnetic layer 110 is switched, a vertical current Isup is generated by the magnetic layer 110, the spin injection layer 130, the spin-charge conversion layer 140, and the current. When flowing through the output layer 150, an output current Iout' may occur.

The spin injection layer 130 may receive a spin current in a direction corresponding to the magnetization direction of the magnetic layer 110. Specifically, as a spin filter, the spin injection layer 130 may pass a spin current having a direction corresponding to the magnetization direction of the magnetic layer 110.

The spin-charge conversion layer 140 converts the spin current passing through the spin injection layer 130 into a charge current and outputs the converted current. In this case, the charge current output from the spin-charge conversion layer 140 flows through the current output layer 150 and serves as an output current Iout'.

Since the direction of the input current I _in ′ and the direction of the output current Iout ′ shown _in FIG. 5 are opposite, it can be understood that the spin logic device 100 operates as an inverter.

7 is a diagram illustrating a buffer constructed using the spin logic device shown in FIG. 1. FIG. 7 shows a current output layer 150 and a second stage (right spin logic device, 100-2) of a first stage (left spin logic device, 100-1) in which two spin logic devices shown in FIG. 2 are connected in series. It can be understood that the input node of is electrically connected.

Referring to FIG. 7, as described above, since the spin logic elements 100-1 and 100-2 each operate as an inverter, the direction of the input current I _in and the direction of the intermediate output current Imed are opposite. The direction of the intermediate output current Imed and the direction of the output current Iout are opposite. That is, the direction of the input current I _in and the direction of the output current Iout are the same.

7, it can be seen that when even number of spin logic devices are connected in series, they can operate as a buffer.

8 is a flow chart illustrating an operation of a spin logic device according to an embodiment of the present invention.

Referring to FIG. 8, the capacitor C is charged by the input current I _in supplied through the input node IN (S100). In other words, when the input current I _in is supplied to the current supply unit 200, the capacitor C is charged.

Current is supplied through the current transfer layer 120 in a direction determined according to the voltage Vc of both ends of the capacitor C (S200). When the voltage Vc corresponding to the input current I _in is charged in the capacitor C, the dependent power supply DS outputs a voltage corresponding to the voltage Vc at both ends of the capacitor C. Accordingly, the transfer transistor TM supplies a current in a direction corresponding to the voltage Vc across the capacitor C, that is, a direction corresponding to the direction of the input current I _in , to the current transfer layer 120 .

The magnetization direction of the magnetic layer is switched according to the direction of the current flowing through the current transfer layer 120 (S300). When a current flows through the current transfer layer 120, a magnetic field is induced corresponding to the direction of the current, and the magnetization direction of the magnetic layer 110 is switched by the induced magnetic field.

A spin current determined according to the magnetization direction of the magnetic layer 100 is injected into the spin-charge conversion layer using a spin filter (S400). When the vertical current Isup flows through the magnetic layer 110, the spin injection layer 130, the spin-charge conversion layer 140, and the current output layer 150, the spin injection layer 130 operates as a spin filter and spins. Current is supplied to the spin-charge conversion layer 140.

The spin current is converted into a charge current and output as an output current (S500). The spin-charge conversion layer 140 converts the injected spin-charge into a charge current and outputs the converted charge current as an output current to the output node OUT through the current output layer 150.

9 is a diagram for describing a majority gate that can be implemented using a spin logic device according to an embodiment of the present invention.

Referring to FIG. 9, a majority gate (MAJ3) may be implemented using one buffer (BUF).

The buffer BUF outputs a value occupying a majority of the input signals A, B, and X as an output signal Out.

In other words, the input signals (A, B, X) are in the form of current, sourcing or sinking the current according to the corresponding value, but the input terminal of the buffer BUF is Current is supplied.

The truth table of the majority vote MAJ3 is as shown in FIG. 9.

Any one of the input signals (A, B, X), for example, depending on the value of the input signal (X), the rest, for example, a logical expression (AND or OR ) Is determined.

10 is a diagram illustrating an inverted majority gate that can be implemented using a spin logic device according to an embodiment of the present invention. The logic circuit shown in FIG. 10 is the same as the logic circuit shown in FIG. 9 except that the buffer BUF is included instead of the fourth inverter INV4.

)를 구현할 수 있다.Referring to FIG. 10, an inverse majority gate using one inverter INV.

) Can be implemented.

The inverter INV inverts a value that occupies a majority of the input signals A, B, and X and outputs the inverted signal as an output signal Out.

In other words, the input signals (A, B, X) are in the form of current, sourcing or sinking the current according to the corresponding value, and the input terminal of the inverter (INV) is Current is supplied, and the inverter INV inverts and outputs the supplied current.

)의 진리표는 도 9에 도시된 바와 같다.Reverse Majority Gate (

The truth table of) is as shown in FIG. 9.

Any one of the input signals (A, B, X), for example, depending on the value of the input signal (X), the rest, for example, a logical expression (NAND or NOR) for the input signals (A, B) ) Is determined.

11 is a diagram for describing a 1-bit full adder that can be implemented using a spin logic device according to an embodiment of the present invention.

)와 2개의 다수결 게이트(MAJ3), 1개의 인버터를 이용해 1-비트 전가산기를 구현할 수 있다.11, one inverted majority gate (

), two majority gates (MAJ3), and one inverter to implement a 1-bit full adder.

The truth table of the 1-bit full adder implemented as described above is shown in FIG. 11.

When implementing a 1-bit full adder using CMOS, the area occupied by using 2 XOR gates, 3 NAND gates and 28 transistors is calculated as 5800 [F ² ]. In contrast, when implementing a 1-bit full adder based on a spin logic device according to an embodiment of the present invention, it is occupied by using one majority circuit consisting of four spin logic devices and three inverting (or non-inverting) majority vote circuits. It has a minimum area of 920 [F ² ]. That is, it can be seen that space saving of about 85% is possible based on the spin logic device of the present invention.

In addition, as a result of the simulation, the energy consumption of the CMOS-based 1-bit full adder was calculated as 142 [aJ], but the energy consumption of the spin logic device-based 1-bit full adder according to the embodiment of the present invention was 27 [aJ], compared to CMOS. It can be reduced by 78%.

Although the present invention has been described with reference to the exemplary embodiment shown in the drawings, this is only exemplary, and those of ordinary skill in the art will appreciate that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

100; Spin logic element
110, 110-1, 110-2; Magnetic layer
120, 120-1, 120-2; Current carrying layer
130, 130-1, 130-2; Spin injection layer
140, 140-1, 140-2; Spin-charge conversion layer
150, 150-1, 150-2; Current output layer

Claims (12)

Magnetic layer;
A current transfer layer formed on one surface of the magnetic layer;
A spin injection layer formed on the one surface of the magnetic layer and spaced apart from the current transfer layer; And
A spin logic device comprising a spin-charge conversion layer formed on the spin injection layer. The method of claim 1,
The magnetic material layer is a spin logic device in which a magnetization direction is switched by a current flowing through the current transfer layer. The method of claim 2,
The current is supplied from a current supply,
The current supply unit,
A capacitor connected between the input node and ground; And
A spin logic device comprising a transistor in which a gate electrode is connected to the input node, a first electrode is connected to a slave power supply, and a second electrode is connected to one end of the current transfer layer. The method of claim 3,
The dependent power supply is a spin logic device that supplies power corresponding to a polarity of a voltage across the capacitor. The method of claim 3,
The other end of the current transfer layer is a spin logic device connected to the ground. The method of claim 1,
The current transfer layer,
A spin logic device comprising at least one of a heavy metal and a phase insulator. The method of claim 1,
The spin injection layer,
A spin logic device for injecting a spin current determined according to the magnetization direction of the magnetic layer into the spin-charge conversion layer as a spin filter. The method of claim 1,
The spin-charge conversion layer,
A spin logic device that converts the spin current injected from the spin injection layer into a charge current and outputs it as an output current. Charging the capacitor by the current supplied through the input node;
Supplying a current through a current transfer layer in a direction corresponding to the polarity of the voltage across the capacitor;
Switching the magnetization direction of the magnetic layer according to the direction of the current;
Injecting a spin current determined according to the magnetization direction of the magnetic layer into the spin-charge conversion layer; And
And converting the spin current into a charge current and outputting the spin current as an output current. The method of claim 9,
The current transfer layer is formed on one surface of the magnetic layer,
The spin injection layer is formed on the one surface of the magnetic layer to be spaced apart from the current transfer layer,
The spin-charge conversion layer is formed on the spin injection layer. The method of claim 10,
The current transfer layer,
A method of operating a spin logic device including at least one of a heavy metal and a phase insulator. The method of claim 10,
The spin injection layer operates as a spin filter.

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