KR20200133686A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor memory device capable of improving reliability and performance by controlling a leakage current, and a manufacturing method thereof. The semiconductor memory device comprises: a substrate having a cell area and a connection area adjacent to the cell area; a lower stacked structure having a plurality of lower insulation layers and a plurality of lower gate layers alternately stacked on the substrate; an upper stacked structure having a plurality of upper insulation layers and a plurality of upper gate layers alternately stacked on the lower stacked structure; a channel hole comprising a lower channel hole extending through the lower stacked structure, and an upper channel hole extending through the upper stacked structure, wherein the upper channel hole extends along the lower channel hole; and a channel structure in the channel hole, wherein the channel structure comprises a barrier layer, a charge storage layer, a tunnel insulation layer, and a channel pattern sequentially formed along a profile of the channel hole and comprises a lower barrier pattern disposed between the barrier layer and the lower gate layers, but not disposed between the barrier layer and the upper gate layers.

Description

TECHNICAL FIELD The semiconductor memory device and manufacturing method thereof TECHNICAL FIELD

The present invention relates to a semiconductor memory device and a method of manufacturing the same.

BACKGROUND ART As electronic products tend to be light, thin, and short, demand for high integration of semiconductor devices is increasing. As semiconductor devices become increasingly highly integrated, the sizes of components included in semiconductor devices (eg, transistors) also decrease, and thus leakage current occurs. Therefore, it is necessary to control the leakage current of the semiconductor device to improve the performance and reliability of the semiconductor device.

Meanwhile, in an electronic system requiring data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a method of increasing the data storage capacity of a semiconductor device is being studied. For example, as one of the methods for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged in a three-dimensional manner instead of memory cells arranged in a two-dimensional manner has been proposed.

The technical problem to be solved by the present invention is to provide a semiconductor memory device capable of improving reliability and performance by controlling a leakage current.

Another problem to be solved by the present invention is to provide a method of manufacturing a semiconductor memory device capable of improving reliability and performance by controlling a leakage current.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem includes a substrate having a cell region and a connection region adjacent to the cell region, a plurality of lower insulating layers and a plurality of lower gate layers alternately stacked on the substrate. A lower stack structure having a lower stack structure, an upper stack structure having a plurality of upper insulating layers and a plurality of upper gate layers alternately stacked on the lower stack structure, a lower channel hole penetrating the lower stack structure, and an upper channel hole penetrating the upper stack structure A channel hole including, wherein the upper channel hole includes a channel hole extending from a lower channel hole, and a channel structure in the channel hole, and the channel structure includes a barrier layer sequentially formed along a profile of the channel hole, a charge storage layer, and a tunnel An insulating layer and a channel pattern are included, and the channel structure includes a lower barrier pattern disposed between the barrier layer and the lower gate layer, and not disposed between the barrier layer and the upper gate layer.

In the method of manufacturing a semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem, a sacrificial source line is formed on a substrate, and a plurality of lower insulating layers and a plurality of lower sacrificial layers are alternately stacked on the sacrificial source line. A layered lower layered structure is formed, a lower channel hole passing through the lower layered structure is formed, a lower barrier pattern is formed along the profile of the lower channel hole, and on the lower barrier pattern, the lower channel hole is filled. 1 A sacrificial layer is formed, and an upper layered structure having a plurality of upper insulating layers and a plurality of upper sacrificial layers alternately stacked is formed on the lower layered structure, penetrating the upper layered structure, and an upper channel connected to the lower channel hole A hole is formed, the first sacrificial layer is removed, a barrier layer disposed along the profile of the sidewall and the lower barrier pattern of the upper channel hole is formed, the sacrificial source line is removed, and the common source is in the region from which the sacrificial source line is removed. A line is formed, a plurality of lower sacrificial layers and a plurality of upper sacrificial layers are removed, a lower gate layer is formed in the region from which the plurality of lower sacrificial layers are removed, and an upper gate layer is formed in the region from which the plurality of upper sacrificial layers are removed Including forming, the lower barrier pattern is disposed between the barrier layer and the lower gate layer, and is not disposed between the barrier layer and the upper gate layer.

Details of other embodiments are included in the detailed description and drawings.

1 is an exemplary circuit diagram for describing a semiconductor memory device according to some embodiments of the present invention.
2 and 3 are schematic cross-sectional views illustrating semiconductor memory devices according to some embodiments of the present invention.
FIG. 4 is an enlarged view illustrating an area E1 of FIG. 2.
5 to 8 are various cross-sectional views illustrating a semiconductor memory device according to some embodiments of the present invention.
9 and 10 are cross-sectional views taken along line AA′ of FIG. 5.
11 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the present invention.
12 is a cross-sectional view taken along line AA′ of FIG. 11.
13 to 16 are cross-sectional views illustrating semiconductor memory devices according to some embodiments of the present invention.
17 and 18 are cross-sectional views illustrating a semiconductor package according to some embodiments of the present invention.
19 to 25B are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor memory device according to some embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1 is an exemplary circuit diagram for describing a semiconductor memory device according to some embodiments of the present invention.

Referring to FIG. 1, a memory cell array of a semiconductor memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

The plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may be spaced apart from each other and extend in the first direction X, respectively. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

The common source line CSL may extend in a second direction Y crossing the first direction X. In some embodiments, a plurality of common source lines CSL may be two-dimensionally arranged. For example, the plurality of common source lines CSL may be spaced apart from each other and extend in the second direction Y, respectively. The same voltage may be electrically applied to the common source lines CSL, or different voltages may be applied and controlled separately.

Each cell string CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and a ground select transistor GST and a string select transistor. A plurality of memory cell transistors MCTs disposed between (SST) may be included. Each memory cell transistor MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistor MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, a ground selection line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2n, and a string selection line SSL may be disposed between the common source line CSL and the bit line BL. The ground selection line GSL can be used as a gate electrode of the ground selection transistor GST, and the word lines WL11 to WL1n and WL21 to WL2n can be used as gate electrodes of the memory cell transistors MCT, and string selection The line SSL may be used as a gate electrode of the string selection transistor SST.

In some embodiments, the erase control transistor ECT may be disposed between the common source line CSL and the ground select transistor GST. The common source line CSL may be commonly connected to sources of the erase control transistors ECT. Also, an erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistors ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

2 and 3 are schematic cross-sectional views illustrating semiconductor memory devices according to some embodiments of the present invention. FIG. 4 is an enlarged view illustrating an area E1 of FIG. 2.

Referring to FIG. 2, a semiconductor memory device according to some embodiments may include a peripheral circuit area PERI and a cell area CELL.

The peripheral circuit area PERI includes a first substrate 100, an interlayer insulating layer 150, a plurality of circuit elements TR1, TR2, TR3, 220a, 220b formed on the first substrate 100, and a plurality of circuit elements. The first metal layers 144, 230a, 230b connected to each of the TR1, TR2, TR3, 220a, 220b, and the second metal layer 240 formed on the first metal layers 144, 230a, 230b, 240a, 240b) may be included.

In some embodiments, the first to third circuit elements TR1, TR2, and TR3 may provide a decoder circuit in the peripheral circuit area PERI. In some embodiments, the fourth circuit element 220a may provide a logic circuit in the peripheral circuit area PERI. In some embodiments, the fifth circuit device 220b may provide a page buffer in the peripheral circuit area PERI.

In this specification, only the first metal layers 144, 230a, and 230b and the second metal layers 240, 240a, and 240b are shown and described, but are not limited thereto, and the second metal layers 240, 240a, and 240b At least one metal layer may be further formed thereon. At least some of the one or more metal layers formed on the second metal layers 240, 240a, and 240b are formed of aluminum or the like having a lower resistance than copper forming the second metal layers 240, 240a, and 240b Can be.

In some embodiments, the first metal layers 144, 230a, and 230b may be formed of tungsten having a relatively high resistance, and the second metal layers 240, 240a, and 240b may be formed of copper having a relatively low resistance. I can.

The interlayer insulating layer 150 covers the plurality of circuit elements TR1, TR2, TR3, 220a, 220b, the first metal layers 144, 230a, 230b, and the second metal layers 240, 240a, 240b. It may be disposed on the first substrate 100.

The cell area CELL may provide at least one memory block. The cell region CELL may include a second substrate 310 and a conductive line 320. On the second substrate 310, a plurality of word lines may be stacked along a vertical direction Z crossing the upper surface of the second substrate 310.

The plurality of word lines may correspond to upper gate layers UCL1 to UCLN and lower gate layers LCL1 to LCLN. A string selection line SSL and a ground selection line GSL may be disposed above and below each of the word lines, and a plurality of word lines may be disposed between the string selection lines SSL and the ground selection line GSL. I can.

The channel structure CH may extend in the vertical direction Z to pass through word lines, string selection lines SSL, and ground selection lines GSL. As shown in FIG. 4, the channel structure CH may include a channel pattern 420 and an information storage layer 430.

The channel pattern 420 may extend in the third direction Z. The channel pattern 420 is illustrated as having a cup shape, but this is only an example, and the channel pattern 420 may have various shapes such as a cylindrical shape, a square cylinder shape, and a filled filler shape. The channel pattern 420 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nano structure, but is not limited thereto.

The information storage layer 430 may be interposed between the channel pattern 420 and word lines. For example, the information storage layer 430 may extend along a side surface of the channel pattern 420.

In some embodiments, the information storage layer 430 may be formed of multiple layers. For example, the information storage layer 430 may include a tunnel insulating layer 431, a charge storage layer 432, and a barrier layer 397c sequentially stacked on the channel pattern 420. The tunnel insulating layer 431 may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). . The charge storage layer 432 may include, for example, silicon nitride. The barrier layer 397c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide.

In some embodiments, the channel structure CH may further include a core pattern 410. The core pattern 410 may be formed to fill the inside of the cup-shaped channel pattern 420. The core pattern 410 may include an insulating material, for example, silicon oxide, but is not limited thereto.

The conductive line 320 may be formed to be connected to the channel pattern 420 of the channel structure CH. Referring to FIG. 3, a semiconductor memory device according to some embodiments may have a chip to chip (C2C) structure. .

In the C2C structure, an upper chip including a cell region (CELL) is manufactured on a first wafer, and a lower chip including a peripheral circuit region (PERI) is manufactured on a second wafer different from the first wafer, and then the upper It may mean that the chip and the lower chip are connected to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on an uppermost metal layer of an upper chip and a bonding metal formed on an uppermost metal layer of a lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

In some embodiments, each of the peripheral circuit area PERI and the cell area CELL may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The word line bonding area WLBA may be defined as an area in which a plurality of cell contact plugs 340 and the like are disposed. Lower bonding metals 271b and 272b may be formed on the second metal layer 240 of the word line bonding region WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to each other through a bonding method with the upper bonding metals 371b and 372b of the cell area CELL. . The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, or tungsten. The cell contact plugs 340 are peripheral circuits through the upper bonding metals 371b and 372b of the cell area CELL and the lower bonding metals 271b and 272b of the peripheral circuit area PERI in the word line bonding area WLBA. It can be connected to the area (PERI).

The bit line bonding area BLBA may be defined as an area in which the channel structure CH and the bit line 360c are disposed. The bit line 360c may be electrically connected to the fifth circuit element 220b in the bit line bonding area BLBA. For example, the bit line 360c is connected to the upper bonding metals 371c and 372c in the peripheral circuit region PERI, and the upper bonding metals 371c and 372c are the lower bonding metals connected to the fifth circuit element 220b. (271c, 272c) can be connected.

A common source line contact plug 380 may be disposed in the external pad bonding area PA. The common source line contact plug 380 is formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the conductive line 320. A first metal layer 350a and a second metal layer 360a may be sequentially stacked on the common source line contact plug 380. For example, an area in which the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as an external pad bonding area PA. Also, input/output pads 205 and 305 may be disposed in the external pad bonding area PA.

In each of the outer pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or The top metal layer may be empty.

In the semiconductor memory device according to some embodiments, in the outer pad bonding area PA, a cell is formed in the uppermost metal layer of the peripheral circuit area PERI in correspondence with the upper metal pattern 372a formed on the uppermost metal layer of the cell area CELL. The lower metal pattern 273a having the same shape as the upper metal pattern 372a of the region CELL may be formed. The lower metal pattern 273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in response to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI in the outer pad bonding region PA, the lower metal pattern of the peripheral circuit region PERI is formed on the upper metal layer of the cell region CELL. An upper metal pattern having the same shape as may be formed.

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 272d formed on the uppermost metal layer of the peripheral circuit area PERI. The upper metal pattern 372d having the same shape as the metal pattern 272d may be formed. A contact may not be formed on the upper metal pattern 372d formed on the uppermost metal layer of the cell region CELL.

As shown in FIG. 4, in some embodiments, the channel structure CH may pass through the conductive line 320 and be buried in the second substrate 310. The conductive line 320 may pass through a portion of the information storage layer 430 and may be connected to a side surface of the channel pattern 420.

The channel structure CH may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In some embodiments, the bit line 360c may extend along a direction parallel to the top surface of the second substrate 310 (eg, the second direction Y). In some embodiments, the bit line 360c may be electrically connected to the fifth circuit element 230b providing a page buffer in the peripheral circuit area PERI.

The word lines may extend in a direction parallel to the top surface of the second substrate 310 (eg, the first direction X), and may be connected to a plurality of cell contact plugs 340. The word lines and the cell contact plugs 340 may be connected to each other by pads provided by extending at least some of the word lines to different lengths. A first metal layer 350b and a second metal layer 360b may be sequentially connected on top of the cell contact plugs 340 connected to the word lines.

In some embodiments, the cell contact plugs 340 may be electrically connected to the first to third circuit elements TR1, TR2, and TR3 providing a decoder circuit in the peripheral circuit area PERI. For example, the first metal layer 350b connected to the cell contact plugs 340 may be connected to the first metal layer 350d by the second metal layer 360b. The first metal layer 350d may be connected to the second metal layer 240 through a connection contact plug 345. Accordingly, the first to third circuit elements TR1, TR2, and TR3 may be electrically connected to the word lines. For example, the first circuit device TR1 may be electrically connected to some of the word lines, the second circuit device TR2 may be electrically connected to the other part of the word lines, and the third circuit device ( TR3) may be electrically connected to another part of the word lines.

In some embodiments, the operating voltage of the first to third circuit elements TR1, TR2, and TR3 may be different from the operating voltage of the fifth circuit element 220b providing a page buffer. For example, the operating voltage of the fifth circuit element 220b may be greater than the operating voltage of the first to third circuit elements TR1, TR2, and TR3.

The common source line contact plug 380 may be electrically connected to the conductive line 320. The common source line contact plug 380 may be formed of a conductive material such as a metal, a metal compound, or polysilicon, and a first metal layer 350a may be formed on the common source line contact plug 380.

In some embodiments, a lower insulating layer 201 covering a lower surface of the first substrate 100 may be formed under the first substrate 100, and the first input/output pad 205 may be formed on the lower insulating layer 201. Can be formed. The first input/output pad 205 is connected to at least one of a plurality of circuit elements TR1, TR2, TR3, 220a, 220b arranged in the peripheral circuit area PERI through the first input/output contact plug 203, It may be separated from the first substrate 100 by the lower insulating layer 201. In addition, a side insulating layer is disposed between the first input/output contact plug 203 and the first substrate 100 to electrically separate the first input/output contact plug 203 from the first substrate 100.

In some embodiments, an upper insulating layer 301 covering an upper surface of the second substrate 310 may be formed on the second substrate 310, and a second input/output pad 305 may be formed on the upper insulating layer 301. Can be placed. The second input/output pad 305 may be connected to at least one of a plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit area PERI through the second input/output contact plug 303. .

In some embodiments, the second substrate 310 and the conductive line 320 may not be disposed in a region where the second input/output contact plug 303 is disposed. Also, the second input/output pad 305 may not overlap with word lines in the vertical direction (Z). The second input/output contact plug 303 is separated from the second substrate 310 in a direction parallel to the top surface of the second substrate 310 (for example, in the first direction X), and the cell area CELL It may be connected to the second input/output pad 305 through the interlayer insulating layer 315.

In some embodiments, the first input/output pad 205 and the second input/output pad 305 may be selectively formed. As an example, the semiconductor memory device according to some embodiments includes only the first input/output pad 205 disposed on the first substrate 100, or the second input/output pad 305 disposed on the second substrate 310. ) Can also be included. Alternatively, the semiconductor memory device according to some embodiments may include both the first input/output pad 205 and the second input/output pad 305.

5 to 8 are various cross-sectional views illustrating a semiconductor memory device according to some embodiments of the present invention. Descriptions overlapping with the above-described embodiments will be simplified or omitted.

For reference, FIGS. 5 to 8 are diagrams illustrating an enlarged area E2 of FIG. 2.

Referring to FIG. 5, a semiconductor memory device includes a lower stack structure 210, an upper stack structure 220, a channel hole 300, a channel structure CH, a bit pad 440, and a conductive line 320. I can.

The lower stack structure 210 may include a plurality of lower insulating layers LIL1 to LILN and a plurality of lower gate layers LCL1 to LCLN. A plurality of lower insulating layers LIL1 to LILN and a plurality of lower gate layers LCL1 to LCLN may be disposed on the substrate 310. The plurality of lower insulating layers LIL1 to LILN and the plurality of lower gate layers LCL1 to LCLN may be alternately stacked.

The plurality of lower gate layers LCL1 to LCLN may be formed of a metal, a metal compound, or a conductive material such as polysilicon. The plurality of lower gate layers LCL1 to LCLN may include, for example, SiN ₄ . The plurality of lower gate layers LCL1 to LCLN may correspond to the word line WL.

The plurality of lower insulating layers LIL1 to LILN may include, for example, an insulating material such as SiO ₂ .

The upper stacked structure 220 may be disposed on the lower stacked structure 210. The upper stack structure 220 may include a plurality of upper insulating layers UIL1 to UILN and a plurality of upper gate layers UCL1 to UCLN. A plurality of upper insulating layers UIL1 to UILN and a plurality of upper gate layers UCL1 to UCLN may be disposed on the substrate 310. A plurality of upper insulating layers (UIL1 to UILN) and a plurality of upper gate layers (UCL1 to UCLN) may be alternately stacked.

The plurality of upper gate layers UCL1 to UCLN may be formed of a metal, a metal compound, or a conductive material such as polysilicon. The plurality of upper gate layers UCL1 to UCLN may include, for example, SiN ₄ . The plurality of upper gate layers UCL1 to UCLN may correspond to a plurality of word lines.

The plurality of upper insulating layers UIL1 to UILN may include, for example, an insulating material such as SiO ₂ .

The channel hole 300 may include a lower channel hole 300H1 and an upper channel hole 300H2.

The lower channel hole 300H1 may be disposed on the conductive line 320. The lower channel hole 300H1 may pass through the lower stacked structure 210.

The lower channel hole 300H1 may be formed in a shape that becomes narrower downward. The shape of the lower channel hole 300H1 is only an example, and the technical idea of the present invention is not limited thereto.

The upper channel hole 300H2 may be disposed on the lower channel hole 300H1. The upper channel hole 300H2 may be connected to the lower channel hole 300H1. The upper channel hole 300H2 may pass through the upper stacked structure 220.

The upper channel hole 300H2 may be formed in a shape that becomes narrower downward. The shape of the lower channel hole 300H1 is only an example, and the technical idea of the present invention is not limited thereto.

The channel structure CH may be disposed in the channel hole 300. The channel structure CH may include a core pattern 410, a channel pattern 420, and an information storage layer 430.

The information storage layer 430 may include a tunnel insulating layer 431, a charge storage layer 432, a barrier layer 433, and a lower barrier pattern 434.

The lower barrier pattern 434 may surround a part of the outer side of the barrier layer 433. The lower barrier pattern 434 may be disposed between the barrier layer 433 and the lower stack structure 210. The lower barrier pattern 434 may not be disposed between the barrier layer 433 and the upper stacked structure 220.

The lower barrier pattern 434 may extend in one direction. The lower barrier pattern 434 may extend parallel to the barrier layer 433. The lower barrier pattern 434 may contact the barrier layer 433.

The lower barrier pattern 434 may include an insulating material such as SiO ₂ .

In FIG. 5, the structure of the lower barrier pattern 434 is shown to extend in one direction, but the technical idea of the present invention is not limited thereto.

At heights corresponding to each other, the barrier layer 433 may have a first thickness W1 and the lower barrier pattern 434 may have a second thickness W2.

The first thickness W1 and the second thickness W2 may be the same. However, this is only an example, and the technical idea of the present invention is not limited thereto.

For example, referring to FIG. 6, the first thickness W1 may be greater than the second thickness W2.

As another example, although not shown, the first thickness W1 may be smaller than the second thickness W2.

The substrate 310 may include a conductive impurity region. The conductive impurity region may correspond to the common source line CSL of FIG. 1.

The channel pattern 420 of the channel structure CH may be electrically connected to a conductive impurity region included in the substrate 310.

Referring to FIG. 7, the lower barrier pattern 434 is disposed between the barrier layer 433 and the lower gate layers LCL1 to LCLN, and is not disposed between the barrier layer 433 and the upper gate layers UCL1 to UCLN. May not. In addition, the lower barrier pattern 434 may be disposed between the barrier layer 433 and the lower insulating layers LIL1 to LILN, and may not be disposed between the barrier layer 433 and the upper insulating layers UIL1 to UILN.

Referring to FIG. 8, the barrier layer 433 may include a first barrier layer 433a and a second barrier layer 433b.

The first barrier layer 433a and the second barrier layer 433b may be disposed along the profile of the channel hole 300. The second barrier layer 433b may be disposed between the first barrier layer 433a and the charge storage layer 432.

The first barrier layer 433a and the second barrier layer 433b may extend in one direction. The first barrier layer 433a and the second barrier layer 433b may extend parallel to the charge storage layer 432. The second barrier layer 433b may contact the charge storage layer 432.

9 and 10 are cross-sectional views taken along line AA′ of FIG. 5. Descriptions overlapping with the above-described embodiments will be simplified or omitted.

For reference, FIGS. 9 and 10 are diagrams for explaining the channel structure CH of the semiconductor memory device of the present invention.

Referring to FIG. 9, the channel structure CH includes a barrier layer 433, a charge storage layer 432, a tunnel insulating layer 431, and a channel pattern 420 sequentially formed along the profile of the channel hole 300. And a core pattern 410.

The core pattern 410 may be formed on the lower barrier pattern 434. The core pattern 410 may fill the lower channel hole 300H1.

The core pattern 410 may be formed in a circular shape. However, the shape of the core pattern 410 is only an example, and the technical idea of the present invention is not limited thereto.

For example, as shown in FIG. 9, the core pattern 410 may be formed in a distorted circle shape.

At a position spaced apart from the upper surface of the substrate 310 by the first height, the thickness of the lower barrier pattern 434 may be uniform. However, the thickness of the lower barrier pattern 434 is only an example, and the technical idea of the present invention is not limited thereto.

For example, as illustrated in FIG. 10, at a position spaced apart from the upper surface of the substrate 310 by a first height, the thickness of the lower barrier pattern 434 may be non-uniform.

11 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the present invention. 12 is a cross-sectional view taken along line AA′ of FIG. 11. For convenience of explanation, the description will focus on differences from those described with reference to FIGS. 5 to 10.

For reference, FIG. 11 is a diagram illustrating an enlarged area E2 of FIG. 2.

Referring to FIG. 11, the lower channel hole 300H1 may include a first sidewall and a second sidewall.

The first sidewall and the second sidewall may face each other.

The lower barrier pattern 434 may be formed along profiles of the first sidewall and the second sidewall of the lower channel hole 300H1.

The upper surface of the lower barrier pattern 434 on the first sidewall of the lower channel hole 300H1 may be located at the first level. The upper surface of the lower barrier pattern 434 on the second sidewall of the lower channel hole 300H1 may be located at the second level.

The height of the uppermost portion of the lower barrier pattern 434 on the first sidewall of the lower channel hole 300H1 may be different from the height of the uppermost portion of the lower barrier pattern 434 on the second sidewall of the lower channel hole 300H1. For example, the height of the top of the lower barrier pattern 434 on the first sidewall of the lower channel hole 300H1 may be greater than the height of the top of the lower barrier pattern 434 on the second sidewall of the lower channel hole 300H1. have.

Referring to FIG. 12, the lower barrier pattern 434 may be formed on the first sidewall of the lower channel hole 300H1. The lower barrier pattern 434 may not be formed on the second sidewall of the lower channel hole 300H1.

Accordingly, referring to FIG. 12, at a position spaced apart from the upper surface of the substrate by a second height, the channel structure CH may include a first region R1 and a second region R2.

The first region R1 may include a lower barrier pattern 434. The lower barrier pattern 434 may be disposed along the outer periphery of the barrier layer 433.

The second region R2 may not include the lower barrier pattern 434. Accordingly, in the second region R2, the channel structure CH has a barrier layer 433, a charge storage layer 432, a tunnel insulating layer 431, and a channel pattern sequentially formed along the profile of the channel hole 300. It may be composed of 420 and a core pattern 410.

13 to 16 are cross-sectional views illustrating semiconductor memory devices according to some embodiments of the present invention. Descriptions overlapping with the above-described embodiments will be simplified or omitted.

For reference, FIGS. 13 to 16 are enlarged cross-sectional views of an area E3 of FIG.

13 and 14, in the semiconductor memory device according to some embodiments of the present invention, the outer side of the lower barrier pattern 434 may be flat.

That is, sidewalls of the lower stacked structure 210 disposed on the outer side of the lower barrier pattern 434 may be formed flat. Sidewalls of the lower stacked structure 210 may not be curved.

The lower insulating layers LIL1 to LILN and the lower gate layers LCL1 to LCLN constituting the lower stacked structure 210 may be disposed in a shape that does not protrude toward the lower barrier pattern 434. This is only exemplary, and the technical idea of the present invention is not limited thereto.

For example, the lower gate layers LCL1 to LCLN may protrude in a direction toward the lower barrier pattern 434. Accordingly, the thickness of the lower barrier pattern 434 between the lower gate layers LCL1 to LCLN and the barrier layer 433 may be reduced.

As another example, the lower insulating layers LIL1 to LILN may protrude in a direction toward the lower barrier pattern 434. Accordingly, the thickness of the lower barrier pattern 434 between the lower insulating layers LIL1 to LILN and the barrier layer 433 may be reduced.

Referring to FIG. 15, the lower gate layer LCL1 according to some embodiments of the present invention may include a high dielectric constant insulating layer 435 and a gate electrode 439.

The high dielectric constant insulating layer 435 may be disposed on the channel structure CH. The high dielectric constant insulating layer 435 and the gate electrode 439 may be sequentially disposed on the channel structure CH, respectively.

The high dielectric constant insulating layer 435 may extend along a side surface of the gate electrode 439.

The high dielectric constant insulating layer 435 may contact the lower barrier pattern 434 and the gate electrode 439. The arrangement of the high dielectric constant insulating layer 435 is only an example, and the technical idea of the present invention is not limited thereto.

The high-k insulating layer 435 may include silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )).

For reference, the semiconductor memory device according to some embodiments of the present invention may further include a gate barrier layer 436.

The gate barrier layer 436 may be disposed on the channel structure CH. The gate barrier layer 436 may be formed along the outer side of the high dielectric constant insulating layer 435. The gate barrier layer 436, the high dielectric constant insulating layer 435, and the gate electrode 439 may be sequentially disposed on the channel structure CH.

The gate barrier layer 436 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide.

Referring to FIG. 16, the high dielectric constant insulating layer 435 may be disposed between the lower barrier pattern 434 and the barrier layer 433.

The high dielectric constant insulating layer 435 may extend in one direction. The high dielectric constant insulating layer 435 may extend parallel to the barrier layer 433.

The high dielectric constant insulating layer 435 may contact the barrier layer 433. The high-k insulating layer 435 may contact the lower gate layers LCL1 to LCLN and the lower barrier pattern 434.

A second sacrificial layer 437 may be formed between the lower barrier pattern 434 and the high-k insulating layer 435. The second sacrificial layer 437 may be formed between the barrier layer 433 and the upper stacked structure 220.

The high dielectric constant insulating layer 435 may be disposed along a portion of the side surface of the second sacrificial layer 437.

17 and 18 are cross-sectional views illustrating a semiconductor package according to some embodiments of the present invention.

Referring to FIG. 17, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body part 2120, package upper pads disposed on an upper surface of the package substrate body part 2120, and a lower pad disposed on or exposed through the lower surface of the package substrate body part 2120. They 2125 and internal wirings 2135 electrically connecting the upper pads and the lower pads 2125 inside the package substrate body 2120 may be included. The upper pads may be electrically connected to the connection structures. Although not shown, the lower pads 2125 may be connected to wiring patterns of the main substrate of the electronic system through conductive connection portions 2800.

Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The semiconductor substrate 3010 may correspond to the first substrate 100 of FIG. 2. The first structure 3100 may correspond to the peripheral circuit area PERI of FIG. 2, and the second structure 3200 may correspond to the cell area CELL of FIG. 2.

For example, the second structure 3200 may include a second substrate 310, a plurality of word lines, a channel structure CH, and a plurality of cell contact plugs 340. Each of the semiconductor chips 2200 may further include an input/output pad electrically connected to the first structure 3100.

Referring to FIG. 18, in the semiconductor package 2003A, each of the semiconductor chips 2200 may include a first structure 3100 and a second structure 3200 bonded by a wafer bonding method. For example, the first structure 3100 may correspond to the peripheral circuit area PERI of FIG. 2, and the second structure 3200 may correspond to the cell area CELL of FIG. 2.

The semiconductor chips 2200 of FIGS. 17 and 18 may be electrically connected to each other by bonding wire-type connection structures. However, in some embodiments, semiconductor chips in one semiconductor package such as the semiconductor chips 2200 of FIGS. 17 and 18 may be electrically connected to each other by a connection structure including a through electrode TSV.

19 to 25B are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor memory device according to some embodiments of the present invention. Descriptions overlapping with the above-described embodiments will be simplified or omitted.

Referring to FIG. 19, a conductive line 320, a plurality of lower insulating layers LIL1 to LILN, and a plurality of lower sacrificial layers LSL1 to LSLN may be formed.

The conductive line 320 may be disposed on the substrate.

A plurality of lower insulating layers LIL1 to LILN and a plurality of lower sacrificial layers LSL1 to LSLN may be disposed on the conductive line 320. A plurality of lower insulating layers LIL1 to LILN and a plurality of lower sacrificial layers LSL1 to LSLN may be alternately stacked.

A plurality of lower insulating layers LIL1 to LILN and a plurality of lower sacrificial layers LSL1 to LSLN alternately stacked may constitute the lower stack structure 210.

Thereafter, a lower channel hole 300H1 penetrating the lower stack structure 210 may be formed.

20A and 20B, a lower barrier pattern 434 and a first sacrificial layer 410a may be formed.

For reference, FIG. 20A is a view for explaining the lower barrier pattern 434 formed through a deposition process.

The lower barrier pattern 434 may be disposed along the profile of the lower channel hole 300H1.

The lower barrier pattern 434 may be formed through a deposition process. Accordingly, the lower barrier pattern 434 may extend in one direction.

The first sacrificial layer 410a may be disposed on the lower barrier pattern 434. The lower channel hole 300H1 may be filled by the first sacrificial layer 410a.

For reference, FIG. 20B is a view for explaining the lower barrier pattern 434 formed through an oxidation process.

The lower barrier pattern 434 may be disposed between the barrier layer 433 and the plurality of lower sacrificial layers LSL1 to LSLN, and not disposed between the barrier layer 433 and the plurality of lower insulating layers LIL1 to LILN. May not.

The lower barrier pattern 434 may be formed through an oxidation process. Accordingly, the lower barrier pattern 434 is disposed between the first sacrificial layer 410a and the plurality of lower sacrificial layers LSL1 to LSLN, and between the first sacrificial layer 410a and the plurality of lower insulating layers LIL1 to LILN. Can be.

The method of processing the lower barrier pattern 434 is only an example, and the technical idea of the present invention is not limited thereto.

For example, the lower barrier pattern 434 may be formed through a deposition process and an oxidation process thereafter.

The first sacrificial layer 410a may be disposed on the lower barrier pattern 434 and the plurality of lower sacrificial layers LSL1 to LSLN. The lower channel hole 300H1 may be filled by the first sacrificial layer 410a.

Referring to FIG. 21, a plurality of upper insulating layers UIL1 to UILN and a plurality of upper sacrificial layers USL1 to USLN may be formed.

A plurality of upper insulating layers UIL1 to UILN and a plurality of upper sacrificial layers USL1 to USLN may be disposed on the lower stacked structure 210. A plurality of upper insulating layers (UIL1 to UILN) and a plurality of upper sacrificial layers (USL1 to USLN) may be alternately stacked.

A plurality of upper insulating layers UIL1 to UILN and a plurality of upper sacrificial layers USL1 to USLN alternately stacked may constitute the upper stacked structure 220.

Referring to FIG. 22, an upper channel hole 300H2 may be formed. The first sacrificial layer 410a may be removed.

The upper channel hole 300H2 may pass through the upper stacked structure 220.

The upper channel hole 300H2 may be connected to the lower channel hole 300H1. The lower channel hole 300H1 and the upper channel hole 300H2 may constitute a channel hole 300.

Referring to FIG. 23, a barrier layer 433 may be formed.

The barrier layer 433 may be disposed along a sidewall of the upper channel hole 300H2 and a profile of the lower barrier pattern 434.

Referring to FIG. 24, a charge storage layer 432, a tunnel insulating layer 431, a channel pattern 420, a core pattern 410, and a bit pad 440 may be formed.

The barrier layer 433, the charge storage layer 432, the tunnel insulating layer 431, and the channel pattern 420 may be sequentially formed along the profile of the channel hole 300.

The core pattern 410 may be formed to fill the inside of the cup-shaped channel pattern 420. The core pattern 410 may include an insulating material, for example, silicon oxide, but is not limited thereto.

The bit pad 440 may be formed on the upper surface of the barrier layer 433, the charge storage layer 432, the tunnel insulating layer 431, the channel pattern 420, and the core pattern 410.

Referring to FIGS. 25A and 25B, the conductive line 320 may be connected to the channel pattern 420.

Specifically, the third sacrificial layer 321 may be removed together with a part of the lower barrier pattern 434, a part of the barrier layer 433, a part of the charge storage layer 432, and a part of the tunnel insulating layer 431. . A conductive line ( 320) can be formed.

The lower sacrificial layers LSL1 to LSLN and the upper sacrificial layers USL1 to USLN may be removed. Thereafter, the lower gate layers LCL1 to LCLN and the upper gate layers UCL1 to UCLN may be formed.

For reference, FIG. 25A is a diagram for describing a semiconductor memory device having a lower barrier pattern 434 formed through a deposition process, and FIG. 25B is a diagram illustrating a semiconductor memory device having a lower barrier pattern 434 formed through an oxidation process. It is a drawing to do.

Some of the lower barrier pattern 434, the barrier layer 433, the charge storage layer 432, and the tunnel insulating layer 431 may be removed, respectively. The conductive line 320 may be filled through a portion of the removed lower barrier pattern 434, the barrier layer 433, the charge storage layer 432, and the tunnel insulating layer 431. Accordingly, the conductive line 320 may be connected to the channel pattern 420.

A plurality of lower gate layers LCL1 to LCLN may be formed in a region from which the plurality of lower sacrificial layers LSL1 to LSLN have been removed. A plurality of upper gate layers UCL1 to UCLN may be formed through the region from which the plurality of upper sacrificial layers USL1 to USLN have been removed.

After the process of connecting the conductive lines 320, a process of forming a gate layer may be performed.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those skilled in the art to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting.

1000: semiconductor device 200, 210, 220: stacked structure
300: channel hole 400: channel structure
420: channel pattern 430: information storage pattern
431: tunnel insulating layer 432: charge storage layer
433: barrier layer 434: lower barrier pattern
LIL, UIL: insulating layer LCL, UCL: gate layer

Claims (10)

A substrate having a cell region and a connection region adjacent to the cell region;
A lower stack structure having a plurality of lower insulating layers and a plurality of lower gate layers alternately stacked on the substrate;
An upper stack structure having a plurality of upper insulating layers and a plurality of upper gate layers alternately stacked on the lower stack structure;
A channel hole including a lower channel hole penetrating the lower stack structure and an upper channel hole penetrating the upper stack structure, the upper channel hole extending from the lower channel hole; And
Including a channel structure in the channel hole,
The channel structure includes a barrier layer sequentially formed along the profile of the channel hole, a charge storage layer, a tunnel insulating layer, and a channel pattern,
The channel structure is disposed between the barrier layer and the lower gate layer, and includes a lower barrier pattern not disposed between the barrier layer and the upper gate layer. The method of claim 1,
At a height corresponding to each other, a thickness of the lower barrier pattern is different from that of the barrier layer. The method of claim 1,
The lower barrier pattern is disposed between the barrier layer and the lower insulating layer, and is not disposed between the barrier layer and the upper insulating layer. The method of claim 1,
The barrier layer includes a first barrier layer and a second barrier layer disposed along a profile of the channel hole,
The second barrier layer is a semiconductor memory device disposed between the first barrier layer and the charge storage layer. The method of claim 1,
A semiconductor memory device having a non-uniform thickness of the lower barrier pattern at a position spaced apart from the upper surface of the substrate by a first height. The method of claim 1,
The lower channel hole includes first sidewalls and second sidewalls facing each other,
A height of an uppermost portion of the lower barrier pattern on the first sidewall of the lower channel hole is different from a height of an uppermost portion of the lower barrier pattern on the second sidewall of the lower channel hole. The method of claim 1,
Each of the lower gate layer and the upper gate layer includes a high dielectric constant insulating layer sequentially disposed on the channel structure, and a gate electrode. The method of claim 7,
The high dielectric constant insulating layer is a semiconductor memory device extending along a side surface of the gate electrode. Forming a sacrificial source line on the substrate,
Forming a lower stack structure having a plurality of lower insulating layers and a plurality of lower sacrificial layers alternately stacked on the sacrificial source line,
Forming a lower channel hole penetrating the lower stack structure,
Forming a lower barrier pattern disposed along the profile of the lower channel hole,
Forming a first sacrificial layer filling the lower channel hole on the lower barrier pattern,
On the lower stack structure, an upper stack structure having a plurality of upper insulating layers and a plurality of upper sacrificial layers alternately stacked is formed,
Forming an upper channel hole passing through the upper stacked structure and connected to the lower channel hole,
Removing the first sacrificial layer,
Forming a barrier layer disposed along a sidewall of the upper channel hole and a profile of the lower barrier pattern,
Remove the sacrificial source line,
Forming a common source line in the region from which the sacrificial source line has been removed,
Removing the plurality of lower sacrificial layers and the plurality of upper sacrificial layers,
Forming a lower gate layer in the region from which the plurality of lower sacrificial layers have been removed,
Forming an upper gate layer in a region from which the plurality of upper sacrificial layers have been removed,
The lower barrier pattern is disposed between the barrier layer and the lower gate layer, and is not disposed between the barrier layer and the upper gate layer. The method of claim 9,
The method of manufacturing a semiconductor memory device, wherein the lower barrier pattern is formed using at least one of an oxidation process and a deposition process.

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