KR20200128808A - Semiconductor package - Google Patents

Abstract

The present invention relates to a semiconductor package with a new structure capable of properly disposing more passive components compared to the same area even though a space for disposing the passive components is limited due to the reduction in package size. The semiconductor package comprises: a connection structure including one or more redistribution layers; a semiconductor chip disposed below the connection structure and having a connection pad electrically connected to the redistribution layers; a first passive component disposed below the connection structure and disposed around the side surface of the semiconductor chip; a second passive component disposed below the first passive component and disposed around the side surface of the semiconductor chip; and a sealing material covering at least a part of each of the semiconductor chip, the first passive component, and the second passive component.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The present disclosure relates to a semiconductor package.

Recently, one of the major trends in technology development for semiconductor chips is to reduce the size of components, and thus, in the package field, it is required to implement a large number of pins while having a small size in accordance with the rapid increase in demand for small semiconductor chips. .

One of the package technologies proposed to meet this is a fan-out package. The fan-out package allows the connection terminal to be rewired outside the area where the semiconductor chip is disposed, so that a large number of pins can be implemented while having a small size.

Meanwhile, in recent years, the portable electronic device market such as netbooks, tablet PCs, smartphones, and portable game consoles occupies most of the semiconductor market, and as the demand for high-speed portable electronic devices increases, low power is required, as well as It is required that power supply is smoothly performed even in a switching situation.

One of the various objects of the present disclosure is to provide a semiconductor package with a new structure capable of appropriately arranging more passive components compared to the same area even though the space for arranging passive components is limited due to a reduction in package size. will be.

One of the various solutions proposed through the present disclosure is to arrange a passive component in a plurality of layers around the semiconductor chip and seal it together with the semiconductor chip.

For example, a semiconductor package according to an example includes: a connection structure including one or more redistribution layers; A semiconductor chip disposed under the connection structure and having a connection pad electrically connected to the redistribution layer; A first passive component disposed under the connection structure and disposed around a side surface of the semiconductor chip; A second passive component disposed below the first passive component and disposed around a side surface of the semiconductor chip; And a sealing material covering at least a portion of each of the semiconductor chip, the first passive component, and the second passive component. It may include.

One of the effects of the present disclosure is to provide a semiconductor package with a new structure capable of appropriately arranging more passive components compared to the same area, although space for arranging passive components is limited due to a reduction in package size. can do.

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3A and 3B are cross-sectional views schematically illustrating a fan-in semiconductor package before and after packaging.
4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.
5 is a schematic cross-sectional view showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.
6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.
7 is a schematic cross-sectional view of a fan-out semiconductor package.
8 is a schematic cross-sectional view illustrating a case where a fan-out semiconductor package is mounted on a main board of an electronic device.
9 is a schematic cross-sectional view of an example of a semiconductor package.
FIG. 10 is a schematic cut-away plan view of the semiconductor package of FIG. 9.
11 is a schematic cross-sectional view of another example of a semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates a main board 1010. A chip set-related part 1020, a network-related part 1030, and other parts 1040 are physically and/or electrically connected to the main board 1010. These are also combined with other components to be described later to form various signal lines 1090.

The chip set related parts 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included, but are not limited thereto, and other types of chip-related components may be included in addition to this. Also, of course, these parts 1020 may be combined with each other.

Network-related parts 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such and beyond, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, it goes without saying that the network-related parts 1030 may be combined with each other together with the chip set-related parts 1020.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser). , It is not limited thereto, and in addition, passive components used for various other purposes may be included. In addition, it goes without saying that the other parts 1040 may be combined with each other together with the chip set related parts 1020 and/or the network related parts 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. For example, the camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (eg, hard disk drive) (not shown), compact disk (CD) (not shown), and DVD There are (digital versatile disk) (not shown), but are not limited thereto, and other parts used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( computer), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and, of course, it may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, a semiconductor package is applied to various electronic devices as described above for various purposes. For example, a printed circuit board 1110 such as a main board is accommodated inside the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically Is connected by In addition, other components that may or may not be physically and/or electrically connected to the printed circuit board 1110 such as the camera 1130 are accommodated in the body 1101. Some of the components 1120 may be chipset related components, for example, the semiconductor package 1121, but are not limited thereto. It goes without saying that the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

Semiconductor package

In general, a semiconductor chip is integrated with a number of microelectronic circuits, but cannot itself serve as a finished semiconductor product, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, but the semiconductor chip is packaged and used in an electronic device.

The reason why semiconductor packaging is necessary is because there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the gap between the connection pads are very small, whereas in the case of a main board used in electronic devices, the size of the component mounting pad and the gap between the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a main board, and a packaging technology capable of buffering the difference in circuit width between each other is required.

Semiconductor packages manufactured by such a packaging technology may be classified into a fan-in semiconductor package and a fan-out semiconductor package according to a structure and use.

Hereinafter, a fan-in semiconductor package and a fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-In Semiconductor Package)

3A and 3B are cross-sectional views schematically illustrating a fan-in semiconductor package before and after packaging.

4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc., and aluminum (Al) formed on one surface of the body 2221. For example, including a connection pad 2222 containing a metallic material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222, It may be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a main board of an electronic device as well as a printed circuit board (PCB) of an intermediate level.

Accordingly, a connection structure 2240 is formed on the semiconductor chip 2220 to match the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. The connection structure 2240 is a via hole 2243h for forming an insulating layer 2241 on the semiconductor chip 2220 with an insulating material such as photo image-able dielectric (PID), and opening the connection pad 2222 ) May be formed, and then a wiring pattern 2242 and a via 2243 may be formed. After that, a passivation layer 2250 for protecting the connection structure 2240 is formed, an opening 2251 is formed, and an under bump metal 2260 or the like is formed. That is, through a series of processes, for example, a fan-in semiconductor package 2200 including a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an under bump metal 2260 is manufactured. do.

As described above, the fan-in semiconductor package is in the form of a package in which all connection pads of a semiconductor chip, such as I/O (Input/Output) terminals, are placed inside the device, and the fan-in semiconductor package has good electrical characteristics and can be produced inexpensively. have. Accordingly, many devices that enter the smartphone are manufactured in the form of fan-in semiconductor packages, and specifically, development is being made in the direction of implementing small and fast signal transmission.

However, the fan-in semiconductor package has many space limitations since all I/O terminals must be placed inside the semiconductor chip. Therefore, this structure has a difficulty in applying to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package cannot be directly mounted and used on the main board of the electronic device. This is because even if the size and spacing of the I/O terminals of the semiconductor chip are enlarged through the rewiring process, they do not have the size and spacing that can be directly mounted on the main board of electronic devices.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.

Referring to the drawings, in the fan-in semiconductor package 2200, the connection pads 2222 of the semiconductor chip 2220, that is, the I/O terminals are rewired once again through the printed circuit board 2301, and finally The fan-in semiconductor package 2200 may be mounted on the main board 2500 of the electronic device while the fan-in semiconductor package 2200 is mounted on the printed circuit board 2301. In this case, the solder ball 2270 may be fixed with an underfill resin 2280 or the like, and the outside may be covered with a molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate printed circuit board 2302, and connection pads of the semiconductor chip 2220 by the printed circuit board 2302 in an embedded state. (2222), that is, the I/O terminals are rewired once again, and may be finally mounted on the main board 2500 of the electronic device.

In this way, since the fan-in semiconductor package is directly mounted on the main board of an electronic device and is difficult to use, it is mounted on a separate printed circuit board and then re-packaged to be mounted on the electronic device main board, or It is used by being mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a schematic cross-sectional view of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by a sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is a connection structure. The rewiring is performed to the outside of the semiconductor chip 2120 by the 2140. In this case, a passivation layer 2150 may be further formed on the connection structure 2140, and an under bump metal 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121 and a connection pad 2122. The connection structure 2140 may include an insulating layer 2141, a wiring layer 2142 formed on the insulating layer 2241, and a via 2143 electrically connecting the connection pad 2122 and the wiring layer 2142, and the like. .

As described above, in the fan-out semiconductor package, the I/O terminals are rearranged and arranged to the outside of the semiconductor chip through the connection structure formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip must be placed inside the semiconductor chip, and when the device size is reduced, the ball size and pitch must be reduced, so a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a form in which the I/O terminals are rearranged and arranged to the outside of the semiconductor chip through the connection structure formed on the semiconductor chip. Even if the size of the semiconductor chip decreases, a standardized ball layout is maintained. Since it can be used as it is, it can be mounted on a main board of an electronic device without a separate printed circuit board as will be described later.

8 is a schematic cross-sectional view illustrating a case where a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, a fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 is a connection structure capable of rewiring the connection pads 2122 on the semiconductor chip 2120 to a fan-out area outside the size of the semiconductor chip 2120 Since the 2140 is formed, a standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of an electronic device without a separate printed circuit board.

In this way, since the fan-out semiconductor package can be mounted on the main board of electronic devices without a separate printed circuit board, it is possible to achieve a smaller thickness and thinner than a fan-in semiconductor package using a printed circuit board. Do. In addition, it is particularly suitable for mobile products due to its excellent thermal and electrical properties. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and can solve a problem due to the occurrence of warpage.

On the other hand, the fan-out semiconductor package refers to a package technology for mounting the semiconductor chip on the main board of an electronic device, and for protecting the semiconductor chip from external impact, and the scale and use thereof are different. It is a different concept from a printed circuit board (PCB) such as a printed circuit board in which a fan-in semiconductor package is embedded.

Hereinafter, a semiconductor package having a new structure capable of appropriately arranging more passive components relative to the same area will be described with reference to the drawings, although the space for arranging passive components is limited due to a reduction in package size. .

9 is a schematic cross-sectional view of an example of a semiconductor package.

FIG. 10 is a schematic cut-away plan view of the semiconductor package of FIG. 9.

Referring to the drawings, a semiconductor package 100A according to an example is disposed under the connection structure 140 including one or more redistribution layers 142 and the connection structure 140, and is electrically connected to the one or more redistribution layers 142. The semiconductor chip 120 having the connected connection pads 120P, the first passive component 170 and the first passive component 170 disposed under the connection structure 140 and disposed around the side of the semiconductor chip 120 The second passive component 180 is disposed below and is disposed around the side of the semiconductor chip 120, and at least a portion of each of the semiconductor chip 120, the first passive component 170, and the second passive component 180 It includes a suture material 130 covering.

In general, when a semiconductor package is mounted on a main board or the like, a connection terminal such as a solder ball is used. These connection terminals are arranged on the other side of the redistribution layer and are electrically connected to the wiring of the redistribution layer. On the other hand, in recent years, a smooth power supply is required, and it is considered to arrange a passive component such as a decoupling capacitor in a part of a region where the connection terminal on the other side of the redistribution layer is disposed. However, since the space in which the connection terminals are arranged is limited, when the number of such decoupling capacitors is increased for smooth power supply, that is, in order to secure capacity, the number of connection terminals that can be arranged decreases. This, conversely, can cause problems with the power supply. As another arrangement form, it may be considered to arrange a passive component around a semiconductor chip on one side of the redistribution layer. However, in this case, only a single layer of passive components are placed within the same area. In the case of a passive component having a thinner thickness compared to a semiconductor chip, the space of the height difference between the semiconductor chip and the passive component after sealing is simply used as a sealing material. Filled, etc., are discarded.

On the other hand, in the semiconductor package 100A according to an example, the first and second passive components 170 and 180 are disposed in parallel with the semiconductor chip 120 under the connection structure 140. Therefore, it does not affect the number of electrical connection metals 160. In addition, since the first and second passive parts 170 and 180 are arranged in a vertically stacked form, it is possible to prevent the space from being wasted. That is, despite the limited space, more passive components 170 and 180 may be disposed around the semiconductor chip 120 within the same area. Accordingly, compared to a conventional semiconductor package, electrical characteristics can be improved without a substantial increase in size.

Meanwhile, the first and second passive components 170 and 180 may be arranged vertically so that at least some of the first and second passive components overlap each other. Through this arrangement, a plurality of passive parts 170 and 180 can be more effectively arranged in a limited space.

On the other hand, the encapsulant 130 includes a first encapsulant 130a covering at least a part of the side surface of the semiconductor chip 120 and at least a part of each of the first passive component 170, and another part of the side surface of the semiconductor chip 120. And a second encapsulant 130b covering at least a portion of each of the second passive components 180. The boundaries of the first and second encapsulants 130a and 130b may be distinguished from each other, and may be integrated depending on materials and processes, and thus the boundary may be unclear. By introducing the first and second encapsulants 130a and 130b, as will be described later, the first and second passive parts 170 and 180 can be more effectively arranged vertically.

Meanwhile, the first passive component 170 may be in the form of a chip having first and second external electrodes 171 and 172 spaced apart from each other, and the third and fourth external electrodes 180 are spaced apart from each other. It may be in the form of a chip having electrodes 181 and 182. That is, these may be passive components in the form of chips that are distinguished from each other. The first and second passive components 170 and 180 may be known passive components, such as capacitors or inductors. The capacitor may be a multi-layer ceramic capacitor (MLCC), and the inductor may be a power inductor (PI), but is not limited thereto.

Meanwhile, a backside wiring layer 135 may be disposed on the lower surface of the encapsulant 130, for example, the lower surface of the second encapsulant 130b. In this case, in an example, the first external electrode 171 of the first passive component 170 may be electrically connected to one or more layers of redistribution layers 142 through the connection via 143 of the connection structure 140, and the first passive component 170 The second external electrode 172 of the component 170 is electrically connected to the fourth external electrode 182 of the second passive component 180 through the first connection via 175 penetrating the first encapsulant 130a. The third external electrode 181 of the second passive component 180 may be electrically connected to the backside wiring layer through the second connection via 185 penetrating the second encapsulant 130b. A vertical electrical connection path from the redistribution layer 142 to the backside wiring layer 135 may be provided through this connection path. In addition, since the first and second passive components 170 and 180 are connected through the first connection via 175, electrical characteristics may be superior compared to a case where they are connected through a separate pattern.

Meanwhile, the semiconductor package 100A according to an example may further include a frame 110 disposed under the connection structure 140 and having a through portion 110H. A semiconductor chip 120 and first and second passive components 170 and 180 may be disposed in the through portion 110H. The encapsulant 130 may fill at least a portion of the through portion 110H. The first and second passive components 170 and 180 may be positioned at a level between the upper and lower surfaces of the frame 110. By introducing the frame 110, the warpage of the package can be more effectively controlled. The frame 110 may include a plurality of wiring layers 112a, 112b, and 112c and a plurality of wiring vias 113a and 113b electrically connecting the plurality of wiring layers 112a, 112b, and 112c. Accordingly, a vertical electrical connection path may be provided through the frame 110. The plurality of wiring layers 112a, 112b, and 112C may be electrically connected to the connection pad 120P through the redistribution layer 142.

Meanwhile, the semiconductor package 100A according to an example may further include a plurality of third passive components 190 disposed above the connection structure 140 and electrically connected to one or more redistribution layers 142, respectively. The plurality of third passive components 190 may be surface mounted using solder paste or the like. Since the plurality of third passive components 190 are electrically connected to the connection pad 120P of the semiconductor chip 120 with the connection structure 140 interposed therebetween, they can have a short electrical connection path, thereby effectively improving electrical characteristics. It can be improved. At least one of the plurality of third passive components 190 may have a relatively larger thickness and size than the first and second passive components 170 and 180. Through this, a more compact design may be possible.

Meanwhile, the semiconductor package 100A according to an example is disposed on an opening of the passivation layer 150 and the passivation layer 150 disposed on the lower surface of the frame 110 and the encapsulant 130 and exposed through the opening. A plurality of electrical connection metals 160 connected to each of the third wiring layer 112c and the backside wiring layer 135 may be further included. Through this, the semiconductor package 100A according to an example may be mounted on other external components, such as a printed circuit board.

Hereinafter, each configuration of the semiconductor package 100A according to an example will be described in more detail with reference to the accompanying drawings.

The frame 110 may maintain the rigidity of the semiconductor package 100A according to an example according to a specific material, and may perform a role of securing uniformity of the thickness of the encapsulant 130. In addition, the frame 110 may provide a vertical electrical connection path within the package. In addition, since the frame 110 includes a plurality of wiring layers 112a, 112b, and 112c, the connection pads 120P of the semiconductor chip 120 can be more effectively rewired, and by providing a wide wiring design area, It is possible to minimize the formation of the redistribution layer in the region. The semiconductor chip 120 and the first and second passive components 170 and 180 are disposed in the through portion 110H to be spaced apart from the wall surface of the through portion 110H by a predetermined distance. However, the present invention is not limited thereto, and the frame 110 may be replaced with other components for vertical electrical connection. For example, it may be replaced with a metal post or the like.

The frame 110 includes a first insulating layer 111a in contact with the connection structure 140, a first wiring layer 112a in contact with the connection structure 140 and buried in the first insulating layer 111a, and a first insulating layer 111a. ), the second wiring layer 112b disposed on the lower surface opposite to the buried side, and the second wiring layer 112b disposed on the lower surface of the first insulating layer 111a, and covering the second wiring layer 112b. And a third wiring layer 112c disposed on a lower surface of the insulating layer 111b and the second insulating layer 111b. The first to third wiring layers 112a, 112b, and 112c may be electrically connected to the connection pad 120P, the first to third passive components 170, 180, 190, and the like. The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c are formed with first and second wiring vias 113a penetrating through the first and second insulating layers 111a and 111b, respectively. 113b).

As the material of the insulating layers 111a and 111b, for example, a material containing an inorganic filler and an insulating resin can be used. For example, thermosetting resins such as epoxy resins, resins containing reinforcing materials such as inorganic fillers such as silica and alumina along with thermoplastic water such as polyimide, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. can be used. Alternatively, a material in which a thermosetting resin or a thermoplastic resin is impregnated in a core material such as glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with an inorganic filler, for example, a prepreg may be used. In this case, it is possible to maintain excellent rigidity, and the frame 110 can be used as a kind of support member.

The wiring layers 112a, 112b, and 112c are copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Metal materials such as alloys thereof may be included. Each of the wiring layers 112a, 112b, and 112c may perform various functions according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. The power (PWR) pattern and the ground (GND) pattern may be the same pattern. In addition, it may include a pad pattern for a connection via, a pad pattern for an electrical connection structure, and the like. The thickness of the wiring layers 112a, 112b, and 112c of the frame 110 may be thicker than the thickness of the redistribution layer 142 of the connection structure 140. This is because the frame 110 may have a thickness similar to that of the semiconductor chip 120, while the connection structure 140 is required to be thinner, and the process is also different.

The wiring vias 113a and 113b penetrate through the insulating layers 111a and 111b and electrically connect the wiring layers 112a, 112b and 112c. The metal material described above may be used as a material for forming the wiring vias 113a and 113b. The wiring vias 113a and 113b may be completely filled with a metal material, or may be formed along a wall surface of the connection via hole. The wiring vias 113a and 113b may have a tapered shape in the same direction. For example, the width of the lower surface may have a tapered shape larger than the width of the upper surface.

The upper surface of the first wiring layer 112a may be positioned below the upper surface of the connection pad 120P of the semiconductor chip 120. This is because the first wiring layer 112a may be recessed into the first insulating layer 111a. In this way, when the first wiring layer 112a is recessed into the inside of the first insulating layer 111a and the upper surface of the first insulating layer 111a and the upper surface of the first wiring layer 112a have a step, the sealing material ( 130) It is possible to prevent the formation material from bleeding and contaminating the first wiring layer 112a. The second wiring layer 112b of the frame 110 may be positioned between an active surface and an inactive surface of the semiconductor chip 120. The first and second wiring vias 113a and 113b may be simultaneously formed and integrated with the second and third wiring layers 112b and 112c, respectively, through a plating process.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The semiconductor chip 120 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material forming a body. Various circuits may be formed in the body. The connection pad 120P is for electrically connecting the semiconductor chip 120 with other components, and a metal material such as copper (Cu) or aluminum (Al) may be used without particular limitation as a forming material. The surface on which the connection pad 120P is disposed becomes an active surface, and the opposite side becomes an inactive surface. If necessary, a passivation film may be formed on the body to cover at least a portion of the connection pad 120P. The passivation film may be an oxide film or a nitride film, or a double layer of an oxide film and a nitride film. An insulating film or the like may be further disposed at other required positions. The semiconductor chip 120 includes, for example, a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), and a flash memory; Application processor chips such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; It may be a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC), but is not limited thereto.

The encapsulant 130 covers at least a portion of each of the frame 110 and the semiconductor chip 120, and fills at least a portion of the through portion 110H. The first and second encapsulants 130a and 130b each contain an insulating material, and the insulating material includes a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin, such as an epoxy resin and The same thermosetting resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler therein, specifically a non-photosensitive insulating material such as ABF or EMC may be used. If necessary, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber may be used. Through this, voids and undulation problems may be improved, and warpage control may be more easily performed. If necessary, PIE (Photo Image-able Encapsulant) can also be used.

The backside wiring layer 135 is copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof It may contain metal materials such as. The backside wiring layer 135 may perform various functions in design design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. The ground (GND) pattern and the power (PWR) pattern may be the same pattern.

The connection structure 140 may rearrange the connection pads 120P of the semiconductor chip 120. In addition, the connection pad 120P and the passive components 170, 180, and 190 may be electrically connected. The connection structure 140 passes through the insulation layer 141, the redistribution layer 142 disposed on the lower surface of the insulation layer 141, and the connection via 143 connected to the redistribution layer 142. Include. The insulating layer 141, the redistribution layer 142, and the connection via 143 may be more or less than those shown in the drawings. That is, the number of layers may vary depending on the design.

An insulating material may be used as the material of the insulating layer 141. In this case, a photosensitive insulating material (PID) may be used as the insulating material, and in this case, it is possible to introduce a fine pitch through a photo via. Advantageous to high-density design, tens to millions of connection pads 120P of the semiconductor chip 120 can be very effectively rewired. The insulating layer 141 may have a boundary separated from each other, or the boundary may be unclear.

The redistribution layer 142 may be electrically connected to the electrical connection metal 160 by redistributing the connection pad 120P of the semiconductor chip 120. Materials for forming the redistribution layer 142 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, metal materials such as alloys thereof may be used. The redistribution layer 142 may also perform various functions according to the design design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the redistribution layer 142 may include various types of via pads and electrical connection metal pads.

The connection via 143 electrically connects the redistribution layers 142 formed on different layers. In addition, the connection pad 120P of the semiconductor chip 120, the wiring layer 112a of the frame 110, and the first external electrode 171 of the first passive component 170 are electrically connected to the redistribution layer 142 do. The connection via 143 may physically contact the connection pad 120P when the semiconductor chip 120 is a bare die. Materials for forming the connection via 143 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, metal materials such as alloys thereof may be used. The connection via 143 may include a signal via, a power via, and a ground via, and the power via and the ground via may be the same via. The connection vias 143 may also be field-type vias each filled with a metallic material, or conformal-type vias in which metallic materials are formed along the walls of the via holes. In addition, it may have a tapered shape in a direction opposite to the wiring vias 113a and 113b.

The passivation layer 150 is an additional component for protecting the third wiring layer 112c and the backside wiring layer 135 from external physical and chemical damage. The passivation layer 150 may include a thermosetting resin. For example, the passivation layer 150 may be ABF, but is not limited thereto. The passivation layer 150 has an opening that opens at least a portion of each of the third wiring layer 112c and the backside wiring layer 135. There may be tens to tens of thousands of openings, and may have a number of more or less. Each opening may be composed of a plurality of holes.

The electrical connection metal 160 is also an additional configuration, and is a configuration for physically and/or electrically connecting the semiconductor package 100A according to an example with the outside. For example, the semiconductor package 100A according to an example may be mounted on a main board of an electronic device through an electrical connection metal 160. The electrical connection metal 160 is disposed on the opening of the passivation layer 150 and may be electrically connected to the exposed backside wiring layer 135 and the third wiring layer 112c, respectively. Each of the electrical connection metals 160 may be composed of a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). More specifically, it may be formed of solder or the like, but this is only an example, and the material is not particularly limited thereto.

The electrical connection metal 160 may be a land, a ball, a pin, or the like. The electrical connection metal 160 may be formed as a multilayer or a single layer. When formed as a multilayer, a copper pillar and solder may be included, and when formed as a single layer, tin-silver solder or copper may be included, but this is also only an example and is not limited thereto. . The number, spacing, and arrangement form of the electrical connection metal 160 are not particularly limited, and may be sufficiently modified according to design matters for a person skilled in the art. For example, the number of the electrical connection metal 160 may be tens to several million, and may be more or less, depending on the number of connection pads 120P.

At least one of the electrical connection metals 160 is disposed in the fan-out area. The fan-out region means a region outside the region in which the semiconductor chip 120 is disposed. The fan-out package is more reliable than the fan-in package, can implement multiple I/O terminals, and 3D interconnection is easy. In addition, compared to a BGA (Ball Grid Array) package and an LGA (Land Grid Array) package, the package thickness can be made thinner, and the price competitiveness is excellent.

Each of the passive components 170, 180, and 190 may independently be various passive components such as capacitors, inductors, and beads. Passive parts 170, 180, 190 may be of the same type or different types. The passive components 170, 180, and 190 may be electrically connected to each other through the redistribution layer 142 of the connection structure 140, and may also be electrically connected to the connection pad 120P of the semiconductor chip 120. Meanwhile, the number of electronic components such as the semiconductor chip 120 or the passive components 170, 180, 190 may be greater or less than those shown in the drawings depending on the design.

The connection vias 175 and 185 pass through the encapsulants 130a and 130b and provide an electrical connection path between the passive components 170 and 180 and the backside wiring layer 135. Materials for forming the connection vias 175 and 185 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti ), or an alloy thereof. The connection vias 175 and 185 may be completely filled with a metal material, or a metal material may be formed along the wall surface of the connection via hole. The connection vias 175 and 185 may have a tapered shape in the same direction. For example, the width of the lower surface may have a tapered shape larger than the width of the upper surface.

11 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, in a semiconductor package 100B according to another example, in the semiconductor package 100A according to the above example, the first and second external electrodes 171 and 172 of the first passive component 170 are Each of the connection structures 140 is electrically connected to one or more redistribution layers 142 through the connection vias 143, and the third and fourth external electrodes 181 and 182 of the second passive component 180 are It is electrically connected to the backside wiring layer through the second connection vias 185a and 185b passing through the encapsulant 130b, respectively. Through this connection path, the first and second passive components 170 and 180 may be focused on the vertical electrical connection, respectively. Other descriptions are substantially the same as those described above, and detailed descriptions will be omitted.

In the present disclosure, the lower side, the lower side, the lower side, etc. are used to mean the downward direction based on the cross section of the drawing for convenience, and the upper side, the upper side, the upper surface, etc. are used to mean the opposite direction. However, this has defined the direction for convenience of explanation, and the scope of the claims is not particularly limited by the description of this direction, and the upper/lower concept may be changed at any time.

In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both physically connected and unconnected cases. In addition, expressions such as first and second are used to distinguish one component from another, and do not limit the order and/or importance of the corresponding components. In some cases, without departing from the scope of the rights, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

The expression example used in the present disclosure does not mean the same embodiment as each other, and is provided to emphasize and describe different unique features. However, the examples presented above are not excluded from being implemented in combination with other example features. For example, even if a matter described in a specific example is not described in another example, it may be understood as a description related to another example unless there is a description contradicting or contradicting the matter in another example.

The terms used in the present disclosure are used only to describe an example, and are not intended to limit the present disclosure. In this case, the singular expression includes a plural expression unless it clearly means differently in the context.

Claims (10)

A connection structure including one or more redistribution layers;
A semiconductor chip disposed under the connection structure and having a connection pad electrically connected to the one or more redistribution layers;
A first passive component disposed under the connection structure and disposed around a side surface of the semiconductor chip;
A second passive component disposed below the first passive component and disposed around a side surface of the semiconductor chip; And
A sealing material covering at least a portion of each of the semiconductor chip, the first passive component, and the second passive component; Containing,
Semiconductor package.
The method of claim 1,
On a plane, the first and second passive parts at least partially overlap each other,
Semiconductor package.
The method of claim 1,
The encapsulant may include a first encapsulant covering a portion of the side surface of the semiconductor chip and at least a portion of each of the first passive components, and a first encapsulant covering at least a portion of the side surface of the semiconductor chip and at least a portion of the second passive component. 2 sutures, containing,
Semiconductor package.
The method of claim 3,
A backside wiring layer disposed on a lower surface of the encapsulant; Further comprising,
Semiconductor package.
The method of claim 4,
The first passive component is in the form of a chip having first and second external electrodes spaced apart from each other,
The second passive component is in the form of a chip having third and fourth external electrodes spaced apart from each other,
The first and second passive components are each at least one of a capacitor and an inductor,
Semiconductor package.
The method of claim 5,
The first external electrode of the first passive component is electrically connected to the one or more redistribution layers through a connection via of the connection structure,
The second external electrode of the first passive component is electrically connected to the fourth external electrode of the second passive component through a first connection via penetrating the first encapsulant,
The third external electrode of the second passive component is electrically connected to the backside wiring layer through a second connection via passing through the second encapsulant,
Semiconductor package.
The method of claim 5,
The first and second external electrodes of the first passive component are electrically connected to the one or more redistribution layers, respectively, through a connection via of the connection structure,
The third and fourth external electrodes of the second passive component are each electrically connected to the backside wiring layer through a second connection via passing through the second encapsulant,
Semiconductor package.
The method of claim 1,
A frame disposed under the connection structure and having a through part; It further includes,
The semiconductor chip, the first passive component, and the second passive component are disposed in the through part,
The encapsulant fills at least a portion of the through part,
The first and second passive parts are located between the upper and lower surfaces of the frame,
Semiconductor package.
The method of claim 8,
The frame includes a plurality of wiring layers,
The plurality of wiring layers are electrically connected to the connection pad through the one or more redistribution layers,
Semiconductor package.
The method of claim 1,
A plurality of third passive components disposed above the connection structure and electrically connected to the one or more redistribution layers, respectively; It further includes,
At least one of the plurality of third passive parts is thicker than the first and second passive parts,
Semiconductor package.

Images