KR20200120496A - Integrated circuit including power gating cell - Google Patents

Abstract

According to the present disclosure, disclosed is an integrated circuit. The integrated circuit includes a power gating circuit receiving a power voltage from a first power line and outputting a first driving voltage to the first virtual power line, and a logic circuit connected to a first virtual power line to receive power from the power gating circuit. The power gating circuit includes a P-type transistor and a first N-type transistor connected in parallel to each other between the first power line and the first virtual power line.

Description

Integrated circuit including power gating cell {INTEGRATED CIRCUIT INCLUDING POWER GATING CELL}

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit including a power gating cell.

In integrated circuit design, a power gating circuit is used to reduce power consumption. The power gating circuit can reduce leakage current by cutting off power supplied to the logic circuit block when operating in a sleep mode. However, the power gating circuit may be required to provide a retention mode that provides a retention voltage lower than an operating voltage in a power-on mode in order to maintain an internal state of a logic circuit block or a register value.

A problem to be solved by the technical idea of the present disclosure is to provide an integrated circuit including a power gating circuit, a method of designing the integrated circuit, and a computing system for designing the integrated circuit.

In the integrated circuit according to the technical idea of the present disclosure, the integrated circuit is connected to a power gating circuit for receiving a power voltage from a first power line and outputting a first driving voltage to a first virtual power line, and a first virtual power line. A logic circuit receiving power from the power gating circuit may be included, and the power gating circuit may include a P-type transistor and a first N-type transistor connected in parallel to each other between the first power line and the first virtual power line.

An integrated circuit according to the inventive concept of the present disclosure is an integrated circuit including a first power gating cell that receives a power voltage from a first power line and provides a first driving voltage to a logic cell through a first virtual power line, 1 The power gating cell is a P-MOS region in which a P-type transistor connected to the first power line and the first virtual power line is formed, and a first N-type connected to the first power line and the first virtual power line. A first N-MOS region in which a transistor is formed, and a second N-MOS region in which a second N-type transistor connected between the first power line and the first virtual power line is formed, and the P-MOS region An N-well doped with an N-type impurity and extending in the first direction may be included.

In the integrated circuit according to the technical idea of the present disclosure, in an integrated circuit including a first power gating cell that receives a ground voltage from a ground line and provides a driving voltage to a logic cell through a virtual ground line, the first power gating cell is An N-MOS region in which an N-type transistor connected to the ground line and a virtual ground line is formed, a first P-MOS region in which a first P-type transistor connected to the ground line and the virtual ground line is formed, and a ground Includes a second P-MOS region in which a second P-type transistor connected between the line and the virtual ground line is formed, and the first P-MOS region is doped with an N-type impurity, and an N-well extending in a first direction Can be formed in

The integrated circuit according to the technical idea of the present disclosure uses a power gating circuit including a plurality of N-type transistors connected between a first power line and a first virtual power line and having different threshold voltages to control driving voltages of various sizes. Can be provided to the circuit. In addition, the integrated circuit according to the technical idea of the present disclosure uses a power gating circuit including a plurality of P-type transistors connected between the second power line and the second virtual power line and having different threshold voltages to drive voltages of various sizes. Can be provided to the logic circuit. Accordingly, the integrated circuit according to the present disclosure may perform retention modes that provide driving voltages of various sizes.

1 is a block diagram showing an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
2 is a circuit diagram showing an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
3A to 3D are diagrams for explaining a voltage provided to a logic circuit according to an operation of the power gating circuit of FIG. 2.
4A is a circuit diagram of an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
4B is a diagram for describing a voltage provided to a logic circuit according to an operation of a power gating circuit according to an exemplary embodiment of the present disclosure.
5 is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
6 is a block diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
7 is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
8 is a block diagram showing an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
9 is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.
10 is a layout diagram illustrating a header cell included in a power gating circuit disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.
11 is a layout diagram illustrating a footer cell included in a power gating cell disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.
12 is a layout diagram illustrating a header cell included in a power gating circuit disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.
13 is a layout diagram illustrating a header cell and a footer cell included in a power gating cell disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.
14 is a flow chart showing a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
Fig. 15 is a block diagram illustrating a computing system including a memory storing a program according to an exemplary embodiment of the present disclosure.

1 is a block diagram showing an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, the integrated circuit 10 may include a logic circuit 200 and a power gating circuit 100 that provides power to the logic circuit 200. The logic circuit 200 is connected to the first virtual power line VVDD and the second power line RGND, and may receive power through the first virtual power line VVDD and the second power line RGND. . In an exemplary embodiment, the second power line RGND may be a ground line, and the logic circuit 200 may be applied with the ground voltage GND through the second power line RGND.

In an exemplary embodiment, the integrated circuit 10 may be a System-On-Chip (SOC). For example, the integrated circuit 10 may be a mobile SOC, an application processor, a media processor, a microprocessor, a central processing unit (CPU), or a similar device.

The power gating circuit 100 may be connected to a first power line RVDD providing a power voltage VDD. The power gating circuit 100 selectively connects the first power line RVDD to the first virtual power line VVDD in response to the control signal IN, thereby providing a first driving voltage to the logic circuit 200. And control the power mode of the logic circuit 200.

For example, the power gating circuit 100 may provide the power voltage VDD to the logic circuit 200 by connecting the first power line RVDD and the first virtual power line VVDD in the power-on mode. In the retention mode, the first power line RVDD and the first virtual power line VVDD are connected, but a high retention voltage VR of a level lower than the power voltage VDD is provided to the logic circuit 200. I can. On the other hand, the power gating circuit 100 may float the first virtual power line VVDD by blocking the first power line RVDD and the first virtual power line VVDD from each other in the power-off mode.

The integrated circuit 10 may further include a power management circuit, and the control signal IN may be provided from a power management circuit external to the power gating circuit 100. The power management circuit may apply a control signal IN to the power gating circuit 100 so that the voltage level provided to the logic circuit 200 varies according to the power mode.

The logic circuit 200 may selectively receive power through the first virtual power line VVDD. The logic circuit 200 may be provided with a first driving voltage of a different level according to the power mode. For example, the logic circuit 200 may be provided with a power supply voltage VDD in a power-on mode, a high retention voltage VR in a retention mode, and power may be cut off in a power-off mode. . Although only one high retention voltage VR is shown in FIG. 1, the integrated circuit 10 according to the present disclosure may include a plurality of retention modes, and high retention voltages of different voltage levels are applied to a logic circuit ( 200) can also be provided.

The logic circuit 200 may include an arbitrary circuit connected to the first virtual power line VVDD. For example, the logic circuit 200 may be implemented as an inverter, a NAND gate, an AND gate, a NOR gate, an OR gate, an XOR gate, an XNOR gate, a multiplexer, an adder, a latch, a flip-flop, or the like.

2 is a circuit diagram showing an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2, the power gating circuit 100 includes a header transistor unit 110 and a header transistor unit 110 connected between a first power line RVDD and a first virtual power line VVDD. It may include a control circuit 120 providing switching signals CS_P, CS_N1, CS_N2. The control circuit 120 may generate switching signals CS_P, CS_N1, and CS_N2 in response to the control signal IN. However, unlike the one shown in FIG. 2, the power gating circuit 100 may not include the control circuit 120, and the header transistor unit 110 includes switching signals CS_P directly from the outside of the power gating circuit 100. , CS_N1, CS_N2) may be received.

The header transistor unit 110 includes a P-type transistor PT, a first N-type transistor NT1, and a second P-type transistor PT connected between the first power line RVDD and the first virtual power line VVDD and connected in parallel. It may include an N-type transistor NT2. Each of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2 of FIG. 2 may be represented by an equivalent transistor, and the P-type transistor PT and the first N-type transistor ( Each of the NT1) and the second N-type transistor NT2 may include a plurality of transistors.

The first N-type transistor NT1 may have a first threshold voltage VTH_N1, and the second N-type transistor NT2 may have a second threshold voltage VTH_N2. In an exemplary embodiment, the first threshold voltage VTH_N1 may be smaller than the second threshold voltage VTH_N2.

The control circuit 120 may selectively turn on transistors included in the header transistor unit 110 in response to the control signal IN. In an exemplary embodiment, the control signal IN may be a 2-bit signal. The control circuit 120 includes a first switching signal CS_P for switching the P-type transistor PT and a second switching signal CS_N1 for switching the first N-type transistor NT1 in response to the control signal IN. And a third switching signal CS_N2 for switching the second N-type transistor NT2.

A first virtual power supply connected to the logic circuit 200 according to the operation of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2 included in the header transistor unit 110 The voltage of the line VVDD may vary, and the power mode of the logic circuit 200 may vary. In an exemplary embodiment, the logic circuit 200 may include an inverter. However, unlike FIG. 2, the logic circuit 200 may include a logic circuit other than an inverter.

The power gating circuit 100 according to an exemplary embodiment of the present disclosure is a logic circuit by turning on a transistor selected from among a P-type transistor PT, a first N-type transistor NT1, and a second N-type transistor NT2. The magnitude of the first driving voltage provided to 200 may be adjusted. A description of the power mode of the logic circuit 200 and the magnitude of the voltage provided to the logic circuit 200 will be described later in FIGS. 3A to 3D.

3A to 3D are diagrams for explaining a voltage provided to a logic circuit according to an operation of the power gating circuit of FIG. 2. Each of FIGS. 3A to 3D is a diagram for explaining a time when the logic circuit 200 operates in a power-on mode, a first retention mode, a second retention mode, and a power-off mode.

Referring to FIG. 3A, in the power-on mode, the control circuit 120 may generate switching signals CS_P, CS_N1, and CS_N2 for turning on the P-type transistor PT. For example, the control circuit 120 may generate a logic low level first switching signal CS_P, a logic low level second switching signal CS_N1, and a logic low level third switching signal CS_N2. have. Of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2, only the P-type transistor PT is turned on, and current flows through the P-type transistor PT. The voltage level of the first virtual power line VVDD may be the same as the power voltage VDD of the first power line RVDD.

Referring to FIG. 3B, in the first retention mode, the control circuit 120 may generate switching signals CS_P, CS_N1, and CS_N2 for turning on the first N-type transistor NT1. For example, the control circuit 120 may generate a logic high level first switching signal CS_P, a logic high level second switching signal CS_N1, and a logic low level third switching signal CS_N2. have.

Of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2, only the first N-type transistor NT1 is turned on, and current through the first N-type transistor NT1 is turned on. Is flowed, and the first virtual power line VVDD may have a voltage level of the first high retention voltage VR1. When the first N-type transistor NT1 is turned on, the first virtual power line VVDD is the first power line RVDD due to the first threshold voltage VTH_N1 of the first N-type transistor NT1. The first high retention voltage VR1 may be lower by the first threshold voltage VTH_N1 than the power voltage VDD of.

Referring to FIG. 3C, in the second retention mode, the control circuit 120 may generate switching signals CS_P, CS_N1, and CS_N2 for turning on the second N-type transistor NT2. For example, the control circuit 120 may generate a logic high level first switching signal CS_P, a logic low level second switching signal CS_N1, and a logic high level third switching signal CS_N2. have.

Of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2, only the second N-type transistor NT2 is turned on, and current through the second N-type transistor NT2 Flows, and the first virtual power line VVDD may have a voltage level of the second high retention voltage VR2. When the second N-type transistor NT2 is turned on, the first virtual power line VVDD becomes the first power line RVDD due to the second threshold voltage VTH_N2 of the second N-type transistor NT2. The second high retention voltage VR2 may be lower by the second threshold voltage VTH_N2 than the power voltage VDD of.

In an exemplary embodiment, the second threshold voltage VTH_N2 may be greater than the first threshold voltage VTH_N1. Accordingly, the second high retention voltage VR2 may have a lower voltage level than the first high retention voltage VR1.

Referring to FIG. 3D, in the power-off mode, the control circuit 120 is switched to turn off all of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2. Signals CS_P, CS_N1, and CS_N2 may be generated. For example, the control circuit 120 may generate a logic high level first switching signal CS_P, a logic low level second switching signal CS_N1, and a logic low level third switching signal CS_N2. have. Since all of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2 are turned off, the first virtual power line VVDD is cut off from the first power line RVDD. , Can be plotted.

3A to 3D, the power gating circuit 100 according to an exemplary embodiment of the present disclosure adjusts the voltage level of the first virtual power line VVDD connected to the logic circuit 200 according to the power mode. I can. Accordingly, the integrated circuit 10 may perform various retention modes (eg, a first retention mode and a second retention mode) in addition to the power-on mode and the power-off mode.

4A is a circuit diagram of an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure. 4B is a diagram for describing a voltage provided to a logic circuit according to an operation of a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 4A, the integrated circuit 10a may include a logic circuit 200 and a power gating circuit 100a that provides power to the logic circuit 200. The power gating circuit 100a may adjust the power mode of the logic circuit 200 in response to the control signal INa, and may provide voltages of various sizes to the logic circuit 200.

The logic circuit 200 is connected to the first virtual power line VVDD and the second power line RGND, and may receive power through the first virtual power line VVDD and the second power line RGND. . In an exemplary embodiment, the second power line RGND may be a ground line.

The power gating circuit 100a is a header transistor unit 110a and a header transistor unit 110a connected between the first power line RVDD and the first virtual power line VVDD, and the switching signals CS_P, CS_N1, CS_N2 , CS_N3) may include a control circuit (120a) providing. The control circuit 120a may generate switching signals CS_P, CS_N1, CS_N2, and CS_N3 in response to the control signal INa.

The header transistor unit 110a is connected between the first power line RVDD and the first virtual power line VVDD, and the P-type transistor PT, the first N-type transistor NT1, and the second It may include an N-type transistor NT2 and a third N-type transistor NT3. In an exemplary embodiment, the third N-type transistor NT3 may include a plurality of transistors, and in FIG. 4A, the third N-type transistor NT3 may be represented as an equivalent transistor.

The third N-type transistor NT3 may have a third threshold voltage VTH_N3. In an exemplary embodiment, the first threshold voltage VTH_N1 may be smaller than the second threshold voltage VTH_N2, and the second threshold voltage VTH_N2 may be smaller than the third threshold voltage VTH_N3.

The control circuit 120a may selectively turn on transistors included in the header transistor unit 110a in response to the control signal INa. In an exemplary embodiment, the control signal INa may be a 2-bit signal. The control circuit 120a includes a first switching signal CS_P for switching the P-type transistor PT and a second switching signal CS_N1 for switching the first N-type transistor NT1 in response to the control signal INa. , A third switching signal CS_N2 for switching the second N-type transistor NT2 and a fourth switching signal CS_N3 for switching the third N-type transistor NT3 may be generated. However, an example in which the control signal INa is a 2-bit signal is an example, and the integrated circuit 10a according to the present disclosure is not limited thereto, and the control signal INa may be variously implemented.

4A and 4B, a P-type transistor PT, a first N-type transistor NT1, a second N-type transistor NT2, and a third N-type transistor NT3 included in the header transistor unit 110a. ) The voltage of the first virtual power line VVDD connected to the logic circuit 200 may vary according to each operation, and the power mode of the logic circuit 200 may vary.

For example, in the power-on mode, only the P-type transistor PT can be turned on, and the first N-type transistor NT1, the second N-type transistor NT2, and the third N-type transistor NT3 Can be turned off. Accordingly, the power voltage VDD may be applied to the first virtual power line VVDD.

In the first retention mode, only the first N-type transistor NT1 can be turned on, and the P-type transistor PT, the second N-type transistor NT2, and the third N-type transistor NT3 are turned on. Can be turned off. Accordingly, the first high retention voltage VR1 may be applied to the first virtual power line VVDD. The first high retention voltage VR1 may be smaller than the power voltage VDD by the first threshold voltage VTH_N1.

In the second retention mode, only the second N-type transistor NT2 can be turned on, and the P-type transistor PT, the first N-type transistor NT1, and the third N-type transistor NT3 are turned on. Can be turned off. Accordingly, the second high retention voltage VR2 may be applied to the first virtual power line VVDD. The second high retention voltage VR2 may be smaller than the power voltage VDD by the second threshold voltage VTH_N2.

In the third retention mode, only the third N-type transistor NT3 can be turned on, and the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2 are turned on. Can be turned off. Accordingly, the third high retention voltage VR3 may be applied to the first virtual power line VVDD. The third high retention voltage VR3 may be smaller than the power voltage VDD by the third threshold voltage VTH_N3. In an exemplary embodiment, the first high retention voltage VR1 may be greater than the second high retention voltage VR2, and the second high retention voltage VR2 is greater than the third high retention voltage VR3. It can be big.

In an exemplary embodiment, the logic circuit 200 may be a circuit that does not operate in a power-off mode. For example, when the logic circuit 200 is the main processor, it may not operate in power-off. When the control signal INa is 2-bit, the power gating circuit 100a electrically connects the first power line RVDD and the first virtual power line VVDD without floating the first virtual power line VVDD. Can be connected by That is, the power gating circuit 100a may turn on at least one of the P-type transistor PT and the first to third N-type transistors NT1 to NT3.

5 is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 5, the integrated circuit 10b may include a logic circuit 200 and a power gating circuit 100b that provides power to the logic circuit 200. The power gating circuit 100b may adjust the power mode of the logic circuit 200 in response to the control signal INb, and may provide the logic circuit 200 with first driving voltages of various sizes.

The power gating circuit 100b includes a header transistor unit 110b and a header transistor unit 110b connected between the first power line RVDD and the first virtual power line VVDD, and the switching signals CS_P, CS_N1 to CS_Nn It may include a control circuit (120b) to provide. The control circuit 120b may generate switching signals CS_P and CS_N1 to CS_Nn in response to the control signal INb.

The header transistor unit 110b includes a P-type transistor PT connected between the first power line RVDD and the first virtual power line VVDD and connected in parallel with each other, and first to n-th N-type transistors NT1. ~NTn) may be included. In an exemplary embodiment, each of the P-type transistor PT and the first to n-th N-th transistors NT1 to NTn may include a plurality of transistors. In FIG. 5, the P-type transistor PT and the Each of the first to n-th N-type transistors NT1 to NTn may be represented as an equivalent transistor. In this case, n may be a natural number of 3 or more.

Each of the first to nth N-th transistors NT1 to NTn may have different threshold voltage values. The n-th transistor NT3 may have an n-th threshold voltage VTH_Nn. In an exemplary embodiment, the first threshold voltage VTH_N1 may be smaller than the second threshold voltage VTH_N2, and the second threshold voltage VTH_N2 may be smaller than the nth threshold voltage VTH_Nn.

The control circuit 120b may selectively turn on transistors included in the header transistor unit 110b in response to the control signal INb. In an exemplary embodiment, the control signal INb may be 3-bit or more. The control circuit 120b includes a first switching signal CS_P for switching the P-type transistor PT and a second switching signal CS_N1 for switching the first N-type transistor NT1 in response to the control signal INb. , A third switching signal CS_N2 for switching the second N-type transistor NT2 and an n+1th switching signal CS_Nn for switching the n-N-th transistor NTn may be generated.

A first virtual power line VVDD connected to the logic circuit 200 according to the operation of the P-type transistor PT included in the header transistor unit 110b and the first to N-th transistors NT1 to NTn. The voltage of may vary, and the power mode of the logic circuit 200 may vary. For example, in the power-on mode, only the P-type transistor PT may be turned on, and the first to n-th N-th transistors NT1 to NTn may be turned off. Accordingly, the power voltage VDD may be applied to the first virtual power line VVDD.

In the nth retention mode, only the n-th transistor NTn can be turned on, and the P-type transistor PT and the first to n-1th transistors NT1 to NTn-1 are turned on. Can be turned off. Accordingly, the nth high retention voltage may be applied to the first virtual power line VVDD. The nth high retention voltage may be smaller than the power voltage VDD by an nth threshold voltage VTH_Nn. In an exemplary embodiment, the first high retention voltage (VR1 in FIG. 3B) and the second high retention voltage (VR2 in FIG. 3B) may be greater than the nth high retention voltage VRn.

The power gating circuit 100b of the integrated circuit 10b according to the present disclosure may be implemented to include various numbers of N-type transistors having different threshold voltages, and the logic circuit 200 may be configured in various numbers of retention modes. It can work. That is, the voltage level of the first virtual power line VVDD connected to the logic circuit 200 may be diversified.

6 is a block diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 6, the integrated circuit 10c may include a logic circuit 200 and a power gating circuit 100c that provides power to the logic circuit 200. The logic circuit 200 is connected to the first power line RVDD and the second virtual power line VGND, and may receive power through the first power line RVDD and the second virtual power line VGND. . For example, the power voltage VDD may be applied to the logic circuit 200 through the first power line RVDD.

The power gating circuit 100c may be connected to the second power line RGND providing the ground voltage GND. The power gating circuit 100c may control the power mode of the logic circuit 200 by selectively connecting the second virtual power line VGND to the second power line RGND in response to the control signal INc. For example, in the power-on mode, the power gating circuit 100c connects the second power line RGND and the second virtual power line VGND to second drive the ground voltage GND to the logic circuit 200. A voltage can be provided, and in the retention mode, the second power line RGND and the second virtual power line VGND are connected, but a low retention voltage of a level higher than the ground voltage GND to the logic circuit 200 ( VGR) may be provided as the second driving voltage. On the other hand, the power gating circuit 100c may float the second virtual power line VGND by blocking the second power line RGND and the second virtual power line VGND from each other in the power-off mode.

The logic circuit 200 may selectively receive power through the second virtual power line VGND. In this case, the logic circuit 200 may be provided with driving power of a different level according to the power mode. For example, the logic circuit 200 may receive a ground voltage GND in a power-on mode, a low retention voltage VGR in a retention mode, and power off in a power-off mode. . In FIG. 8, only one low retention voltage VGR is shown, but the integrated circuit 10c according to the present disclosure may include a plurality of retention modes, and low retention voltages of different voltage levels are applied to a logic circuit ( 200) can also be provided.

7 is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7, the power gating circuit 100c includes a footer transistor unit 110c and a footer transistor unit 110c connected between a second power line RGND and a second virtual power line VGND. A control circuit 120c that provides switching signals CS_N, CS_P1, and CS_P2 may be included. The control circuit 120c may generate switching signals CS_P, CS_N1, and CS_NT2 in response to the control signal INc. However, unlike FIG. 7, the power gating circuit 100c may not include the control circuit 120c, and the footer transistor unit 110c includes switching signals CS_N, from outside of the power gating circuit 100c. CS_P1, CS_P2) may also be received.

The footer transistor unit 110c is connected between the second power line RGND and the second virtual power line VGND and is connected in parallel with each other, an N-type transistor NT, a first P-type transistor PT1, and a second It may include a P-type transistor PT2. In FIG. 7, each of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2 may represent a plurality of transistors as equivalent transistors.

The first P-type transistor PT1 may have a first threshold voltage VTH_P1, and the second P-type transistor PT2 may have a second threshold voltage VTH_P2. In an exemplary embodiment, the first threshold voltage VTH_P1 and the second threshold voltage VTH_P2 may be different from each other.

The control circuit 120c may selectively turn on transistors included in the footer transistor unit 110c in response to the control signal INc. The control circuit 120c includes a first switching signal CS_N for switching the N-type transistor NT and a second switching signal CS_P1 for switching the first P-type transistor PT1 in response to the control signal INc. And a third switching signal CS_P2 for switching the second P-type transistor PT2.

A second virtual power supply connected to the logic circuit 200 according to the operation of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2 included in the footer transistor unit 110c The second driving voltage of the line VGND may be different, and the power mode of the logic circuit 200 may be different. For example, the logic circuit 200 may operate in a power-on mode, a first retention mode, a second retention mode, and a power-off mode.

In the power-on mode, the control circuit 120c may generate switching signals CS_N, CS_P1, and CS_P2 for turning on the N-type transistor NT. For example, the control circuit 120c may generate a logic high level first switching signal CS_N, a logic high level second switching signal CS_P1, and a logic high level third switching signal CS_P2. have. Of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2, only the N-type transistor NT is turned on, and a current flows through the N-type transistor NT, The second driving voltage of the second virtual power line VGND may be equal to the ground voltage GND of the second power line RGND.

In the first retention mode, the control circuit 120c may generate switching signals CS_N, CS_P1, and CS_P2 for turning on the first P-type transistor PT1. For example, the control circuit 120c may generate a logic low level first switching signal CS_N, a logic low level second switching signal CS_P1, and a logic high level third switching signal CS_P2. have. Of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2, only the first P-type transistor PT1 is turned on, and current through the first P-type transistor PT1 is turned on. Can flow. Due to the first threshold voltage VTH_P1 of the first P-type transistor PT1, the second virtual power line VGND is a first low retention voltage that is greater than the ground voltage GND by the first threshold voltage VTH_P1. Can have

In the second retention mode, the control circuit 120c may generate switching signals CS_N, CS_P1, and CS_P2 for turning on the second P-type transistor PT2. For example, the control circuit 120c may generate a logic low level first switching signal CS_N, a logic high level second switching signal CS_P1, and a logic low level third switching signal CS_P2. have. Of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2, only the second P-type transistor PT2 is turned on, and current through the second P-type transistor PT2 Can flow. Due to the second threshold voltage VTH_P2 of the second P-type transistor PT2, the second virtual power line VGND is a second low retention voltage that is greater than the ground voltage GND by the amount of the second threshold voltage VTH_P2. Can have In an exemplary embodiment, the second threshold voltage VTH_P2 may have a different value from the first threshold voltage VTH_P1.

In the power-off mode, the control circuit 120c includes switching signals CS_N and CS_P1 for turning off all of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2. , CS_P2) can be created. For example, the control circuit 120c may generate a logic low level first switching signal CS_N, a logic high level second switching signal CS_P1, and a logic high level third switching signal CS_P2. have. Since all of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2 are turned off, the second virtual power line VGND is cut off from the second power line RGND. , Can be plotted.

In FIG. 7, it is shown that the footer transistor unit 110c includes only the first P-type transistor PT1 and the second P-type transistor PT2, which are two transistors having different threshold voltages, but power gating according to the present disclosure. The circuit 100c may include various numbers of P-type transistors having different threshold voltages, and thus various retention modes may be provided to the logic circuit 200. In an exemplary embodiment, the power gating circuit 100c may not operate in the power-off mode.

8 is a block diagram showing an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8, the integrated circuit 10d may include a logic circuit 200 and a power gating circuit 100d that provides power to the logic circuit 200. The logic circuit 200 is connected to the first virtual power line (VVDD) and the second virtual power line (VGND), and receives power through the first virtual power line (VVDD) and the second virtual power line (VGND). I can.

The power gating circuit 100d may be connected to a first power line RVDD providing a power voltage VDD and may be connected to a second power line RGND providing a ground voltage GND. The power gating circuit 100d selectively connects the first virtual power line VVDD to the first power line RVDD and connects the second virtual power line VGND to the second power line in response to the control signal INd. By selectively connecting to (RGND), the power mode of the logic circuit 200 can be adjusted.

For example, in the power-on mode, the power gating circuit 100d connects the first power line RVDD and the first virtual power line VVDD, and connects the second power line RGND and the second virtual power line ( VGND) may provide a power voltage VDD and a ground voltage GND to the logic circuit 200. The power gating circuit 100d provides a high retention voltage VR to a first virtual power line VVDD or a low retention voltage VGR to a second virtual power line VGND in a retention mode. can do. On the other hand, in the power-off mode, the power gating circuit 100d blocks the first power line RVDD and the first virtual power line VVDD from each other, and the second power line RGND and the second virtual power line VGND. By blocking each other, the first virtual power line VVDD and the second virtual power line VGND may be in a floating state. In FIG. 8, only one high retention voltage VR and a low retention voltage VGR are shown, but the integrated circuit 10d according to the present disclosure includes high retention voltages and low retention voltages having different voltage levels. They may be provided as a logic circuit 200.

9 is a circuit diagram illustrating an integrated circuit including a power gating circuit according to an exemplary embodiment of the present disclosure.

9, the power gating circuit 100d includes a header transistor unit 110_1d connected between a first power line RVDD and a first virtual power line VVDD, a second power line RGND, and a second power supply line. Switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, CS_P2 are respectively supplied to the footer transistor unit 110_2d connected between the virtual power line VGND, and the header transistor unit 110_1d and the footer transistor unit 110_2d. It may include a control circuit (120d) to provide. The control circuit 120d may generate switching signals CS_P, CS_N1, and CS_NT2 in response to the control signal INd. However, unlike FIG. 9, the power gating circuit 100d may not include the control circuit 120d.

The header transistor unit 110_1d is connected between the first power line RVDD and the first virtual power line VVDD, and the P-type transistor PT, the first N-type transistor NT1, and the second It may include an N-type transistor NT2. In an exemplary embodiment, each of the P-type transistor PT, the first N-type transistor NT1, and the second N-type transistor NT2 may represent a plurality of transistors connected in parallel as equivalent transistors. For the header transistor unit 110_1d, the description of the transistor unit 110_2 of FIG. 2 may be the same.

The footer transistor unit 110_2d is connected between the second power line RGND and the second virtual power line VGND and is connected in parallel with each other. The N-type transistor NT, the first P-type transistor PT1, and the second It may include a P-type transistor PT2. In an exemplary embodiment, each of the N-type transistor NT, the first P-type transistor PT1, and the second P-type transistor PT2 may represent a plurality of transistors connected in parallel as equivalent transistors. The description of the transistor unit 110c of FIG. 7 may be applied to the footer transistor unit 110_2d in the same manner.

The control circuit 120d may selectively turn on transistors included in the header transistor unit 110_1d and the footer transistor unit 110_2d in response to the control signal INd. In response to the control signal INd, the control circuit 120d includes a first header switching signal CS_P for switching the P-type transistor PT, and a second header switching signal CS_P for switching the first N-type transistor NT1. A third header switching signal CS_N2 for switching CS_N1 and the second N-type transistor NT2 may be generated. In addition, the control circuit 120d has a first footer switching signal CS_N for switching the N-type transistor NT and a second footer switching for switching the first P-type transistor PT1 in response to the control signal INd. A third footer switching signal CS_P2 for switching the signal CS_P1 and the second P-type transistor PT2 may be generated.

The first driving voltage of the first virtual power line VVDD and the second virtual power line VGND connected to the logic circuit 200 according to the operation of the header transistor unit 110_1d and the footer transistor unit 110_2d The driving voltage may vary, and the power mode of the logic circuit 200 may vary. For example, the logic circuit 200 may operate in a power-on mode, a plurality of retention modes, and a power-off mode.

In the power-on mode, the control circuit 120d includes switching signals CS_P for turning on the P-type transistor PT of the header transistor unit 110_1d and the N-type transistor NT of the footer transistor unit 110_2d. , CS_N1, CS_N2, CS_N, CS_P1, CS_P2) can be generated. As a current flows through the P-type transistor PT of the header transistor unit 110_1d and the N-type transistor NT of the footer transistor unit 110_2d, the voltage level of the first virtual power line VVDD becomes the first power line RVDD. ), and the second driving voltage of the second virtual power line VGND may be equal to the ground voltage GND of the second power line RGND.

In each of the plurality of retention modes, the control circuit 120d turns on one of the first N-type transistor NT1 and the second N-type transistor NT2 of the header transistor unit 110_1d, or a footer transistor. The unit 110_2d may generate switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 for turning on one of the first P-type transistor PT1 and the second P-type transistor PT2. In the plurality of retention modes, a first high retention voltage (for example, VR1 in FIG. 3B) or a second high retention voltage (for example, VR2 in FIG. 3C) is applied to the first virtual power line VVDD. Alternatively, a first low retention voltage or a second low retention voltage may be applied to the second virtual power line VGND.

In an exemplary embodiment, the first threshold voltage VTH_N1 of the first N-type transistor NT1, the second threshold voltage VTH_N2 of the second N-type transistor NT2, and the first P-type transistor PT1 The first threshold voltage VTH_P1 and the second threshold voltage VTH_P2 of the second P-type transistor PT2 may be different from each other. In this case, the power gating circuit 100d may drive the logic circuit 200 in eight different retention modes.

In the power-off mode, the control circuit 120d includes switching signals CS_P, CS_N1, CS_N2, CS_N, CS_P1, and CS_P2 for turning off at least one of the header transistor unit 110_1d and the footer transistor unit 110_2d. Can be created. When at least one of the header transistor unit 110_1d and the footer transistor unit 110_2d is turned off, the first virtual power line VVDD may float or the second virtual power line VGND may float. Accordingly, the power of the logic circuit 200 may be cut off.

In FIG. 9, the header transistor unit 110_1d includes only the first N-type transistor NT1 and the second N-type transistor NT2, and the footer transistor unit 110_2d is the first P-type transistor PT1 and the second P-type transistor. Although illustrated as including only the transistor PT2, the power gating circuit 100d according to the present disclosure may include various numbers of N-type transistors and P-type transistors having different threshold voltages. Accordingly, the power gating circuit 100d may provide various retention modes to the logic circuit 200.

10 is a layout diagram illustrating a header cell included in a power gating cell disposed in an integrated circuit according to an exemplary embodiment of the present disclosure. This layout diagram is a diagram showing a plane consisting of a first direction (X) and a second direction (Y). Components arranged in the third direction (Z) relative to other components may be referred to as being on top of other components, and components arranged in a direction opposite to the third direction (Z) than other components An element may be referred to as being underneath another component.

Referring to FIG. 10, the first to fifth header cells C110_1 and C110_1a to C110_1d may include an N-well extending in a first direction X on a substrate and doped with an N-type impurity, and the substrate It may be doped with P-type impurities. Accordingly, N-MOS regions NA1 to NA4 in which N-type transistors are formed may be formed in the substrate, and P-MOS regions PA in which P-type transistors are formed may be formed in the N-well. Header transistors of the power gating circuit may be formed in each of the first to fifth header cells C110_1 and C110_1a to C110_1d.

In an exemplary embodiment, each of the N-MOS regions NA, NA1, NA2, NA3, and NA4 and the P-MOS region PA may include a fin extending in the first direction X. Alternatively, in an exemplary embodiment, each of the N-MOS regions NA, NA1, NA2, NA3, and NA4 and the P-MOS region PA may include a nanosheet extending in the first direction X.

Each of the first to fifth header cells C110_1 and C110_1a to C110_1d may be electrically connected to a logic cell, and may provide power to the logic cell. The logic cell can be implemented with various types of circuits, for example, an inverter, a NAND gate, an AND gate, a NOR gate, an OR gate, an XOR gate, an XNOR gate, a multiplexer, an adder, a latch, a flip-flop, etc. I can.

Each of the first to fifth header cells C110_1 and C110_1a to C110_1d may be connected to a first power line (eg, RVDD in FIG. 1) and a first virtual power line (eg, VVDD in FIG. 1 ). . Each of the first to fifth header cells C110_1 and C110_1a to C110_1d may have an input pin and an output pin. In an exemplary embodiment, the input pins of each of the first to fifth header cells C110_1 and C110_1a to C110_1d may be connected to a gate electrode of a transistor formed in each of the first to fifth header cells C110_1 and C110_1a to C110_1d, , Switching signals provided from the control circuit may be input. Output pins of each of the first to fifth header cells C110_1 and C110_1a to C110_1d may be connected to the first virtual power line VVDD.

The first header cell C110_1 may include a first N-MOS region NA1 in which N-type transistors having a first threshold voltage VTH_N1 are formed, and a P-MOS region PA in which P-type transistors are formed. have. The first header cell C110_1 may have a first height H1 defined in the second direction Y.

The second header cell C110_1a is a first N-MOS region NA1 in which N-type transistors having a first threshold voltage VTH_N1 are formed, and a second N-type transistor having a second threshold voltage VTH_N2 is formed. It may include an N-MOS region NA2 and a P-MOS region PA in which P-type transistors are formed. The second header cell C110_1a may have a second height H2 defined in the second direction Y.

The P-MOS region PA of the second header cell C110_1a may be disposed between the first N-MOS region NA1 and the second N-MOS region NA2. For example, in the second header cell C110_1a, the second N-MOS region NA2, the P-MOS region PA, and the first N-MOS region NA1 are arranged side by side in the second direction Y. I can.

In an exemplary embodiment, the first threshold voltage VTH_N1 and the second threshold voltage VTH_N2 may be different from each other, and thus, the second header cell C110_1a has a higher retention that is more diverse than the first header cell C110_1. Voltages may be provided to the logic cell connected to the second header cell C110_1a. In addition, the second height H2 may be greater than the first height H1, and the P-MOS region PA of the second header cell C110_1a is greater than the P-MOS region PA of the first header cell C110_1. ) May be formed in a large number of P-type transistors, and a power supply voltage (eg, VDD of FIG. 1) may be relatively stably provided to the logic circuit in the power-on mode.

The third header cell C110_1b is a first N-MOS region NA1 in which N-type transistors having a first threshold voltage VTH_N1 are formed, and a second N-type transistor having a second threshold voltage VTH_N2 is formed. It may include an N-MOS region NA2 and a P-MOS region PA in which P-type transistors are formed. The P-MOS region PA of the third header cell C110_1b may be disposed between the first N-MOS region NA1 and the second N-MOS region NA2. For example, in the third header cell C110_1b, the second N-MOS region NA2, the P-MOS region PA, and the first N-MOS region NA1 are arranged side by side in the second direction Y. I can.

The third header cell C110_1b may have a third height H3 defined in the second direction Y. The P-MOS area PA of the third header cell C110_1b may be wider than the P-MOS area PA of the second header cell C110_1a, and the third height H3 is greater than the second height H2. It can be big. Accordingly, the number of P-type transistors formed in the P-MOS region PA of the third header cell C110_1b may be larger than that of the P-MOS region PA of the second header cell C110_1a, and in the power-on mode A power supply voltage (eg, VDD in FIG. 1) can be stably provided to the logic circuit.

The fourth header cell C110_1c is a first N-MOS region NA1 in which N-type transistors having a first threshold voltage VTH_N1 are formed, and a second N-type transistor having a second threshold voltage VTH_N2 is formed. An N-MOS region NA2, a third N-MOS region NA3 in which N-type transistors having a third threshold voltage VTH_N3 are formed, and a P-MOS region PA in which P-type transistors are formed. I can. In an exemplary embodiment, the first threshold voltage VTH_N1, the second threshold voltage VTH_N2, and the third threshold voltage VTH_N3 may be different from each other. Accordingly, the fourth header cell C110_1c may provide various higher retention voltages to the logic cell than the first to third header cells C110_1, C110_1a, and C110_1b.

The first N-MOS region NA1 and the second N-MOS region NA2 may be disposed to be adjacent to the P-MOS region PA of the fourth header cell C110_1c in the second direction Y, and The third N-MOS region NA3 may be disposed to be adjacent to the P-MOS region PA of the fourth header cell C110_1c in the reverse direction of the second direction Y. In an exemplary embodiment, the third N-MOS region NA3 may be wider than the first N-MOS region NA1 and the second N-MOS region NA2, and is formed in the third N-MOS region NA3. The number of formed N-type transistors may be greater than the number of N-type transistors formed in the first N-MOS region NA1 and greater than the number of N-type transistors formed in the second N-MOS region NA2. have. For example, N-type transistors for providing a specific retention mode with a relatively high frequency of use may be formed in the third N-MOS region NA3, and in the specific retention mode, the fourth header cell C110_1c A voltage equal to subtracting the third threshold voltage VTH_N3 from the power voltage may be provided to the logic cell connected to.

The fifth header cell C110_1d is a first N-MOS region NA1 in which N-type transistors having a first threshold voltage VTH_N1 are formed, and a second N-type transistor having a second threshold voltage VTH_N2 is formed. An N-MOS region NA2, a third N-MOS region NA3 in which N-type transistors having a third threshold voltage VTH_N3 are formed, and a fourth N-type transistor having a fourth threshold voltage VTH_N4 are formed. An N-MOS region NA4 and a P-MOS region PA in which P-type transistors are formed may be included. In an exemplary embodiment, the first to fourth threshold voltages VTH_N1 to VTH_N4 may be different from each other, and thus, the fifth header cell C110_1d is more than the first to fourth header cells C110_1 and C110_1a to C110_1c. Various high retention voltages can be provided to the logic circuit.

The first N-MOS region NA1 and the second N-MOS region NA2 may be disposed to be adjacent to the P-MOS region PA of the fifth header cell C110_1d in the second direction Y, and The third N-MOS region NA3 and the fourth N-MOS region NA4 may be disposed to be adjacent to the P-MOS region PA of the fifth header cell C110_1d in the reverse direction of the second direction Y. have.

The second header cell C110_1a and the third header cell C110_1b may correspond to the header transistor unit 110 of FIG. 2, and the fourth header cell C110_1c corresponds to the header transistor unit 110a of FIG. 4A. Can be. Alternatively, the fourth header cell C110_1c and the fifth header cell C110_1d may correspond to the header transistor unit 120b of FIG. 5. The first to fifth header cells C110_1 and C110_1a to C110_1d illustrated in FIG. 10 are examples in which a power gating circuit including a header transistor unit is implemented as a header cell, and the power gating circuit according to the present disclosure is not limited thereto, and various It can be implemented as a structure header cell.

11 is a layout diagram illustrating a footer cell included in a power gating cell disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11, the first to fifth footer cells C110_2 and C110_2a to C110_2d may include an N-well extending in a first direction X on a substrate and doped with an N-type impurity, and the substrate It may be doped with P-type impurities. Accordingly, the N-MOS region NA in which the N-type transistor is formed may be formed in the substrate, and the P-MOS regions PA1 to PA4 in the N-well where the P-type transistor is formed may be formed. In each of the first to fifth footer cells C110_2 and C110_2a to C110_2d, a footer transistor of the power gating circuit may be formed.

Each of the first to fifth footer cells C110_2 and C110_2a to C110_2d may be connected to a second power line (eg, RGND of FIG. 6) and a second virtual power line VGND. Each of the first to fifth footer cells C110_2 and C110_2a to C110_2d may have an input pin and an output pin. In an exemplary embodiment, the input pins of each of the first to fifth footer cells C110_2 and C110_2a to C110_2d may be connected to a gate electrode of a transistor formed in each of the first to fifth footer cells C110_2 and C110_2a to C110_2d, , Switching signals provided from the control circuit may be input. Output pins of each of the first to fifth footer cells C110_2 and C110_2a to C110_2d may be connected to the second virtual power line VGND.

The first footer cell C110_2 may include a first P-MOS region PA1 in which P-type transistors having a first threshold voltage VTH_P1 are formed, and an N-MOS region NA in which N-type transistors are formed. have. The first footer cell C110_2 may have a first height H1 ′ defined in the second direction Y.

The second footer cell C110_2a includes a first P-MOS region PA1 in which P-type transistors having a first threshold voltage VTH_P1 are formed, and a second P-type transistor having a second threshold voltage VTH_P2 is formed. A P-MOS region PA2 and an N-MOS region NA in which N-type transistors are formed may be included. The second footer cell C110_2a may have a second height H2 ′ defined in the second direction Y.

The N-MOS region NA of the second footer cell C110_2a may be disposed between the first P-MOS region PA1 and the second P-MOS region PA2. For example, in the second footer cell C110_2a, the second P-MOS region PA2, the N-MOS region NA, and the first P-MOS region PA1 are arranged side by side in the second direction Y. I can.

In an exemplary embodiment, the first threshold voltage VTH_P1 and the second threshold voltage VTH_P2 may be different from each other, and thus, the second footer cell C110_2a has various row retentions than the first footer cell C110_2. Voltages may be provided to a logic cell connected to the second footer cell C110_2a. Further, the second height H2 ′ may be greater than the first height H1 ′, and the N-MOS region of the second footer cell C110_2a is greater than the N-MOS region NA of the first footer cell C110_2 The number of N-type transistors formed in (NA) may be large, and a ground voltage (eg, GND in FIG. 7) may be relatively stably provided to a logic cell in a power-on mode.

The third footer cell C110_2b includes a first P-MOS region PA1 in which P-type transistors having a first threshold voltage VTH_P1 are formed, and a second P-type transistor having a second threshold voltage VTH_P2 is formed. A P-MOS region PA2 and an N-MOS region NA in which N-type transistors are formed may be included. The N-MOS region NA of the third footer cell C110_2b may be disposed between the first P-MOS region PA1 and the second P-MOS region PA2. For example, in the third footer cell C110_2b, the second P-MOS region PA2, the N-MOS region NA, and the first P-MOS region PA1 are arranged side by side in the second direction Y. I can.

The third footer cell C110_2b may have a third height H3 ′ defined in the second direction Y. The N-MOS region NA of the third footer cell C110_2b may be wider than the N-MOS region NA of the second footer cell C110_2a, and the third height H3 ′ is the second height H2 ′. Can be greater than ). Accordingly, the number of N-type transistors formed in the N-MOS region NA of the third footer cell C110_2b may be larger than that of the N-MOS region NA of the second footer cell C110_2a, and in the power-on mode A ground voltage (eg, GND in FIG. 7) can be stably provided to the logic cell.

The fourth footer cell C110_2c includes a first P-MOS region PA1 in which P-type transistors having a first threshold voltage VTH_P1 are formed, and a second P-type transistor having a second threshold voltage VTH_P2 is formed. A P-MOS region PA2, a third P-MOS region PA3 in which P-type transistors having a third threshold voltage VTH_P3 are formed, and an N-MOS region NA in which N-type transistors are formed. I can. In an exemplary embodiment, the first threshold voltage VTH_P1, the second threshold voltage VTH_P2, and the third threshold voltage VTH_P3 may be different from each other. Accordingly, the fourth footer cell C110_2c may provide various lower retention voltages to the logic cell than the first to third footer cells C110_2, C110_2a, and C110_2b.

The first P-MOS area PA1 and the second P-MOS area PA2 may be disposed to be adjacent to the N-MOS area NA of the fourth footer cell C110_2c in the second direction Y, and The third P-MOS region PA3 may be disposed to be adjacent to the N-MOS region NA of the fourth footer cell C110_2c in the reverse direction of the second direction Y. In an exemplary embodiment, the third P-MOS area PA3 may be wider than the first P-MOS area PA1 and the second P-MOS area PA2, and is formed in the third P-MOS area PA3. The number of P-type transistors formed may be greater than the number of P-type transistors formed in the first P-MOS region PA1, and may be greater than the number of P-type transistors formed in the second P-MOS region PA2. have. For example, P-type transistors for providing a specific retention mode with a relatively high frequency of use may be formed in the third P-MOS region PA3. In the specific retention mode, the fourth footer cell C110_2c A voltage equal to subtracting the third threshold voltage VTH_P3 from the power supply voltage may be provided to the logic cell connected to.

The fifth footer cell C110_2d includes a first P-MOS region PA1 in which P-type transistors having a first threshold voltage VTH_P1 are formed, and a second P-type transistor having a second threshold voltage VTH_P2 is formed. P-MOS region PA2, a third P-MOS region PA3 in which P-type transistors having a third threshold voltage VTH_P3 are formed, and a fourth P-type transistor having a fourth threshold voltage VTH_P4 are formed. A P-MOS region PA4 and an N-MOS region NA in which N-type transistors are formed may be included. In an exemplary embodiment, the first to fourth threshold voltages VTH_P1 to VTH_P4 may be different from each other, and thus, the fifth footer cell C110_2d is more than the first to fourth footer cells C110_2 and C110_2a to C110_2c. Various low retention voltages can be provided to the logic circuit.

The first P-MOS region PA1 and the second P-MOS region PA2 may be disposed to be adjacent to the N-MOS region NA of the fifth footer cell C110_2d in the second direction Y, and The third P-MOS region PA3 and the fourth P-MOS region PA4 may be disposed to be adjacent to the N-MOS region NA of the fifth footer cell C110_2d in the reverse direction of the second direction Y. have.

The second footer cell C110_2a and the third footer cell C110_2b may correspond to the footer transistor unit 110c of FIG. 7. The first to fifth footer cells C110_2 and C110_2a to C110_2d illustrated in FIG. 11 are examples in which a power gating circuit including a footer transistor unit is implemented as a footer cell, and the power gating circuit according to the present disclosure is not limited thereto, and various It can be implemented as a structured footer cell.

12 is a layout diagram illustrating a header cell included in a power gating cell disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 12, a header cell group C100e may include a first type header cell C110_1b and a second type header cell C110_1b'. Each of the first type header cell C110_1b and the second type header cell C110_1b' is a first power line (eg, RVDD in FIG. 1) and a first virtual power line (eg, VVDD in FIG. 1) Can be connected with.

The first type header cell C110_1b and the second type header cell C110_1b' included in the header cell group C100e may include transistors having different threshold voltages. For example, the first type header cell C110_1b is a first N-MOS region NA1 in which N-type transistors having a first threshold voltage VTH_N1 are formed, and an N-type transistor having a second threshold voltage VTH_N2 A second N-MOS region NA2 in which they are formed, and a P-MOS region PA in which P-type transistors are formed. In addition, for example, the second type header cell C110_1b' has a third N-MOS region NA3 in which N-type transistors having a third threshold voltage VTH_N3 are formed and a fourth threshold voltage VTH_N4. A fourth N-MOS region NA4 in which N-type transistors are formed and a P-MOS region PA in which P-type transistors are formed may be included. In an exemplary embodiment, the first to fourth threshold voltages VTH_N1 to VTH_N4 may be different from each other, but are not limited thereto, and some of the first to fourth threshold voltages VTH_N1 to VTH_N4 may be the same. have.

In FIG. 12, each of the first type header cell C110_1b and the second type header cell C110_1b' is illustrated to have the same shape as the third header cell C110_1b of FIG. 10, but the header cell group C100e according to the present disclosure ) Is not limited thereto. The header cell group C100e may include at least one of the first to fifth header cells C110_1 and C110_1a to C110_1d of FIG. 10.

In an exemplary embodiment, the first type header cell C110_1b and the second type header cell C110_1b ′ included in the header cell group C100e may be arranged side by side in the first direction X, but the present disclosure It is not limited to this. In an exemplary embodiment, the first type header cell C110_1b and the second type header cell C110_1b' included in the header cell group C100e may have the same height, but the present disclosure is not limited thereto.

The first output pin P1 of the first type header cell C110_1b included in the header cell group C100e and the second output pin P2 of the second type header cell C110_1b' may be connected to each other. The first output pin P1 and the second output pin P2 may be connected to a first virtual power line (eg, VVDD of FIG. 1 ). The header cell group C100e can be driven as one header cell. For example, the header cell group C100e may operate similarly to the fifth header cell C110_1d of FIG. 10.

When the number of N-type transistors included in one header cell increases, the size of the header cell may gradually increase, and as the ratio of the P-type transistor to the N-type transistor in one header standard cell gradually decreases, the power- Resistance can be increased in the on mode. Therefore, when the header transistor part of the power gating circuit is implemented with one header cell group C100e, the ratio of the P-type transistor to the N-type transistor is reduced compared to that of implementing the header transistor part with the fifth header cell C110_1d. This can be prevented, and operation characteristics of the header cell group C100e can be easily predicted.

To arrange the header cell group C100e in the integrated circuit, a first type header cell C110_1b and a second type header cell C110_1b' are arranged, and an output pin and a second type header of the first type header cell C110_1b The output pin of the cell C110_1b' may be connected. When the header transistor part of the power gating circuit is implemented with the fifth header cell C110_1d of FIG. 10, routing may be easier compared to that of implementing the header transistor part with the header cell group C100e.

12 illustrates an embodiment in which different types of header cells form one header cell group, but different types of footer cells may form one footer cell group. Output pins of each of the footer cells included in the footer cell group may be connected. For example, the integrated circuit may include a first type footer cell and a second type footer cell connected to the second power line RGND and the second virtual power line VGND, and the first type footer cell The first P-MOS region (PA1 in FIG. 11) in which the first P-type transistors having 1 threshold voltage (VTH_P1 in FIG. 11) are formed and the second P-type transistors having a second threshold voltage (VTH_P2 in FIG. 11) are A second P-MOS region (PA2 in FIG. 11) may be formed, and the second type footer cell is a third P-type transistor in which third P-type transistors having a third threshold voltage (VTH_P3 in FIG. 11) are formed. A fourth P-MOS region in which fourth P-type transistors having a MOS region and a fourth threshold voltage VTH_P4 are formed may be included. In an exemplary embodiment, the first type footer cell and the second type footer cell may be arranged side by side in the first direction (X), and the output pin of the first type footer cell and the output pin of the second type footer cell are Can be connected to each other.

13 is a layout diagram illustrating a header cell and a footer cell included in a power gating cell disposed in an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13, the power gating cell group C100f may correspond to the header transistor unit 110_1d and the footer transistor unit 110_2d of FIG. 9. The power gating cell group C100f may include a third header cell C110_1b and a third footer cell C110_2b. The third header cell C110_1b may be connected to a first power line (eg, RVDD of FIG. 1) and a first virtual power line (eg, VVDD of FIG. 1 ). The third footer cell C110_2b may be connected to a second power line (eg, RVDD in FIG. 1) and a second virtual power line (eg, VVDD in FIG. 1 ). For example, the output pin of the third header cell C110_1b may be connected to the first virtual power line VVDD, and the output pin of the third footer cell C110_2b may be connected to the second virtual power line VGND. have.

In an exemplary embodiment, the third header cell C110_1b and the third footer cell C110_2b included in the power gating cell group C100f may be disposed to overlap each other in the first direction X.

For convenience of explanation, the power gating cell group C100f including the third header cell C110_1b of FIG. 10 and the third footer cell C110_2b of FIG. 11 is shown, but includes header cells and footer cells of various shapes. Various groups of power gating cells may form the power gating circuit 100f. For example, one header cell selected from the first to fifth header cells C110_1 and C110_1a to C110_1d of FIG. 10 and one header selected from the first to fifth footer cells C110_2 and C110_2a to C110_2d of FIG. 11 Cells may constitute a group of power gating cells.

14 is a flow chart showing a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 14, the standard cell library D10 may include information on standard cells, for example, function information, characteristic information, layout information, and the like. The standard cell library D10 may include data defining a layout of a standard cell.

The standard cell library D10 may define a layout of header cells (eg, first to fifth header cells C110_1 and C110_1a to C110_1d in FIG. 10 ). The standard cell library D10 may define a layout of footer cells (eg, first to fifth footer cells C110_2 and C110_2a to C110_2d in FIG. 11 ). In addition, the standard cell library D10 includes the layout of the header cell group (eg, the header cell group C100e of FIG. 12), the layout of the footer cell group, and the power gating cell group (eg, the power gating of FIG. The layout of the cell group C100f) may be defined.

In step S10, a logical synthesis operation of generating netlist data from RTL data may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) refers to a standard cell library (D10) from RTL data written as a hardware description language (HDL) such as VHDL (VHSIC Hardware Description Language) and Verilog to synthesize logic. By performing, it is possible to generate netlist data including a bitstream or netlist.

In step S20, a Place & Routing (P&R) operation of generating layout data D20 from netlist data may be performed with reference to the standard cell library D10. In the arrangement and routing step S20, an operation of arranging standard cells, creating interconnections, and generating layout data D20 may be performed.

For example, a semiconductor design tool (eg, a P&R tool) may arrange a plurality of standard cells by referring to the standard cell library D10 from netlist data. For example, the semiconductor design tool may refer to the standard cell library D10 to select one of layouts of standard cells defined by netlist data, and may arrange the selected layout of the standard cells.

For example, the semiconductor design tool may select one of the first to fifth header cells C110_1 and C110_1a to C110_1d of FIG. 10 and arrange them as a power gating circuit, and the first to fifth footer cells of FIG. C110_2, C110_2a to C110_2d) may be selected and disposed as a power gating circuit. Also, for example, the semiconductor design tool may arrange the header cell group C100e of FIG. 12 as a power gating circuit, and may arrange the power gating cell group C100f of FIG. 13 as a power gating circuit. The semiconductor design tool may arrange a standard cell in consideration of an aspect of easiness in predicting the operating characteristics of a standard cell disposed as a power gating circuit, a size aspect of a resistance in a power-on mode, and an aspect of ease of routing.

The interconnection may electrically connect the output pin and the input pin of the standard cell, and may include, for example, at least one via and at least one routing wire. The layout data D20 may have, for example, a format such as GDSII, and may include geometric information of standard cells and interconnections.

In step S30, OPC (Optical Proximity Correction) may be performed. OPC can refer to an operation for forming a pattern of a desired shape by correcting distortion such as refraction caused by the characteristics of light in photolithography included in a semiconductor process for manufacturing an integrated circuit, and layout data By applying OPC to (D20), the pattern on the mask may be determined.

In step S40, an operation of manufacturing a mask may be performed. For example, as OPC is applied to the layout data D20, patterns on a mask may be defined in order to form patterns formed on a plurality of layers, and at least one mask for forming patterns of each of the plurality of layers (or , Photomask) can be produced.

In step S50, an operation of fabricating an integrated circuit may be performed. For example, an integrated circuit may be manufactured by patterning a plurality of layers using at least one mask manufactured in step S40. In an exemplary embodiment, step S50 may include steps S51 and S52.

In step S51, a front-end-of-line (FEOL) process may be performed. FEOL may refer to a process of forming individual devices, for example, transistors, capacitors, resistors, etc., on a substrate in the manufacturing process of an integrated circuit.

In step S52, a back-end-of-line (BEOL) process may be performed. BEOL may refer to a process of interconnecting individual elements, for example, transistors, capacitors, resistors, etc. in the manufacturing process of an integrated circuit.

Fig. 15 is a block diagram illustrating a computing system including a memory storing a program according to an exemplary embodiment of the present disclosure. At least some of the steps included in a method for manufacturing an integrated circuit (eg, a method for manufacturing an integrated circuit in FIG. 14) according to an exemplary embodiment of the present disclosure may be performed in the computing system 1000. I can.

Referring to FIG. 15, the computing system 1000 may be a fixed computing system such as a desktop computer, a workstation, or a server, or a portable computing system such as a laptop computer. The computing system 1000 includes a processor 1100, input/output devices 1200, a network interface 1300, a random access memory (RAM) 1400, a read only memory (ROM) 1500, and a storage device 1600. Can include. The processor 1100, the input/output devices 1200, the network interface 1300, the RAM 1400, the ROM 1500, and the storage device 1600 may communicate with each other through the bus 1700.

The processor 1100 may be referred to as a processing unit, and an arbitrary instruction set such as a micro-processor, an application processor (AP), a digital signal processor (DSP), and a graphic processing unit (GPU). It may include at least one core capable of executing. For example, the processor 1100 may access memory, that is, the RAM 1400 or the ROM 1500 through the bus 1700, and may execute instructions stored in the RAM 1400 or ROM 1500. .

The RAM 1400 may store a program 1400_1 for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure or at least a portion thereof. For example, the program 1400_1 may include a semiconductor design tool, for example, a logic synthesis tool and a P&R tool.

The program 1400_1 may cause the processor 1100 to perform at least some of the steps included in the method for manufacturing the integrated circuit of FIG. 14. That is, the program 1400_1 may include a plurality of instructions executable by the processor 1100, and the plurality of instructions included in the program 1400_1 cause the processor 1100 to manufacture the integrated circuit of FIG. 14 At least some of the steps included in the method may be performed.

The storage device 1600 may not lose stored data even when power supplied to the computing system 1000 is cut off. For example, the storage device 1600 may include a nonvolatile memory device or a storage medium such as a magnetic tape, an optical disk, or a magnetic disk. The storage device 1600 may store the program 1400_1 according to an exemplary embodiment of the present disclosure, and before the program 1400_1 is executed by the processor 1100, the program 1400_1 or the program 1400_1 from the storage device 1600 At least a portion of it may be loaded into RAM 1400. Alternatively, the storage device 1600 may store a file written in a program language, and a program 1400_1 generated from the file by a compiler or the like or at least a portion thereof may be loaded into the RAM 1400.

The storage device 1600 may store the database 1600_1, and the database 1600_1 may include information necessary for designing an integrated circuit. For example, the database 1600_1 may include the standard cell library D10 of FIG. 14. In addition, the storage device 1600 may store data to be processed by the processor 1100 or data processed by the processor 1100.

The input/output devices 1200 may include an input device such as a keyboard and a pointing device, and may include an output device such as a display device and a printer. The network interface 1300 may provide access to a network outside the computing system 1000.

Claims (20)

A power gating circuit for receiving a power voltage from the first power line and outputting a first driving voltage to the first virtual power line; And
A logic circuit connected to the first virtual power line to receive power from the power gating circuit,
The power gating circuit,
And a P-type transistor and a first N-type transistor connected in parallel between the first power line and the first virtual power line. The method of claim 1,
The power gating circuit operates in a power-on mode, a retention mode, and a power-off mode,
In the power-on mode, the P-type transistor is turned on and the first N-type transistor is turned off, and in the retention mode, the P-type transistor is turned off and the first N-type transistor is turned- And the P-type transistor and the first N-type transistor are turned off in the power-off mode. The method of claim 1,
The power gating circuit operates in a power-on mode and a retention mode,
The power gating circuit outputs a first driving voltage of the power supply voltage in the power-on mode, and outputs a first driving voltage of the retention voltage in the retention mode,
Wherein the retention voltage is a voltage lower than the power supply voltage by a first threshold voltage of the first N-type transistor. The method of claim 1,
The power gating circuit further includes a second N-type transistor connected between the first power line and the first virtual power line,
The integrated circuit, characterized in that the first threshold voltage of the first N-type transistor and the second threshold voltage of the second N-type transistor are different from each other. The method of claim 1,
And the logic circuit is connected to a second power line to which a ground voltage is applied. The method of claim 1,
The power gating circuit receives a ground voltage from a second power line, outputs a second driving voltage to a second virtual power line,
Wherein the power gating circuit comprises an N-type transistor and a P-type transistor connected in parallel to each other between the second power line and the second virtual power line. An integrated circuit comprising a first power gating cell receiving a power voltage from a first power line and providing a first driving voltage to a logic cell through a first virtual power line,
The first power gating cell,
A P-MOS region in which a P-type transistor connected between the first power line and the first virtual power line is formed;
A first N-MOS region in which a first N-type transistor connected between the first power line and the first virtual power line is formed; And
And a second N-MOS region in which a second N-type transistor connected between the first power line and the first virtual power line is formed,
Wherein the P-MOS region is doped with an N-type impurity and includes an N well extending in a first direction. The method of claim 7,
The P-MOS region is disposed between the first N-MOS region and the second N-MOS region. The method of claim 7,
The integrated circuit, characterized in that the first threshold voltage of the first N-type transistor and the second threshold voltage of the second N-type transistor are different from each other. The method of claim 7,
The first power gating cell,
Further comprising a third N-MOS region in which a third N-type transistor connected between the first power line and the first virtual power line is formed,
The first N-MOS region and the second N-MOS region are disposed adjacent to the P-MOS region in a second direction perpendicular to the first direction, and the third N-MOS region is disposed in the second direction. The integrated circuit, characterized in that disposed adjacent to the P-MOS region in the reverse direction of. The method of claim 10,
An integrated circuit, wherein an area of the third N-MOS area is larger than an area of the first N-MOS area. The method of claim 7,
The integrated circuit further includes a second power gating cell that provides the first driving voltage to the logic cell,
The second power gating cell,
A P-MOS region in which a P-type transistor connected between the first power line and the first virtual power line is formed;
A third N-MOS region in which a third N-type transistor connected between the first power line and the first virtual power line is formed; And
And a second N-MOS region in which a fourth N-type transistor connected between the first power line and the first virtual power line is formed. The method of claim 12,
The integrated circuit, characterized in that the first output pin of the first power gating cell and the second output pin of the second power gating cell are connected to each other. The method of claim 7,
The integrated circuit further includes a third power gating cell receiving a ground voltage from a second power line and providing a second driving voltage to the logic cell through a second virtual power line,
The third power gating cell,
An N-MOS region in which an N-type transistor connected between the second power line and the second virtual power line is formed;
A first P-MOS region in which a first P-type transistor connected between the second power line and the second virtual power line is formed; And
And a second P-MOS region in which a second P-type transistor connected between the second power line and the second virtual power line is formed. An integrated circuit comprising a first power gating cell receiving a ground voltage from a ground line and providing a driving voltage to a logic cell through a virtual ground line,
The first power gating cell,
An N-MOS region in which an N-type transistor connected between the ground line and the virtual ground line is formed;
A first P-MOS region in which a first P-type transistor connected between the ground line and the virtual ground line is formed; And
And a second P-MOS region in which a second P-type transistor connected between the ground line and the virtual ground line is formed,
The first P-MOS region is doped with an N-type impurity and is formed in an N well extending in a first direction. The method of claim 15,
And the N-MOS region is disposed between the first P-MOS region and the second P-MOS region. The method of claim 15,
The integrated circuit, characterized in that the first threshold voltage of the first P-type transistor and the second threshold voltage of the second P-type transistor are different from each other. The method of claim 15,
The first power gating cell,
Further comprising a third P-MOS region in which a third P-type transistor connected between the ground line and the virtual ground line is formed,
The first P-MOS region and the second P-MOS region are disposed adjacent to the N-MOS region in a second direction perpendicular to the first direction, and the third P-MOS region is in the second direction. The integrated circuit, characterized in that disposed adjacent to the N-MOS region in the reverse direction of. The method of claim 18,
An integrated circuit, wherein an area of the third P-MOS area is larger than an area of the first P-MOS area. The method of claim 15,
The integrated circuit further includes a second power gating cell that provides the driving voltage to the logic cell,
The second power gating cell,
An N-MOS region in which an N-type transistor connected between the ground line and the virtual ground line is formed;
A third P-MOS region in which a third P-type transistor connected between the ground line and the virtual ground line is formed; And
And a fourth P-MOS region in which a fourth P-type transistor connected between the ground line and the virtual ground line is formed.

Images