KR20200108226A - Gamma voltage generating circuit, source driver and display device including the same - Google Patents

Abstract

A gamma voltage generation circuit includes a first resistor string for setting a voltage range of gamma voltages. A gamma buffers output a selected part of voltages divided within the voltage range. A second resistance string includes tabs respectively connected to output terminals of the gamma buffers, and divides the voltage between the taps to generate the gamma voltages. At least some of the gamma buffers are turned on in a first section and turned off in a second section different from the first section. In the present invention, the range of gamma voltages may be changed according to luminance.

Description

Gamma voltage generation circuit, source driver and display device including the same {GAMMA VOLTAGE GENERATING CIRCUIT, SOURCE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME}

An embodiment of the present invention relates to a gamma voltage generation circuit, a source driver including the same, and a display device.

The display device includes a display panel and a driver. The display panel includes scan lines, data lines, and pixels. The driver includes a scan driver that sequentially provides scan signals to the scan lines and a data driver that provides data signals to the data lines. Each of the pixels may emit light with a luminance corresponding to a data signal provided through a corresponding data line in response to a scanning signal provided through a corresponding scan line.

The data driver may generate gamma voltages corresponding to a plurality of gray levels, and convert a gray level value of image data into a data signal using the gamma voltages.

The range of gamma voltages may be changed according to luminance, and in some cases, characteristics of gamma voltages having changed voltage levels may be different from ideal gamma voltages.

An object of the present invention is to provide a gamma voltage generation circuit that generates ideal gamma voltages, a source driver including the same, and a display device.

In order to achieve an object of the present invention, a display device according to embodiments of the present invention includes: a display unit including a scan line, a data line, and a pixel connected to the scan line and the data line; A gate driver providing a scan signal to the scan line; And a source driver providing a data voltage to the data line, the source driver comprising: a gamma voltage generator generating gamma voltages having different voltage levels in response to a gamma enable signal; A digital-to-analog converter that generates the data voltage corresponding to a gray level value using the gamma voltages; And a source buffer configured to output the data voltage to the data line, wherein the gamma voltage generator comprises: a first resistor string for setting a voltage range of the gamma voltages; Gamma buffers outputting a selected part of voltages divided within the voltage range; And a second resistor string including tabs respectively connected to the output terminals of the gamma buffers, dividing a voltage between the taps to generate the gamma voltages, and at least some of the gamma buffers It is turned on in the first section and turned off in a second section different from the first section.

According to an embodiment, the gamma voltage generator may be a digital gamma voltage generator.

According to an embodiment, the gamma voltage generator may include: a first buffer applying a maximum gamma voltage to one end of the first resistance string; And a second buffer for applying a minimum gamma voltage to the other end of the first resistance string, and the minimum gamma voltage of the second buffer may vary according to a display luminance of the display.

According to an embodiment, the gamma voltages may be non-linear in the first period, and the gamma voltages may be linear in the second period.

According to an embodiment, the first section and the second section are included in one horizontal period, and the source driver may provide the data voltage to the data line at a cycle of the one horizontal period.

According to an embodiment, the scan signal may have a turn-off voltage level in the first period, and the scan signal may have a turn-on voltage level in the second period.

According to an embodiment, some of the gamma buffers may be turned off when the scan signal transitions from the turn-off voltage level to the turn-on voltage level.

According to an embodiment, some of the gamma buffers may be turned off after a point in time when the scan signal transitions from a turn-off voltage level to a turn-on voltage level.

According to an embodiment, in the second period, a first gamma buffer connected to an uppermost tap of the second resistance string among the gamma buffers maintains a turned-on state, and in the second period, among the gamma buffers The second gamma buffer connected to the lowermost tap of the second resistance string may maintain a turned-on state.

According to an embodiment, in the second period, the remaining buffers other than the first and second gamma buffers among the buffers may be turned off.

According to an embodiment, in the second period, a third gamma buffer that is furthest away from the first and second gamma buffers among the buffers may maintain a turned-on state.

According to an embodiment, the first gamma buffer or a fourth gamma buffer adjacent to the second gamma buffer may maintain a turned-on state.

According to an embodiment, the frame section includes a display section in which an image is displayed and a porch section between the display section and another display section, and the display section includes the first section and the second section, and the source The buffer may be turned off in the porch period and turned on in the display period, and at least some of the gamma buffers may be turned off in the porch period and turned on in the display period.

According to an embodiment, the at least some of the gamma buffers may be turned off after the start of the porch period, and the at least some of the gamma buffers may be turned on before the end of the porch period.

According to an embodiment, the display period includes a black period in which a black data voltage corresponding to a black color is provided to the display unit and a valid period different from the black period, and the source buffer is turned off in the black period. It is turned on in the valid period, at least some of the gamma buffers may be turned off in the black period and turned on in the valid period.

According to an embodiment, the first section and the second section may be included in the valid section.

According to an embodiment, in the black period, a first gamma buffer connected to an uppermost tap of the second resistance string among the gamma buffers maintains a turned-on state, and the remaining buffers except for the first gamma buffer Buffers can be turned off.

According to an embodiment, the at least some of the gamma buffers may be turned off after the start of the black period, and the at least some of the gamma buffers may be turned on before the end of the black period.

In order to achieve an object of the present invention, a source driver according to embodiments of the present invention includes: a gamma voltage generator for generating gamma voltages having different voltage levels in response to a gamma enable signal; A digital-to-analog converter that generates a data voltage corresponding to a gray level value by using the gamma voltages; And source buffers outputting the data voltage, wherein the gamma voltage generator comprises: a first resistor string setting a voltage range of the gamma voltages; Gamma buffers outputting a selected part of voltages divided within the voltage range; And a second resistor string including tabs respectively connected to the output terminals of the gamma buffers, dividing a voltage between the taps to generate the gamma voltages, and at least some of the gamma buffers It may be turned on in the first section and turned off in a second section different from the first section.

In order to achieve an object of the present invention, a gamma voltage generation circuit according to embodiments of the present invention includes: a first resistance string for setting a voltage range of gamma voltages; Gamma buffers outputting a selected part of voltages divided within the voltage range; And a second resistor string including tabs respectively connected to the output terminals of the gamma buffers, dividing a voltage between the taps to generate the gamma voltages, and at least some of the gamma buffers It may be turned on in the first section and turned off in a second section different from the first section.

The gamma voltage generation circuit, the source driver, and the display device according to the exemplary embodiments of the present invention generate gamma voltages by using a resistance string, and resistance by using gamma buffers (or gamma amplifiers) in a first section. By applying representative gamma voltages to the tabs of the string, the gamma voltages are rapidly changed to ideal gamma voltages, and at least some of the gamma buffers are turned off (or the output is cut off) in the second period. An error component due to offsets of buffers can be removed. Thus, gamma voltages equal to ideal gamma voltages can be generated. That is, linearity of the gamma voltages can be guaranteed.

In addition, the source driver and the display device may be configured to source The output of the buffer (or the source amplifier) may be reduced and at least some of the gamma buffers may be turned off. Thus, power consumption can be reduced.

1 is a block diagram illustrating a display device according to example embodiments.
2 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1.
3 is a block diagram illustrating an example of a data driver included in the display device of FIG. 1.
4 is a block diagram illustrating an example of a data driver of FIG. 3.
5 is a circuit diagram illustrating an example of a gamma voltage generator included in the data driver of FIG. 3.
6 is a circuit diagram illustrating an example of gamma buffers connected to a third resistor string included in the gamma voltage generator of FIG. 5.
7 is a diagram illustrating an example of gamma voltages output from the gamma voltage generator of FIG. 5.
8A and 8B are waveform diagrams illustrating an operation of the gamma voltage generator of FIG. 5.
9 is a circuit diagram illustrating an example of an operation of the gamma voltage generator of FIG. 5.
10 is a circuit diagram illustrating another example of an operation of the gamma voltage generator of FIG. 5.
11 is a circuit diagram illustrating another example of the operation of the gamma voltage generator of FIG. 5.
12 is a waveform diagram illustrating an example of an operation of the data driver of FIG. 3.
13 is a waveform diagram illustrating another example of the operation of the data driver of FIG. 3.
14 is a waveform diagram illustrating another example of the operation of the data driver of FIG. 3.

In the present invention, various modifications can be made and various forms can be applied, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, the present invention is not limited to the embodiments disclosed below, and may be changed in various forms and implemented.

Meanwhile, in the drawings, some constituent elements not directly related to the features of the present invention may be omitted in order to clearly illustrate the present invention. In addition, some of the components in the drawings may have their size or ratio somewhat exaggerated. Throughout the drawings, the same or similar components are assigned the same reference numerals and reference numerals as much as possible even though they are displayed on different drawings, and redundant descriptions will be omitted.

1 is a block diagram illustrating a display device according to example embodiments.

Referring to FIG. 1, the display device 100 includes a display unit 110 (or a display panel), a scan driver 120 (or a scan driver, a gate driver), and a data driver 130 (or a data driver, source driver), a timing controller 140 (or timing controller), and a light emitting driver 150 (or an emission driver).

The display unit 110 includes scan lines SL1 to SLn, where n is a positive integer (or gate lines), data lines DL1 to DLm, where m is a positive integer, and emission control lines EL1 to ELn. ), and a pixel PXL. The pixel PXL may be disposed in a region (eg, a pixel region) partitioned by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the emission control lines EL1 to ELn.

The pixel PXL may be connected to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the emission control lines EL1 to ELn. For example, the pixel PXL may be connected to the scan line SLi, the previous scan line SLi-1 adjacent to the scan line SLi, the data line DLj, and the emission control line ELi (however, i and j each is a positive integer).

The pixel PXL is initialized in response to a scan signal (or a scan signal provided at a previous time point, a previous gate signal) provided through the previous scan line SLi-1, and a scan signal provided through the scan line SLi (or , In response to a scanning signal and a gate signal provided at the present time), a data signal provided through the data line DLj is stored or recorded, and a data signal stored in response to a light emission control signal provided through the emission control line ELi It can emit light with a luminance corresponding to.

First and second power voltages VDD and VSS may be provided to the display unit 110. The power voltages VDD and VSS are voltages required for the operation of the pixel PXL, and the first power voltage VDD may have a voltage level higher than the voltage level of the second power voltage VSS. Also, an initialization power voltage Vint may be provided to the display unit 110. The first and second power voltages VDD and VSS, and the initialization power voltage Vint may be provided to the display unit 110 from a separate power supply.

The scan driver 120 may generate a scan signal based on the scan control signal SCS and sequentially provide the scan signal to the scan lines SL1 to SLn. Here, the scan control signal SCS includes a start signal, clock signals, and the like, and may be provided from the timing controller 140. For example, the scan driver 120 may include a shift register (or stage) for sequentially generating and outputting a pulsed scan signal corresponding to a pulsed start signal using clock signals. have.

The light emission driver 150 may generate a light emission control signal based on the light emission drive control signal ECS, and may sequentially or simultaneously provide the light emission control signal to the light emission control lines EL1 to ELn. Here, the emission driving control signal ECS includes an emission start signal, emission clock signals, and the like, and may be provided from the timing controller 140. For example, the light emission driver 150 may include a shift register that sequentially generates and outputs a pulse type emission control signal corresponding to a pulse type emission start signal using emission clock signals.

The data driver 130 generates data signals based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and converts the data signals to the display unit 110 (or the pixel PXL). Can be provided. Here, the data control signal DCS is a signal that controls the operation of the data driver 130 and may include a load signal (or a data enable signal) instructing the output of a valid data signal.

In embodiments, the data driver 130 may generate gamma voltages, select one of gamma voltages corresponding to a gray level value in the image data DATA2, and output a data signal (or a data voltage). . The data driver 130 outputs at least some of the gamma voltages (eg, representative gamma voltages) through gamma buffers (or gamma amplifiers), and at least some of the gamma buffers are periodically Can be turned off.

Depending on the luminance, the entire voltage range of the gamma voltages and the target voltage levels of the gamma voltages may be changed. In this case, the actual voltage levels of the gamma voltages output from the gamma buffers are error based on the target voltage levels by the offset of the gamma buffers (or, as an offset voltage, the difference between the ideal output voltage and the actual output voltage). Can have. That is, gamma voltages output from the gamma buffers may have nonlinear characteristics.

Accordingly, the display device 100 (or the data driver 130) according to the embodiments of the present invention turns on the gamma buffers in the first section, and at least some of the gamma buffers (for example, Gamma buffers that output intermediate gamma voltages corresponding to the intermediate gray levels) may be turned off. Here, the second section is a data signal generation section in which a data signal is generated by selecting one of gamma voltages corresponding to a gray level value, and the first section may be a section prior to the second section. In this case, in the first section, gamma voltages are rapidly changed or charged to voltage levels similar to target voltage levels by the turned-on gamma buffers, and in the second section, offset components of the gamma buffers are removed, and the gamma voltage The linearity of (especially, intermediate gamma voltages) can be ensured.

A configuration for generating gamma voltages and a configuration for controlling gamma buffers will be described later with reference to FIGS. 5 to 11.

In embodiments, the data driver 130 may turn off at least some of the gamma buffers in a Porch period (or a blank period) and a black period. Here, the porch section is a section between display sections (ie, sections in which an image is displayed), and the black section may be a section in which only a black image is displayed among the display sections. This is because a valid data signal is not generated in the porch section, and only a gamma voltage corresponding to the black color is required in the black section. Accordingly, power consumption of the data driver 130 (and the display device 100) may be reduced.

A configuration for controlling the gamma buffers in the porch period and the black period will be described later with reference to FIGS. 12 to 14.

The timing controller 140 receives input image data DATA1 and a control signal CS from an external (for example, a graphic processor), and based on the control signal CS, a scan control signal SCS and a data control signal (DCS) is generated, and the image data DATA2 may be generated by converting the input image data DATA1. Here, the control signal CS may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock CLK. The vertical synchronization signal represents the start of frame data (i.e., data corresponding to a frame section in which one frame image is displayed), and the horizontal synchronization signal is a data row (i.e., one of a plurality of data rows included in the frame data). Can indicate the beginning of a row). For example, the timing controller 140 may convert the input image data DATA1 in the RGB format into the image data DATA2 in the RGBG format corresponding to the pixel arrangement in the display unit 110.

Meanwhile, at least one of the scan driver 120, the data driver 130, the timing controller 140, and the light emission driver 150 is formed on the display unit 110 or implemented as an IC to form a tape carrier package. ) Can be connected. Also, at least two of the scan driver 120, the data driver 130, the timing controller 140, and the light emission driver 150 may be implemented as one IC.

2 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1.

Referring to FIG. 2, the pixel PXL may include first to seventh transistors T1 to T7, a storage capacitor Cst, and a light emitting device LD.

Each of the first to seventh transistors T1 to T7 may be implemented as a P-type transistor, but is not limited thereto. For example, at least some of the first to seventh transistors T1 to T7 may be implemented as an N-type transistor.

The first electrode of the first transistor T1 (driving transistor) is connected to the second node N2, or via the fifth transistor T5, to which the first power line (ie, the first power voltage VDD) is applied. Power line). The second electrode of the first transistor T1 may be connected to the first node N1 or may be connected to the anode of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 is a power line that transmits a second power line (that is, a second power voltage VSS) from the first power line through the light emitting element LD in response to the voltage of the third node N3. The amount of current flowing through) can be controlled.

The second transistor T2 (switching transistor) may be connected between the data line DLj and the second node N2. The gate electrode of the second transistor T2 may be connected to the scan line SLi. The second transistor T2 is turned on when a scan signal is supplied to the scan line SLi to electrically connect the data line DLj to the first electrode of the first transistor T1.

The third transistor T3 may be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be connected to the scan line SLi. The third transistor T3 is turned on when a scan signal is supplied to the scan line SLi to electrically connect the first node N1 and the third node N3. Accordingly, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store a data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

The fourth transistor T4 may be connected between the third node N3 and an initialization power line (ie, a power line that transfers the initialization power voltage Vint). The gate electrode of the fourth transistor T4 may be connected to the previous scan line SLi-1. The fourth transistor T4 is turned on when a scan signal is supplied to the previous scan line SLi-1 to supply the initialization power voltage Vint to the first node N1. Here, the initialization power voltage Vint may be set to have a voltage level lower than that of the data signal.

The fifth transistor T5 may be connected between the first power line and the second node N2. The gate electrode of the fifth transistor T5 may be connected to the emission control line ELi. The fifth transistor T5 may be turned off when a light emission control signal is supplied to the light emission control line ELi, and may be turned on in other cases.

The sixth transistor T6 may be connected between the first node N1 and the light emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the emission control line ELi. The sixth transistor T6 may be turned off when the emission control signal is supplied to the emission control line ELi, and may be turned on in other cases.

The seventh transistor T7 may be connected between the initialization power line and the anode of the light emitting device LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SLi. The seventh transistor T7 is turned on when a scan signal is supplied to the scan line SLi to supply the initialization power voltage Vint to the anode of the light emitting element LD.

The anode of the light emitting element LD may be connected to the first transistor T1 via the sixth transistor T6, and the cathode may be connected to the second power line. The light-emitting device LD may generate light of a predetermined luminance in response to the current supplied from the first transistor T1. The first power voltage VDD may be set to have a higher voltage level than the second power voltage VSS so that current flows through the light emitting device LD.

3 is a block diagram illustrating an example of a data driver included in the display device of FIG. 1.

1 and 3, the data driver 130 (or source driver) includes a control unit 310 (or a control circuit), a bias voltage generation unit 320 (or a bias voltage generation circuit), and a gamma voltage. A generation unit 330 (or a gamma voltage generation circuit), a shift register 340, a latch 350, a decoder 360 (or, a digital-analog converter, DAC), and an output buffer 370 may be included. have.

The control unit 310 may receive a data control signal DCS from the timing control unit 140.

The controller 310 may generate a bias control signal BCS based on the data control signal DCS. The bias control signal BCS may be used to adjust the bias voltage Vbias applied to source buffers (or source amplifiers) constituting the output buffer 370.

As will be described later with reference to FIG. 12, in the porch period (and black period), the bias voltage Vbias may be reduced. Power consumption of the output buffer 370 and the data driver 130 may be reduced.

The controller 310 may generate a gamma enable signal G_EN. The gamma enable signal G_EN may control the gamma voltage generator 330 to cause the gamma voltage generator 330 to generate gamma voltages VG0 to VG2047. Here, the gamma voltages VG0 to VG2047 may be used to convert the data DATA (ie, the image data DATA2 described with reference to FIG. 1) into a data voltage (ie, a gray scale voltage). . Meanwhile, the gamma voltages VG0 to V2047 may include 2048 gamma voltages corresponding to 11-bit data, but this is exemplary and is not limited thereto.

The controller 310 may change the serialized data received from the timing controller 140 into parallelized data DATA. The control unit 310 may provide parallelized data DATA to the shift register 340.

The bias voltage generator 320 may generate a bias voltage Vbias having various voltage levels in response to the bias control signal BCS.

The gamma voltage generator 330 may receive the gamma enable signal G_EN to generate gamma voltages VG0 to VG2047 having various voltage levels.

In embodiments, the gamma voltage generator 330 includes a resistance string and gamma buffers that transfer representative gamma voltages to taps of the resistance string, turning on gamma buffers in a first period, and gamma buffers in a second period. At least some of them (eg, gamma buffers that output intermediate gamma voltages corresponding to intermediate gray levels) may be turned off.

In an embodiment, the gamma voltage generator 330 may turn off at least some of the gamma buffers in the porch period and the black period.

In an embodiment, the gamma voltage generator 330 may be a digital gamma voltage generator. In this case, the gamma voltages output from the gamma voltage generator 330 may be linear.

The shift register 340 may provide parallelized data DATA to the latch 350. The shift register 340 may generate a latch clock signal and provide it to the latch, and the latch clock signal may be used to control timing at which parallelized data DATA is output.

The latch 350 may latch or temporarily store data sequentially received from the shift register 340 and transmit it to the decoder 360.

The decoder 360 may convert digital data (ie, a gray scale value of parallelized data DATA) into an analog data signal (or data voltage) using gamma voltages VG0 to VG2047. .

The output buffer 370 may receive the data signal and output it to the data lines DLs (that is, the data lines DL1 to DLm of the display unit 110 described with reference to FIG. 1 ). The output buffer 370 may include source buffers connected to the data lines DLs.

4 is a block diagram illustrating an example of a data driver of FIG. 3. In FIG. 4, for convenience of explanation, focusing on a bias voltage generator 320, a gamma voltage generator 330, a decoder 360, and an output buffer 370 required to drive one pixel PXL, The data driver 130 is shown briefly. Since the bias voltage generator 320, the gamma voltage generator 330, the decoder 360, and the output buffer 370 have been described with reference to FIG. 3, overlapping descriptions will not be repeated.

The gamma voltages VG0 to VG2047 output from the gamma voltage generator 330 may be linear. For example, the gamma voltages VG0 to VG2047 may be located on a straight line corresponding to a linear equation for the gamma code CODE (or digital input value).

The decoder 360 may select one of the gamma voltages VG0 to VG2047 based on the gray value in the data DATA, and output it as the data voltage VGS. For example, the decoder 360 uses a separate lookup table in which the relationship between the gray level value GRAY and the gamma voltages VG0 to VG2047 is defined, or through logical processing on the gray level value, corresponds to the gray level value. The data voltage (VGS) can be output. For example, the data voltage VGS may have 265 voltage levels corresponding to 8-bit gray scale values. The data voltage VGS for each gray level may be located on a gamma curve (eg, a 2.2 gamma curve). That is, the decoder 360 may logically process the linear gamma voltages VG0 to VG2047 to output the data voltage VGS conforming to the 2.2 gamma curve.

The output buffer 370 may include a source buffer 381 (or a source amplifier).

The source buffer 381 may receive a data voltage VGS (or a data signal, a gray voltage) from the decoder 360 and drive the data voltage VGS according to the level of the bias voltage Vbias. The driven data voltage VGS may be output to the pixel PXL through the data line DL. Since a large amount of current is consumed to drive the pixel PXL, the data voltage VGS may be provided to the pixel PXL through the source buffer 381.

5 is a circuit diagram illustrating an example of a gamma voltage generator included in the data driver of FIG. 3. 6 is a circuit diagram illustrating an example of gamma buffers connected to a third resistor string included in the gamma voltage generator of FIG. 5.

3 to 5, the gamma voltage generator 330 includes a first resistance string RST1, a second resistance string RST2, a third resistance string RST3, a first reference selector DEC_TOP, and a first reference selector DEC_TOP. 2 A reference selector DEC_BOT, selectors DEC1 to DEC10, a first reference buffer AMP_REF1, a second reference buffer AMP_REF2, a first buffer AMP_TOP, a second buffer AMP_BOT, and the first to the first 10 gamma buffers AMP_G1 to AMP_G10 (or first to tenth gamma amplifiers) may be included. Although ten gamma buffers AMP_G1 to AMP_G10 are illustrated in FIG. 5, this is exemplary and the number of gamma buffers may be variously changed as necessary.

The first reference buffer AMP_REF1 may output a first reference voltage VREF1, and the second reference buffer AMP_REF2 may output a second reference voltage VREF2. Here, the first reference voltage VREF1 is the minimum voltage that the gamma voltages VG0 to VG2047 can have, the second reference voltage VREF2 is the maximum voltage that the gamma voltages VG0 to VG2047 can have, Each of the first and second reference voltages VREF1 and VREF2 is set based on a driving voltage (or power voltage) applied to the gamma voltage generation circuit, and, for example, the first and second reference voltages VREF1 Each of VREF2 may be selected from voltages obtained by dividing the driving voltage applied to the gamma voltage generating circuit and provided to the first and second reference buffers AMP_REF1 and AMP_REF2.

The first resistance string RST1 is composed of a plurality of resistors, and a voltage between the first and second reference voltages VREF1 and VREF2 may be divided by the resistors.

The first reference selector DEC_TOP selects one of the voltages divided by the first resistance string RST1, and the first buffer AMP_TOP outputs the selected one of the divided voltages as the maximum gamma voltage VG_TOP. can do. Here, the maximum gamma voltage VG_TOP may be set as a gamma voltage having the largest voltage level among the gamma voltages VG0 to VG2047 (eg, a reference gamma voltage VG0 corresponding to the minimum gray level).

Similarly, the second reference selector DEC_BOT selects the other one of the voltages divided by the first resistance string RST1, and the second buffer AMP_BOT selects the other one of the divided voltages as the minimum gamma voltage. It can be output as (VG_BOT). Here, the minimum gamma voltage VG_BOT may define a minimum value of the range of the gamma voltages VG0 to VG2047.

Each of the first and second reference selectors DEC_TOP and DEC_BOT may be implemented with a 12-bit decoder, but this is exemplary and is not limited thereto.

The second resistance string RST2 includes a plurality of first resistors Ra, and a range of the gamma voltages VG0 to VG2047 may be set. The maximum gamma voltage VG_TOP is provided to one end (eg, the upper tap) of the second resistor string RST2, and the minimum gamma voltage (eg, the lower tap) of the second resistor string RST2 VG_BOT) is provided, and the second resistance string RST2 may divide a voltage between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT through the first resistors Ra. Meanwhile, the first resistors Ra may have the same resistance value.

The first selector DEC1 selects one of voltages divided by the second resistance string RST2, and the first gamma buffer AMP_G1 is one selected from among voltages divided by the second resistance string RST2. Is output, and the selected one of the divided voltages may be set as a gamma voltage of the lowest gray scale (or a first gamma voltage VG1, a first representative gamma voltage VGR1, a first tap gamma voltage).

Similarly, each of the second to tenth selectors DEC2 to DEC10 selects one of the voltages divided by the second resistance string RST2, and the second to tenth gamma buffers AMP_G2 to AMP_G10 are Voltages selected by the second to tenth selectors DEC2 to DEC10 may be output, respectively. The voltage selected by the tenth selector DEC10 and output through the tenth gamma buffer AMP_G10 is the maximum gamma voltage VG2047 (or the tenth representative gamma voltage VGR10, the tenth tap gamma voltage). The voltages output through the second to ninth gamma buffers AMP_G2 to AMP_G9 are gamma voltages VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823) (or the second To ninth representative gamma voltages VGR2 to VGR9, second to ninth tap gamma voltages, and tap gamma voltages of intermediate gray levels).

Each of the first to tenth selectors DEC1 to DEC10 may be implemented with a 13-bit decoder, but this is exemplary and is not limited thereto.

Gamma voltages VG1, VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823, VG2047) (or tap gamma voltages) output through the first to tenth gamma buffers AMP_G1 to AMP_G10 are In general, they can be set at equal intervals.

The third resistor string RST3 includes a plurality of second resistors Rb, and may generate gamma voltages VG1 to VG2047 within a gamma voltage range set in the second resistor string RST2. The second resistors Rb may have the same resistance value.

As shown in FIG. 6, the first to tenth gamma buffers AMP_G1 to AMP_G10 are connected to specific taps (or specific tap points) of the third resistance string RST3, and gamma voltages VG1, Reduces the RC delay of VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823, VG2047), and reduces the gamma voltages (VG1, VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823, VG2047). Setting time can be shortened. That is, the first to tenth gamma buffers AMP_G1 to AMP_G10 rapidly charge the gamma voltages VG1, VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823, VG2047 to target gamma voltages, The linearity of the gamma voltages is improved, and the gamma voltages can be more easily controlled.

In embodiments, the second buffer AMP_BOT may change the minimum gamma voltage VG_BOT in response to the luminance control signal LCS. Here, the luminance control signal LCS may be provided from an external device (eg, the timing controller 140). That is, the second buffer AMP_BOT may vary the minimum gamma voltage VG_BOT according to the display luminance of the display device 100, and accordingly, the range of the gamma voltages V0 to V2047 may be adjusted.

However, in this case, nonlinear characteristics may occur in the gamma voltages due to the offset of the first to tenth gamma buffers AMP_G1 to AMP_G10. That is, the analog output may have a nonlinear characteristic compared to the digital input value (CODE).

Meanwhile, at least some of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be turned on or turned off by a gamma buffer control signal CS_AMP (or a gamma enable signal G_EN, see FIG. 3). have. The turn-on/turn-off operation of the first to tenth gamma buffers AMP_G1 to AMP_G10 will be described later with reference to FIG. 8.

7 is a diagram illustrating an example of gamma voltages output from the gamma voltage generator of FIG. 5.

5 to 7, the first curve CURVE1 is when only the first and tenth gamma buffers AMP_G1 and AMP_G10 are operated or turned on (that is, the second to ninth buffers AMP_G2 to AMP_G9). When this is not operated or turned off), gamma voltages output through the third resistance string RST3 corresponding to the first luminance are represented. The second curve CURVE2 represents gamma voltages output through the third resistor string RST3 corresponding to the first luminance when the first to tenth gamma buffers AMP_G1 to AMP_G10 operate. When the first to tenth gamma buffers AMP_G1 to AMP_G10 are operated, the third curve CURVE3 and the fourth curve CURVE4 form a third resistance string RST3 corresponding to the second and third luminances. Each of the gamma voltages output through is represented.

Referring to the first curve CURVE1, when only the first and tenth gamma buffers AMP_G1 and AMP_G10 operate (that is, when the second to ninth buffers AMP_G2 to AMP_G9 do not operate or are turned off) ), tap gamma voltages (especially, intermediate gamma voltages) do not reach target gamma voltages (that is, gamma voltages on the second curve CURVE2) within a specific time due to RC delay, and exhibit a nonlinear characteristic. I can.

Referring to the second curve CURVE2, when all of the first to tenth gamma buffers AMP_G1 to AMP_G10 operate, the RC delay of the gamma voltages is determined by the first to tenth gamma buffers AMP_G1 to AMP_G10. It is reduced, and the gamma voltages reach the target gamma voltages within a specific time, and may have a linear characteristic.

Referring to the third curve CURVE3, when the display luminance of the display device 100 is changed from the first luminance to the second luminance, the minimum gamma voltage VG_BOT described with reference to FIG. 5 is changed. The first to tenth gamma buffers AMP_G1 to AMP_G10 may output tap gamma voltages corresponding to the second luminance. However, as the offset of each of the first to tenth gamma buffers AMP_G1 to AMP_G10 changes according to the change of the minimum gamma voltage VG_BOT, the gamma voltages VG1, VG233, VG455, VG1135, VG1823, and VG2047 are the targets. It may have an error based on the gamma voltages (eg, a dotted line intersecting the third curve CURVE3), and may have a nonlinear characteristic as a whole. Accordingly, the display device 100 may not accurately display a desired image, and display quality may be degraded.

In response to the second luminance, the settings of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be changed, or the control values of the first to tenth selectors DEC1 to DEC10 may be changed, but all luminances that can be changed When the control values of the first to tenth selectors DEC1 to DEC10 are set for these, the cost may increase.

Similar to the third curve CURVE3, when the display luminance of the display device 100 is changed to the third luminance, the gamma voltages according to the fourth curve CURVE4 have a nonlinear characteristic.

Accordingly, the gamma voltage generator 330 according to the embodiments of the present invention turns on the gamma buffers in the first period (eg, the period before generating the data voltage) to bring the gamma voltages closer to the target gamma voltages. Quickly charge, and turn at least some of the gamma buffers (eg, at least one of the second to ninth gamma buffers AMP_G2 to AMP_G9) in the second period (eg, the period for generating the data voltage) By turning it off, errors in gamma voltages can be removed. For example, in the second period, the first and tenth gamma buffers AMP_G1 and AMP_G10 prevent fluctuations in the maximum gamma voltage and the minimum gamma voltage while maintaining the turn-on state, and the second to ninth gamma buffers AMP_G2 To AMP_G9) are turned off, so that the gamma tap points are in a floating state (that is, a state in which the voltage at the corresponding point is variable), and each of the gamma voltages is adjusted by the third resistance string RST3, so that in the first period Error components of the gamma voltages of may be removed.

8A and 8B are waveform diagrams illustrating an operation of the gamma voltage generator of FIG. 5. 8A and 8B illustrate a scanning signal SCAN, a horizontal synchronization signal HSYNC, and a gamma buffer control signal CS_AMP for controlling operations of the gamma buffers AMP_G1 to AMP_G10 described with reference to FIG. 1. . The gamma buffer control signal CS_AMP may be included in the gamma enable signal G_EN described with reference to FIG. 3 or may be provided from the controller 310 to the gamma voltage generator 330 together with the gamma enable signal G_EN. have. 9 is a circuit diagram illustrating an example of an operation of the gamma voltage generator of FIG. 5. 9 illustrates an operation of the gamma voltage generator 330 in the first section shown in FIG. 8.

First, referring to FIGS. 1, 5, and 8A, at a first time point t1, the scan signal SCAN may have a turn-off voltage level (or a logic high level). Therefore, the data signal may not be provided to the pixel PXL.

The horizontal synchronization signal HSYNC transitions from the turn-off voltage level to the turn-on voltage level (eg, a logic low level), and may be maintained at the turn-on voltage level for a predetermined time. That is, the horizontal synchronization signal HSYNC has a first pulse having a turn-on voltage level at a first time point t1, and for example, the first pulse may have a first pulse width PW1.

The gamma buffer control signal CS_AMP may have a first value (eg, FULL) (or a first state). The gamma buffer control signal CS_AMP may have a first value in response to the horizontal synchronization signal HSYNC of the turn-on voltage level. For example, the control unit 310 described with reference to FIG. 3 is a horizontal synchronization signal HSYNC. Based on the gamma buffer control signal CS_AMP may be generated.

In this case, all of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be turned on or maintained in a turned-on state in response to the gamma buffer control signal CS_AMP having the first value. Like the third curve CURVE3 (or fourth curve CURVE4) described with reference to FIG. 7, gamma voltages can be quickly charged to voltages close to target gamma voltages, and the gamma voltages are gamma buffers ( AMP_G1 to AMP_G10) may have an error due to an offset or may exhibit a non-linear characteristic.

Thereafter, at a second time point t2, the gamma buffer control signal CS_AMP may have a second value (eg, LESS) (or a second state) from the first value. In this case, at least some of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be turned off in response to the gamma buffer control signal CS_AMP having the second value.

For example, as illustrated in FIG. 9, the second to ninth gamma buffers AMP_G2 to AMP_G9 (that is, gamma buffers included in the first group GROUP1) may be turned off. The first and tenth gamma buffers AMP_G1 and AMP_G10 may maintain a turn-on state.

In this case, the maximum gamma voltage and the minimum gamma voltage among the gamma voltages maintain a fixed voltage level according to the outputs of the first and tenth gamma buffers AMP_G1 and AMP_G10, and intermediate gamma voltages (for example, Gamma voltages corresponding to the second to ninth gamma buffers AMP_G2 to AMP_G9 may be freed from the outputs of the second to ninth gamma buffers AMP_G2 to AMP_G9. Accordingly, the intermediate gamma voltages are adjusted by the third resistor string RST3, and an error component due to the offset of the gamma buffers AMP_G1 to AMP_G10 may be removed. That is, the intermediate gamma voltages may have a linear characteristic.

Meanwhile, at the second time point t2, the scan signal SCAN may have a turn-on voltage level. For example, the scan signal SCAN may have a pulse having a turn-on voltage level during the second pulse width PWM2. In response to the scan signal SCAN, the data driver 130 generates a data signal using gamma voltages (that is, gamma voltages having a linear characteristic at a second time point t2), and referring to FIG. The described pixel PXL may emit light with a luminance corresponding to a data signal (ie, a data voltage having a more accurate voltage level) in response to the scan signal SCAN.

Meanwhile, the scanning signal SCAN, the horizontal synchronization signal HSYNC, and the gamma buffer control signal CS_AMP at the third time point t3 are the scanning signal SCAN and the horizontal synchronization signal at the first time point t1. HSYNC), and the gamma buffer control signal CS_AMP. That is, the scan signal SCAN, the horizontal synchronization signal HSYNC, and the gamma buffer control signal CS_AMP may have a period between the first time point t1 and the third time point t3.

As described with reference to FIGS. 8A and 9, in the first period P1 in which the scan signal SCAN has a turn-off voltage level (or a period in which the horizontal synchronization signal HSYNC has a turn-on voltage level), gamma All of the buffers AMP_G1 to AMP_G10 are turned on, and in the second period P2 in which the scan signal SCNA has a turn-on voltage level (or a period in which the horizontal synchronization signal HSYNC has a turn-off voltage level), gamma At least some of the buffers AMP_G1 to AMP_G10 (eg, the second to ninth gamma buffers AMP_G2 to AMP_G9) may be turned off. Therefore, while the gamma voltages are more easily controlled, the linear characteristics of the gamma voltages can be ensured.

Meanwhile, in FIG. 8A, at least some of the gamma buffers AMP_G1 to AMP_G10 are turned off at a second time point t2 (ie, a time point at which the scan signal SCAN transitions from the turn-off voltage level to the turn-on voltage level). It has been described as being, but is not limited thereto. For example, as shown in FIG. 8B, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off at a third time point t3, and a third time point t3 is a second time point t2. ) (That is, a time point at which the scan signal SCAN transitions from the turn-off voltage level to the turn-on voltage level). A delay may occur even when the data voltage is written to the pixel (PXL, see FIG. 4), and in consideration of this, the first section P1' may partially overlap the section in which the scan signal SCAN has a turn-on voltage level. May be.

As described with reference to FIGS. 8 and 9, in the first section P1 in which the scan signal SCAN has a turn-off voltage level (or a section in which the horizontal synchronization signal HSYNC has a turn-on voltage level), gamma All of the buffers AMP_G1 to AMP_G10 are turned on, and in the second period P2 in which the scan signal SCNA has a turn-on voltage level (or a period in which the horizontal synchronization signal HSYNC has a turn-off voltage level), gamma At least some of the buffers AMP_G1 to AMP_G10 (eg, the second to ninth gamma buffers AMP_G2 to AMP_G9) may be turned off. Therefore, while the gamma voltages are more easily controlled, the linear characteristics of the gamma voltages can be ensured.

10 is a circuit diagram illustrating another example of an operation of the gamma voltage generator of FIG. 5. 11 is a circuit diagram illustrating another example of the operation of the gamma voltage generator of FIG. 5. 10 and 11 exemplarily illustrate the operation of the gamma voltage generator 330 in the second section P2 shown in FIG. 8.

8A and 10, in the second period P2, first and tenth gamma buffers corresponding to the maximum gamma voltage and the minimum gamma voltage among the first to tenth gamma buffers AMP_G1 to AMP_G10 ( AMP_G1, AMP_G10) may maintain a turned-on state. In addition, a gamma buffer closest to an average of the maximum gamma voltage and the minimum gamma voltage (or the gamma buffer most spaced apart from the first and tenth gamma buffers AMP_G1 and AMP_G10) may maintain a turn-on state. For example, as illustrated in FIG. 10, the fifth gamma buffer AMP_G5 and the sixth gamma buffer AMP_G6 may maintain a turned-on state. The average of the first gamma voltage VG1 and the 2047th gamma voltage VG2047 is the 1024th gamma voltage, and the 1135th gamma voltage (and/or the 911th gamma voltage) may be closest to the 1024th gamma voltage. Accordingly, the fifth gamma buffer AMP_G5 and the sixth gamma buffer AMP_G6 may maintain the turned-on state. Meanwhile, the second to fourth gamma buffers AMP_G2 to AMP_G4 (i.e., gamma buffers included in the second group GROUP2), and the seventh to ninth gamma buffers AMP_G7 to AMP_G9 (i.e. Gamma buffers included in group 3 (GROUP3) may be turned off.

For reference, as the distance from the maximum gamma voltage and the minimum gamma voltage increases, the likelihood that the corresponding gamma voltage deviates from the target gamma voltage may increase. Accordingly, the maximum gamma voltage and the intermediate voltage farthest from the minimum gamma voltage can be fixed by the gamma buffer.

Meanwhile, in FIG. 10, the second to fourth and seventh to ninth gamma buffers AMP_G2 to AMP_G4 and AMP_G7 to AMP_G9 are shown to be turned off, but are not limited thereto. For example, at least one of the third and eighth gamma buffers AMP_G3 and AMP_G8 may further maintain a turn-on state.

8 and 11, only gamma buffers corresponding to a specific grayscale region may be turned off in the second period P2. For example, as shown in FIG. 11, the second to fourth gamma buffers AMP_G2 to AMP_G4 corresponding to the low grayscale region (that is, gamma buffers included in the second group GROUP2) are turned off. Then, the first and fifth to tenth gamma buffers AMP_G1 and AMP_G5 to AMP_G10 may maintain a turned-on state.

That is, only gamma buffers corresponding to a gray scale region in which a gamma voltage that is wrong due to an offset or the like is visually recognized by a user may be turned off.

Meanwhile, in FIG. 11, it is shown that the second to fourth gamma buffers AMP_G2 to AMP_G4 are turned off, but this is illustrative and is not limited thereto. For example, at least one of the sixth to ninth gamma buffers AMP_G6 to AMP_G9 may be turned on.

12 is a waveform diagram illustrating an example of an operation of the data driver of FIG. 3. 12 shows a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), a data enable signal (D_EN), a source buffer control signal (CS_SAP) (or the bias voltage described with reference to FIG. Vbias)), power consumption (SAP) of the source buffer 381 (see FIG. 4), and a gamma buffer control signal CS_AMP described with reference to FIG. 8A are shown. As described with reference to FIG. 1, the vertical synchronization signal VSYNC defines a frame section in which a frame image is displayed, and the horizontal synchronization signal HSYNC defines a horizontal section in which the data driver 130 outputs a data signal. . The data enable signal (D_EN) defines the display section (DISP) (or the effective section (ACTIVE) in which a valid data signal is provided) and the porch section (PORCH) (or blank section), and in the display section (DISP) An image corresponding to the frame data is provided and displayed, and the porch section PORCH may be a section between the end time point and the start time point of the display section DISP.

1, 3, 4, 5, and 12, the horizontal synchronization signal HSYNC may be a pulse signal having a logic low level periodically. The period of the horizontal synchronization signal HSYNC may be defined as one horizontal time (1H).

At the first time point t1, the display section DISP may be terminated according to the data enable signal D_EN, and the porch section PORCH may be started. For example, the data enable signal D_EN may have a logic low level in the display period DISP and a logic high level in the porch period PORCH.

At the second point in time t2, the source buffer control signal CS_SAP may change from a first state value FULL SAP to a second state value LESS SAP. When the source buffer control signal CS_SAP has a first state value (FULL SAP), a full bias voltage is applied to the source buffer 381, and the source buffer control signal CS_SAP has a second state value (LESS SAP). In this case, a relatively low bias voltage may be applied to the source buffer 381. That is, this is because the source buffer 381 that boosts the data voltage does not require a large amount of power consumption in the porch period (PCRCH) period.

The source buffer control signal CS_SAP may change based on the data enable signal D_EN. For example, the state value of the source buffer control signal CS_SAP may change after the first horizontal time 1H when the value of the data enable signal D_EN changes from a logic low level to a logic high level. .

The power consumption SAP of the source buffer 381 may be lowered in response to the second state value LESS SAP of the source buffer control signal CS_SAP.

The gamma buffer control signal CS_AMP may change from a first value FULL to a second value LESS. As described with reference to FIG. 8, when the gamma buffer control signal CS_AMP has a first value FULL, all of the gamma buffers AMP_G1 to AMP_G10 are turned on or maintain a turn-on state, and the gamma buffer control signal CS_AMP When) has the second value LESS, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off. For example, all of the gamma buffers AMP_G1 to AMP_G10 may be turned off.

Since a valid data signal is not generated in the porch period (PCRCH) period, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off. Thus, power consumption can be reduced.

At a third time point t3, the vertical synchronization signal VSYNC may transition from a logic high level to a logic low level.

Thereafter, at a fourth time point t4, the source buffer control signal CS_SAP may change from the second state value LESS SAP to the first state value FULL SAP. For example, the source buffer control signal CS_SAP may change to have a first state value FULL SAP from a second state value LESS SAP in response to the vertical synchronization signal VSYNC.

The power consumption SAP of the source buffer 381 may increase in response to the first state value FULL SAP of the source buffer control signal CS_SAP.

Also, the gamma buffer control signal CS_AMP may be changed to have a first value FULL from a second value LESS. In response to the first value FULL of the gamma buffer control signal CS_AMP, all of the gamma buffers AMP_G1 to AMP_G10 may be turned on.

That is, at the fourth time point t4, the gamma buffers AMP_G1 to AMP_G10 and the source buffer 381 can prepare for generation of a valid data signal (or generation of gamma voltages used to generate a data signal) and output. have.

Thereafter, at a fifth time point t5, the porch section PORCH ends according to the data enable signal D_EN, and the display section DISP may start. That is, before the start of the display period DISP (for example, before the first horizontal time 1H), the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 are normally driven, and the source buffer 381 ) And the charging time of the gamma buffers AMP_G1 to AMP_G10 may be secured.

The width of the section in which the source buffer control signal CS_SAP and the gamma buffer control signal CS_AMP have a logic low level is smaller than the porch section PORCH, is included in the porch section PORCH, and the start point of the porch section PORCH And, a margin (eg, 1 horizontal time (1H)) may be secured based on each of the end points.

Since the operation of the data driving unit 130 at the sixth time point t6 is substantially the same as the operation of the data driving unit 130 at the first time point t1, a duplicate description will not be repeated.

Meanwhile, in FIG. 12, it is shown that the gamma buffer control signal CS_AMP has only the first state value FULL (or a logic high level) in the display period DISP. CS_AMP) is not limited thereto. For example, as described with reference to FIG. 8, the gamma buffer control signal CS_AMP may have a state change within 1 horizontal time (1H) in response to the horizontal synchronization signal HSYNC, and accordingly, the display section In (DISP), at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned on and off at a period of 1 horizontal time (1H).

13 is a waveform diagram illustrating another example of the operation of the data driver of FIG. 3. 14 is a waveform diagram illustrating another example of the operation of the data driver of FIG. 3. 13 and 14 illustrate signals corresponding to FIG. 12.

First, referring to FIGS. 12 and 13, the operation of the data driver 130 at each of the first to sixth time points t1 to t6 is performed at the first to sixth time points t1 to t6 described with reference to FIG. 12. ) Since the operation of the data driver 130 is substantially the same in each of the above, duplicate descriptions will not be repeated.

The data enable signal D_EN may include an effective period ACTIVE and a black period BLACK in the display period DISP. For example, when the display device 100 is driven in a low power mode that displays an image only in a specific region of the display unit 110, such as a watch image, the image data DATA2 (refer to FIG. 1) is For example, it may have a grayscale value that is effective only for a field of view image) and a black grayscale value (eg, a minimum grayscale value) in the remaining area. The effective period ACTIVE may be a period in which an image corresponding to a valid gray level value is displayed, and the black period may be a period in which only an image corresponding to the black gray level value is displayed.

At a fifth point in time t5, the display period DISP may be started according to the data enable signal D_EN, but the black period may be started.

At a seventh time point t7, the source buffer control signal CS_SAP may change from a first state value FULL SAP to a second state value LESS SAP. This is because power consumption of the source buffer 381 that boosts only the black data voltage is required to be relatively low.

The state value of the source buffer control signal CS_SAP may change after the first horizontal time 1H from the start of the black period BLACK.

The power consumption SAP of the source buffer 381 may be lowered in response to the second state value LESS SAP of the source buffer control signal CS_SAP.

The gamma buffer control signal CS_AMP may change from a first value FULL to a second value LESS. Since only the data signal corresponding to black is generated in the porch period (PCRCH) period, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off. For example, all of the gamma buffers AMP_G1 to AMP_G10 may be turned off. As another example, the second to tenth gamma buffers AMP_G2 to AMP_G10 among the gamma buffers AMP_G1 to AMP_G10 may be turned off, and the first gamma buffer AMP_G1 may maintain a turned-on state. Thus, power consumption can be reduced.

In an embodiment, at a seventh time point t7, the source buffer control signal CS_SAP may have a third state value. When the source buffer control signal CS_SAP has a third state value, only the first gamma buffer AMP_G1 is maintained in a turned-on state, and the second to ninth gamma buffers AMP_G2 to AMP_G10 may be turned off. That is, since only the first gamma voltage GV1 is used to implement the black color, only the first gamma buffer AMP_G1 corresponding thereto may maintain the turn-on state. Therefore, the power consumption can be further reduced.

Thereafter, at the eighth time point t8, the source buffer control signal CS_SAP changes to have a first state value FULL SAP from the second state value LESS SAP, and the gamma buffer control signal CS_AMP is a second state value. It can be changed to have a first value FULL from the value LESS. Thereafter, at the ninth time point t9, the valid period ACTIVE may start according to the data enable signal D_EN.

That is, like the operation of the data driver 130 at the fourth time point t4 and the fifth time point t5 described with reference to FIG. At the eighth time point t8 that is before time 1H, the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 are normally driven, and the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 are charged. Time can be secured.

The operation of the data driver 130 at the tenth time point t10, the eleventh time point t11, and the twelfth time point t12 is the fifth time point t5, the seventh time point t7, and the eighth time point t8. ) Is substantially the same as or similar to the operation of the data driver 130 in ), so that the overlapping description will not be repeated.

Meanwhile, in FIG. 13, the black period BLACK is shown to be located between the porch period PORCH and the valid period ACTIVE, but the present invention is not limited thereto.

As shown in FIG. 14, the black period BALCK may be included in the display period DISP and may be located between the valid period ACTIVE and the other valid period ACTIVE. The operations of the data driver 130 (refer to FIG. 1) at the thirteenth time point t13, the 14th time point t14, the fifteenth time point t15, and the sixteenth time point t16 are the fifth time point described with reference to FIG. Since the operation of the data driver 130 is substantially the same at (t5), the seventh time point (t7), the eighth time point (t8), and the ninth time point (t9), overlapping descriptions will not be repeated.

The scope of the present invention is not limited to the content described in the detailed description of the specification, but should be defined by the claims. In addition, the meaning and scope of the claims, and all changes or modified forms derived from the concept of equivalents thereof should be construed as being included in the scope of the present invention.

100: display device 110: display unit
120: scan driver 130: data driver
140: timing control unit 150: light emitting driver
310: control unit 320: bias voltage generation unit
330: gamma voltage generator 340: shift register
350: latch 360: decoder
370: output buffer 381: source buffer
AMP_G1 to AMP_G10: first to tenth gamma buffers

Claims (20)

A display unit including a scan line, a data line, and a pixel connected to the scan line and the data line;
A gate driver providing a scan signal to the scan line; And
And a source driver providing a data voltage to the data line,
The source driver,
A gamma voltage generator for generating gamma voltages having different voltage levels in response to the gamma enable signal;
A digital-to-analog converter that generates the data voltage corresponding to a gray level value using the gamma voltages; And
A source buffer for outputting the data voltage to the data line,
The gamma voltage generator,
A first resistance string setting a voltage range of the gamma voltages;
Gamma buffers outputting a selected part of voltages divided within the voltage range; And
A second resistor string comprising taps respectively connected to output terminals of the gamma buffers, dividing a voltage between the taps to generate the gamma voltages,
At least some of the gamma buffers are turned on in a first period and turned off in a second period different from the first period. The display device of claim 1, wherein the gamma voltage generator is a digital gamma voltage generator. The method of claim 1, wherein the gamma voltage generator,
A first buffer applying a maximum gamma voltage to one end of the first resistance string; And
Further comprising a second buffer for applying a minimum gamma voltage to the other end of the first resistance string,
The display device, wherein the minimum gamma voltage of the second buffer varies according to the display luminance of the display unit. The method of claim 1, wherein the gamma voltages in the first section are nonlinear,
The display device, wherein the gamma voltages are linear in the second period. The method of claim 4, wherein the first section and the second section are included in one horizontal period,
The display device, wherein the source driver provides the data voltage to the data line at a cycle of the one horizontal period. The method of claim 5, wherein the scan signal has a turn-off voltage level in the first period,
The display device, wherein the scan signal has a turn-on voltage level in the second period. The display device of claim 6, wherein some of the gamma buffers are turned off when the scan signal transitions from a turn-off voltage level to a turn-on voltage level. The display device of claim 6, wherein after the scan signal transitions from a turn-off voltage level to a turn-on voltage level, some of the gamma buffers are turned off. The method of claim 1, wherein in the second period, a first gamma buffer connected to an uppermost tap of the second resistance string among the gamma buffers maintains a turned-on state,
In the second period, the second gamma buffer connected to the lowermost tap of the second resistance string among the gamma buffers maintains a turned-on state. The display device of claim 9, wherein in the second period, the remaining buffers except for the first and second gamma buffers are turned off. The display device of claim 9, wherein in the second period, a third gamma buffer, which is furthest away from the first and second gamma buffers among the buffers, maintains a turned-on state. The display device of claim 9, wherein the first gamma buffer or a fourth gamma buffer adjacent to the second gamma buffer maintains a turned-on state. The method of claim 1, wherein the frame section includes a display section in which an image is displayed and a porch section between the display section and another display section,
The display section includes the first section and the second section,
The source buffer is turned off in the porch section and turned on in the display section,
At least some of the gamma buffers are turned off in the porch section and turned on in the display section. The method of claim 13, wherein the at least some of the gamma buffers are turned off after the start of the porch section,
The display device, wherein at least some of the gamma buffers are turned on before the end time of the porch section. The method of claim 13, wherein the display period includes a black period in which a black data voltage corresponding to a black color is provided to the display unit and a valid period different from the black period,
The source buffer is turned off in the black period and turned on in the valid period,
At least some of the gamma buffers are turned off in the black period and turned on in the valid period. The display device of claim 15, wherein the first section and the second section are included in the valid section. The method of claim 15, wherein in the black period, a first gamma buffer connected to an uppermost tap of the second resistance string among the gamma buffers maintains a turned-on state,
The remaining buffers other than the first gamma buffer among the buffers are turned off,
Display device. The method of claim 15, wherein the at least some of the gamma buffers are turned off after the start of the black period,
The display device, wherein the at least some of the gamma buffers are turned on before the end of the black period. A gamma voltage generator for generating gamma voltages having different voltage levels in response to the gamma enable signal;
A digital-to-analog converter that generates a data voltage corresponding to a gray level value by using the gamma voltages; And
Including source buffers for outputting the data voltage,
The gamma voltage generator,
A first resistance string setting a voltage range of the gamma voltages;
Gamma buffers outputting a selected part of voltages divided within the voltage range; And
A second resistance string comprising tabs respectively connected to output terminals of the gamma buffers, dividing a voltage between the taps to generate the gamma voltages,
At least some of the gamma buffers are turned on in a first period and turned off in a second period different from the first period. A first resistance string for setting a voltage range of gamma voltages;
Gamma buffers outputting a selected part of voltages divided within the voltage range; And
A second resistor string comprising taps respectively connected to output terminals of the gamma buffers, dividing a voltage between the taps to generate the gamma voltages,
At least some of the gamma buffers are turned on in a first period and turned off in a second period different from the first period.

Images