KR20200101110A - Copper interconnector, method of manufacturing the copper interconnector, and semiconductor device having the copper interconnector - Google Patents

Abstract

A copper interconnector is disclosed. The copper interconnector includes: a first conductor; a capping layer disposed to cover an upper surface of the first conductor and formed of an electrically conductive material; a dielectric layer disposed on the capping layer and including a trench from which a portion of the capping layer is etched to be removed; a diffusion barrier layer formed with a first thickness on a region of the surface of the dielectric layer which forms a side surface of the trench and a region of the upper surface of the first conductor exposed by the trench, wherein the diffusion barrier layer is formed of amorphous tantalum-manganese oxide; and a second conductor disposed inside the trench covered by the diffusion barrier layer and formed of copper (Cu). Therefore, the present invention can provide the copper interconnector capable of effectively preventing the diffusion of copper.

Description

A copper interconnector, a method of manufacturing the same, and a semiconductor device including the same TECHNICAL FIELD [0002] COPPER INTERCONNECTOR, METHOD OF MANUFACTURING THE COPPER INTERCONNECTOR, AND SEMICONDUCTOR DEVICE HAVING THE COPPER INTERCONNECTOR}

The present invention relates to a copper interconnect for electrically connecting elements in a semiconductor integrated circuit, a method of manufacturing the same, and a semiconductor device including the same.

) 보다 낮은 1.7

을 가지므로, 고집적 회로에 적합하다. Interconnector technology is a technology for electrically connecting devices and devices when manufacturing semiconductor devices.In current semiconductor devices, the specific resistance is lower than that of conventional aluminum or tungsten, and electromigration (EM) and stress migration (SM) are used. Copper (Cu), which has excellent reliability in terms of etc., is widely applied. Copper not only has a higher melting point than aluminum used as a conventional interconnect material, but also has a specific resistance of aluminum (2.7

) Lower than 1.7

As it has, it is suitable for highly integrated circuits.

However, since copper has a very fast diffusivity in silicon or oxide compared to aluminum, there is a need for a diffusion barrier that can block the diffusion of copper. The diffusion barrier is formed of metal materials such as tantalum (Ta), titanium (Ti), cobalt (Co), ruthenium (Ru), which are metals that do not react with copper, and nitride materials such as TaN, TiN, WN, and TaSiN. Has become.

However, according to a recent report, when a diffusion barrier film having a thickness of several nanometers is formed from a metal or nitride, there is a problem that the diffusion of copper cannot be controlled. In addition, when the diffusion barrier layer is formed of nitride, even if the diffusion barrier layer is formed of an amorphous material due to a very good chemical affinity between copper and silicon, there is a problem in that the diffusion barrier performance is deteriorated because it is changed to crystalline at a relatively low temperature.

One object of the present invention is to provide a copper interconnector capable of effectively preventing the diffusion of copper by providing a diffusion barrier layer made of tantalum-manganese oxide.

Another object of the present invention is to provide a method of manufacturing the copper intercancer.

Still another object of the present invention is to provide a semiconductor device including the copper interconnector.

A copper interconnector according to an embodiment of the present invention includes a first conductor; A capping layer disposed to cover an upper surface of the first conductor and formed of an electrically conductive material; A dielectric layer disposed on the capping layer and including a trench for etching a portion of the capping layer; An amorphous tantalum-manganese oxide formed with a first thickness on a region of the surface of the dielectric layer forming a side surface of the trench and a region of the upper surface of the capping layer exposed by the trench, and having a composition of Formula 1 A diffusion barrier layer formed of; And a second conductor disposed inside the trench covered by the diffusion barrier layer and formed of copper (Cu).

[Formula 1]

In Formula 1, x may be a real number of 0.09 or more and 0.6 or less, and y may be a real number of 2 or more and 3 or less.

In one embodiment, x may be a real number of 0.35 or more and 0.55 or less.

In an embodiment, the tantalum-manganese oxide composition may be uniform so that a difference in the ratio of each of the tantalum element and the manganese element is 10% or less in the entire area of the diffusion barrier layer.

In one embodiment, the diffusion barrier layer may have a thickness of 0.5 nm or more and 3 nm or less.

In one embodiment, the first conductor may be formed of copper (Cu) or aluminum (Al).

In one embodiment, the capping layer may be formed of one or more materials selected from the group consisting of CoWP, CoWB, NiMoP, Co, SiN, SiCN, SiC, SiON, and SiCON.

In one embodiment, the dielectric layer may be formed of silicon oxide or silicon nitride.

A method of manufacturing a copper interconnector according to an embodiment of the present invention includes sequentially forming a capping layer and a dielectric thin film on a first conductor; Forming a dielectric layer by forming a trench exposing a portion of the capping layer in the dielectric thin film; Forming an anti-diffusion thin film formed of amorphous tantalum-manganese oxide and having a first thickness on the surface of the dielectric layer including the inside of the trench through a physical vapor deposition (PVD) process; Forming a copper film filling the trench covered with the diffusion barrier film; And removing portions of the diffusion barrier thin film and the copper thin film located outside the trench through a chemical mechanical polishing (CMP) process.

[Formula 1]

In Formula 1, x is a real number of 0.09 or more and 0.6 or less, and y is a real number of 2 or more and 3 or less.

In one embodiment, the trench is formed by a dual damascene process, and is positioned above the lower region and the lower region having a first width adjacent to the capping layer and having a second width greater than the first width. It can be formed to have an upper region.

In one embodiment, the copper thin film may be formed through an electroplating process or a physical vapor deposition (PVD) process.

A semiconductor device according to an embodiment of the present invention includes a first element; A second element disposed to be spaced apart from the first element; And a copper interconnect electrically connecting the first device and the second device, wherein the copper interconnect comprises: a first conductor electrically connected to the first device; A capping layer disposed to cover an upper surface of the first conductor and selectively formed; A dielectric layer disposed on the capping layer and including a trench exposing a portion of the capping layer; Amorphous tantalum-manganese oxide formed to a first thickness on a region of the surface of the dielectric layer forming a side surface of the trench and a region of the upper surface of the capping layer etched by the trench, and having a composition of Formula 1 A diffusion barrier layer formed of; And a second conductor disposed inside the trench covered by the diffusion barrier layer, formed of copper (Cu), and electrically connected to the second device.

[Formula 1]

In Formula 1, x is a real number of 0.09 or more and 0.6 or less, and y is a real number of 2 or more and 3 or less.

In one embodiment, the diffusion barrier layer has a thickness of 0.5 nm or more and 3 nm or less, and the capping layer is at least one material selected from the group consisting of CoWP, CoWB, NiMoP, Co, SiN, SiCN, SiC, SiON, and SiCON. And the first conductor and the second conductor may be electrically connected.

According to the copper interconnector according to the present invention and a semiconductor device having the same, a tantalum-manganese oxide formed by chemical bonding of tantalum (Ta), manganese (Mn), and oxygen (O), which are heat-resistant or wear-resistant metals. By providing a diffusion barrier layer made of, not only can the diffusion of copper effectively be prevented, but even if the diffusion barrier layer is formed to a thickness of about 0.5 to 3 nm, diffusion of copper can be prevented, so that the wiring made of the first conductor and the second conductor is The resistance can be reduced, and as a result, the process temperature range for forming the interconnector wiring can be widened, and the performance and reliability of the semiconductor device can be improved.

1 is a cross-sectional view illustrating a copper interconnector according to an embodiment of the present invention.
2A through 2D are cross-sectional views illustrating a method of manufacturing the copper interconnector shown in FIG. 1.
3 shows the XPS analysis results of each element of the Ta _1-x Mn _x O _y thin film having a thickness of 1 nm of Example 1.
4 are HR-TEM results measured in an initial state after depositing a Ta _1-x Mn _x O _y thin film in the laminates of Examples 1 and 2;
5 is an HR-TEM result measured in an initial state after depositing a Ta _1-x Mn _x O _y thin film in the laminate of Comparative Example 1.
6A and 6B show EDS and EELS element analysis results measured in an initial state after depositing a Ta _1-x Mn _x O _y thin film in the laminate of Example 1.
7A and 7B show EDS and EELS element analysis results measured in an initial state after depositing a Ta _1-x Mn _x O _y thin film in the laminate of Example 2.
8 shows TEM images, EDS, and EELS element analysis results measured after depositing a Ta _1-x Mn _x O _y thin film in the laminate of Example 1 and then heat treatment at 400° C. for 10 hours.
9 are graphs showing IV characteristics and CV characteristics of the laminate of Example 1 before and after heat treatment at 400° C. for 10 hours.
10 to 12 show XPS analysis results and IV characteristics in the laminates of Comparative Example 2, Example 3, and Example 4.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present invention, various modifications may be made and various forms may be applied, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention. In describing each drawing, similar reference numerals have been used for similar elements.

The terms used in the present application are only used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features or steps. It is to be understood that it does not preclude the possibility of addition or presence of, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

1 is a cross-sectional view illustrating a copper interconnector according to an embodiment of the present invention, and FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing the copper interconnector illustrated in FIG. 1.

1, a copper interconnector according to an embodiment of the present invention comprises a first conductor 110, a capping layer 120, a dielectric layer 130, a diffusion barrier layer 140, and a second conductor 150. Can include.

The first conductor 110 may be electrically connected to a first device (not shown), and may be formed of a conductive material. As a material of the first conductor 110, a known wiring material for semiconductor devices may be applied without limitation. For example, the first conductor 110 may be formed of a metal such as copper (Cu), aluminum (Al), and cobalt (Co). Meanwhile, in FIG. 1, the first conductor 110 is shown to be exposed to the outside, but the first conductor 110 may be mounted inside a substrate or dielectric.

The capping layer 120 may be disposed on the first conductor 110 and may be formed of a conductive material. The capping layer 120 prevents contact between the first conductor 110 and the dielectric layer 130 to prevent the metal component of the first conductor 110 from diffusing into the dielectric layer 130. It can play a role of improving reliability by controlling the electromigration of copper. To this end, the capping layer 120 may be formed of a material such as CoWP, CoWB, NiMoP, Co, SiN, SiCN, SiC, SiON, and SiCON.

The dielectric layer 130 is disposed on the capping layer 120 and may include a trench pattern (131 in FIG. 2A) removed by etching the capping layer 120 and a portion of the dielectric layer 130. The trench (131 in FIG. 2A) may be formed such that a lower region adjacent to the capping layer 120 has a first width, and an upper region has a second width greater than the first width. The dielectric layer 130 may be formed of a dielectric material. For example, the dielectric layer 130 may be formed of a material such as silicon oxide, silicon nitride, and low-k dielectric material, and the low-k dielectric material is SiOF, SiOC, SiCOH, porous SiCOH, zeolites, and oxy Materials such as carbosilanes may be included.

The diffusion barrier layer 140 is a surface forming a trench of the dielectric layer 130, for example, a surface of the dielectric layer 310 forming a side surface of the trench and the first conductivity exposed by the trench. The second conductor 150 may be formed on the upper surface of the sieve 110 to have a predetermined thickness, and the second conductor 150 may be disposed inside the trench 131 covered by the diffusion barrier layer 140.

The second conductor 150 may be formed by a copper (Cu) dual damascene process, and the diffusion barrier layer 140 is formed of copper of the second conductor 150 as the dielectric layer 130. It can prevent spreading inside. The second conductor 150 may be electrically connected to a second element (not shown) or a third conductor (not shown), and the first and second conductors 110 and 150 An element (not shown) and the second element or the third conductor may be electrically connected.

In one embodiment, the diffusion barrier layer 140 may be formed of a tantalum-manganese oxide having a composition of the following formula (1), and the tantalum-manganese oxide is uniform throughout the entire area within the diffusion barrier layer 140. It has a composition and can have an amorphous structure without a fast diffusion path of copper. The fact that the tantalum-manganese oxide has a uniform composition over the entire region in the diffusion barrier layer 140 means that the difference between the ratio of the tantalum element and the manganese element is about 10% or less, preferably about 5% or less.

[Formula 1]

In Formula 1, x may be a real number of about 0.09 or more and 0.6 or less, and y may be a real number of about 2 or more and 3 or less. When the value of x is less than 0.09 or exceeds 0.6, the diffusion barrier 140 may not effectively prevent the diffusion of copper. In one embodiment, x may be a real number of about 0.35 or more and 0.55 or less.

Meanwhile, in order to effectively prevent diffusion of copper from the second conductor 150 to the dielectric layer 130, the diffusion barrier layer 140 may have a thickness of about 0.5 nm or more and 3 nm or less. If the thickness of the diffusion barrier layer 140 is less than 0.5 nm, there may be a problem in that copper diffusion cannot be prevented due to the too thin thickness, and when it exceeds 3 nm, tantalum and manganese may occur inside the diffusion barrier layer 140. Due to the phase separation, not only the performance of preventing diffusion of copper is lowered, but also the electrical resistance increases as the copper region inside the second conductor 150 decreases due to an increase in thickness. For example, the diffusion barrier layer 140 may have a thickness of about 1 nm or more and 2.5 nm or less.

Referring to FIGS. 2A to 2D together with FIG. 1, in order to manufacture a copper interconnector according to an embodiment of the present invention, as shown in FIG. 2A, the capping layer ( 120) and a dielectric thin film having a predetermined thickness may be sequentially formed, and then the trench 131 may be formed in the dielectric thin film to form the dielectric layer 130.

A method of forming the trench 131 in the dielectric thin film is not particularly limited.

Subsequently, as shown in FIG. 2B, a diffusion barrier thin film 140 ′ may be formed on the surface of the dielectric layer 130 and the surface of the first conductor 110 exposed by the trench 131.

In one embodiment, the diffusion preventing thin film 140 ′ may be formed by a physical vapor deposition (PVD) method, for example, the first conductor 110 and the capping layer inside a physical vapor deposition chamber. 120) and the structure on which the dielectric layer 130 is formed, a tantalum (Ta) target, and a manganese (Mn) target are mounted, and then argon gas is injected into the deposition chamber in a vacuum to generate argon plasma, and then, The argon plasma collides with the tantalum and manganese targets to deposit tantalum and manganese atoms protruding from the targets on the surface of the dielectric layer 130, and then oxidize them to form the diffusion preventing thin film 140'. The structure, the tantalum target, and the manganese target are mounted inside the deposition chamber so that the surface of the dielectric layer 130 of the structure is parallel to the tantalum target and the manganese target while maintaining a certain distance. Can be.

At this time, after supplying the argon gas, the chamber is maintained at an atmospheric pressure of about 4.0 to 6.0 mTorr, preferably about 5.5 mTorr, with a power of about 5 to 25 W or less, preferably about 5 to 10 W. Argon plasma may be formed by ionizing argon gas, and argon ions forming the plasma may be accelerated to each target by an electric field to collide with the surfaces of the targets. By such collision, atoms or molecules located on the surface of each target physically protrude, and the protruding atoms or molecules will be deposited on the surface of the dielectric layer 130 in the form of an amorphous tantalum-manganese alloy (Ta _x Mn _y ). I can. In addition, since the deposited tantalum-manganese alloy (Ta _x Mn _y ) material is a material having a very high oxygen affinity, it may be oxidized by bonding with oxygen when taken out from the inside of the deposition chamber. The physical vapor deposition process may be performed in a temperature range of about 25° C. to 100° C., the dielectric thin film may be formed to a thickness of about 10 Å to 25 Å, and the tantalum-manganese alloy (Ta _x Mn _y ), the content of manganese may be deposited to be about 9 to 60 atomic%.

Subsequently, as shown in FIGS. 2C and 2D, a copper thin film 150 ″ filling the trench may be formed on the diffusion barrier thin film 140 ′. In an embodiment, the copper thin film 150 ″ may be formed. Silver may be formed through an electroplating process In this case, as shown in FIG. 2C, the copper thin film 150 ″ may be formed by performing an electroplating process after forming a copper seed layer 150 ′. .

Subsequently, as shown in FIG. 1, through a chemical mechanical polishing (CMP) process, a portion of the diffusion preventing thin film 140 ′ and the copper thin film 150 ″ positioned inside the trench 131 The diffusion barrier layer 140 and the second conductor 150 may be formed by removing the remaining portions except for the elements.

According to the copper interconnector according to the present invention and a semiconductor device having the same, a tantalum-manganese oxide formed by chemical bonding of tantalum (Ta), manganese (Mn), and oxygen (O), which are heat-resistant or wear-resistant metals. By providing a diffusion prevention layer made of, not only can the diffusion of copper effectively be prevented, but also by forming the diffusion prevention layer to a thickness of about 0.5 to 3 nm, it is possible to reduce the resistance of the wiring made of the first conductor and the second conductor, As a result, the process temperature range for forming the interconnector wiring can be widened, and the performance and reliability of the semiconductor device can be improved.

Hereinafter, examples, comparative examples, and experimental examples of the present invention will be described. However, the following examples are only some embodiments of the present invention, and the scope of the present invention is not limited to the following examples.

[Examples 1 and 2]

Ta ₁ having a thickness of 1.0 nm (Example 1) and 2.5 nm (Example 2) through a physical vapor deposition (PVD) process using a tantalum target and a manganese target on two silicon wafers coated with a SiO ₂ dielectric layer. _-x Mn _x O _y thin films were formed, respectively, and copper thin films were formed on top of them through a sputtering process. At this time, in the Ta _1-x Mn _x O _y thin films, the ratio of manganese atoms and tantalum atoms was measured to be 53.45:46.55 (see FIG. 3).

[Comparative Example 1]

Except that the formation of the thickness of the Ta _1-x Mn _x O _y thin film as 8nm in Example 1 and 2 with the same method as SiO ₂ dielectric layer is coated with a silicon wafer onto the Ta _1-x Mn _x O _y thin film, and copper Thin films were sequentially formed.

[Experimental Example]

3 shows the XPS analysis results of each element of the Ta _1-x Mn _x O _y thin film having a thickness of 1 nm of Example 1.

Referring to FIG. 3, it can be confirmed that in the Ta _1-x Mn _x O _y thin film, tantalum oxide mostly exists in the form of Ta ₂ O ₅ and manganese oxide exists in the form of MnO, MnO ₂ and Mn ₂ O ₃ . have. In addition, it can be seen that the manganese element and the tantalum element are included in the Ta _1-x Mn _x O _y thin film in a ratio of about 53.45:46.55. From this, in the Ta _x Mn _y O _z thin film, the ratio of the manganese element to the sum of the manganese element and the tantalum element is up to about 0.60 at%, preferably up to about 0.55 at%, stably functioning as a copper diffusion barrier. I think there will be.

4 shows HR-TEM results measured in an initial state after depositing a Ta _1-x Mn _x O _y thin film in the stacks of Examples 1 and 2, and FIG. 5 is a stack of Comparative Example 1, Ta This is the HR-TEM result measured in the initial state after depositing a _1-x Mn _x O _y thin film.

4 and 5, it can be seen that the Ta _1-x Mn _x O _y thin films of Examples 1 and 2 do not cause phase separation and are in an amorphous state, but Ta _1-x Mn _x O _y of Comparative Example 1 In the thin film, it can be seen that the phase separation between the Mn layer and the Ta layer occurred and exist in a crystalline state rather than an amorphous state. Therefore, the thickness of the Ta _1-x Mn _x O _y thin film is preferably less than 8nm, preferably 5nm or less, and more preferably less than or equal to 3nm.

6A and 6B show EDS and EELS element analysis results measured in an initial state after depositing a Ta _1-x Mn _x O _y thin film in the laminate of Example 1, and FIGS. 7A and 7B are Example 2 In the laminate of, the EDS and EELS element analysis results measured in the initial state after depositing a Ta _1-x Mn _x O _y thin film are shown.

6A, 6B, 7A, and 7B, in the laminates of Examples 1 and 2, it can be seen that copper (Cu) did not diffuse into the SiO ₂ dielectric layer during the manufacturing process. That is, it can be seen that the Ta _1-x Mn _x O _y thin films of Examples 1 and 2 function as very excellent copper diffusion barriers.

8 shows TEM images, EDS, and EELS element analysis results measured after depositing a Ta _1-x Mn _x O _y thin film in the laminate of Example 1 and then heat treatment at 400° C. for 10 hours.

Referring to FIG. 8, it can be seen that copper (Cu) did not diffuse into the SiO ₂ dielectric layer even during heat treatment at 400° C. for 10 hours, and any phase separation inside the Ta _1-x Mn _x O _y thin film of Example 1 It can be seen that also did not occur.

9 are graphs showing I-V characteristics and C-V characteristics before and after heat treatment at 400° C. for 10 hours for the laminate of Example 1;

Referring to FIG. 9, in the laminate of Example 1, it was confirmed that there was no change in dielectric breakdown voltage before and after heat treatment, and it was confirmed that the hysteresis curve exhibited by copper diffusion did not appear at all. . In view of these results, it can be seen that the Ta _1-x Mn _x O _y thin film of Example 1 is an excellent and reliable copper diffusion barrier layer.

[Examples 3 and 4]

Ta _1-x Mn _x O _y thin films having a thickness of 1.0 nm were formed on two silicon wafers coated with a SiO ₂ dielectric layer through a physical vapor deposition (PVD) process using a tantalum target and a manganese target. Copper thin films were respectively formed on top of them through a sputtering process. At this time, Embodiment 3 of the Ta _1-x Mn _x O _y Mn ratio of the atom and tantalum atom in the thin film was 37.4: manganese atoms in was 62.6, the third embodiment of the Ta _1-x Mn _x O _y thin film The ratio of and tantalum atoms was 43.5:56.5.

[Comparative Example 2]

Ta _1-x Mn _x O _y thin films having a thickness of 1.0 nm were formed on two silicon wafers coated with a SiO ₂ dielectric layer through a physical vapor deposition (PVD) process using a tantalum target and a manganese target. Copper thin films were respectively formed on top of them through a sputtering process. At this time, the ratio of manganese atoms and tantalum atoms in the Ta _1-x Mn _x O _y thin film of Comparative Example 2 was 8.5:91.5.

[Experimental Example]

10 to 12 show XPS analysis results and I-V characteristics in the laminates of Comparative Example 2, Example 3, and Example 4.

Referring to FIG. 10, in the laminate of Comparative Example 2, it was found that the dielectric breakdown voltage was lowered after heat treatment at 400° C. for 10 hours. That is, it was found that a Ta _1-x Mn _x O _y thin film with a manganese ratio of 8.5 at% or less could not function as a reliable copper diffusion barrier.

However, referring to FIGS. 11 and 12, it was found that in the laminates of Examples 3 and 4, the dielectric breakdown voltage hardly changed even after heat treatment at 400° C. for 10 hours. That is, it can be seen that the Ta _1-x Mn _x O _y thin films of Examples 3 and 4 can function as a reliable copper diffusion barrier.

Based on the above, in order for the Ta _1-x Mn _x O _y thin film to function as a reliable copper diffusion barrier, manganese atoms are about 9 at% or more, preferably about 9 at% or more, based on the sum of manganese atoms and tantalum atoms. It is judged that it would be desirable to contain 35 at% or more.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the present invention described in the following claims. You will understand that you can.

100: copper interconnect 110: first conductor
120: capping layer 130: dielectric layer
140: diffusion barrier layer 150: second conductor

Claims (13)

A first conductor;
A capping layer disposed to cover an upper surface of the first conductor and formed of a stable material;
A dielectric layer disposed on the capping layer and including a trench for etching a portion of the capping layer;
An amorphous tantalum-manganese formed with a first thickness on a region of the surface of the dielectric layer forming a side surface of the trench and a region of the upper surface of the first conductor exposed by the trench, and having a composition of the following formula (1) A diffusion barrier layer formed of an oxide; And
A copper interconnector comprising a second conductor formed of copper (Cu) and disposed inside the trench covered by the diffusion barrier layer:
[Formula 1]

In Formula 1, x is a real number of 0.09 or more and 0.6 or less, and y is a real number of 2 or more and 3 or less. The method of claim 1,
The x is characterized in that the real number of 0.35 or more and 0.55 or less, the copper interconnector. The method of claim 1,
The copper interconnector, wherein the composition of the tantalum-manganese oxide is uniform so that a difference in the ratio of each of the tantalum element and the manganese element is 10% or less in the entire region of the diffusion barrier layer. The method of claim 1,
The diffusion barrier layer is characterized in that it has a thickness of 0.5 nm or more and 3 nm or less, the copper interconnector. The method of claim 1,
The copper interconnector, characterized in that the first conductor is formed of copper (Cu) or aluminum (Al). The method of claim 1,
The capping layer is formed of at least one material selected from the group consisting of CoWP, CoWB, NiMoP, Co, SiN, SiCN, SiC, SiON, and SiCON. The method of claim 1,
The dielectric layer is a copper interconnect, characterized in that formed of silicon oxide, silicon nitride, low-k dielectric material (SiOF, SiOC, SiCOH, Porous SiCOH, Zeolites, Oxycarbosilanes, etc.). The method of claim 1,
The copper interconnector, characterized in that the first conductor and the second conductor are electrically connected. Sequentially forming a capping layer and a dielectric thin film on the first conductor;
Forming a dielectric layer by forming a trench for etching a portion of the capping layer in the dielectric thin film;
Forming an anti-diffusion thin film formed of amorphous tantalum-manganese oxide and having a first thickness on the surface of the dielectric layer including the inside of the trench through a physical vapor deposition (PVD) process;
Forming a copper film filling the trench covered with the diffusion barrier film; And
A method of manufacturing a copper interconnect, comprising the step of removing portions of the diffusion barrier thin film and the copper thin film located outside the trench through a chemical mechanical polishing (CMP) process:
[Formula 1]

In Formula 1, x is a real number of 0.09 or more and 0.6 or less, and y is a real number of 2 or more and 3 or less. The method of claim 9,
The trench is formed to have a lower region having a first width adjacent to the capping layer, and an upper region positioned above the lower region and having a second width greater than the first width. The method of claim 9,
The copper thin film is characterized in that formed through a dual damascene (Dual Damascene) process, a method of manufacturing a copper interconnector. A first element; A second element or a third conductor disposed to be spaced apart from the first element; And a copper interconnect electrically connecting the first device and the second device or the third conductor, wherein the copper interconnect comprises:
A first conductor electrically connected to the first element;
A capping layer disposed to cover an upper surface of the first conductor and formed of an electrically conductive material;
A dielectric layer disposed on the capping layer and including a trench removed by etching a portion of the capping layer;
An amorphous tantalum-manganese oxide formed with a first thickness on a region of the surface of the dielectric layer forming a side surface of the trench and a region of the upper surface of the capping layer exposed by the trench, and having a composition of Formula 1 A diffusion barrier layer formed of; And
A semiconductor device comprising a second conductor disposed inside the trench covered by the diffusion barrier layer, formed of copper (Cu), and electrically connected to the second element or the third conductor:
[Formula 1]

In Formula 1, x is a real number of 0.09 or more and 0.6 or less, and y is a real number of 2 or more and 3 or less. The method of claim 12,
The diffusion barrier layer has a thickness of 0.5 nm or more and 3 nm or less,
The capping layer is formed of at least one material selected from the group consisting of CoWP, CoWB, NiMoP, Co, SiN, SiCN, SiC, SiON, and SiCON,
The semiconductor device, characterized in that the first conductor and the second conductor are electrically connected.

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