KR20200098296A - Dc-dc converter based on chaotic modulation - Google Patents

Abstract

The present invention provides a direct current (DC)-DC converter based on chaotic modulation which can reduce electromagnetic interference (EMI) generated during switching operation. The DC-DC converter based on chaotic modulation comprises: a LC filter including an inductor and a first capacitor connected in series with a voltage source to receive a voltage and providing an output voltage through the first capacitor; a first switching element having one end connected to a current source and the other end connected to one end of the inductor; a second switching element having one end connected to a contact point between the first switching element and the inductor and the other end connected to the ground; and a chaotic pulse-width modulation (CPWM) controller applying a chaotic triangular ramp signal, as a drive signal, to the first and second switching elements, respectively.

Description

Chaos modulation based DC-DC converter {DC-DC CONVERTER BASED ON CHAOTIC MODULATION}

The present invention relates to a DC-DC converter with reduced electromagnetic interference (EMI).

In recent years, portable/wearable electronic devices include circuits such as analog circuits, high-speed digital circuits, high-speed memory, RF circuits, and antennas into a single system-on-chip (SoC) or system. By incorporating in a system-in-package (SiP), its size is decreasing. Since such an electronic device is preferably small and light and has a long battery life, a switched-mode DC-DC converter having high power conversion efficiency is widely used.

However, the high periodical switching frequency of the DC-DC converter generates switching noise, which produces a spectrum noise tone at the fundamental switching frequency and its harmonics. Can cause serious EMI problems. These EMI issues can be particularly serious for SoC or SiP applications that contain sensitive blocks (especially RF or sensor circuits, etc.).

Conventionally, in order to reduce the EMI of the DC-DC converter, a method of optimizing the PCB (printed circuit board) layout, which has a large influence on EMI, has been proposed to reduce EMI. At this time, ringing EMI can be reduced by using a passive loss-less snubber cell. In addition, an EMI filter is sometimes used as a general method to solve the EMI problem.

However, additional components are required to apply these existing EMI reduction methods, which increases manufacturing cost and PCB area, making them unsuitable for small SoC and SiP applications.

On the other hand, since the source of EMI generation in the DC-DC converter is the switching operation, in order to reduce the EMI, problems must be solved during the switching operation. If the switching operation of such a DC-DC converter is properly handled, the need for an additional passive off-chip can be eliminated, as well as superior low-frequency EMI performance compared to the previously proposed EMI reduction methods. Can provide.

Republic of Korea Patent Publication No. 10-2016-0071587 (name of the invention: buck converter)

The problem to be solved by the present invention is to provide a DC-DC converter capable of reducing EMI generated during a switching operation based on chaotic modulation.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

Chaos modulation-based DC-DC converter according to an aspect of the present invention for solving the above-described problem includes an inductor and a first capacitor connected in series with a voltage source to receive a voltage, and the output voltage is supplied through the first capacitor. LC filter provided; A first switching element having one end connected to the current source and the other end connected to one end of the inductor; A second switching element having one end connected to a contact point between the first switching element and an inductor, and the other end connected to a ground; And a chaotic pulse-width modulation (CPWM) controller for applying a chaotic triangular ramp signal as a driving signal to the first and second switching elements, respectively.

In this case, the chaotic pulse width modulation controller includes a second capacitor, a single-pole double-throw switch for charging and discharging the second capacitor, and a controller providing a control signal for triggering the single-pole double-throw switch Chaos signal generator comprising a; And a triangular ramp signal generator configured to receive a chaos signal according to an output voltage by the second capacitor, and generate a chaotic triangular ramp signal by using the chaos signal as a switching driving signal.

In addition, the controller includes: a first comparator for comparing the voltage of the second capacitor with an upper limit reference voltage of the capacitor; A second comparator comparing the voltage of the second capacitor with a lower limit reference voltage of the capacitor; A second SR latch receiving an output of the second comparator and a clock signal; An AND gate receiving an output of the second SR latch and an output of the first comparator; A first SR latch receiving an output of the AND gate and a clock signal; And an XOR gate receiving an output of the first SR latch and the second SR latch, and an output of the XOR gate is a control signal for triggering the single pole double throw switch, and becomes the single pole double throw switch.

In addition, the triangular ramp signal generator includes an error amplifier receiving an output voltage from the second capacitor through a first input terminal, a resistance connected to the second input terminal of the error amplifier and connected to the other terminal to the ground, and increasing the N channel. A first transistor, which is a type MOSFET, with a source connected to a contact point between one end of the resistor and a second input terminal of the error amplifier and a gate connected to the output terminal of the error amplifier, and a second transistor, each of which is a P-channel increasing type MOSFET A voltage current converter including a fifth transistor; One timing capacitor; A comparator including a low threshold comparator to which an output voltage and a low threshold voltage by the timing capacitor are input, and a high threshold comparator to which an output voltage and a high threshold voltage by the timing capacitor are input; A seventh transistor which is an N-channel increase-type MOSFET and operates as a switch by inputting an output of the comparator to a gate; Sixth and eighth transistors each of which are N-channel increase-type MOSFETs and have gates connected to each other; A ninth transistor that is a P-channel increase-type MOSFET, the gate and the gate of each of the second and fourth transistors are connected to each other to operate as a current mirror; And a tenth transistor, which is a P-channel increasing MOSFET, and is connected to a gate and a gate of each of the third and fifth transistors to operate as a current mirror, wherein one end of the timing capacitor is a drain of the fourth transistor and the seventh transistor. It is connected to the drain of the transistor and the input terminal of the comparator, and the other terminal is connected to the ground.

Further, gates of each of the third, fifth and tenth transistors are connected to each other, a source is connected to a power supply voltage, and a drain is connected to a source of the second, fourth and ninth transistors, respectively; The gates of the sixth and eighth transistors are connected to each other, the drains of the eighth and ninth transistors are connected to each other, and the source is connected to the ground.

Further, a current ratio between the third and fifth transistors and the tenth transistor is 2:1, and a current ratio between the second and fourth transistors and the ninth transistor is 2:1.

In addition, the chaos modulation-based DC-DC converter receives a voltage applied to a first resistor and a reference voltage among a first resistor and a second resistor for distributing an output voltage by the first capacitor, respectively, and receives the chaotic triangle ramp signal. An error amplifier for inputting an output signal to an input comparator; A first compensation capacitor connected in parallel to the input terminal and the output terminal of the error amplifier; A first compensation resistor and a second compensation capacitor connected in series to each other and connected in parallel to the first compensation capacitor; And a type-III compensation network circuit connected in series with each other and including a second compensation resistor and a third compensation capacitor connected in parallel to both ends of the first compensation resistor.

In addition, the chaos modulation-based DC-DC converter further includes a PFM controller for outputting a pulse-frequency modulated signal to the first and second switching elements, wherein the PFM controller includes a load current level When (load current level) is less than or equal to a preset threshold voltage, the PFM signal is output, and when the load current level exceeds the threshold voltage, the chaotic triangle ramp signal is output.

Other specific details of the present invention are included in the detailed description and drawings.

According to the disclosed embodiment, by using a chaotic triangle ramp signal as a driving signal of a switch of a DC-DC converter, it is possible to solve an EMI problem that may occur during switching.

In addition, the simplicity of circuit implementation, high EMI improvement, and LC size mitigation can solve EMI problems in many applications such as on-chip and SiP.

1 is a block diagram of a buck converter based on chaos modulation according to an embodiment of the present invention.
2 is a block diagram of a CPWM signal generator according to an embodiment of the present invention.
3 is a circuit diagram of a chaos signal generator according to an embodiment of the present invention.
FIG. 4 is a diagram showing a finite state machine model for explaining the operation of the chaotic signal generator of FIG. 3.
5 is an example of a branch diagram of a mathematical model of an N-type chaos signal generator according to an embodiment of the present invention.
6 is a circuit diagram of a chaotic triangle ramp signal generator according to an embodiment of the present invention.
7 is a diagram illustrating a process of modulating a chaotic triangle ramp signal according to an embodiment of the present invention.
8 is an example of a result of simulating the performance of a buck converter based on chaos modulation according to an embodiment of the present invention.
9 is a diagram showing an example of a phase-portrait between two internal states (inductor current and output voltage) in an operation mode of the buck converter based on chaos modulation under the simulation condition of FIG. 8.
10 is a diagram illustrating a switching frequency distribution according to a simulation result of a chaotic triangle ramp signal generator using slope modulation according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily implement the present invention. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. In order to clearly describe the present invention, parts irrelevant to the description are omitted in the drawings, and similar reference numerals are assigned to similar parts throughout the specification. In addition, while describing with reference to the drawings, drawing numbers may vary depending on the drawings even if the configuration is indicated by the same name, and the drawing numbers are only described for convenience of description, and the concept, characteristics, and functions of each configuration are indicated by the corresponding drawing numbers. Or the effect is not to be interpreted as limiting.

Throughout the specification, when a part is said to be "connected" with another part, this includes not only "directly connected" but also "electrically connected" with another element interposed therebetween. . In addition, when a part "includes" a certain component, it means that other components may be further included, and one or more other components are not excluded unless specifically stated to the contrary. It is to be understood that the presence or addition of features, numbers, steps, actions, elements, parts, or combinations thereof, does not preclude the possibility of preliminary exclusion.

Before describing the structure and operation of a DC-DC converter based on chaotic modulation according to an embodiment of the present invention, a spread-spectrum technique applied to a switching operation to reduce EMI of the DC-DC converter ) Should be explained in general.

In general, the spread spectrum technique can be applied in the controller design stage of the DC-DC converter, and this a priori approach focuses on preventing EMI directly from the switching signal.

In the spread spectrum technique, the shape of the power spectrum of the switching drive signal is adjusted to reduce harmonic peaks. As an example, as one of the conventional spread spectrum techniques for reducing EMI, there is a method using carrier frequency modulation (CFM). According to this method, a flat power spectrum can be obtained by using sinusoidal modulation in which the driving signal is a sinusoidal wave. This method has the advantage of being simple to implement, but the EMI reduction performance is not high in that it generates a "U"-shaped power spectrum that peaks at the two end points. Accordingly, there is a method of using a cubic waveform as a driving signal to mitigate the peaks at the two end points of the "U"-shaped power spectrum while maintaining the sine wave-based modulation, but this greatly increases the complexity of the circuit. Let it. On the other hand, a triangular waveform or a sawtooth waveform is easy to implement a circuit, and among them, the triangular waveform can provide EMI performance similar to that of a third-order waveform-based modulation. Accordingly, the DC-DC converter according to an embodiment of the present invention replaces a third-order waveform as a switching driving signal with a triangular waveform and applies it to CFM.

Meanwhile, the general CFM spread spectrum technique has a limitation in generating a discrete modulated power spectrum by a periodic characteristic of a driving signal. In order to overcome this limitation, random pulse-amplitude modulation may be used when generating a power spectrum. That is, if a uniform random distribution can be obtained using random pulse amplitude modulation, the resulting EMI spectrum can be continuous.

For example, a random source can be approximated using a chaos generator. For reference, chaos phenomenon is a phenomenon that occurs widely in nonlinear dynamometers, and the chaos signal generated through the chaos signal generation circuit is used for encryption of communication messages or randomly randomized due to its unique characteristic that generates a “noise-like” signal. It can be utilized as a source for generating a signal.

According to this approach, self-tuning offset and amplitude-adaptive ramp control for DC-DC converters (e.g. buck converter and boost converter, etc.) control). This solution significantly improves EMI reduction in both the buck converter and the boost converter, but has the disadvantage of being costly and applicable only at the PCB level. In addition, the offset amplitude tuning method may improve EMI reduction, but may cause a problem in the stability of the DC-DC converter.

Accordingly, the DC-DC converter according to an embodiment of the present invention is a spread spectrum to be applied to a switching operation, such as randomized pulse-width modulation (RPWM) and chaotic pulse-width modulation (CPWM). Use. At this time, the spread spectrum method applied to the DC-DC converter is realized by operating the DC-DC converter in an aperiodic mode.

For reference, an analog chaotic generator can be used to form a CPWM for the converter. In this case, excellent performance for EMI reduction can be achieved, and the design is simple and flexible. However, the oscillation circuit of this analog chaos generator may be unsuitable for small applications because of a number of commercially available (off-the-shelf) need a passive inductor and capacitor (passive inductor / capacitor (μ H and μ F range)). Accordingly, the DC-DC converter according to an embodiment of the present invention may include an on-chip CMOS-based CPWM signal generator. That is, a digital chaos signal generator may be used as a chaotic signal generator that generates a constant switching frequency of the DC-DC converter.

Meanwhile, the CPWM generator used in the DC-DC converter modulates only for chaotically hopping among four fixed frequency levels that generate an upper limit for EMI reduction. Accordingly, the DC-DC converter according to an embodiment of the present invention may additionally apply an RPWM technique, which is an approach based on a spread spectrum technique called frequency hopping. Specifically, the RPWM scheme randomly distributes the switching frequency to 8 fixed frequency sets, thereby reducing the spectrum only around a predefined frequency set.

However, RPWM and CPWM methods have high output voltage and inductor current ripple. To solve this, the DC-DC converter according to an embodiment of the present invention processes a dual mode (ie, pulse width modulation (PWM) and pulse-frequency modulation (PFM)) voltage control.

At this time, the DC-DC converter includes a simple and complete on-chip CMOS chaos signal generator associated with an N-shaped chaos map to generate a controllable chaos signal. For reference, a stroboscopic sampling method can be used as a mathematical model for the chaos map circuit, and the chaos behavior can be analyzed through Lyapunov exponent theory and bifurcation diagram. .

Hereinafter, a buck converter will be described as a DC-DC converter based on chaos modulation according to an embodiment of the present invention. For reference, the buck converter is applied to most battery-powered devices due to its simple power conversion step and high power efficiency.

1 is a block diagram of a buck converter based on chaos modulation according to an embodiment of the present invention.

In FIG. 1, a schematic diagram of a dual-mode PWM/PFM buck converter 100 with reduced EMI based on chaotic modulation is shown, but a SiP buck receiving power from a battery indicated by a voltage source (V _IN or V _BAT ) 111 The converter 100 is shown.

In the buck converter 100, the high-side switch (HSW) 112 and the (low-side switche, LSW) 113 may each be implemented as a switching element such as a transistor, and two switches 112, 113) is turned on/off by a driving signal input from the PWM controller 20 and the PFM controller 30. Accordingly, the voltage output of the buck converter 100 is controlled.

The PWM controller 20 turns on/off the HSW 112 and the LSW 113 using CPWMP/CPWMN which is a non-overlapping pulse. The CPWMP/CPWMN signals are input to the HSW 112 and LSW 113, respectively, and are applied through the dead time buffer 114.

The LC filter 10 includes an inductor L 11 and a capacitor C _OUT (hereinafter, referred to as “output capacitor” for differentiation from other capacitors) 13, and ERL 12 and ESR 14 ) Denotes parasitic resistance inside the inductor (L) 11 and the output capacitor 13, respectively.

At this time, one end of the HSW 112 is connected to the voltage source 111 and the other end is connected to one end of the inductor 11. One end of the output capacitor 13 is connected to the other end of the inductor 11, and the other end of the output capacitor 13 is connected to the ground. In addition, one end of the LSW 113 is connected to a contact point between the HSW 112 and the inductor 11, and the other end of the LSW 113 is connected to the ground.

An input voltage is supplied from the voltage source 111 to the LC filter 10, and an output voltage V _OUT is provided through the inductor 11 and the output capacitor 13. At this time, the output voltage V _OUT is a voltage applied to both ends of the output capacitor 13 and is supplied to the load R _LOAD . In addition, the output voltage V _OUT is divided by the two resistors (R _FB1 , R _FB2 ) (116, 117) to become the feedback voltage FB, and this feedback voltage FB is an error amplifier (EA) of the PWM controller 20 (23) and the PFM controller 30, respectively. Resistors R _FB1 and R _FB2 (116, 117) are connected in series with each other, one end of R _FB1 (116) is connected to the contact between the inductor (11) and the output capacitor (13), and the other end of R _FB1 (116) is One end of R _FB2 (117) is connected, and the other end of R _FB2 (117) is connected to ground.

The error amplifier 23 amplifies a difference value between the reference voltage V _REF input from the BGR circuit 50 and the output voltage by the output capacitor 13 to generate an output signal.

The bandgap reference (BGR) circuit 50 adjusts the output voltage of the converter 100 by outputting a preset reference level voltage V _REF (for example, 1.2V).

The zero-current detection comparator 115 turns off the LSW 113 in order to eliminate conduction losses when the buck converter 100 enters a low load state. ZCD) signal is output. At this time, the zero-current detection comparator 115 outputs a result of comparing the switching node voltage V _SW and the ground voltage to control turn-off of the LSW 113.

The buck converter 100 has an automatic mode change function between PWM and PFM according to a load current level.

For example, assuming that the output corresponding to the load is 50mA ~ 500mA, the buck converter 100 operates in PWM mode when the load current is greater than 200mA, and when the load current is less than 200mA, the power stage is reduced according to the load demand. It can automatically switch to the intermittent PFM mode. At this time, in PFM mode, switching activity is reduced to minimize switching losses and maintain high power efficiency of the converter.

2 is a block diagram of a CPWM signal generator according to an embodiment of the present invention.

Referring to FIG. 2, in order to generate a CPWM signal, the buck converter 100 includes a type-III compensation network circuit 60.

For reference, type III compensation is a voltage-mode-controlled converter operating in a continuous conduction mode (CCM) compared to type-I and type-II. ) Is used for optimized loop bandwidth and fast transient response. Accordingly, the buck converter 100 generates a CPWM signal for EMI reduction by using a type III compensation network.

The output voltage by the output capacitor 13 is input to the error amplifier 23 using this type III compensation network circuit 60.

Specifically, the type-III compensation network circuit 60 includes a first compensation capacitor C1 connected in parallel to the input terminal and the output terminal of the error amplifier 23, and a first compensation capacitor connected in series with each other. A first compensation resistor (R1) and a second compensation capacitor (C2) connected in parallel to C1), a second compensation resistor (R2) and a third compensation capacitor (R2) connected in series to each other but connected in parallel to both ends of R _FB1 (116) ( C3).

In addition, as shown in FIG. 1 above, the PWM controller 20 of the buck converter 100 includes an N-shaped chaos generator circuit 21 and a symmetrically triangular ramp generator ( 22).

At this time, the output of the N-type chaos signal generator 21 (that is, the chaos signal Vchaos) is applied to V _H or V _BR of the symmetric triangular ramp generator 22, and accordingly, the symmetric triangular ramp generator 22 (chaotic triangular ramp signal, V _CTR ) is generated.

The comparator 24 receives the chaotic triangle ramp signal generated through the chaotic signal generator 21 and the triangle ramp generator 22 and the output signal V _EA of the error amplifier 23. Accordingly, the comparator 24 compares the slowly changing signals V _EA and V _CTR signals in the error amplifier 23, and as a result, generates CPWM to control the power switch operation of the HSW 112 and LSW 113. Output as a drive signal. As described above, the CPWM signal output through the comparator 24 is applied to the HSW 112 and LSW 113 through the dead time buffer 114 as CPWMP and CPWMN signals, respectively.

In this chaotic operation mode, the switching period (T _SW ) of the HSW 112 and LSW 113 changes in a disorderly manner, and the duty cycle also changes from cycle to cycle. However, since the average duty cycle is constant, this means that the output voltage follows a predetermined value as expected. In addition, the inductor current and output voltage also change chaoticly, so that the associated spectrum can spread over a specific frequency range. In this way, EMI is significantly reduced by using the characteristics of the broadband frequency spectrum in the chaotic signal. In addition, the switching frequency F _SW is continuously modulated within a predefined range, which is equivalent to hopping between infinite switching frequencies. Thus, it is possible to completely eliminate the peaks in the power spectrum that appear in standard fixed frequency PWM mode.

Meanwhile, as described above, the EMI reduction method through the spread spectrum technique may result in the following performance reduction of the buck converter. That is, an increase in output voltage ripple, an increase in inductor current ripple, and a decrease in power efficiency may occur. In order to solve this problem, there is a method of increasing the size of the passive LC filter of the buck converter, but when designing the SiP buck converter, the space inside the package is limited, so it is difficult to use a large LC filter.

Accordingly, the buck converter 100 according to an embodiment of the present invention mitigates side effects of the spread spectrum technique by using a ramp generator that generates a triangular waveform signal instead of a sawtooth waveform. The triangular waveform signal mitigates the ripple in the inductor current, which can mitigate the performance degradation of the buck converter even if a large LC filter is not used.

3 is a circuit diagram of a chaos signal generator according to an embodiment of the present invention. And FIG. 4 is a diagram showing a finite state machine model for explaining the operation of the chaos signal generator of FIG. 3.

As shown in Figure 3, the N-type chaos signal generator 21 is one capacitor (C) 211, which are charged and discharged respectively by a current source (I ₁ ) and a current sink (I ₂ ), a single pole double throw switch (single-pole double-throw switch, SPDT) 218, and an SPDT controller that provides a control signal to trigger the SPDT 218. At this time, the SPDT controller includes first and second comparators (U1, U2) 212, 213, first and second SR latches 214 and 215, one AND gate 216, and one XOR gate 217. ).

The N-type chaos signal generator 21 may be implemented as a complementary metal-oxide semiconductor (CMOS) chaos signal generation circuit.

Specifically, the first comparator (U1) 212 resets the first SR latch 214 so that the capacitor 211 is charged. In addition, the second comparator (U2) 213 sets the second SR latch 215 so that the capacitor 211 is discharged.

The first comparator (U1) 212 receives and compares the voltage of the capacitor 211 and the upper limit reference voltage V _HC, and inputs the result to the first SR latch 214. Also, the first SR latch 214 receives a clock signal. Here, V _HC corresponds to the upper limit of the voltage of the capacitor 211.

The second comparator (U2) 213 receives and compares the voltage of the capacitor 211 with the lower limit reference voltage V _LC, and inputs the result to the second SR latch 215. At this time, the AND gate 216 receives the output of the second comparator (U2) 213 and the output of the first latch 214, and inputs the corresponding output signal to the second latch 215. Also, the second latch 215 receives a clock signal. Here, V _LC corresponds to the lower limit of the voltage of the capacitor 211.

The XOR gate 217 receives signals from the two SR latches 214 and 215 and applies an output signal V _ctr to the SPDT 218 to control its driving. Accordingly, the voltage v(t) applied to the capacitor 211 changes. That is, in the N-type chaos signal generator 21, the state variable is v(t).

In this way, the N-type chaos signal generator 21 uses two comparators to use two references, so that the output value v(t) can be prevented from being trapped at a specific point outside the chaos map according to noise or parameter variables. I can.

Specifically, the operation of the N-type chaos signal generator 21 may be expressed by a finite state machine (FSM) model as shown in FIG. 4A.

As shown in (a) of FIG. 4, the finite state machine of the N-type chaos signal generator 21 can be represented by three states of S1, S2, and S3. At this time, S1 and S3 correspond to the state of charge of the capacitor 211 when v(t) is the rising edge of the clock period T or when V _HC is reached, and S2 corresponds to the state of charge of the capacitor 211 when v(t) is the V _LC It corresponds to the discharge state of the capacitor 211 when it reaches. At this time, as mentioned above, the N-type chaos signal generator 21 may be expressed as a 1D piece-wise map by applying a stroboscope map based on a strobe sampling technique.

Specifically, when the capacitor 211 reaches V _HC at time t _H , the control signal V _ctr is triggered high (Q = 1), and the capacitor 211 is Equation 1 below through the sink current I ₂ Is discharged as.

In addition, at the start of the next period T (t _k ), the control signal V _ctr is triggered low (Q = 0) by the clock signal, so that the capacitor 211 is charged as shown in Equation 2 below through the current source (I ₁ ). do.

On the other hand, the finite state machine can evolve according to three possibilities, which depends on the value of the state variable v(t) at the beginning of the next period T (t _k ).

First, the state space can be divided into two sub-spaces (R1 and R2+R3) depending on the boundary condition V _b1 related to V _LC . V _b1 is defined as the voltage level at which v(t) is charged from V _LC to V _b1 within one clock period T. V _b1 can be calculated by Equation 3 below.

For example, if V _k <V _b1 at time t _k , capacitor 211 continues charging for the next clock cycle according to the finite machine state S1. This scenario is shown in (b) of FIG. 4, and referring to this, the variable v(t) at t _k is located in the state subspace R1.

However, if V _k >V _b1 at time t _k , the sub-space representing a voltage higher than V _b1 is additionally divided into two sub-spaces R2 and R3. It can be separated depending on the boundary condition V _b2 .

At this time, when the variable v(t) is located in the state subspace R2 at t _k , the capacitor 211 is charged until reaching V _HC during the period t _{a and} then discharged during the period t _b . This is shown in Figure 4 (c). The periods t _a and t _b can be calculated by Equation 4 below.

In addition, when the variable v(t) is located in the state subspace R3 at t _k , the capacitor 211 continues charging for _a period t _a until reaching V _HC , and then discharges for a period t _b until V _LC , Start charging again and charge for a period of t _c . This is shown in Fig. 4(d). In this case, the sum of the periods t _a and t _b is smaller than the period T, and the periods t _b and t _c may be calculated through Equation 5 below.

Here, the second boundary condition V _b2 can be derived under the same conditions as in Equation 6 below.

On the other hand, as a stroboscopic map applied to the N-type chaos signal generator 21, an N-shaped map relating the value of the state variable v(t) for every clock instant is Equation 7 below. It can be expressed as

This N-type map may be normalized and parameterized as shown in Equation 8 below.

Accordingly, the standardized chaos map of the N-type chaos signal generator 21 can be expressed as Equation 9 below.

At this time, x is a system variable, and T ₁ and T ₂ are new parameters obtained by parameterizing circuit parameters T, I ₁ , I ₂ , and reference voltages V _R and C.

Meanwhile, prior to implementing the circuit of the chaotic signal generator, a mathematical model for the chaotic signal generator may be implemented to find a range of system parameters for the circuit to output a chaotic signal.

The dynamic behavior of the chaos system can be qualitatively obtained through Lyapunov exponents, and the Lyapunov exponent of the N-type map can theoretically be calculated through Equation 10 below.

In this case, f'(.) is a differential value of the chaos map f(.), and can be derived through Equation 11 below.

Accordingly, the Liapunov index can be calculated as in Equation 12 below.

Here, n is the number of x points used in the calculation, and i, j, k are the number of times that x falls in the three ranges [0, x _b1 ], [x _b1 , x _b2 ], and [x _b2 , 1], respectively. Means.

In Equation 12, when (T ₂ /T ₁ )>1 and λ>0, the N-type map is cyclically branched twice, thereby generating a chaotic signal. On the other hand, if (T ₂ /T ₁ )<1 and λ<0, the system output is in a periodic state or converges to a stable point.

In addition, the chaotic dynamics can be observed through a bifurcation diagram.

5 is an example of a branch diagram of a mathematical model of an N-type chaos signal generator according to an embodiment of the present invention.

For example, if T ₁ =0.5 and T ₂ gradually increases from 0, the branching diagram can be represented as shown in FIG. 5, through which the dynamic behaviors, periodicity, and chaos (density High area). Referring to FIG. 5, the range of T ₂ related to the dense area of the diagram shows a chaotic behavior, which can be used to design a CMOS chaotic signal generation circuit. That is, parameters for designing the circuit of the N-type chaos signal generator 21 can be conveniently selected based on the branch diagram of FIG. 5. In addition, the branch diagram emphasizes the rigidity of the system parameter (T ₂ ) versus chaos generation in the N-type map.

Meanwhile, as described above, in the voltage mode of the buck converter 100, a ramp signal is required for PWM signal modulation.

Basically, as two types of forming a ramp signal, there are a sawtooth ramp signal and a triangular ramp signal. Among them, a symmetrical triangular ramp signal having the same rising and falling slope can effectively alleviate the unbalance of the inductor current. That is, side effects of the aforementioned spread spectrum technique can be alleviated without affecting the inductor current spectrum (ie, EMI performance). Accordingly, in order to reduce EMI and minimize side effects due to inductor current imbalance in the chaotic mode, the buck converter 100 uses a PWM ramp generator (ie, a symmetric triangular ramp generator 22) that generates a triangular waveform signal.

Hereinafter, a chaos triangle ramp signal generator will be described with reference to FIG. 6.

6 is a circuit diagram of a chaotic triangle ramp signal generator according to an embodiment of the present invention.

6(a) is a circuit diagram of a triangular ramp generator, and FIG. 6(b) is a circuit diagram of an analog chaos signal generator.

The chaotic triangular ramp signal generator according to an embodiment of the present invention includes the N-type chaos signal generator 21 and a symmetric triangular ramp generator 22 connected thereto.

In addition, FIG. 6A shows the circuit of the symmetric triangular lamp generator 22 mentioned in FIGS. 1 and 2 above.

The triangular lamp generator 22 is a wide-swing current source (M2 to M5) using an error amplifier (EA), a resistor (R), a transistor (M1), and a cascade current mirror. ) Consisting of a voltage-current (VI) converter. Further, the triangular lamp generator 22 further includes current mirrors M6, M8 to M10, a transistor M7 operating as a switch, a timing capacitor C1, and two comparators U ₁ and U ₂ .

At this time, the VI converter controls the charging current I _Chg =V _BR /R. This charging current I _Chg is copied by the current mirrors M6, M8 to M10 to form a current sink that controls the discharge current I _DChg .

As shown in (a) of FIG. 6, the transistor M1, the current mirrors M2 to M6, M8 to M10, and the transistor M7 are each implemented as an N-channel increase-type MOSFET or a P-channel increase-type MOSFET. Can be. Hereinafter, for convenience of description, the transistor M1, the current mirrors M2 to M6, M8 to M10, and the transistor M7 will be referred to as first to tenth transistors, respectively.

Referring to FIG. 6A, the first transistor M1 is an N-channel increasing MOSFET, and at this time, the gate of the transistor M1 is connected to the output terminal of the error amplifier EA, and the first transistor M1 is The source is connected to one end of the resistor R, and the other end of the resistor R is connected to ground. In addition, the drain of the transistor M1 is connected to the gate of each of the third, fifth, and ninth transistors M3, M5, and M9 and the drain of the second transistor M2.

In addition, the second transistors M2 to the fifth transistors M5 and the ninth and tenth transistors M9 and M10 are P-channel increasing MOSFETs, respectively, and the sixth to eighth transistors M6, M7 and M8 are respectively It is an N-channel incremental MOSFET.

The third, fifth, and tenth transistors M3, M5, and M10 have gates connected to each other, and their respective sources are connected to a power supply voltage VDD. Further, the drains of the third, fifth, and tenth transistors M3, M5, and M10 are connected to the sources of the second, fourth, and ninth transistors M2, M4, and M9, respectively.

The drain of the fourth transistor M4 is connected to an edge between the drain of the seventh transistor M7 and one end of the timing capacitor C1. In this case, the input terminals of the low and high threshold comparators U ₁ and U ₂ are also connected to the drain of the fourth transistor M4. The other end of the timing capacitor C1 is connected to the ground.

The sixth and eighth transistors M6 and M8 have gates connected to each other, and their sources are connected to ground. Further, the drain of the eighth transistor M8 is connected to the drain of the ninth transistor M9, and the drains of the sixth and eighth transistors M6 and M8 are respectively connected to the drains of the eighth and ninth transistors M8 and M9. The gate is connected.

Outputs from the low threshold comparator U ₁ and the high threshold comparator U ₂ are input to the gate of the seventh transistor M7. At this time, low threshold comparator (U ₁₎ is input to the low threshold limit V _L and V _ramp timing capacitor voltage, high threshold comparator (U _2), the high threshold limit V _H and V _ramp timing capacitor voltage is input.

The error amplifier EA receives the output of the first transistor M1 and _VBR .

Unlike the sawtooth lamp generator, where the discharge time is much shorter than the charge time, the charge and discharge times must be the same in the triangular lamp generator. Therefore, in the triangular ramp signal generator, the charging/discharging speed is controlled using a current source and a current sink to optimize accuracy.

At this time, as mentioned above, since the charging and discharging times of the timing capacitor C1 should be the same, the discharge current I _DChg is equal to 2I _Chg . This may be implemented by setting the current ratio between the fourth and fifth transistors M4 and M5 and the ninth and tenth transistors M9 and M10 to 2:1.

The operation of the symmetric triangular ramp generator 22 is as follows.

First, after an initial reset event (i.e., a triangular signal at low threshold limit V _L ), the switch (i.e., the seventh transistor M7) is turned off, and the capacitor voltage V _ramp is V Timing capacitor C1 is charged slowly until _H is reached. At this point, the comparator 26 is tripped, the switch M7 is turned on, and the lamp is discharged to V _L by the current sink (ie, the sixth transistor M6) with I _DChg = 2I _Chg . Another cycle begins when the triangular waveform signal falls to V _L.

For reference, in order to reduce the asymmetry of the triangular lamp signal due to the current mismatch of the current mirror, the length of the current mirror transistor must be large.

6B shows the circuit of the N-type chaos signal generator 21 described above. In this circuit, the two inverters M _N6 and M _P6 serve as the SPDT 218, and the two transistors M _PCS1 and M _{NCS1 operate} as a current source I ₁ and a current sink I _2, respectively.

Also, since the clock signal CLK is ideally configured as an impulse train at a rate of f=1/T, a one-shot circuit is used to generate a short pulse for the SR latch. These impulses are approximated by narrow pulses and implemented using a one-shot circuit.

The parameters of the N-type chaos signal generation circuit are designed based on the selection of parameters T ₁ and T ₂ of the mathematical model. At this time, T ₂ is selected from the chaotic region shown in FIG. 5 in order to generate a strong chaotic signal for changes inherent in process manufacturing. As long as (T ₂ /T ₁ )>1, when using the N-type chaos signal generator 21, the output is a chaotic signal. This condition can be satisfied irrespective of the variation of the capacitor C2 (eg, up to 30% of the design value).

Also, since T ₁ = T Х I ₁ /(V _H C), T ₂ = T Х I ₂ /(V _H C), setting the ratio (T ₂ /T ₁ )>1 is the ratio (I ₂ / It is the same as setting I ₁ )>1. This can be easily controlled at the circuit level by using a basic current mirror and matching the layout between the current source and current sink (M _PCS1 and M _NCS1 ).

Meanwhile, as described above, the chaos triangular ramp signal generator is configured by connecting a symmetric triangular ramp generator 22 and an N-type chaos signal generator 21.

The switching frequency by the symmetric triangular ramp generator 22 shown in FIG. 7 can be expressed as Equation 13 below.

In this case, V _H and V _L denote the upper and lower limits of the triangular ramp signal, respectively. Through Equation 13, it can be seen that the two parameters (ie, the boundary of the ramp signal (ie, V _H and V _L ) and the charging current of the triangular signal (I _Chg )) define the switching frequency of the triangular ramp generator. .

In order to change the switching frequency for each cycle, one or two of the above two parameters are modulated using the chaos signal V _chaos generated by the N-type chaotic signal generator 21.

7 is a diagram illustrating a process of modulating a chaotic triangle ramp signal according to an embodiment of the present invention.

FIG. 7A shows a timing diagram according to a peak modulation technique, which is a first modulation technique.

Referring to (a) of FIG. 7, in the case of the first technique, peak modulation, if V _L and the charging current I _Chg are kept unchanged, the switching frequency of the lamp generator depends only on V _H. At this time, the chaos signal generated by the N-type chaotic signal generator 21 is directly supplied to the V _H of the comparator is a V _H = V _chaos. Accordingly, the switching frequency of the ramp signal generator is chaotically modulated.

FIG. 7B shows a timing diagram according to a second modulation technique, a slope modulation technique.

Referring to (b) of FIG. 7, in the case of slope modulation, which is the second technique, the chaotic signal generated from the N-type chaos signal generator 21 is indirectly supplied from V _BR to the VI converter, and accordingly, V _BR = V becomes _chaos . At this time, the chaotic signal is converted into a chaotic charging/discharging current, and accordingly, the ramp signal and the switching frequency are chaotically modulated.

As described above, since the continuous chaotic signal changes charging and discharging currents within one cycle, the chaotic signal of the N-type chaotic signal generator 21 cannot be directly supplied to V _BR . Accordingly, the chaotic signal is sampled only at the end of each cycle by the impulse signal S from the low threshold comparator U1 inside the circuit of the symmetric ramp signal generator 22. Through this, the disturbance of the triangular waveform is removed without changing the charge/discharge current (I _Chg /I _DChg ) until the end of the current cycle.

The switching frequency deviation (ΔF _SW ) in the chaotic mode is set near the fixed frequency mode at an arbitrary frequency (e.g. 2.1 MHz), and the frequency envelope of the chaotic triangle ramp signal is the following equation for peak modulation. It is within the range of 14, and slope modulation is within the range of Equation 15 below.

By using Equations 14 and 15 above, circuit parameters C1, I _Chg , V _H , V _L , V _HC and V _LC of the chaotic triangle ramp signal generator can be derived.

The values of V _HC and V _LC derived through Equations 14 and 15 are combined with Equation 8, which is the above-described normalized and parameterized equation, and T, I ₁ as circuit parameters of the N-type chaos signal generator 21 , I ₂ and C can be used to calculate.

The N-type chaos signal generator 21 limits the chaotic signal at the output in two predefined bands, V _HC and V _LC , by using two comparators. This shows that the frequency deviation of the chaotic ramp signal can be accurately controlled. In addition, this characteristic is to add additional controllability to the chaos ramp signal generator, since the frequency deviation can be customized by the user.

Among the two techniques for generating the chaotic triangle ramp signal above, the peak level injection technique can be more easily implemented. This is more complicated as slope modulation requires an additional chaos signal sampling circuit, and the high bandwidth because the rate at which the chaos signal is converted into a chaotic current must be fast enough for the charging current to switch from one level to another at the beginning of each cycle. This is because it requires a VI conversion circuit. Typically, the bandwidth of the V-I converter is set to at least 10 times the switching frequency. On the other hand, when designing a triangular waveform circuit, since the ramp down slope of the triangular waveform is smaller than that of the sawtooth ramp generator, the design of the comparator is simple and its power consumption is low.

Meanwhile, since the ramp amplitude directly affects the stability of the buck converter in voltage mode, it is important to design a compensation network for a buck converter including a triangular ramp signal generator that performs peak modulation. On the other hand, in the case of the slope modulation technique, if the amplitude of the ramp signal is kept constant and the correction network is fixed, the stability does not change.

In the above, a SiP buck converter including an on-chip chaotic triangular ramp signal generator for reducing EMI according to an embodiment of the present invention has been described.

The on-chip chaos triangular ramp signal generator consists of a symmetric triangular ramp generator and an N-type chaos signal generator. The on-chip chaos signal generator generates a controllable chaos signal and applies it to modulate the slope of the triangular signal. The triangular waveform signal modulated based on the N-type chaos circuit is applied to the spread spectrum of a dual-mode PFM/PWM SiP buck converter with EMI reduction effect.

In order to confirm the validity verification result of such a chaotic modulation technique, the verification result by fabricating a buck converter according to an embodiment of the present invention using a standard 0.18 μm CMOS process will be described with reference to FIGS. 8 and 9 below.

8 is an example of a result of simulating the performance of a buck converter based on chaos modulation according to an embodiment of the present invention.

9 is a diagram showing an example of a phase-portrait between two internal states (inductor current and output voltage) in an operation mode of the buck converter based on chaos modulation under the simulation condition of FIG. 8.

In FIG. 8, a simulation result of a steady-state time-domain of the converter 100 in a chaotic mode using a chaotic triangular ramp signal generator using slope modulation is shown. At this time, the chaos ramp signal generator is applied to the dual mode PWM/PFM buck converter shown in FIG. 1. In addition, simulations were performed for both standard mode and chaos mode so that the results of the simulation can be easily compared.

10%인 1.08 MHz to 1.32 MHz와 노멀 스위칭 주파수 F_SW의

20%인 0.96 MHz to 1.44 MHz로 설정하였다. In the standard mode, the normal switching frequency F _SW is set to 1.2 MHz, and the chaos frequency range is the normal switching frequency F _SW .

10% of 1.08 MHz to 1.32 MHz and normal switching frequency F _SW

It was set to 20%, 0.96 MHz to 1.44 MHz.

The design parameters of the triangular waveform in standard mode were set to V _BR = 0.6V, C = 3pF, V _H = 1.5V and V _L = 0.8V to achieve F _SW = 1.2 MHz.

10% 및

20% 주파수 편차를 달성하기 위해, 램프의 V_BR에 적용된 카오스 신호 V_Chaos의 경계는 V_HC = 0.66V, V_LC = 0.514 V, V_HC = 0.71V 및 V_LC = 0.46V로 설정하였다. Around the normal switching frequency F _SW

10% and

To achieve a 20% frequency deviation, the boundaries of the chaos signal V _Chaos applied to V _BR of the ramp were set to V _HC = 0.66V, V _LC = 0.514 V, V _HC = 0.71V, and V _LC = 0.46V.

In the chaotic mode, the normal switching frequency F _SW is defined using the average value of V _HC and V _LC for the average value of 1.2 MHz.

To output a chaotic signal, the parameters of the N-type chaotic signal circuit are C = 3 pF, I ₁ = ₁ μA, I ₂ = in both cases, depending on the condition T ₂ /T ₁ >1 or I ₂ /I ₁ >1 6 μA, and C _K = 1 MHz.

The simulation settings of the converter were set to V _IN = 3V, V _OUT = 1.8V, I _OUT = 250mA, L = 2.2μH and C _OUT = 2.2μF.

In addition, the capacitor's ESR value (ESR = 30 mΩ) and other components of the compensation network were selected from commercial devices to provide an appropriate prediction result when comparing the simulation with the actual test chip measurement results.

At this time, referring to FIG. 8, the chaos signal of the N-type chaos signal generator is sampled at the beginning of each switching cycle and then supplied to the VI converter from V _BR of the triangular waveform generator (ie, a symmetric triangular ramp signal generator). As a result, the converter operates in chaos mode.

Meanwhile, referring to FIG. 9, a chaotic change in the inductor current can be confirmed, and through this, it can be seen that EMI performance is improved.

The operation of the buck converter 100 in the chaotic mode shown in FIG. 9B can be confirmed from a phase trajectory between two internal chaotic states (inductor current I _L and output voltage V _OUT ). In this case, compared with the standard mode shown in FIG. 9A, the operation in the standard mode is stable between two equilibrium points and is expressed only with a single trajectory, but the chaotic operation is not repeated indicating chaos. It shows a complex pattern that includes orbits that are not.

10 is a diagram illustrating a switching frequency distribution according to a simulation result of a chaotic triangle ramp signal generator using slope modulation according to an embodiment of the present invention.

10%인 1.08MHz 내지 1.32MHz일 때의 스위칭 주파수 분포이고, 도 10의 (b)는 1.2MHz의

20%인 0.96MHz 내지 1.44MHz일 때의 스위칭 주파수 분포이다.In this case, the simulation result of FIG. 10 is a result of proceeding under the simulation conditions of FIG. 8 described above, and FIG. 10 (a) is

10% of the switching frequency distribution at 1.08MHz to 1.32MHz, Figure 10 (b) is 1.2MHz

It is a switching frequency distribution in the case of 20% of 0.96MHz to 1.44MHz.

In order to obtain the flattest power spectrum, uniformly distributed switching frequencies must be obtained. Referring to FIG. 10, it can be seen that the distribution of the chaotic switching frequency is not uniformly distributed over a desired frequency range, but continuously spreads in a predefined range. Thus, harmonic peaks in the power spectrum are eliminated in the chaotic mode.

In the above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features. You can understand. Therefore, the embodiments described above are illustrative in all respects, and should be understood as non-limiting.

100: Chaos Modulation Based Buck Converter
10: LC filter
20: PWM controller
30: PFM controller
21: Chaos Signal Generator
22: triangular ramp signal generator
60: compensation circuit

Claims (8)

An LC filter comprising an inductor and a first capacitor connected in series with a voltage source to receive a voltage, and providing an output voltage through the first capacitor;
A first switching element having one end connected to the current source and the other end connected to one end of the inductor;
A second switching element having one end connected to a contact point between the first switching element and an inductor, and the other end connected to a ground; And
Chaotic modulation-based DC-DC converter comprising a chaotic pulse-width modulation (CPWM) controller for applying a chaotic triangular ramp signal as a drive signal to the first and second switching elements, respectively . The method of claim 1,
The chaos pulse width modulation controller,
A chaos signal generator including a second capacitor, a single-pole double-throw switch for charging and discharging the second capacitor, and a controller providing a control signal for triggering the single-pole double-throw switch; And
A chaos modulation-based DC-DC converter comprising a triangular ramp signal generator configured to receive a chaotic signal according to an output voltage by the second capacitor and generate a chaotic triangular ramp signal by using the chaos signal as a switching driving signal. The method of claim 2,
The controller,
A first comparator comparing the voltage of the second capacitor with an upper limit reference voltage of the capacitor;
A second comparator comparing the voltage of the second capacitor with a lower limit reference voltage of the capacitor;
A second SR latch receiving an output of the second comparator and a clock signal;
An AND gate receiving an output of the second SR latch and an output of the first comparator;
A first SR latch receiving an output of the AND gate and a clock signal; And
And an XOR gate receiving an output of the first SR latch and the second SR latch,
The output of the XOR gate is input to the single pole double throw switch as a control signal for triggering the single pole double throw switch, chaos modulation based DC-DC converter. The method of claim 3,
The triangular ramp signal generator,
An error amplifier receiving an output voltage from the second capacitor through a first input terminal, a resistance connected to the second input terminal of the error amplifier and the other terminal connected to the ground, an N-channel increasing type MOSFET, and one end of the resistance and the Voltage current including a first transistor, a source connected to a contact point between the second input terminal of the error amplifier and a gate connected to the output terminal of the error amplifier, and second to fifth transistors each of which are P-channel increasing MOSFETs Converter;
One timing capacitor;
A comparator including a low threshold comparator to which an output voltage and a low threshold voltage by the timing capacitor are input, and a high threshold comparator to which an output voltage and a high threshold voltage by the timing capacitor are input;
A seventh transistor which is an N-channel increase-type MOSFET and operates as a switch by inputting an output of the comparator to a gate;
Sixth and eighth transistors each of which are N-channel increase-type MOSFETs and have gates connected to each other;
A ninth transistor that is a P-channel increase-type MOSFET, the gates and gates of the second and fourth transistors are connected to each other to operate as a current mirror; And
A P-channel increase-type MOSFET, the gate and the gate of each of the third and fifth transistors are connected to each other to include a tenth transistor operating as a current mirror,
One end of the timing capacitor is connected to a drain of the fourth transistor, a drain of the seventh transistor, and an input terminal of the comparator, and the other end is connected to a ground. The method of claim 4,
The gates of each of the third, fifth and tenth transistors are connected to each other, a source is connected to a power voltage, a drain is connected to a source of the second, fourth and ninth transistors, respectively,
The gates of each of the sixth and eighth transistors are connected to each other, the drains of the eighth and ninth transistors are connected to each other, and a source is connected to a ground. The method of claim 5,
A current ratio of the third and fifth transistors and the tenth transistor is 2:1,
The current ratio of the second and fourth transistors and the ninth transistor is 2:1, chaos modulation-based DC-DC converter. The method of claim 2,
An error amplifier that receives a voltage applied to a first resistor and a reference voltage among a first resistor and a second resistor for distributing the output voltage by the first capacitor, and inputs an output signal to a comparator receiving the chaos triangle ramp signal ;
A first compensation capacitor connected in parallel to the input terminal and the output terminal of the error amplifier;
A first compensation resistor and a second compensation capacitor connected in series to each other and connected in parallel to the first compensation capacitor; And
Chaos modulation-based DC-DC further comprising a type-III compensation network circuit connected in series with each other and including a second compensation resistor and a third compensation capacitor connected in parallel to both ends of the first compensation resistor converter. The method of claim 1,
Further comprising a PFM controller for outputting the pulse-frequency modulated (PFM) signal to the first and second switching elements,
The PFM controller outputs the PFM signal when a load current level is less than a preset threshold voltage,
When the load current level exceeds the threshold voltage, the chaotic triangular ramp signal is output.

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