KR20200097529A - Apparatus for controlling operation of buck-boost converter based on stacked switch - Google Patents

Abstract

The present invention relates to a stack switch-based apparatus for controlling a buck-boost converter, capable of controlling the converter with optimum efficiency. According to the present invention, the stack switch-based apparatus for controlling the buck-boost converter includes: a mode determination unit; a mode selection unit; a logic control unit; a logic driving unit for generating a drive control signal for turning on or off each of the stack switching transistors constituting a non-inverting buck-boost converter; the non-inverting buck-boost converter for executing one of a pulse width modulation (PWM) operation mode, a pulse frequency modulation (PFM) operation mode, and a retention operation mode according to the drive control signal; a current sensor; and a converter control unit.

Description

Stack switch-based buck-boost converter control device {APPARATUS FOR CONTROLLING OPERATION OF BUCK-BOOST CONVERTER BASED ON STACKED SWITCH}

The present invention relates to a buck-boost converter control device, and more particularly, a stacked switch-based buck-boost converter capable of controlling a stacked switch-based buck-boost converter with optimum efficiency. It relates to a control device.

In general, as a switching mode converter that converts power using a power semiconductor or the like, for example, a buck type converter, a boost type converter, and the like are known.

Here, the buck-type converter is a method of outputting the output voltage lower than the input voltage, so it is also defined as a step-down converter. In the buck-type converter, the ratio of the input voltage to the output voltage is proportional to the duty cycle (D) of the power semiconductor. In addition, the boost type converter is a method that outputs the output voltage higher than the input voltage, so it is also defined as a step-up converter. In the boost type converter, the ratio of the input voltage to the output voltage is generally inversely proportional to (1-D).

On the other hand, the converter may be fixed to one type, but it must be able to operate while changing into a plurality of types (buck type, boost type) as needed.

For example, it is necessary to operate in a buck mode in a specific section and a boost mode in other specific sections. Therefore, a buck-boost converter is required for this function.

Korean Patent Registration No. 1816928 (announcement date: 2018. 02. 21.)

The present invention controls the converter with optimal efficiency based on the triple mode (high load current mode, low load current mode, ultra low load current mode) based on the measured output current of a stacked switch-based buck-boost converter. It is intended to provide a buck-boost converter control device based on a stackable switch.

The problem to be solved by the present invention is not limited to the ones mentioned above, and another problem to be solved that is not mentioned can be clearly understood by those of ordinary skill in the art from the following descriptions. will be.

According to one aspect, the present invention provides a mode determination unit determining an operation mode of the non-inverting buck-boost converter based on an output voltage Vout output from the non-inverting buck-boost converter, and the mode determination unit A mode selection unit that determines a logic so that the non-inverting buck-boost converter operates as one of a plurality of preset control logics based on a mode determination signal and a sensed voltage signal Vsense provided from a current sensor. , Based on a logic control signal provided from the mode selection unit, an output voltage signal Vout of the non-inverting buck-boost converter, a retention voltage signal V _RETENTION or an output voltage signal provided from the converter control unit. A logic control unit that generates a logic control signal, and a logic that generates a driving control signal for turning on or off each of the stack switching transistors constituting the non-inverting buck-boost converter based on a logic control signal provided from the logic control unit. A driving unit and the non-inverting buck-boost converter executing any one of a PWM (Pulse Width Modulation) operation mode, a PFM (Pulse Frequency Modulation) operation mode, and a retention operation mode according to the driving control signal, The current sensor providing the sensed voltage signal V _SENSE obtained by sensing the current delivered to the output node of the non-inverting buck-boost converter to the mode selection unit, an output voltage signal for PWM control, PFM It is possible to provide a stack switch-based buck-boost converter control device including the converter control unit that generates any one of an output voltage signal for control and a retention voltage signal for retention control and provides it to the logic control unit.

The plurality of preset control logics of the present invention may include PWM control logic, PFM control logic, and retention control logic.

The logic control unit of the present invention may generate the logic control signal to have a different control method according to the current of the load of the driving logic.

The logic control unit of the present invention generates a logic control signal for executing the non-inverting buck-boost converter as a PWM control operation when the load current of the non-inverting buck-boost converter is greater than or equal to a predetermined first load current, and the load Generates a logic control signal for executing the non-inverting buck-boost converter as a PFM control operation when a current is less than a predetermined second load current, and a predetermined third load current having the load current smaller than the predetermined second load current In the following cases, a logic control signal for executing the non-inverting buck-boost converter as a retention control operation may be generated.

In the non-inverting buck-boost converter of the present invention, a high-side buck transistor unit configured by stacking a plurality of switching transistors, a low side buck transistor unit configured by stacking a plurality of switching transistors, and a plurality of switching transistors are stacked. It may include a high-side boost transistor unit configured to be configured and a low side boost transistor unit configured by stacking a plurality of switching transistors.

The high-side buck transistor unit of the present invention is connected between the input voltage node Vin of the non-inverting buck-boost converter and a node Lx1 to which the high-side buck transistor and the low-side buck transistor unit are connected, and source/ It may include three P-channel transistors with drain paths.

The low-side buck transistor unit of the present invention may include three N-channel transistors connected between the node Lx1 and a ground and having a drain/source path.

The high-side boost transistor unit of the present invention is connected between the output voltage node Vout of the non-inverting buck-boost converter and a node Lx2 to which the high-side boost transistor and the low-side boost transistor are connected, and source/ It may include three P-channel transistors with drain paths.

The low-side boost transistor unit of the present invention may include three N-channel transistors connected between the node Lx2 and a ground and having a drain/source path.

The converter control unit of the present invention includes a PWM control unit that generates an output voltage signal for PWM control and provides it to the logic control unit, a PFM control unit that generates an output voltage signal for PFM control and provides it to the logic control unit, And a retention control unit that generates a retention voltage signal for the retention control and provides it to the logic control unit.

According to an embodiment of the present invention, the converter is configured based on a triple mode (high load current mode, low load current mode, ultra low load current mode) based on the measured output current of a stacked switch-based buck-boost converter. It can be controlled with optimum efficiency.

According to an embodiment of the present invention, for each transistor part constituting a non-inverting buck-boost converter, a voltage that one transistor cannot withstand by stacking three transistors to drop a voltage is sufficient for a relatively high voltage. In addition, it is possible to obtain an effect that can withstand high voltage, and also effectively compensate for the low efficiency due to Ron drop caused by the stack switch at a relatively low input voltage.

1 is a block diagram of an apparatus for controlling a buck-boost converter based on a stack switch according to an embodiment of the present invention.
2 is an exemplary diagram for explaining a main process of executing a stack switch-based buck-boost converter in a PWM mode according to an embodiment of the present invention.
3 is an exemplary diagram for explaining a main process of executing a stack switch-based buck-boost converter in a PFM mode according to an embodiment of the present invention.
4 is an exemplary diagram for explaining a main process of executing a stack switch-based buck-boost converter in a retention mode according to an embodiment of the present invention.

First, the advantages and features of the present invention, and a method of achieving them will become apparent with reference to embodiments to be described later in detail together with the accompanying drawings. Here, the present invention is not limited to the embodiments disclosed below, but may be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present invention, and are common in the technical field to which the present invention pertains. Since it is provided by way of example in order to allow a person skilled in the art to clearly understand the scope of the invention, the technical scope of the invention should be defined by the claims.

In addition, in the following description of the present invention, if it is determined that a detailed description of known functions or configurations may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. In addition, terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the technical idea described throughout the specification.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an apparatus for controlling a buck-boost converter based on a stack switch according to an embodiment of the present invention. A mode determination unit 102, a mode selection unit 104, a logic control unit 106, and a logic driving unit 108 , A reference voltage providing unit 110, a non-inverting buck-boost converter 112, a current sensor 114, and a converter control unit 116.

Referring to FIG. 1, the mode determination unit 102 may be defined as, for example, a buck / boost / buck-boost mode selector, which will be described later. Determining (determining) the operation mode of the non-inverting buck-boost converter 112 based on the output voltage Vout output from the buck-boost converter 112 in real time, for example, among buck mode, boost mode, and buck-boost mode. It can provide a function such as determining which one to do. Here, the determined mode determination signal may be transmitted to the mode selection unit 104 of the next stage.

That is, the mode determination unit 102 analyzes the output voltage Vout of the non-inverting buck-boost converter 112 so that the non-inverting buck-boost converter 112 is in any one of a buck mode, a boost mode, and a buck-boost mode. After determining information on whether to operate with a mode, a mode determination signal may be provided to the mode selection unit 104.

In addition, the mode selection unit 104 may be defined as, for example, PWM (Pulse Width Modulation) / PFM (Pulse Frequency Modulation) / Retention (Retention) mode selector (Mode Selector), from the mode determination unit 102 The control method of the buck-boost converter may be determined according to the mode determination signal provided and the sensed current value Vsense provided from the current sensor 114 to be described later.

That is, the mode selection unit 104 is a PWM control logic (Control Logic), PFM control logic (Control Logic) through the Vsense voltage signal provided from the current sensor 114 and the mode determination signal provided from the mode determination unit 102. , A logic control signal capable of determining which logic is to be operated from among the retention control logics may be generated and provided to the logic controller 106.

Here, the PWM control logic is logic for operating the non-inverting buck-boost converter 112 in the PWM mode, and the PFM control logic is logic for operating the non-inverting buck-boost converter 112 in the PFM mode, and The tension control logic is a logic for operating the non-inverting buck-boost converter 112 in a retention mode.

To this end, when the operation of the non-inverting buck-boost converter 112 is either a PWM mode or a PFM mode, the mode selector 104 transmits a 0 or 1 signal to the multiplexer (MUX) 1168, The non-inverting buck-boost converter 112 can be controlled to execute a PWM operation or a PFM operation.

In addition, when the operation of the non-inverting buck-boost converter 112 is not in the PWM mode or the PFM mode, the mode selector 104 enables a retention enable signal, thereby enabling the non-inverting buck-boost converter ( 112) can be controlled to operate in a retention mode.

Next, the logic control unit 106 includes a logic control signal provided from the mode selection unit 104, an output voltage signal Vout of the non-inverting buck-boost converter 112, and a retention control unit 1166 to be described later. Based on the V _RETENTION voltage signal and the output voltage signal of the multiplexer 1168, a function such as generating a logic control signal that allows the driving logic to have a different control method according to the current of the load may be provided.

For example, when the load current of the non-inverting buck-boost converter 112 is greater than or equal to a predetermined first load current, the logic control signal is provided to the logic driver 108 so that the non-inverting buck-boost converter 112 executes a PWM control operation. The non-inverting buck-boost converter 112 may provide a logic control signal to the logic driver 108 to execute the PFM control operation when the load current is less than or equal to the second load current, and the load current is predetermined. A logic control signal may be provided to the logic driver 108 so that the non-inverting buck-boost converter 112 executes a retention control operation when it is less than a predetermined third load current that is less than the second load current of.

In addition, the logic driver 108 is based on a logic control signal provided from the logic control unit 106, for example, a logic control signal for a PWM control operation, a logic control signal for a PFM control operation, and a logic control signal for a retention control operation. Thus, driving control signals (ø1 to ø12) for turning on or off each of the switching transistors (TR1 to TR12) constituting the non-inverting buck-boost converter 112 are respectively generated and provided to the non-inverting buck-boost converter 112 It can provide functions such as doing.

Here, the reference voltage providing unit 110 may provide a function such as generating reference voltages such as VREF1, VREF2, and VREF3 and providing them to each component in the converter controller 116.

Next, the non-inverting buck-boost converter 112, that is, a stacked switch-based non-inverting buck-boost converter, is a PWM (Pulse) according to the driving control signals ø1 to ø12 provided from the logic driver 108. A function such as executing any one of a width modulation) operation mode, a pulse frequency modulation (PFM) operation mode, and a retention operation mode may be provided.

To this end, the non-inverting buck-boost converter 112 may include an input voltage node to which an input voltage Vin is applied, and a high-side buck transistor unit 1122 and a low A side buck transistor unit 1124, a high side boost transistor unit 1126, and a low side boost transistor unit 1128 may be included.

Here, the high-side buck transistor unit 1122 is connected between the input voltage node Vin and the node Lx1 to which the high-side buck transistor 1122 and the low-side buck transistor unit 1124 are connected, so that the source/drain It may include three P-channel transistors TR1 to TR3 having paths, and the low-side buck transistor unit 1124 is connected between the node Lx1 and the ground to have three N-channels having drain/source paths. Transistors TR4 to TR6 may be included.

In addition, the high-side boost transistor unit 1126 is an output voltage node Vout of the non-inverting buck-boost converter 112 and a node Lx2 to which the high-side boost transistor 1126 and the low-side boost transistor 1128 are connected. It may include three P-channel transistors TR7 to TR9 that are connected between and have source/drain paths, and the low-side boost transistor unit 1128 is connected between the node Lx2 and the ground to be drain/source. It may include three N-channel transistors TR10 to TR12 having a path.

Further, each of the gates of each of the switching transistors TR1 to TR12 is connected to the output of the logic driver 108, the inductor is connected between the node Lx1 and the node Lx2, and the output capacitor is the output voltage node ( Vout) is connected to the output voltage node between the ground node. In addition, the load may be connected in parallel with the output capacitance between the output voltage node and the ground node.

At this time, the duty cycle in the buck operation mode can be defined as D=ton/T, where ton is the on time of the high-side buck transistor (switching transistor), and T is the switching period of the converter and the switching frequency (fsw) Is the inverse of (T=1/fsw).

In addition, the duty cycle in the boost operation mode may be defined as D=ton/T, and may mean the on time of the high side boost transistor divided by the switching period of the converter.

Again, referring to the non-inverting buck-boost converter 112, each of the switching transistors TR1 to TR6 corresponding to the driving control signals ø1, ø2, ø3, ø4, ø5, and ø6 uses a buck-boost converter in the buck operation mode. It can function as a power switch for.

In the buck operation mode, the switching transistors TR7 to TR9 corresponding to the drive control signals ø7, ø8 and ø9 are always turned on, and the switching transistors TR10 to TR12 corresponding to the drive control signals ø10, ø11 and ø12 are always turned off. to be.

Similarly, in the boost operation mode, the switching transistors TR7 to TR12 corresponding to the driving control signals ø7, ø8, ø9, ø10, ø11, and ø12 are power switches for the buck-boost converter in the boost mode.

In the boost operation mode, the switching transistors TR1 to TR3 corresponding to the drive control signals ø1, ø2 and ø3 are always turned on, and the switching transistors TR4 to TR6 corresponding to the drive control signals ø4, ø5 and ø6 are always turned off. to be.

In the buck-boost operation mode, the switching transistors (TR1 to TR3, TR10 to TR12) corresponding to the drive control signals ø1, ø2, ø3, ø10, ø11, ø12 are turned on, and the drive control signals ø4, ø5, ø6, ø7, A state in which the switching transistors TR4 to TR9 corresponding to ø8 and ø9 are turned on may be periodically repeated.

Here, for each transistor unit, since three transistors are stacked to drop a voltage that one transistor cannot withstand, it is possible to obtain an effect capable of sufficiently withstanding a relatively high voltage.

Next, the current sensor 114 senses the current delivered to the output node of the non-inverting buck-boost converter 112 and transfers the obtained result value (sensed voltage signal) to the mode selector 106. Function can be provided.

That is, the current sensor 114 senses the current through the voltages V _L and V _R at both ends of the resistor through which the current flowing through the inductor equally flows, and converts the sensed current information into a corresponding voltage signal Vsense, and the mode selector (106) can be provided.

In addition, the converter control unit 116 selectively generates any one of an output voltage signal for PWM control, an output voltage signal for PFM control, and a V _RETENTION voltage signal for retention control and provides it to the logic control unit 106. To this end, the converter control unit 116 may include a PWM control unit 1162, a PFM control unit 1164, a retention control unit 1166, a multiplexer 1168, and the like.

First, the PWM control unit 1162 may provide a function such as generating an output voltage signal for PWM control of the converter and providing it to the logic control unit 106. For this purpose, the amplifier 202 and the first comparator 204 And the like.

Here, at the inverting input node (-) of the amplifier 202, the output node of the non-inverting buck-boost converter 112 (that is, the output voltage of the non-inverting buck-boost converter 112 is divided through a resistive divider). The voltage signal VoutD) is connected, and the VREF1 signal provided by the reference voltage providing unit 110 is connected to the non-inverting input node (+) of the amplifier 202.

In addition, a resistor is connected between the inverting input node of the amplifier 202 and the output node of the non-inverting buck-boost converter 112, and a passive element connected in series with a capacitor and a resistor is connected in parallel with another resistor.

In addition, the output of the amplifier 202 is connected to the inverting input node (-) of the first comparator 204, and the voltage value of the current sensor 114 is connected to the non-inverting input node (+) of the first comparator 204 ( The voltage value generated by allowing a current corresponding to the sum of the current value converted from Vsense) to a current value and a voltage value (Vosc) generated by a ramp generator to a current value flows through the resistor Is provided.

Here, the output voltage signal of the first comparator 204, that is, the output voltage signal for PWM control of the converter is transmitted to the input of the multiplexer 1168 and provided to the logic control unit 106.

Next, the PFM control unit 1164 may provide a function such as generating an output voltage signal for PFM control of the converter and providing it to the logic control unit 106. For this purpose, the second comparator 302 and the third comparator (304), a first latch 306, and the like.

Here, the VREF2 signal provided from the reference voltage providing unit 110 is connected to the non-inverting input node (+) of the second comparator 302, and the non-inverting input node (-) of the second comparator 302 The output node of the buck-boost converter 112, that is, the voltage signal VoutD, in which the output voltage of the non-inverting buck-boost converter 112 is divided through a resistor divider, is connected.

In addition, the VREF3 signal provided from the reference voltage providing unit 110 is connected to the inverting input node (-) of the third comparator 304, and a current sensor (+) to the non-inverting input node (+) of the third comparator 304 The voltage signal Vsense provided from 114) is connected.

Here, each output of the second comparator 302 and the third comparator 304 is connected to each input (S, R) of the first latch 306 through an on-shoot trigger.

In addition, the first latch 306 may provide a function of latching the output of the second comparator 302 or the output of the third comparator 304, and the output voltage signal of the first latch 306, that is, The output voltage signal for PFM control of the converter is transmitted to the input of the multiplexer 1168 and provided to the logic control unit 106.

Next, the retention control unit 1166 may provide a function such as generating a retention voltage signal V _RETENTION for controlling the retention of the converter and providing it to the logic control unit 106. For this purpose, a retention oscillator An (OSC) 402, a divider/delay cell (/N DIVIDER & DELAY CELL) 404, a fourth comparator 406, a second latch 408, and the like may be included.

Here, the retention oscillator 402 starts operation by a retention enable signal provided from the mode selection unit 104, and the divider/delay cell 404 provides a clock signal from the retention oscillator 402 And the output of this divider/delay cell 404 is connected to the S input of the second latch 408.

In addition, the VREF2 signal provided from the reference voltage providing unit 110 is connected to the inverting input node (-) of the fourth comparator 406, and the non-inverting buck is connected to the non-inverting input node (+) of the fourth comparator 406. -The output Vout of the boost converter 112 is connected, and the output of the fourth comparator 406 is connected to the R input of the second latch 408.

In addition, the second latch 408 may provide a function of latching the output of the divider/delay cell 404 or the output of the fourth comparator 406, and the output of the second latch 408 (node Q Of the clock signal), that is, the output voltage signal V _RETENTION for controlling the retention of the converter is provided to the logic controller 106.

Next, a series of operations for adaptively performing a PWM mode, a PFM mode, and a retention mode through the stack switch-based buck-boost converter control apparatus according to the present embodiment having the configuration as described above are illustrated in FIG. 2. It will be described in detail with reference to FIG. 4.

2 is an exemplary diagram for explaining a main process of executing a stack switch-based buck-boost converter in a PWM mode according to an embodiment of the present invention. Here, the PWM mode may be defined as, for example, a high load current mode.

Referring to FIG. 2, the stack switch-based non-inverse buck-boost converter 112 can perform a PWM mode operation. When the current of the load is higher than a certain current, it can operate in a PWM mode corresponding to the high load current mode. have.

Through the current sensor 114, voltages V _L and V _R of both ends of the resistor connected to the rear end of the inductor of the buck-boost converter 112 are sensed, and current information flowing through the inductor is extracted through the sensed voltage information. This current information is converted into voltage information corresponding to Vsense, is transmitted to the PWM control unit 1162, and is then provided as an input of the multiplexer 1168 through the amplifier 202 and the first comparator 204.

In addition, the output of the multiplexer 1168 (i.e., an output voltage signal for PWM control) is provided to the logic control unit 106, and the logic control unit 106 has a current delivered to the load more than a certain current based on the provided Vsense information. In this case, a logic control signal for executing a PWM operation is generated and provided to the logic driver 108, and the logic driver 108 generates a corresponding driving control signal (ie, a driving control signal for executing the PWM operation mode). Thus, the non-inverting buck-boost converter 112 is provided.

For example, the logic driver 108 generates driving control signals of ø1, ø2, ø3, ø4, ø5, ø6, ø7, ø8, ø9, ø10, ø11, ø12 required for the PWM mode operation, and generates a high-side buck transistor. By providing the unit 1122, the low side buck transistor unit 1124, the high side boost transistor unit 1126, and the low side boost transistor unit 1128, respectively, to drive on or off of each of the switching transistors TR1 to TR12 Control.

Accordingly, the non-inverting buck-boost converter 112 executes the PWM mode according to the driving control signal provided from the logic driver 108.

3 is an exemplary diagram for explaining a main process of executing a stack switch-based buck-boost converter in a PFM mode according to an embodiment of the present invention. Here, the PFM mode may be defined as, for example, a low load current mode.

Referring to FIG. 3, the stack switch-based non-inverse buck-boost converter 112 can perform a PFM mode operation. When the current of the load is lower than a certain current, it operates in the PFM mode corresponding to the low load current mode. I can.

The voltages V _L and V _R at both ends of the resistor connected to the rear end of the inductor are sensed through the current sensor 114, and current information flowing through the inductor is extracted through the sensed voltage information. This current information is converted into voltage information corresponding to Vsense, transmitted to the PFM control unit 1164, and then provided as an input of the multiplexer 1168 through the second and third comparators 302 and 304, the latch 306, etc. do.

In addition, the output of the multiplexer 1168 (that is, the output voltage signal for PFM control) is provided to the logic control unit 106, and the logic control unit 106 has a current delivered to the load less than a certain current based on the provided Vsense information. In this case, a logic control signal for executing the PFM operation is generated and provided to the logic driving unit 108, and the logic driving unit 108 generates a corresponding driving control signal (i.e., a driving control signal for executing the PFM operation mode). Thus, the non-inverting buck-boost converter 112 is provided.

For example, the logic driver 108 generates driving control signals of ø1, ø2, ø3, ø4, ø5, ø6, ø7, ø8, ø9, ø10, ø11, ø12 required for the PFM mode operation to generate a high-side buck transistor. By providing the unit 1122, the low side buck transistor unit 1124, the high side boost transistor unit 1126, and the low side boost transistor unit 1128, respectively, to drive on or off of each of the switching transistors TR1 to TR12 Control.

Accordingly, the non-inverting buck-boost converter 112 executes the PFM mode according to the driving control signal provided from the logic driver 108.

4 is an exemplary diagram for explaining a main process of executing a stack switch-based buck-boost converter in a retention mode according to an embodiment of the present invention. Here, the retention mode may be defined as, for example, an ultra-low load current mode.

Referring to FIG. 4, the stack switch-based non-inverse buck-boost converter 112 can perform a retention mode operation, and when the current of the load is lower than the current corresponding to the PFM operation, it corresponds to the ultra-low load current mode. It can operate in retention mode.

The output of the node Q of the second latch 408 in the retention control unit 1166 is provided to the logic control unit 106, and the logic control unit 106 performs retention when the current delivered to the load is less than the current corresponding to the PFM operation. A logic control signal for executing an operation is generated and provided to the logic driving unit 108, and the logic driving unit 108 generates a corresponding driving control signal (ie, a driving control signal for executing the retention operation mode). It is provided to a non-inverting buck-boost converter 112.

For example, the logic driver 108 generates driving control signals of ø1, ø2, ø3, ø4, ø5, ø6, ø7, ø8, ø9, ø10, ø11, ø12 required for the retention mode operation, and generates a high-side buck. By providing the transistor unit 1122, the low side buck transistor unit 1124, the high side boost transistor unit 1126, and the low side boost transistor unit 1128, respectively, the switching transistors TR1 to TR12 are turned on or off. Drive control.

Accordingly, the non-inverting buck-boost converter 112 executes the retention mode according to the driving control signal provided from the logic driver 108.

The above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains, various substitutions, modifications, and changes, etc., within the scope not departing from the essential characteristics of the present invention. It will be easy to see that this is possible. That is, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments.

Accordingly, the scope of protection of the present invention should be interpreted by the claims to be described later, and all technical thoughts within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

102: mode determination unit
104: mode selector
106: logic control unit
108: logic driver
110: reference voltage supply unit
112: non-inverting buck-boost converter
114: current sensor
116: converter control unit
1162: PWM control unit
1164: PFM control unit
1166: retention control unit

Claims (10)

A mode determination unit that determines an operation mode of the non-inverting buck-boost converter based on an output voltage Vout output from a non-inverting buck-boost converter,
Based on a mode determination signal provided from the mode determination unit and a sensed voltage signal Vsense provided from a current sensor, the non-inverting buck-boost converter operates as one of a plurality of preset control logics. A mode selector to determine,
Logic based on a logic control signal provided from the mode selection unit, an output voltage signal Vout of the non-inverting buck-boost converter, a retention voltage signal V _RETENTION or an output voltage signal provided from the converter control unit. A logic control unit for generating a control signal,
A logic driver for generating a driving control signal for turning on or off each of the stack switching transistors constituting the non-inverting buck-boost converter based on a logic control signal provided from the logic controller;
The non-inverting buck-boost converter for executing any one of a PWM (Pulse Width Modulation) operation mode, a PFM (Pulse Frequency Modulation) operation mode, and a Retention operation mode according to the driving control signal,
The current sensor providing the sensed voltage signal V _SENSE obtained by sensing a current delivered to an output node of the non-inverting buck-boost converter to the mode selection unit,
Comprising the converter control unit for generating any one of an output voltage signal for PWM control, an output voltage signal for PFM control, and a retention voltage signal for retention control to provide to the logic control unit.
Stack switch-based buck-boost converter control unit. The method of claim 1,
The preset plurality of control logic,
Including PWM control logic, PFM control logic, and retention control logic
Stack switch-based buck-boost converter control unit. The method of claim 1,
The logic control unit,
To generate the logic control signal to have a different control method according to the current of the load of the driving logic
Stack switch-based buck-boost converter control unit. The method of claim 3,
The logic control unit,
When the load current of the non-inverting buck-boost converter is greater than or equal to a predetermined first load current, a logic control signal for executing the non-inverting buck-boost converter through a PWM control operation is generated, and the load current is a predetermined second load current Generates a logic control signal for executing the non-inverting buck-boost converter as a PFM control operation when it is less than or equal to, and when the load current is less than a predetermined third load current less than the predetermined second load current, the non-inverting buck-boost Generates a logic control signal that executes the converter as a retention control operation.
Stack switch-based buck-boost converter control unit. The method of claim 1,
The non-inverting buck-boost converter,
A high-side buck transistor unit comprising a plurality of switching transistors stacked;
A low-side buck transistor unit comprising a plurality of switching transistors stacked;
A high-side boost transistor unit configured by stacking a plurality of switching transistors;
Including a low-side boost transistor unit configured by stacking a plurality of switching transistors
Stack switch-based buck-boost converter control unit. The method of claim 5,
The high side buck transistor unit,
Three P-channel transistors having source/drain paths connected between the input voltage node Vin of the non-inverting buck-boost converter and a node Lx1 to which the high-side buck transistor and the low-side buck transistor unit are connected. Including
Stack switch-based buck-boost converter control unit. The method of claim 6,
The low side buck transistor unit,
Including three N-channel transistors connected between the node Lx1 and the ground and having a drain/source path
Stack switch-based buck-boost converter control unit. The method of claim 5,
The high side boost transistor unit,
Three P-channel transistors having source/drain paths connected between the output voltage node Vout of the non-inverting buck-boost converter and a node Lx2 to which the high-side boost transistor and the low-side boost transistor are connected. Including
Stack switch-based buck-boost converter control unit. The method of claim 8,
The low side boost transistor unit,
Including three N-channel transistors connected between the node Lx2 and ground and having a drain/source path
Stack switch-based buck-boost converter control unit. The method of claim 1,
The converter control unit,
A PWM control unit that generates an output voltage signal for the PWM control and provides it to the logic control unit,
A PFM control unit generating an output voltage signal for controlling the PFM and providing it to the logic control unit,
And a retention control unit that generates a retention voltage signal for the retention control and provides it to the logic control unit.
Stack switch-based buck-boost converter control unit.

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