KR20200092278A - Three-dimensional semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

According to the present invention, disclosed are a method of manufacturing a three-dimensional semiconductor memory device and a three-dimensional semiconductor memory device manufactured therethrough. The method includes the following steps of: forming a thin film structure by stacking sacrifice films and preparatory interlayer insulation films alternately on a substrate; forming channel holes penetrating the thin film structure; and forming a blocking insulation film, a charge storage film and a tunneling insulation film on side walls of the preparatory interlayer insulation films and the sacrifice films exposed through the channel holes. The formation of the blocking insulation film includes the following steps of: depositing first insulation films on the side walls of the preparatory interlayer insulation films and the sacrifice films, and oxidizing some of the films; etching some of the preparatory interlayer insulation films and the first insulation films through a first etching process; depositing second insulation films on the side walls of the preparatory interlayer insulation films and the sacrifice films, and oxidizing some of the films; etching some of the second insulation films through a second etching process; and depositing third insulation films on the second insulation films, and oxidizing the first to third insulation films. Some of the sacrifice films include dented parts formed on a side wall exposed through the channel holes, and the blocking insulation film fills the dented parts.

Description

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a three-dimensional semiconductor memory device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor memory device having improved electrical properties and a manufacturing method thereof.

In order to meet the excellent performance and low price required by consumers, it is required to increase the degree of integration of semiconductor devices. In the case of a semiconductor device, since the integration degree is an important factor determining the price of a product, an increased integration degree is particularly required. In the case of a two-dimensional or planar semiconductor device, the degree of integration is largely determined by the area occupied by the unit memory cells, and thus is greatly influenced by the level of fine pattern formation technology. However, since the ultra-high-priced equipments are required for pattern miniaturization, the density of the two-dimensional semiconductor device is increasing, but it is still limited. Accordingly, three-dimensional semiconductor memory devices having memory cells arranged in three dimensions have been proposed.

One technical problem of the present invention is to provide a three-dimensional semiconductor memory device with improved electrical characteristics and a method for manufacturing the same.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above technical problems, a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention includes alternately laminating sacrificial films and preliminary interlayer insulating films on a substrate to form a thin film structure, penetrating the thin film structure Forming channel holes, and sequentially forming a blocking insulating layer, a charge storage layer, and a tunneling insulating layer on sidewalls of the sacrificial layers and the preliminary interlayer insulating layers exposed by the channel holes. To form: depositing a first insulating film on sidewalls of the sacrificial films and the preliminary interlayer insulating films, and oxidizing a part thereof, a part of the first insulating film and the preliminary interlayer insulating films through a first etching process Etching, depositing a second insulating film on the sidewalls of the sacrificial films and the preliminary interlayer insulating films, oxidizing a part thereof, etching a part of the second insulating film through a second etching process, And depositing a third insulating film on the second insulating film, and oxidizing the first to third insulating films, and some of the sacrificial films have depressions formed on sidewalls exposed by the channel holes. , The blocking insulating layer may fill the depressions.

In the 3D semiconductor memory device according to an embodiment of the present invention, channel holes are prevented from being connected to each other by filling the depressions that may occur on the sidewalls of the sacrificial films in the process of forming the channel holes, thereby improving reliability and electrical characteristics. Can be.

In addition, in the 3D semiconductor memory device according to an exemplary embodiment of the present invention, cell characteristics may be improved by convexly forming the sidewall profiles of the sacrificial films.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to embodiments of the present invention.
2 is a plan view of a 3D semiconductor memory device according to embodiments of the present invention.
3A, 4, 5A, 14, 15, 16, 17, and 18A are cross-sectional views of a 3D semiconductor memory device according to embodiments of the present invention, respectively. Corresponds to the section cut by the line.
3B, 5B, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are enlarged views showing a portion of a 3D semiconductor memory device according to embodiments of the present invention. As, respectively, it corresponds to part A of the corresponding sectional view.
3C, 5C, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are enlarged views showing a portion of a 3D semiconductor memory device according to embodiments of the present invention As, respectively, it corresponds to part B of the corresponding sectional view.
18B is an enlarged view illustrating a portion of a 3D semiconductor memory device according to embodiments of the present invention, and corresponds to portion C of FIG. 18A.

Hereinafter, a 3D semiconductor memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a cell array of a 3D semiconductor memory device includes a common source line CSL, a plurality of bit lines BL0-BL2, and a common source line CSL and bit lines BL0-BL2. It may include a plurality of cell strings (CSTR) provided.

The cell strings CSTR may be arranged two-dimensionally along the first direction D1 and the second direction D2 intersecting the first direction D1. For example, the second direction D2 may be a direction orthogonal to the first direction D1. The cell strings CSTR may respectively extend along the third direction D3. For example, the third direction D3 may be a direction orthogonal to the first direction D1 and the second direction D2. The bit lines BL0-BL2 may be spaced apart from each other in the first direction D1. The bit lines BL0-BL2 may extend in the second direction D2, respectively.

A plurality of cell strings CSTR may be connected to each of the bit lines BL0-BL2 in parallel. The cell strings CSTR may be commonly connected to the common source line CSL. A plurality of cell strings CSTR may be provided between the plurality of bit lines BL0-BL2 and one common source line CSL. A plurality of common source lines CSL may be provided. The plurality of common source lines CSL may be arranged two-dimensionally. The same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

According to embodiments, each of the cell strings CSTR is a series connected first and second string select transistors SST1 and SST2, a series connected memory cell transistors MCT, a ground select transistor GST, and an erase control. It may be composed of a transistor (ECT). Also, each of the memory cell transistors MCT includes a data storage element.

For example, each cell string CSTR may include first and second string select transistors SST1 and SST2 connected in series, and the second string select transistor SST2 may include bit lines BL0-BL2. ). Alternatively, each cell string CSTR may include one string select transistor. As another example, the ground select transistor GST in each cell string CSTR may be composed of a plurality of morse transistors connected in series, similar to the first and second string select transistors SST1 and SST2. have.

One cell string CSTR may be formed of a plurality of memory cell transistors MCT having different distances from the common source lines CSL. The memory cell transistors MCT may be connected in series between the first string select transistor SST1 and the ground select transistor GST. The erase control transistor ECT may be connected between the ground selection transistor GST and the common source lines CSL. Each of the cell strings CSTR is between the first of the first string select transistor SST1 and the memory cell transistors MCT, and between the ground of the ground select transistor GST and the lowest of the memory cell transistors MCT. Each of the dummy cell transistors (DMC) may be further included.

According to embodiments, the first string select transistor SST1 may be controlled by the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select transistor SST2 may be It can be controlled by the second string selection lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors MCT may be respectively controlled by a plurality of word lines WL0-WLn, and the dummy cell transistors DMC may be respectively controlled by a dummy word line DWL. The ground select transistor GST may be controlled by the ground select lines GSL0, GSL1, and GSL2, and the erase control transistor ECT may be controlled by the erase control line ECL. The erase control transistor ECT may be provided in plural. The common source lines CSL may be commonly connected to the sources of the erase control transistors ECT.

The gate electrodes of the memory cell transistors MCT, which are provided at substantially the same distance from the common source lines CSL, may be in an equipotential state by being commonly connected to one of the word lines WL0-WLn and DWL. . Alternatively, even if the gate electrodes of the memory cell transistors MCT are provided at substantially the same level from the common source lines CSL, the gate electrodes provided in different rows or columns can be independently controlled.

The ground selection lines (GSL0-GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) are It extends along the first direction D1 and may be spaced apart from each other in the second direction D2. Ground selection lines (GSL0-GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection line provided at substantially the same level from the common source lines (CSL) The fields SSL2-1, SSL2-2, and SSL2-3 may be electrically separated from each other. Also, the erase control transistors ECT of the different cell strings CSTR may be controlled by a common erase control line ECL. The erase control transistors ECT may generate a gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines BL0-BL2 and/or the common source lines CSL during the erase operation of the memory cell array, and the string select transistor SST and/or erase may be applied. A gate induced leakage current may be generated in the control transistors ECT.

2 is a plan view of a 3D semiconductor memory device according to embodiments of the present invention. 3A is a cross-sectional view of a 3D semiconductor memory device according to embodiments of the present invention, and corresponds to a cross-section of FIG. 2 taken along line I-I'. 3B is an enlarged view showing a part of a 3D semiconductor memory device according to embodiments of the present invention, and corresponds to part A of FIG. 3A. 3C is an enlarged view showing a part of a 3D semiconductor memory device according to embodiments of the present invention, and corresponds to part B of FIG. 3A.

2, 3A, 3B, and 3C, stacked structures ST may be disposed on the substrate 100. The stacked structures ST extend side by side in the first direction D1 and may be spaced apart from each other in the second direction D2. The substrate 100 may be a semiconductor substrate doped with impurities. The substrate 100 may be a semiconductor substrate doped with impurities having a first conductivity type (eg, P type). The substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate.

The stacked structures ST include gate electrodes EL and first and second interlayer insulating layers ILDa and ILDb alternately stacked in a third direction D3 perpendicular to an upper surface of the substrate 100, respectively. Can. The stacked structures ST may have a substantially flat top surface. The top surface of the stacked structures ST may be parallel to the top surface of the substrate 100.

Referring again to FIG. 1, the gate electrodes EL are respectively erased control lines ECL, ground selection lines GSL0-GSL2, and word lines WL0-WLn and DWL stacked on the substrate 100 in turn. ), the first string selection lines SSL1-1, SSL1-2, and SSL1-3 and the second string selection lines SSL2-1, SSL2-2, and SSL2-3. Each of the gate electrodes EL may have substantially the same thickness. The thickness of each of the gate electrodes EL may be smaller than the thickness of each of the first and second interlayer insulating layers ILDa and ILDb. The gate electrodes EL are, for example, doped semiconductors (ex, doped silicon, etc.), metals (ex, tungsten, copper, aluminum, etc.), conductive metal nitrides (ex, titanium nitride, tantalum nitride, etc.) Or it may include at least one selected from transition metals (ex, titanium, tantalum, etc.).

Although not shown, each end of each of the stacked structures ST may have a stepwise structure along the first direction D1. Specifically, the length of the gate electrodes EL of the stacked structures ST in the first direction D1 may decrease as the distance from the substrate 100 increases. The uppermost gate electrode ELt may have the smallest length extending in the first direction D1 among the gate electrodes EL, and the distance between the substrate 100 and the third direction D3 may be largest. . The lowermost gate electrode ELb may have the largest length extending in the first direction D1 among the gate electrodes EL, and the distance spaced apart from the substrate 100 and the third direction D3 may be the smallest. .

Each of the first and second interlayer insulating layers ILDa and ILDb may have a different thickness. The second interlayer insulating films ILDb refer to interlayer insulating films provided on the lower gate electrode ELb and above and below the uppermost gate electrode ELt, and the first interlayer insulating films ILDa are other interlayer insulating films Refers to them. For example, each of the first interlayer insulating films ILDa has substantially the same thickness, each of the second interlayer insulating films ILDb has substantially the same thickness, and the thickness and the second of the first interlayer insulating films ILDa. Interlayer insulating layers ILDb may have different thicknesses. The thickness of the second interlayer insulating layers ILDb may be greater than the thickness of the first interlayer insulating layers ILDa. However, the present invention is not limited thereto, and each of the first interlayer insulating films ILDa may have a different thickness, and each of the second interlayer insulating films ILDb may have a different thickness. The first and second interlayer insulating layers ILDa and ILDb may include, for example, silicon oxide.

A buffer insulating layer 105 may be provided between the substrate 100 and the stacked structures ST. The thickness of the buffer insulating layer 105 may be smaller than the thickness of the first and second interlayer insulating layers ILDa and ILDb. The buffer insulating film 105 may include silicon oxide, for example.

A plurality of channel holes CH passing through a part of the stack structures ST and the substrate 100 may be provided. Vertical structures VS may be provided in the channel holes CH. A portion of each of the vertical structures VS may be embedded in the substrate 100, and the lower surface of the vertical structures VS may be positioned at a lower level than the upper surface of the substrate 100. The vertical structures VS may be connected to the substrate 100.

A plurality of columns of vertical structures VS passing through any one of the stacked structures ST may be provided. For example, as illustrated in FIG. 2, rows of two vertical structures VS may pass through one of the stacked structures ST. However, the present invention is not limited thereto, and columns of three or more vertical structures VS may pass through one of the stacked structures ST. In a pair of adjacent columns, the vertical structures VS corresponding to one column may be shifted from the vertical structures VS corresponding to the other adjacent column in the first direction D1. In plan view, the vertical structures VS may be arranged in a zigzag form along the first direction D1.

The vertical structures VS may be in the form of a cylinder having a long axis extending in the third direction D3 from the substrate 100. The widths of the vertical structures VS in the first direction D1 and the second direction D2 may increase as the direction of the third direction D3 increases. The upper surfaces of the vertical structures VS may be circular, elliptical, or bar.

Each of the vertical structures VS may include a data storage pattern DSP, a vertical semiconductor pattern VSP, and a filling insulation pattern VI. In each of the vertical structures VS, the data storage pattern DSP and the vertical semiconductor pattern VSP may have an open pipe shape or a macaroni shape. The filling insulation pattern VI may fill a space surrounded by a data storage pattern DSP and a vertical semiconductor pattern VSP. The filling insulation pattern VI may include silicon oxide, for example. However, the present invention is not limited thereto, and the vertical semiconductor pattern VSP may completely fill each of the channel holes CH surrounded by the data storage pattern DSP, and in this case, the filling insulation pattern VI may be omitted. Can.

The vertical semiconductor pattern VSP may be surrounded by a data storage pattern DSP. Referring again to FIG. 1, the vertical structures VS include the erase control transistor ECT, the first and second string select transistors SST1 and SST2, and the ground select transistor GST and memory cell transistors MCT. It may correspond to the channels of. The vertical semiconductor pattern VSP may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical semiconductor pattern VSP may include a semiconductor doped with impurities, an intrinsic semiconductor or a polycrystalline semiconductor material without impurities. For example, the vertical semiconductor pattern VSP may include a semiconductor material doped with impurities having the same conductivity type as the substrate 100.

The data storage pattern DSP may include a blocking insulating layer BLK, a charge storage layer CIL, and a tunneling insulating layer TIL. The blocking insulating layer BLK may be adjacent to the stacked structures ST, and the tunneling insulating layer TIL may be adjacent to the vertical semiconductor pattern VSP. The charge storage layer CIL may be interposed between the blocking insulating layer BLK and the tunneling insulating layer TIL. The blocking insulating layer BLK, the charge storage layer CIL, and the tunneling insulating layer TIL may extend in the third direction D3 between the stacked structures ST and the vertical semiconductor pattern VSP. Due to the Fowler-Nordheim tunneling phenomenon induced by the voltage difference between the vertical semiconductor pattern VSP and the gate electrodes EL, the data storage pattern DSP stores and/or changes data. Can. For example, the blocking insulating layer BLK and the tunneling insulating layer TIL may include silicon oxide, and the charge storage layer CIL may include silicon nitride or silicon oxynitride.

3B and 3C, the blocking insulating layer BLK includes a first surface BLKa adjacent to the charge storage layer CIL, first and second interlayer insulating layers ILDa, ILDb, and gate electrodes EL ) May have a second surface BLKb adjacent to it. The first surface BLKa and the second surface BLKb of the blocking insulating layer BLK may have different profiles.

The first surface BLKa of the blocking insulating layer BLK may have a straight profile extending along the third direction D3. However, the present invention is not limited to this, and the first surface BLKa may have a straight profile having a constant slope with the third direction D3. Since the first surface BLKa has a profile parallel to the third direction D3, the charge storage layer CIL and the tunneling insulating layer TIL may extend along the third direction D3.

The second surface BLKb of the blocking insulating layer BLK has a concave or convex profile in portions adjacent to the gate electrodes EL and portions adjacent to the first and second interlayer insulating layers ILDa and ILDb. Can. Portions adjacent to the first and second interlayer insulating films ILDa and ILDb on the second surface BLKb may have a convex profile toward the first and second interlayer insulating films ILDa and ILDb. Portions adjacent to the gate electrodes EL on the second surface BLKb may have a concave profile toward the gate electrodes EL.

Due to the profile of the first surface BLKa and the second surface BLKb, a first distance defined by an interval between gate electrodes EL facing each other with one of the vertical structures VS interposed therebetween is a vertical structure It may be smaller than a second distance defined by a gap between first interlayer insulating layers ILDa (or a gap between second interlayer insulating layers ILDb) facing each other with one of the fields VS interposed therebetween.

In particular, referring to FIG. 3B, a part of the blocking insulating layer BLK may have a protrusion PP protruding toward any one of the gate electrodes EL. Some of the portions adjacent to the gate electrodes EL on the second surface BLKb of the blocking insulating layer BLK may have a profile protruding toward the gate electrodes EL, and the gate electrodes EL may be A part of the blocking insulating layer BLK having a profile protruding toward may be defined as a protrusion PP.

A conductive pad PAD connected to the bit line contact plug BPLG may be provided on the upper surface of each of the vertical structures VS. The conductive pad PAD may be connected to upper portions of the data storage pattern DSP, the vertical semiconductor pattern VSP, and the filling insulation pattern VI. The upper surface of the conductive pad PAD may be substantially coplanar with the upper surface of the uppermost one of the second interlayer insulating films ILDb. The uppermost of the second interlayer insulating films ILDb may be an interlayer insulating film provided on the uppermost gate electrode ELt. The conductive pad PAD may include a semiconductor or a conductive material doped with impurities. For example, the conductive pad PAD may include a semiconductor doped with impurities of a different conductivity type from the vertical semiconductor pattern VSP.

Between the stacked structures ST adjacent to each other, a separation trench TR extending in the first direction D1 may be provided. The common source region CSR may be provided inside the substrate 100 exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 in the substrate 100. The common source region CSR may have a second conductivity type (eg, N type) different from the first conductivity type. The common source area CSR may correspond to the common source line CSL of FIG. 1.

A common source plug (CSP) can be provided in the isolation trench (TR). The common source plug CSP may be connected to the common source area CSR. The upper surface of the common source plug CSP may be substantially coplanar with the upper surface of the stacked structures ST. The common source plug CSP may be in the form of a flat plate extending in the first direction D1 and the third direction D3. Insulating spacers SP may be interposed between the common source plug CSP and the stacked structures ST. The insulating spacers SP may be provided to face each other between the stacked structures ST adjacent to each other. The insulating spacers SP may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

The capping insulating layer 130 may be provided on the stacked structures ST, the vertical structures VS, and the common source plug CSP. The capping insulating layer 130 may cover the upper surface of the uppermost of the second interlayer insulating layers ILDb, the upper surface of the conductive pad PAD, and the upper surface of the common source plug CSP. A bit line contact plug BPLG connected to the conductive pad PAD may be provided inside the capping insulating layer 130. For example, the capping insulating layer 130 may include insulating materials different from the first and second interlayer insulating layers ILDa and ILDb.

A bit line BL may be provided on the capping insulating layer 130 and the bit line contact plug BPLG. The bit line BL may extend in the second direction D2. The bit line BL may be connected to the vertical structures VS through a bit line contact plug BPLG. The bit line BL and the bit line contact plug BPLG may include a conductive material. The bit line BL may correspond to any one of the plurality of bit lines BL0-BL2 of FIG. 1.

4, 5A, 14, 15, 16, and 17 are cross-sectional views of a 3D semiconductor memory device according to embodiments of the present invention, each of which corresponds to a cross-section of FIG. 2 taken along line I-I'. do. 5B, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are enlarged views showing portions of a 3D semiconductor memory device according to embodiments of the present invention, respectively. Corresponds to part A of the corresponding cross section. 5C, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are enlarged views showing portions of a 3D semiconductor memory device according to embodiments of the present invention, respectively. It corresponds to part B of the corresponding sectional view.

A method of manufacturing a 3D semiconductor memory device according to embodiments of the present invention will be described with reference to FIGS. 4 to 17.

Referring to FIG. 4, a buffer insulating layer 105, sacrificial layers 111, and first and second preliminary interlayer insulating layers 113a and 113b may be formed on the substrate 100. The sacrificial films 111 and the first and second preliminary interlayer insulating films 113a and 113b are alternately stacked in a third direction D3 perpendicular to the upper surface of the substrate 100 to form the thin film structure 110. have. The sacrificial films 111 and the first and second preliminary interlayer insulating films 113a and 113b may be formed by, for example, a chemical vapor deposition method. The first and second preliminary interlayer insulating layers 113a and 113b may correspond to the first and second interlayer insulating layers ILDa and ILDb of FIG. 3A.

The sacrificial films 111 of the thin film structure 110 may include a material having etch selectivity for the first and second preliminary interlayer insulating films 113a and 113b. For example, the sacrificial films 111 may include silicon nitride, and the first and second preliminary interlayer insulating films 113a and 113b may include silicon oxide.

The buffer insulating layer 105 formed between the bottom of the sacrificial layers 111 and the substrate 100 may be formed by, for example, a chemical vapor deposition method. The buffer insulating layer 105 may be formed through a thermal oxidation process after the deposition process.

5A, 5B and 5C, channel holes CH passing through the thin film structure 110 may be formed. The channel holes CH may recess a portion of the substrate 100 and expose the top surface of the substrate 100. The channel holes CH may expose sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b.

The channel holes CH may be formed by forming a mask pattern on the thin film structure 110 and performing an anisotropic etching process using the mask pattern as an etching mask. The top surface of the substrate 100 may be excessively etched by an anisotropic etching process. The channel holes CH may have a plurality of rows in the plan view of FIG. 2 and may be arranged in a zigzag form.

In the process of forming the channel holes CH, the first recessed portion S1 or the second recessed portion S2 may be formed on sidewalls of some of the sacrificial films 111 during the anisotropic etching process. For example, the first depression S1 may be formed on each of the sacrificial films 111 positioned above, but the present invention is not limited thereto. Among the sacrificial films 111, the first depression S1 is formed in the portion A of FIG. 5A (the second sacrificial film from the top), and the portion B of FIG. 5A of the sacrificial films 111 (the fifth sacrificial film from the top) Although it is shown that the second depression S2 is formed in the film), the present invention is not limited thereto. That is, the position of the sacrificial film in which the first recessed portion S1 or the second recessed portion S2 is formed is not limited by that shown.

The first depression S1 may be defined as a recessed portion of one of the sacrificial films 111 along one surface of the upper and lower surfaces of the first interlayer insulating layer ILDa and the upper and lower surfaces of the second interlayer insulating layer ILDb. have. The second recessed portion S2 may be defined as a portion in which one side wall of the sacrificial films 111 is recessed.

6A and 6B, the first insulating film 210 is formed on sidewalls of the sacrificial films 111 exposed by the channel holes CH and the first and second preliminary interlayer insulating films 113a and 113b. It can be formed conformally. The first insulating film 210 may include, for example, silicon nitride. The first insulating layer 210 may be formed to a thickness of about 50 Å to 150 Å. More preferably, the first insulating film 210 may be formed to a thickness of about 60 Å to 100 Å.

The first insulating layer 210 may fill the first recessed portion S1 and the second recessed portion S2. Sidewalls of the first insulating layer 210 exposed by the channel holes CH may have a profile similar to the first recessed portion S1 and the second recessed portion S2, but the recessed degree may be reduced.

For example, some of the sacrificial films 111 may have first depressions S1 formed on both sidewalls, respectively. Through filling the first insulating layer 210 inside the first depression S1, it is possible to prevent the first depressions S1 formed on both side walls of some of the sacrificial layers 111 from being connected to each other. have. Accordingly, vertical structures (VS, see FIG. 3A) to be provided inside each channel hole CH may be prevented from being connected to each other, and reliability and electrical characteristics of the 3D semiconductor memory device, which has been manufactured, may be improved. Can.

7A and 7B, a portion of the first insulating layer 210 is oxidized to form the second insulating layer 230. For example, the process of oxidizing a part of the first insulating film 210 may be performed in an in-situ process together with the process of depositing the first insulating film 210. The first insulating layer 210 and the second insulating layer 230 may be sequentially formed on the sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b. However, the present invention is not limited to this, and as illustrated, the first insulating film 210 is sufficiently oxidized so that the second insulating film 230 is the sacrificial films 111, the first and second preliminary interlayer insulating films 113a, 113b). The first recessed part S1 and the second recessed part S2 may be completely filled by the first insulating film 210 and the second insulating film 230.

8A and 8B, a first etching process for the first insulating layer 210 and the second insulating layer 230 may be performed. A portion of the second insulating layer 230 and the first insulating layer 210 may be removed by the first etching process. The first etching process may be, for example, a wet etching process using an etching solution. During the first etching process, etch rates for silicon oxide and silicon nitride may be different. For the first etching process, for example, a 40:1 hydrofluoric acid (HF) aqueous solution can be used. Profiles of sidewalls of the sacrificial layers 111, the first and second preliminary interlayer insulating layers 113a and 113b may be changed by the first etching process.

Sidewalls of the first and second preliminary interlayer insulating layers 113a and 113b may be etched more than sidewalls of the sacrificial layers 111. Accordingly, sidewalls of the first and second preliminary interlayer insulating layers 113a and 113b may have a concave profile toward the channel holes CH, and sidewalls of the sacrificial layers 111 toward the channel holes CH. It can have a convex profile.

In FIG. 8A, a portion of the first insulating layer 210 filling the first recessed portion S1 may remain on the sacrificial layers 111 after the first etching process. The remaining first insulating film 210 may include a recessed portion similar to the first recessed portion S1. In FIG. 8B, a portion where the sidewall is recessed recessed in the sacrificial films 111 after the first etching process may disappear. Due to the profile in which the sidewall recessed portion disappears, the cell characteristics may be improved by reducing charge loss in the 3D semiconductor memory device having been manufactured, and as a result, electrical characteristics may be improved.

9A and 9B, a third insulating layer 250 may be conformally formed on sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b. The third insulating film 250 may include, for example, silicon nitride.

The sidewalls of the third insulating layer 250 exposed by the channel holes CH may have a profile similar to the sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b.

10A and 10B, a part of the third insulating film 250 is oxidized to form a fourth insulating film 260. For example, the process of oxidizing a part of the third insulating film 250 may be performed in an in-situ process together with the process of depositing the third insulating film 250. The third insulating layer 250 and the fourth insulating layer 260 may be sequentially formed on the sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b. However, the present invention is not limited to this, and as illustrated, the third insulating film 250 is sufficiently oxidized so that the fourth insulating film 260 is the sacrificial films 111, the first and second preliminary interlayer insulating films 113a, 113b).

11A and 11B, a part of the fourth insulating layer 260 may be removed through a second etching process. The second etching process may be, for example, a wet etching process using an etching solution. For the second etching process, for example, a 200:1 hydrofluoric acid (HF) aqueous solution can be used. By the second etching process, the profile of the sidewall of the fourth insulating layer 260 may be closer to the straight line than the sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b.

12A and 12B, a fifth insulating layer 280 may be conformally formed on a sidewall of the fourth insulating layer 260. The fifth insulating layer 280 may include, for example, silicon nitride. The sidewall of the fifth insulating layer 280 exposed by the channel holes CH may be closer to the straight line than the sidewall of the fourth insulating layer 260. Referring back to FIG. 5A, the sidewall of the fifth insulating layer 280 may have a profile substantially parallel to the third direction D3 perpendicular to the top surface of the substrate 100. However, the present invention is not limited to this, and the sidewall of the fifth insulating layer 280 may have a straight profile having a constant slope with the third direction D3.

12A, 12B, 13A, and 13B, a part of the remaining first insulating film 210 and third to fifth insulating films 250, 260, and 280 are oxidized to form a blocking insulating film BLK Can be. A portion of the first insulating layer 210 may remain even after the blocking insulating layer BLK is formed. The remaining first insulating film 210 may be positioned between one of the sacrificial films 111 and the blocking insulating film BLK.

The blocking insulating layer BLK includes a first surface BLKa exposed by channel holes CH and a second surface BLKb adjacent to the first and second interlayer insulating layers ILDa and ILDb and the gate electrodes EL. ). The first surface BLKa and the second surface BLKb of the blocking insulating layer BLK may have different profiles. The profiles of the first surface BLKa and the second surface BLKb may be the same as those described with reference to FIGS. 3B and 3C.

Referring to FIG. 14, a charge storage layer (see CIL, see FIGS. 3A and 3B) and a tunneling insulating layer (see TIL, FIGS. 3A and 3B) may be formed inside the channel holes CH in which the blocking insulating layer BLK is formed. have. The blocking insulating film BLK, the charge storage film (CIL, see FIGS. 3A and 3B) and the tunneling insulating film (TIL) on the sidewalls of the sacrificial films 111, the first and second preliminary interlayer insulating films 113a and 113b , See FIGS. 3A and 3B ), a data storage pattern DSP may be formed. The blocking insulating layer BLK may be formed through the process described with reference to FIGS. 5B, 5C, and 6A to 13B.

Accordingly, vertical structures VS including the data storage pattern DSP, the vertical semiconductor pattern VSP, and the filling insulation pattern VI may be formed inside the channel holes CH. The vertical semiconductor pattern VSP may be conformally deposited on the data storage pattern DSP exposed by the channel holes CH. The data storage pattern (DSP) and the vertical semiconductor pattern (VSP) may be formed by a chemical vapor deposition method or an atomic layer deposition method.

The filling insulation pattern VI may fill a space surrounded by a data storage pattern DSP and a vertical semiconductor pattern VSP. The filling insulation pattern VI is formed by filling the inner space of each of the channel holes CH surrounded by the vertical semiconductor pattern VSP with an insulating material and performing a planarization process so that the upper surface of the thin film structure 110 is exposed. Can.

A conductive pad PAD may be formed on each of the vertical structures VS. The conductive pad PAD may be formed by recessing some of the vertical structures VS and filling a doped semiconductor material or conductive material in the recessed region.

15, a separation trench TR penetrating through the thin film structure 110 may be formed. The separation trench TR may recess a portion of the substrate 100 and expose the top surface of the substrate 100. The separation trench TR may expose sidewalls of the sacrificial layers 111 and the first and second preliminary interlayer insulating layers 113a and 113b.

The separation trench TR may be formed by forming a mask pattern on the thin film structure 110 and patterning the mask pattern using an etch mask. The top surface of the substrate 100 may be excessively etched by patterning. The separation trench TR may have a line shape extending in the first direction D1 from the plan view of FIG. 2.

Referring to FIG. 16, sacrificial films 111 exposed by the separation trench TR may be selectively removed. The selective removal of the sacrificial layers 111 may be performed through a wet etching process using an etching solution. For example, the sacrificial films 111 may be selectively removed using an etchant solution containing hydrofluoric acid or phosphoric acid. Referring to FIG. 13A, when the sacrificial films 111 are removed, a part of the first insulating layer 210 remaining inside the first recessed portion S1 may be removed together.

The sacrificial layers 111 may be removed to form gate regions GR. The gate regions GR may be defined as regions extending horizontally from the isolation trench TR between the first and second preliminary interlayer insulating layers 113a and 113b.

16 and 17, gate electrodes EL filling the gate regions GR may be formed. The gate electrodes EL may be formed by forming a conductive layer filling part of the gate regions GR and the isolation trench TR and removing the conductive layer formed inside the isolation trench TR. The gate electrodes EL may be formed by, for example, a chemical vapor deposition method or an atomic layer deposition method.

As the gate electrodes EL are formed, the gate electrodes EL, the first and second interlayer insulating layers ILDa and ILDb alternately stacked in the third direction D3 perpendicular to the upper surface of the substrate 100 Stacked structures (ST) may be formed. The stacked structures ST may extend in the first direction D1 from the plan view of FIG. 2 and may be spaced apart from each other in the second direction D2. A portion of the upper surface of the substrate 100 may be exposed between the stacked structures ST adjacent to each other.

Impurities of a different conductivity type from the substrate 100 may be doped on the upper surface of the substrate 100 exposed by the separation trench TR, and accordingly, within the substrate 100 between the stacked structures ST adjacent to each other. The common source region CSR may be formed.

Referring back to FIG. 3A, insulating spacers SP covering sidewalls of the isolation trench TR may be formed. The insulating spacers SP conformally deposit the spacer film on the substrate 100 and the stacked structures ST shown in FIG. 17 and expose the common source region CSR through an etch-back process or the like. Can be formed through. A common source plug CSP may be formed in a space inside the isolation trench TR surrounded by the insulating spacers SP.

The capping insulating layer 130 may be formed on the stacked structures ST, the vertical structures VS, and the common source plug CSP. The capping insulating layer 130 may cover the upper surface of the uppermost of the second interlayer insulating layers ILDb, the upper surface of the conductive pad PAD, and the upper surface of the common source plug CSP. Subsequently, a bit line contact plug BPLG that penetrates the capping insulating layer 130 and is connected to the conductive pad PAD may be formed. Subsequently, a bit line BL extending in the second direction D2 on the capping insulating layer 130 and connected to the bit line contact plug BPLG may be formed.

18A is a cross-sectional view of a 3D semiconductor memory device according to embodiments of the present invention, and corresponds to a cross-section of FIG. 2 taken along line I-I'. 18B is an enlarged view illustrating a portion of a 3D semiconductor memory device according to embodiments of the present invention, and corresponds to portion C of FIG. 18A.

18A and 18B, a buffer insulating layer 105, sacrificial layers 111, and first and second preliminary interlayer insulating layers 121 and 123 may be formed on the substrate 100. The sacrificial films 111 and the first and second preliminary interlayer insulating films 121 and 123 are alternately stacked in a third direction D3 perpendicular to the upper surface of the substrate 100 to form the thin film structure 120. have. The first preliminary interlayer insulating films 121 may be insulating films below the thin film structure 120 adjacent to the top surface of the substrate 100, and the second preliminary interlayer insulating films 123 may be insulating films above the thin film structure 120. Can. For example, one or more (eg, 1 to 3) interlayer insulating films may be defined as the first preliminary interlayer insulating films 121 in the order close to the upper surface of the substrate 100, and the remaining interlayer insulating films These may be defined as second preliminary interlayer insulating films 123.

The first preliminary interlayer insulating films 121 and the second preliminary interlayer insulating films 123 may include, for example, silicon oxide. The first preliminary interlayer insulating layers 121 and the second preliminary interlayer insulating layers 123 may include silicon oxides having different wet etch rates. For example, the wet etching rate of silicon oxide included in the first preliminary interlayer insulating layers 121 may be greater than the wet etching rate of silicon oxide included in the second preliminary interlayer insulating layers 123. However, the present invention is not limited thereto, and the first and second preliminary interlayer insulating layers 121 and 123 may include silicon oxide having a higher wet etching rate as it approaches the upper surface of the substrate 100.

The sacrificial films 111 and the first and second preliminary interlayer insulating films 121 and 123 alternately stack the silicon nitride film and the silicon oxide film through a deposition process such as a chemical vapor deposition method, the thin film structure 120 and the substrate Forming a plurality of channel holes (CH) penetrating a part of the (100), and selectively sidewalls of the first and second preliminary interlayer insulating films (121, 123) exposed by the channel holes (CH) The recess may be formed through performing a recess process.

Recessing the sidewalls of the first and second preliminary interlayer insulating layers 121 and 123 exposed by the channel holes CH may be performed, for example, through a wet etching process using an etching solution. For example, sidewalls of the first and second preliminary interlayer insulating layers 121 and 123 may be recessed using an etchant solution containing hydrofluoric acid or phosphoric acid.

Since the first preliminary interlayer insulating films 121 and the second preliminary interlayer insulating films 123 include silicon oxides having different wet etch rates, the first and second preliminary interlayer insulating films 121 , 123) may be recessed to a uniform extent. For example, the first width W1 indicating the degree to which the first preliminary interlayer insulating films 121 are recessed is equal to the second width W2 indicating the degree to which the second preliminary interlayer insulating films 123 are recessed. It may be substantially the same.

Since the sidewalls of the first and second preliminary interlayer insulating films 121 and 123 are recessed, the sacrificial films 111 exposed by the channel holes CH, the first and second preliminary interlayer insulating films 121 , 123) may have the profile of the sidewalls of FIG. 18B. Specifically, sidewalls of the sacrificial films 111 may have a convex profile toward the channel holes CH, and sidewalls of the first and second preliminary interlayer insulating films 121 and 123 toward the channel holes CH It can have a concave profile. Due to such a profile, cell characteristics may be improved by reducing charge loss in a 3D semiconductor memory device that has been manufactured, and as a result, electrical characteristics may be improved.

After the sidewalls of the first and second preliminary interlayer insulating layers 121 and 123 exposed by the channel holes CH are recessed, the manufacturing method described with reference to FIGS. 6A and 6B to 17 Through this, a 3D semiconductor memory device can be manufactured.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but a person having ordinary knowledge in the technical field to which the present invention pertains can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (10)

Forming a thin film structure by alternately laminating sacrificial films and preliminary interlayer insulating films on a substrate;
Forming channel holes through the thin film structure; And
Forming a blocking insulating layer, a charge storage layer, and a tunneling insulating layer on the sidewalls of the sacrificial layers and the preliminary interlayer insulating layers exposed by the channel holes,
Forming the blocking insulating film is:
Depositing a first insulating film on the sidewalls of the sacrificial films and the preliminary interlayer insulating films, and oxidizing a part thereof;
Etching a portion of the first insulating layer and the preliminary interlayer insulating layers through a first etching process;
Depositing a second insulating film on the sidewalls of the sacrificial films and the preliminary interlayer insulating films, and oxidizing a part thereof;
Etching a portion of the second insulating layer through a second etching process; And
Depositing a third insulating film on the second insulating film, and oxidizing the first to third insulating films,
Some of the sacrificial films have depressions formed on the sidewalls exposed by the channel holes,
The blocking insulating film is a manufacturing method of a three-dimensional semiconductor memory device filling the depressions.
According to claim 1,
A method of manufacturing a three-dimensional semiconductor memory device in which a portion of the first insulating layer remains inside some of the depressions.
According to claim 1,
The first insulating film is a method of manufacturing a 3D semiconductor memory device including the same material as the sacrificial films.
According to claim 1,
After forming the channel holes, and before forming the blocking insulating layer, a 3D semiconductor further comprising performing a recessing process to selectively recess sidewalls of the preliminary interlayer insulating layers exposed by the channel holes. A method of manufacturing a memory device.
The method of claim 4,
The recessing process includes performing a wet etching process on the preliminary interlayer insulating films,
During the wet etching process, a method of manufacturing a 3D semiconductor memory device having different etching rates of one to three of the preliminary interlayer insulating films close to an upper surface of the substrate among the preliminary interlayer insulating films and an etching rate of the rest of the preliminary interlayer insulating films. .
According to claim 1,
The first etching process and the second etching process are three-dimensional semiconductor memory device manufacturing method including a wet etching process using a hydrofluoric acid (HF) aqueous solution.
According to claim 1,
The first insulating film is a method of manufacturing a 3D semiconductor memory device deposited on the sidewalls of the sacrificial films and the preliminary interlayer insulating films with a thickness of 60 Å to 100 Å.
According to claim 1,
Forming a vertical semiconductor pattern filling the channel holes;
Forming a separation trench penetrating the thin film structure;
Selectively removing the sacrificial films exposed by the separation trench;
Forming gate electrodes in a region where the sacrificial films are removed; And
And forming a common source plug filling the isolation trench.
The method of claim 8,
Each of the gate electrodes has a sidewall adjacent to the blocking insulating film and has a convex profile toward the blocking insulating film.
According to claim 1,
Further comprising forming a vertical semiconductor pattern filling the channel holes,
The blocking insulating film has a first surface adjacent to the vertical semiconductor pattern and a second surface opposite to the first surface,
The first surface is a manufacturing method of a three-dimensional semiconductor memory device having a straight profile perpendicular to the upper surface of the substrate.

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