KR20200086859A - Lightweight block cryptography device - Google Patents

Abstract

The present invention relates to a lightweight block encryption device. The block encryption device performs encryption and decryption in accordance with a mode selection signal and comprises: a control unit to generate and output a round signal of a form increasing at each clock to display a current round and a count signal controlled in accordance with an input signal for separating key data and plaintext data; a key generation unit to determine an encryption or decryption mode in accordance with the mode selection signal and receive key data to generate and output an n-bit round key at each round; and a round unit to use the round signal and the round key to perform encryption or decryption on plaintext data to output a result value. The key generation unit uses a white key of an m^th round to reversely generate a round key from the m^th round to a first round to transfer the round key to the round unit without storing and transferring a round key used during previous encryption in some rounds of a decryption mode.

Description

Block encryption device {LIGHTWEIGHT BLOCK CRYPTOGRAPHY DEVICE}

The present invention relates to an information encryption device, and more particularly to a lightweight block encryption device.

As the transmission of various information through a communication network is becoming common, the amount of information being exchanged is also rapidly increasing. In addition, considering that personal information such as personal information is included in the exchange or transmission information, it is necessary to increase the security of the information so that the information does not leak to others. In particular, with the advent of the Internet of Things (IoT) era, the importance of information security is increasingly emphasized, and due to the nature of the IoT field requiring light weight/low power, an appropriate encryption processor is considered an important technology in the IoT field.

For reference, symmetric key encryption algorithm (TWINE) developed by NEC in Japan in 2012 supports 80-bit and 128-bit key lengths, and is a lightweight block encryption algorithm with a block size of 64-bit. Since it uses only S-box and XOR, it is developed with a focus on weight reduction so that it can be used for security of environments that require weight reduction such as IoT, WSN, etc. This encryption algorithm (TWINE) has the characteristics described above, yet has a security strength similar to that of the existing block encryption algorithm, and is made to implement various hardware from low-end hardware to high-end hardware.

However, since the symmetric key encryption algorithm (TWINE) exemplified above is also a method of storing a round key used for encryption and decryption, there is a limitation in implementing a low area and reducing the weight of the product because a register for key storage is required.

Republic of Korea Patent Publication No. 2003-0087893

Accordingly, the present invention is an invention created to solve the above-mentioned problems, and the main object of the present invention is to provide a low-area implementation and a lightweight block encryption device.

Furthermore, another object of the present invention is to provide a lightweight block encryption device capable of sharing hardware resources during encryption and decryption computation to implement lightweight hardware.

A block encryption device according to an embodiment of the present invention for achieving the above object is a block encryption device that performs encryption and decryption according to a mode selection signal,

A control unit for generating and outputting a round signal in a form of increasing every clock to display a current round, and a count signal controlled according to an input signal for distinguishing key data and plain text data;

A key generation unit for determining a dark and a decryption mode according to the mode selection signal and receiving key data to generate and output an n-bit round key every round;

Includes; a round unit for performing encryption or decryption of the plain text data using the round signal and the round key to output the result value;

The key generation unit inversely generates round keys from the mth to the first round using the fake key of the mth round without storing and transmitting the round key used in the previous encryption in some rounds of the decryption mode. It is characterized by delivering to the round part,

Furthermore, it is another feature that the round unit is implemented with logic to integrally process the odd digit calculation process of the plain text data in the process of encrypting or decrypting the plain text data.

According to the above technical problem solving means, the present invention does not store and use the round key used for the previous encryption in a separate register in some rounds of the decryption mode. Since the method of generating the round key up to the first round in reverse is adopted, as a result, the number of registers for storing the round key is reduced, thereby making the block encryption device lighter.

In addition, the block encryption device according to an embodiment of the present invention has an advantage of providing a low-area, lightweight block encryption device by integrating and implementing parts that require the same operation in each operation process of encrypting or decrypting plaintext. .

1 is an exemplary 80-bit and 128-bit key scheduler algorithm.
2 is an exemplary 80-bit key scheduler.
3 is an exemplary S-box table.
4 is an example of a constant table.
5 is an exemplary diagram of the TWINE encryption algorithm.
6 is an example of a round function of TWINE.
7 is an exemplary PI substitution table.
8 is an exemplary diagram of a TWINE decoding algorithm.
9 is an exemplary block diagram of a block encryption device according to an embodiment of the present invention.
FIG. 10 is an exemplary block diagram of an 80-bit key length inside the key generator 200 in FIG. 9.
FIG. 11 is a block diagram showing the length of a 128-bit key in the key generator 200 in FIG. 9.
12 and 13 are diagrams illustrating 80-bit and 128-bit encryption operation processes, respectively.
14 and 15 are examples of 80-bit and 128-bit inverse key generation algorithms, respectively.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the present invention, if it is determined that related functions or configurations may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

First, the symmetric key encryption algorithm (TWINE) developed by NEC of Japan is a lightweight block encryption algorithm that encrypts or decrypts 64-bit data with an 80-bit or 128-bit master key. In this TWINE algorithm, the encryption and decryption process goes through 36 rounds. The key value is changed every round, and the encryption and decryption of the data is performed with the changed key in each round, and the data from the last round is returned as the result. . Therefore, TWINE algorithm can be divided into two parts: key generation, encryption, and decryption.

The operations used in both the key generation, encryption, and decryption are XOR, 4-bit cyclic shift, and S-box, and the constant table used only for key generation and the PI replacement table used only for encryption and decryption are used. Have.

Also, all data is processed in 4-bit units. The S-box serves to return different values depending on the received data, and the constant table returns different values every round. Finally, the PI substitution table plays a role of changing the position of each sub-block (data divided into 4-bit units) during cancer and decoding.

Hereinafter, the key generation procedure will be explained.

First, FIG. 1 illustrates an 80-bit and 128-bit key scheduler algorithm, FIG. 2 illustrates an 80-bit key scheduler, and FIGS. 3 and 4 illustrate S-box tables and constant tables, respectively. Since the 80-bit key generation and 128-bit key generation algorithms are almost similar, in the following, only the 80-bit key will be described, and the first number of each line of the 80-bit algorithm will be described.

(1) Since data is processed in 4-bit units, the 80-bit master key entered as an input is divided into a total of 20 sub-blocks with 4-bit WK (White Key).

(2) Subsequently, RK (Round Key) is generated in each round after 35 repetitions from Fig. 1 to 3. to 9. The RK is a key value used during encryption and decryption.

(3) Among 20 sub-blocks of 4-bit WK, a fixed sub-block is taken as the RK value. The superscript r of RK means the current round, and the subscript 32 means 8 bits of 4-bit WK, so it means 32-bit.

(4)~(5) According to the current WK value, the calculated result is put into the first WK and the fourth WK using an S-box that returns a different value as shown in FIG. 3.

(6) to (7) As shown in Fig. 4, CON returns a 6-bit value every round. Therefore, one block of WK is 4-bit, so to match 4-bit, cut the CON value in half, divide it into High, Low, and add 0 at the beginning to match 4 bits. The calculated result is put into the 7th WK and the 19th WK.

(8)~(9) Rota(b) means to shift b to the left by a-bit. Therefore, since one block of WK is 4-bit, shift is performed accordingly.

(10) If the loop of 2. goes through 35 times, 35 RKs are finally created, and the 36th RK is created to have the last RK.

(11) Finally, 36 RKs are made.

36 RKs created through this process are used for cancer and decryption every round.

Hereinafter, cancer and decryption will be described in detail.

FIG. 5 illustrates the TWINE encryption algorithm, FIG. 6 illustrates the TWINE round function, and FIG. 7 illustrates the PI substitution table.

First, as shown in FIG. 5, the process of encryption starts with 64-bit plaintext data and 32-bit RK 36 inputs. And if the round function of TWINE is as illustrated in Fig. 6,

(1) 64-bit plain text data is divided into 16 4-bit sub-blocks. The superscript 1 of X means the current round, and the subscripts 0(4) to 15(4) mean 16 subblocks of 4-bit.

(2) 36 32-bit RKs created in key generation are separated into round units. Superscripts 1 to 36 mean rounds, and subscript 32 means 32-bits.

(3) 35 repetitions are performed from 4. to 6. The round increases each time i increases.

(4) The 32-bit RK of the current round is divided into 4-bit units. The superscript i means the current round, and the subscripts 0(4) to 7(4) refer to 8 4-bit subblocks.

(5) The result calculated using RK and S-box is substituted into the odd digit of the plain text data of the current round.

(6) As it increases from the current round to the next round, the seat is changed by referring to the PI substitution table shown in FIG. 7.

(7) After the 35 iterations in 3. are over, the last 36th round operation is performed.

(8) The final ciphertext is returned.

Hereinafter, a block encryption device according to an embodiment of the present invention designed based on the above-described TWINE algorithm will be described in detail.

First, the block encryption apparatus of the present invention based on the TWINE algorithm is composed of a control unit 100, a key generation unit (Key_gen) 200, and a round unit 300 as shown in FIG. The function of each port name shown in FIG. 9 is shown in Table 1 below.

In FIG. 9, if the input signal'iMode' is'low', encryption is performed, and if it is'high', decryption is performed. Also, if the input signal'ikey_sel' is'low', it means that an 80-bit key is used, and if it is'high', a 128-bit key is used. If the input signal'iplain_in' is'low', the data coming into the idata[31:0] port is the key data, and if it is'high', the data coming into the idata[31:0] port is the plain text data. If a 128-bit key is used, 32-bit data will be input 4 times into the idata[31:0] port, and 64-bit plain text data will be input twice through the 32-bit data into the idata[31:0] port.

For reference, the key generating unit (Key_gen) 200 sends rk[31:0] generated in each round to the round unit 300, and in the round unit 300, rnd[5: 0] and rk[31:0] to perform encryption and decryption. When the result of the dark and decoded data is output from the round unit 300, 32-bits are cut out to output a total of 64-bit data twice.

The control unit 100 controls the 32-bit data coming into the idata[31:0] port using the count[2:0] signal to match the length of the 80-bit key, 128-bit key, and 64-bit plain text data. And the rnd[5:0] signal is used to inform the round unit 300 how many rounds the current round is.

Hereinafter, each block will be described in more detail.

First, the key generating unit 200 is a block for generating a round key rk to be used in the round unit 300. It receives data on the key and generates each round key in 1-clk/1-round units, and supports 80-bit and 128-bit. The key generating unit 200 is as shown in FIGS. 10 and 11, and the contents of the 80-bit key length and the 128-bit key length inside the key generating unit 200 are divided into two block diagrams. .

As shown in FIGS. 10 and 11, the key generator 200 shifts the 32-bit key data input 4 times and stores it in a 128-bit register. The key length is determined through the iKey_sel signal, and the dark and decryption modes are determined according to the iMode signal. Both the arm and decryption for the 80-bit and 128-bit key lengths are performed in the operation process, the shift process, and the round key generation process, and are controlled by the rnd value received as input through the control unit 100.

The encryption operation process for the 80-bit key length is as shown in FIG. 12.

The 80-bit WK is divided into 4-bit units, and the value of a specific location is calculated using s_box and RCON values. Since RCON is 6-bit, it is divided into RCONH and RCONL by 3 bits, then 0 is added to the most significant bit to make it 4-bit. The encryption operation process for the 128-bit key length is as shown in FIG. 13, and a specific location for calculating the WK and one operation using s_box are added, and the other contents are the encryption operation process for the 80-bit key length. same.

On the other hand, in the decryption process, in contrast to encryption, from the 36th round key to the first round key, it is necessary in reverse order. To solve this, the existing key generation algorithm uses a method of storing and using the round key generated in the encryption process in a register with respect to the round key in the decryption process. This method is unsuitable for the purpose of weight reduction because it requires a large number of resistors.

In order to solve this problem, in the embodiment of the present invention, an inverse key generation algorithm was created and applied to hardware implementation. The 80-bit inverse key generation algorithm is as shown in FIG. 14, and the 128-bit inverse key generation algorithm is as shown in FIG.

If the inverse key generation algorithm has the white key of the 36th round, the existing key generation algorithm may be performed in the reverse order to generate the first round key. If the 80-bit inverse key generation algorithm is described as an example, the operation using S-box and XOR from 4 to 7 in FIG. 14 and the row replacement process from 8 to 9 are the same as those of the existing key generation algorithm. You can see that the contents of the specific white key shift and how many bits are shifted are different. By using such an algorithm, the final target low area can be implemented without using a register that stores a round key.

Referring to FIG. 9 again, the round unit 300 uses the round key generated by the key generating unit 200 to generate a plain text as an encrypted text. A 64-bit plaintext is received as input, and a ciphertext is generated through a total of 36 rounds, and the process is as illustrated in FIG. 16.

First, the 32-bit text data input is shifted twice and stored in a 64-bit register. The whole process consists of arithmetic and shifting. It can be confirmed through the process 5 of FIG. 5 and FIG. 8 that the process of the encryption and decryption is the same for both the odd and the digits. In the exemplary embodiment of the present invention, a low area is pursued by integrating odd and digit arithmetic processes of encryption and decryption using such a common point.

Thereafter, encryption and decryption are performed inside the shifter to perform each shift process through an iMode signal. In the case of encryption, 64-bit data is rearranged, and the ciphertext is output without going through this process in the 36th round, the last round. The decryption process uses a 64-bit input as the ciphertext that has been passed through the encryption process, and unlike the encryption, the row operation process is reversed, and there is no difference from the encryption process.

The control unit 100 is a block for generating an rnd signal and a count signal to be used in the key generation unit 200 and the round unit 300. The rnd signal is a signal indicating the current round that increases by 1 for each clock, and the progress of the round can be grasped through the rnd signal. This count signal first receives 32-bit data only when the value changes, and serves to shift 32-bit to the right while receiving 32-bit data for subsequent changes. The value of the count signal changes 4 times in total and is controlled by iplain_in.

As described above, the key generation unit 200 of the block encryption apparatus according to the embodiment of the present invention generates a round key RK corresponding to one round during 1-clock (clk) and the round unit 300 The operation corresponding to one round is processed using this RK. Therefore, the plaintext is input and the encrypted text or the decrypted text is output after 36-clock. Since the operation of the fifth process of the encryption and decryption algorithms shown in FIGS. 5 and 8 are the same, in the embodiment of the present invention, less hardware resources are used by sharing the operators for this part when designing the hardware for weight reduction. It was designed as possible.

Regarding register savings, it has been proposed to store all 36 32-bit RKs that require the existing TWINE algorithm. In this case, 32-bit * 36 = 1152-bit registers are needed to store all 36 RKs. However, if one RK is generated and used every round, only 32-bit registers are used, which significantly reduces the use of registers, but there is a problem in decoding.

The first problem is that the RK used for encryption is used in the order of 1 round to 36 rounds, so there is no difficulty in generating the RK required for each round using the master key. However, since the RK used for decoding is used in the order of 1 round to 36 rounds, an additional 128-bit register that stores the white key (WK) of the 36 rounds is required to generate the RK of the 36 rounds.

The second problem is that the key generation algorithm shown in FIG. 1 is an algorithm for generating RKs from the first round to the 36th round with the master key. However, since the RK used for decoding must be used in order from round 36 to round 1, a new algorithm for generating RK from round 36 to round 1 with a WK of 36 rounds is needed.

In order to solve the second problem, the block encryption apparatus according to the embodiment of the present invention uses an inverse key generation algorithm that generates RK from 36 rounds to 1 round as shown in FIG. 14. By using the inverse key generation algorithm, RK is generated from 36 rounds to 1 round in order, thereby generating RK corresponding to each round. As a result, two problems caused by designing to reduce the use of resistors for weight reduction can be solved normally.

The present invention has been described above with reference to the embodiments shown in the drawings, but these are merely exemplary, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be defined only by the appended claims.

Claims (3)

In the block encryption device for performing encryption and decryption according to the mode selection signal,
A control unit for generating and outputting a count signal controlled according to an input signal for distinguishing key data and plain text data, and a round signal which increases in every clock to display the current round;
A key generation unit for determining a dark and a decryption mode according to the mode selection signal, receiving key data, and generating and outputting an n-bit round key every round;
Includes a round unit for performing encryption or decryption of plain text data using the round signal and the round key and outputting the result value.
The key generation unit inversely generates the round keys from the m th to the first round using the fake key of the m th round without storing and transmitting the round key used for the previous encryption in some rounds of the decryption mode. Block encryption device characterized in that the transmission to the round part.
The method according to claim 1, The round portion,
A block encryption device, characterized in that logic is implemented to integrally process the odd-digit operation of the plaintext data in the process of encrypting or decrypting the plaintext data.
The method according to claim 1, wherein the key generation unit in the decryption mode, using the 36th round of the fake key, the block encryption device characterized in that the inverse generation of the round key from the 36th to the first round is transmitted to the round unit.

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