KR20200086485A - Method and Apparatus for Recognizing Defect Patterns in Wafer Map - Google Patents

Abstract

Disclosed are a method for recognizing a wafer map defect pattern and a device thereof. According to an embodiment of the present invention, provided is a method for analyzing a situation in which a wafer map is a video including a noise signal, a situation in which sufficient data for feature learning can be secured, a situation in which most of the wafer maps are good products due to a characteristic of mass production and a small number of the defect pattern is recognized, and a difficult situation to perform labeling of experts since the defect pattern is difficult to be standardized.

Description

Method and Apparatus for Recognizing Defect Patterns in Wafer Map}

This embodiment relates to a method and apparatus for recognizing a wafer map defect pattern.

The contents described below merely provide background information related to the present embodiment, and do not constitute a prior art.

The technique of determining the defect pattern of the wafer map is one of the most important techniques for tracking the cause of the defect. In particular, determining the presence or absence of four types of defect patterns, known as the causes of defects, circular, (partially) annular, scratched, and area-type, is an important task to improve productivity by taking timely measures for semiconductor equipment. to be. However, because the global and random noise-shaped wafer map pattern is due to various causes, it is difficult to see it as a great concern in facility measures.

The existing wafer map analysis method is a method of segmenting an area and generating a feature vector, but this has limitations in patterning for each area when defect patterns exist across different areas, and human intervention is required in area segmentation. There is a limit that the error can be very large. In addition, the existing CNN (Convolutional Neural Networks, CNN) based wafer map analysis method is a method of learning a classifier based on the above-described four types of defect patterns, but in the case of an actual mass-produced wafer, the location, size, and location of defect patterns There is a problem in that it is difficult to shape defect patterns accurately into four because the shapes such as angles are very diverse.

In addition, the existing yield map analysis method defines a pattern for determining the type of wafer failure, and based on this, there is a method of calculating the wafer yield by in-division variance analysis, but the criteria for pattern classification is ambiguous and human intervention and There is a problem that it is difficult to trust the classified results because judgment is required.

In the present embodiment, the wafer map is an image that includes a noise signal, a situation in which sufficient data for feature learning is not secured, and the mass production characteristics are mostly good and few defect patterns are recognized. The purpose is to provide an analysis method for situations in which expert labeling is difficult due to the difficulty in standardizing the situation and defect patterns.

According to an aspect of the present embodiment, a wafer map generation unit that generates a wafer map corresponding to each of the wafers to be inspected using specific test results for chips present on a plurality of wafers to be inspected. ; A pre-processing unit generating a pre-processed wafer map by removing a noise pattern included in the wafer map; A first clustering unit to classify a defect suspect wafer map by performing primary clustering on the preprocessed wafer map; A feature extraction unit for extracting feature information for recognizing defect pattern information from the defect suspect wafer map and generating a feature extraction wafer map; And a second clustering unit to classify a defect wafer map by performing secondary clustering on the feature extraction wafer map.

According to another aspect of the present embodiment, a wafer map generation process of generating a wafer map corresponding to each of the wafers to be inspected by using specific test results for chips present on a plurality of wafers to be inspected ; A pre-processing process of generating a pre-processed wafer map by removing a noise pattern included in the wafer map; A first clustering process of classifying a defect suspect wafer map by performing primary clustering on the preprocessed wafer map; A feature extraction process of extracting feature information for recognizing defect pattern information from the defect suspect wafer map and generating a feature extraction wafer map; And a second clustering process of classifying defect wafer maps by performing secondary clustering on the feature extraction wafer maps.

As described above, according to the present embodiment, the wafer map is an image including a noise signal, a situation in which sufficient data for feature learning is not secured, and most of the mass production is good. It has an effect of providing an analysis method for situations in which a small number of defect patterns need to be recognized, and difficult for human labeling due to difficulty in standardizing defect patterns.

In addition, according to the present embodiment, in a situation in which it is difficult to apply deep learning that requires a large amount of labels, unsupervised learning secures a meaningful defect pattern of the wafer and gives it based on this. There is an effect of improving defect recognition performance by semi-supervised learning.

1 is a block diagram schematically showing a wafer map defect pattern recognition apparatus according to the present embodiment.
2 is a block diagram schematically showing a pre-processing unit of the wafer map defect pattern recognition apparatus according to the present embodiment.
3 is a diagram for explaining a process of generating a pre-processed wafer map of the pre-processing unit.
4 is a view for explaining a process of generating a feature extraction wafer map in the feature extraction unit.
5 is a flowchart illustrating a method of recognizing a wafer map defect pattern according to the present embodiment.
6 is a flowchart illustrating a process of generating a pre-processed wafer map in the pre-processing unit.

Hereinafter, this embodiment will be described in detail with reference to the accompanying drawings. In describing the components of the present invention, terms such as primary and secondary may be used. These terms are only for distinguishing the component from other components, and the nature, order, or order of the component is not limited by the term.

EDS (Electrical Die Sorting, EDS) test, which is one of the semiconductor manufacturing processes, is a process of inspecting the electrical operation of each semiconductor chip formed on a wafer to select defective products. Engineers acquire wafer maps as a result of EDS testing.

In the wafer map, the types of defects for each die can be divided into categorical defects and parametric defects. Categorical defects may be represented in the form of BIN data defining quantity/defect information for each chip in a semiconductor wafer. For example, the BIN data may be data defining a good die for BIN 1, a short fail for BIN 2, and an open fail for BIN 3. Parametric defects can be determined based on data values of items that do not satisfy the reference value among the characteristics of each die in the semiconductor wafer. For example, characteristics that the die may have include a reference voltage (Vref) and a threshold voltage (Vt).

The defect pattern of the wafer map can be divided into four types. In more detail, the defect pattern of the wafer map may be divided into circular, partially annular, scratched, and area-shaped. Circular defect patterns are caused by uniformity problems in the chemical mechanical planarization (CMP) stage. Partial annular defect patterns are caused by misalignment between layers, scratch-type defect patterns are caused by particle aggregation or pad hardening, and area-type defect patterns are caused by cleansing problems, respectively.

The wafer map defect pattern recognition apparatus 100 according to the present exemplary embodiment may distinguish a defect pattern of a wafer map when deep learning cannot be performed because a large amount of label data cannot be obtained. It is not limited to such a case, and can be used even when deep learning can be performed.

1 is a block diagram schematically showing a wafer map defect pattern recognition apparatus according to the present embodiment.

Referring to FIG. 1, the wafer map defect pattern recognition apparatus 100 according to the present embodiment includes a wafer map generation unit 110, a pre-processing unit 120, a first clustering unit 130, a feature extraction unit 140, and It includes a second clustering unit 150. The components included in the wafer map defect pattern recognition apparatus 100 are not necessarily limited thereto.

The wafer map generation unit 110 generates at least one wafer map based on a plurality of wafers to be inspected. The wafer map includes defect presence information and defect type information for each die. More specifically, the wafer map includes defect type information for each die in the case of categorical defects, and information in which actual data values of items that do not satisfy a reference value are visualized in case of parametric defects. Meanwhile, the wafer map may be generated as binary image information, but is not limited thereto.

The wafer map generator 110 generates a wafer map corresponding to each wafer to be inspected by using specific test results for chips present on a plurality of wafers to be inspected. Here, the specific test means a variety of good quality tests for each chip, such as a read/write test and a constant temperature and humidity test. The wafer map generation unit 110 generates a wafer map by considering a result of performing a specific test as a binary image.

The pre-processing unit 120 removes a noise pattern included in the wafer map to generate a pre-processed wafer map. A noise pattern is sporadically generated in the wafer map generated by the wafer map generator 110. Therefore, the pre-processing unit 120 removes the noise pattern sporadically to generate a pre-processed wafer map, and the generated pre-processed wafer map is transmitted to the first clustering unit 130. The pre-processing unit 120 will be described later with reference to FIGS. 2 and 3.

The first clustering unit 130 performs primary clustering on the pre-processed wafer map based on a novelty detection algorithm to classify the pre-processed wafer map into a normal wafer map or a suspected defect wafer map. The wafer to be inspected corresponding to the normal wafer map is classified as a good product wafer, and the defect suspect wafer map is transmitted to the feature extraction unit 140 to be described later.

The wafer to be inspected, which is the object of the wafer map defect pattern recognition apparatus 100 according to the present embodiment, is composed of a majority of good quality wafers and a small number of defect wafers. Accordingly, the first clustering unit 130 may improve the clustering quality and the calculation speed of the actual defect pattern by first selecting a good quality wafer that occupies most of the wafers to be inspected as primary clustering. Meanwhile, the first clustering unit 130 may define a ratio of defect patterns existing in the pre-processed wafer map as a removal ratio parameter.

The first clustering unit 130 may use an OC-SVM (One-Class Support Vector Machine), Isolation Forest, Robust Covariance or Local Outlier Factor as an outlier detection algorithm, but is not limited thereto, and is out of the normal range Any algorithm that can detect data should be interpreted as being available.

The first clustering unit 130 checks whether good product labeling exists in the pre-processed wafer map. The first clustering unit 130 checks the number of defective dies in the pre-processed wafer map when it is determined that good quality labeling is present. The first clustering unit 130 compares the threshold value preset by the user with the number of bad dies. When the number of defective dies exceeds a threshold value, the first clustering unit 130 may quantitatively determine that the performance of the wafer to be inspected is not good.

The first clustering unit 130 transmits a defect suspect wafer map to a control unit (not shown) according to the number of labeled data for performing feature learning. When the number of labeled data is greater than or equal to a preset threshold, the controller transmits a defect doubt wafer map to a machine learning model unit (not shown) to classify a defect pattern based on deep learning, and when the number of labeled data is less than a threshold, the defect doubt wafer map It is transmitted to the feature extraction unit 140.

The feature extracting unit 140 receives the defect suspect wafer map classified by the first clustering unit 130. The feature extraction unit 140 extracts feature information for recognizing defect pattern information from the defect suspect wafer map and generates a feature extraction wafer map. The feature extraction wafer map will be described later with reference to FIG. 4.

The feature extraction unit 140 may use an edge detector to extract feature information. Here, the feature extraction unit 140 is an edge detector, in addition to a Canny Edge Detector, a Sobel Edge Detector, and a Roberts Edge Detector, as well as a Hog Feature Descriptor and a Dog Feature You can use the DOG Feature Descriptor. In addition, the feature extraction unit 140 may use an LM filter bank (Leung-Malik Filter Bank), a Schmid filter bank (Schmid Filter Bank), an MR filter bank (Maximum Response Filter Bank), or the like.

The second clustering unit 150 performs secondary clustering on the feature extraction wafer map and classifies it into a normal wafer map or a defective wafer map. More specifically, the second clustering unit 150 separates the same defect pattern information by performing secondary clustering based on the defect pattern information of the feature extraction wafer map. Accordingly, the user can ultimately recognize defect pattern information of the wafer map even in situations in which labeled data based on primary clustering, feature extraction, and secondary clustering is not sufficiently secured.

If the label of the defect wafer map is present, the second clustering unit 150 corresponds to the defect wafer map using an adjusted land index (ARI), normalized mutual information (NMI), or the like. The performance of the defective wafer can be quantitatively confirmed. On the other hand, if the label of the defect wafer map does not exist, the second clustering unit 150 may use it as an indirect indicator for confirming the performance of the defect wafer using a silhouette coefficient.

The second clustering unit 150 preferably uses a hierarchical clustering technique, but is not limited thereto.

The wafer map defect pattern recognition apparatus 100 may be equipped with a wafer map defect pattern recognition program on a separate hardware to provide a wafer map defect pattern recognition service to a user. The wafer map defect pattern recognition program means a program installed in a computer when the wafer map defect pattern recognition apparatus 100 is a computer. The wafer map defect pattern recognition apparatus 100 drives a wafer map defect pattern recognition program by a user's operation or command.

The wafer map defect pattern recognition program may be stored in a computer-readable recording medium to provide a wafer map defect pattern recognition service. Here, the computer-readable recording medium includes all kinds of recording devices that store data that can be read by a computer system. That is, the computer-readable recording medium includes magnetic storage media (eg, ROM, floppy disk, hard disk, etc.), optical reading media (eg, CD-ROM, DVD, etc.) and carrier waves (eg, the Internet). Storage). In addition, the computer-readable recording medium may be distributed over network-connected computer systems so that the computer-readable code is stored and executed in a distributed manner.

2 is a block diagram schematically showing a pre-processing unit of the wafer map defect pattern recognition apparatus according to the present embodiment.

Referring to FIG. 2, the pre-processing unit 120 includes a Laplacian filter unit 210, a downsampling unit 220, and a local average filter unit 230. The components included in the pre-processing unit 120 are not necessarily limited thereto.

Since the wafer map generated by the wafer map generator 110 is binary image information having the same signal and noise level of 1, the defect pattern boundary becomes unclear when a general filter in the image processing field is used. do. Therefore, the Laplacian filter unit 210 removes a high-frequency component by using a Laplacian filter to suppress the global and randomly scattered noise patterns, thereby extracting the primary processed wafer map. To create.

The down-sampling unit 220 performs down-sampling by a preset number of times on the primary processing wafer map to prevent a curse of dimensionality in performing the primary clustering, and the secondary processing wafer Create a map. In this embodiment, twice downsampling is performed, but the present invention is not limited to this, and can be freely set by the user.

The local average filter 230 removes a noise pattern based on a local mean filter to finally generate a preprocessed wafer map.

3 is a diagram for explaining a process of generating a preprocessed wafer map of the preprocessing unit.

Referring to FIG. 3, the Laplacian filter unit 210 receives the wafer map generated by the wafer map generation unit.

The Laplacian filter unit 210 separates the high-frequency component and the low-frequency component from the wafer map, and generates a primary processed wafer map in which only the low-frequency component remains because the high-frequency component is removed.

The downsampling unit 220 receives the primary processing wafer map, and performs downsampling by a preset number of times by the user to generate a secondary processing wafer map.

The local average filter unit 230 generates a pre-processed wafer map by removing noise patterns from the secondary processed wafer map. This series of processes can be repeatedly performed until the noise pattern is completely removed.

The filter used in the pre-processing unit 120 is not necessarily limited to this, and the user can apply or place the filter used during the pre-processing according to the type of the wafer map.

4 is a view for explaining a process of generating a feature extraction wafer map in the feature extraction unit.

The feature extraction unit 140 receives the defect suspicion wafer map from the first clustering unit 130. Referring to FIG. 3, the feature extraction unit 140 generates feature extraction wafer maps by extracting features from a suspected defect wafer map based on a Canny edge detector, a Sobel edge detector, and a Roberts edge detector. The feature extraction wafer map may be generated by F1 to Fn according to the type and number of detectors used. That is, the feature extracting unit 140 extracts the feature of the defect suspicious wafer map to generate a feature extraction wafer map when the labeled data for performing feature learning is not secured by deep learning, and generates the feature extraction wafer map. It supports to perform secondary clustering based.

5 is a flowchart illustrating a method of recognizing a wafer map defect pattern according to the present embodiment.

Referring to FIG. 5, the wafer map defect pattern recognition apparatus 100 generates a wafer map including defect information for each die based on a semiconductor test process result (S502). Wafer map is binary image information with defect information corresponding to 0 and 1, respectively. If a filter commonly used in the image processing field is used, the boundary of the pattern becomes unclear, so it is necessary to perform a process of preprocessing the wafer map. have.

The wafer map defect pattern recognition apparatus 100 generates a pre-processed wafer map through a pre-processing process of removing noise patterns from the generated wafer map (S504). The pre-treatment wafer map pre-treatment process will be described later with reference to FIG. 6.

The wafer map defect pattern recognition apparatus 100 performs primary clustering for classifying good quality wafers based on a pre-processed wafer map (S506). For example, the wafer map defect pattern recognition apparatus 100 distinguishes a good-quality wafer, that is, a wafer having 0 for each die, from a pre-processed wafer map suppressed through a pre-processing process.

The wafer map defect pattern recognition apparatus 100 compares the number of defective dies with a preset threshold value by a user when a label of a good-quality wafer is given to the pre-processed wafer map. When the number of defective dies exceeds a threshold value, the wafer map defect pattern recognition apparatus 100 may quantitatively determine that the performance of the wafer to be inspected is poor.

The wafer map defect pattern recognition apparatus 100 determines whether there is more than a predetermined number of label data (S508). The wafer map defect pattern recognition apparatus 100 recognizes a defect pattern by performing feature learning based on deep learning when there is more than a predetermined number of label data (S512).

The wafer map defect pattern recognition apparatus 100 generates feature extraction wafer maps by extracting feature information for the defect suspect wafer map when there is no preset number of label data or more (S510 ). The wafer map defect pattern recognition apparatus 100 may generate a feature extraction wafer map based on a Canny edge detector, a Sobel edge detector, or the like.

The wafer map defect pattern recognition apparatus 100 finally classifies the defect wafer map by performing secondary clustering, that is, hierarchical clustering, on the feature extraction wafer map (S514 ).

Although FIG. 5 describes that steps S502 to S514 are executed sequentially, the present invention is not limited thereto. In other words, since the steps described in FIG. 5 may be changed and executed or one or more steps may be executed in parallel, FIG. 5 is not limited to the time series order.

6 is a flowchart illustrating a process of generating a pre-processed wafer map in the pre-processing unit.

Referring to FIG. 6, the pre-processing unit 120 of the wafer map defect pattern recognition apparatus 100 removes the high-frequency component of the wafer map generated by the wafer map generation unit 110 to generate a primary processed wafer map (S602). ). The primary processed wafer map is preferably removed by using a Laplacian filter, but is not limited thereto.

The pre-processing unit 120 performs downsampling by a preset multiple of the primary processed wafer map to generate a secondary processed wafer map (S604). In more detail, the pre-processor 120 performs downsampling to prevent dimensional curse from occurring when clustering is performed. The pre-processing unit 120 may allow the user to arbitrarily adjust the downsampling multiple so as to distinguish the pattern of the primary processing wafer map.

The pre-processing unit 120 removes the noise pattern of the secondary processed wafer map to finally generate a pre-processed wafer map (S606). The pre-processing unit 120 preferably removes a noise pattern by applying a local average filter on a secondary processed wafer map whose size is reduced due to downsampling, but is not limited thereto.

The pre-processing unit 120 transmits the pre-processed wafer map to the first clustering unit 130 (S608).

In FIG. 6, steps S602 to S608 are sequentially executed, but the present invention is not limited thereto. In other words, since the steps described in FIG. 6 may be changed and executed or one or more steps may be executed in parallel, FIG. 6 is not limited to the time series order.

The above description is merely illustrative of the technical idea of the present embodiment, and those skilled in the art to which this embodiment belongs may be capable of various modifications and variations without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical spirit of the present embodiment, but to explain, and the scope of the technical spirit of the present embodiment is not limited by these embodiments. The protection scope of the present embodiment should be interpreted by the claims below, and all technical spirits within the equivalent range should be interpreted as being included in the scope of the present embodiment.

100: wafer map defect pattern recognition device 110: wafer map generation unit
120: pre-processing unit 130: first clustering unit
140: feature extraction unit 150: second clustering unit
210: Laplacian filter unit 220: Downsampling unit
230: local average filter unit

Claims (9)

A wafer map generator configured to generate a wafer map corresponding to each of the wafers to be inspected by using specific test results for chips present on a plurality of wafers to be inspected;
A pre-processing unit generating a pre-processed wafer map by removing a noise pattern included in the wafer map;
A first clustering unit to classify a defect suspect wafer map by performing primary clustering on the preprocessed wafer map;
A feature extraction unit for extracting feature information for recognizing defect pattern information from the defect suspect wafer map and generating a feature extraction wafer map; And
A second clustering unit that classifies a defect wafer map by performing secondary clustering on the feature extraction wafer map
Wafer map defect pattern recognition apparatus comprising a. According to claim 1,
The pre-processing unit,
A Laplacian filter unit for generating a primary processed wafer map by removing high-frequency components of the wafer map;
A down-sampling unit for generating a secondary-processed wafer map by down-sampling at a preset multiple in the primary-processed wafer map; And
A local average filter unit for generating the pre-processed wafer map by removing the noise pattern of the secondary processed wafer map
Wafer map defect pattern recognition apparatus comprising a. According to claim 1,
The first clustering unit,
Wafer map defect pattern recognition apparatus characterized in that it is checked whether there is a good labeling (Labeling) in the pre-processed wafer map based on the Novelty Detection Algorithm (Novelty Detection Algorithm). According to claim 1,
The second clustering unit,
Wafer map defect pattern recognition apparatus characterized in that the defect pattern information is classified into a circular, partially annular, scratched, and area type and clustered. According to claim 2,
The feature extraction unit,
Wafer map defect pattern recognition apparatus characterized by generating the feature extraction wafer map by extracting the feature information based on an edge detector. The method of claim 3,
The first clustering unit,
When it is determined that the good labeling is present, quantitatively determining the performance of the wafer to be inspected corresponding to the pre-processed wafer map according to a result of comparing the number of defective dies present in the processed wafer map with a preset threshold value. Wafer map defect pattern recognition device, characterized in that. According to claim 1,
The wafer map,
Wafer map defect pattern recognition apparatus, characterized in that the binary image information including defect presence information and defect type information for each die (Die) of the wafer to be inspected. A wafer map generation process of generating a wafer map corresponding to each of the wafers to be inspected by using specific test results for chips present on a plurality of wafers to be inspected;
A pre-processing process of generating a pre-processed wafer map by removing a noise pattern included in the wafer map;
A first clustering process of classifying a defect suspect wafer map by performing primary clustering on the preprocessed wafer map;
A feature extraction process of extracting feature information for recognizing defect pattern information from the defect suspect wafer map and generating a feature extraction wafer map; And
A second clustering process of classifying a defect wafer map by performing secondary clustering on the feature extraction wafer map
Wafer map defect pattern recognition method comprising a. Wafer map defect pattern recognition program is combined with hardware,
A wafer map generation process of generating a wafer map corresponding to each of the wafers to be inspected by using specific test results for chips present on a plurality of wafers to be inspected;
A pre-processing process of generating a pre-processed wafer map by removing a noise pattern included in the wafer map;
A first clustering process of classifying a defect suspect wafer map by performing primary clustering on the preprocessed wafer map;
A feature extraction process of extracting feature information for recognizing defect pattern information from the defect suspect wafer map and generating a feature extraction wafer map; And
A second clustering process of classifying a defect wafer map by performing secondary clustering on the feature extraction wafer map
Wafer map defect pattern recognition program stored in the recording medium to execute the.

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