KR20200085243A - Semiconductor memory device and method of fabricating the same - Google Patents

Abstract

Provided is a semiconductor memory device with improved product reliability. The semiconductor memory device comprises: a first laminated structure in which a plurality of first conductive films are stacked on a substrate; a second laminated structure in which a plurality of second conductive films are laminated on the first laminated structure; a first channel structure penetrating the first laminated structure and the second laminated structure, and including a channel film; and a sacrificial channel structure penetrating the first laminated structure, not penetrating the second laminated structure, and including a metal layer, wherein the first laminated structure includes first and second areas different from each other, the first channel structure is disposed in the first area, and the sacrificial channel structure is disposed in the second area.

Description

Semiconductor memory device and manufacturing method therefor{SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a semiconductor memory device and a method for manufacturing the same.

In order to satisfy the excellent performance and low price required by consumers, the degree of integration of semiconductor memory devices is increasing. In the case of a two-dimensional or planar semiconductor memory device, the degree of integration is determined by the area occupied by the unit memory cells. Accordingly, recently, a three-dimensional semiconductor memory device in which unit memory cells are vertically arranged has been developed.

In addition, in order to improve the degree of integration of semiconductor devices, the number of word lines stacked vertically in the semiconductor memory device is increasing. Accordingly, research is being conducted on a multi-stack structure stacking a plurality of stack structures.

The technical problem to be solved by the present invention is to provide a semiconductor memory device with improved product reliability.

Another technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor memory device capable of manufacturing a semiconductor memory device with improved product reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem, a first stacked structure on which a plurality of first conductive films are stacked on a substrate, and a plurality of second conductors on a first stacked structure The second stacked structure, the first stacked structure and the second stacked structure, in which the film is stacked, penetrates the first channel structure including the channel film, and penetrates the first stacked structure and penetrates the second stacked structure, but not through the metal layer. It includes a sacrificial channel structure, the first stacked structure includes different first and second regions, the first channel structure is disposed in the first region, and the sacrificial channel structure is disposed in the second region.

A method of manufacturing a semiconductor memory device in accordance with some embodiments of the present invention for achieving the above technical problem, a first insulating film and a first sacrificial film alternately stacked on the first stacked structure, the first through the first stacked structure A channel hole is formed and a sacrificial channel structure including a metal layer and a channel sacrificial layer surrounding the metal layer is formed in the first channel hole, wherein the top surface of the metal layer is disposed on the same plane as the top surface of the channel sacrificial layer, and the first stacked structure A second stacked structure in which a second insulating film and a second sacrificial film are alternately stacked is formed on the second channel hole, and a second channel hole passing through the second stacked structure is formed on the sacrificial channel structure. Forming a channel structure filling the two channel holes, forming a first trench spaced apart from the channel structure, penetrating the first and second stacked structures, and the first sacrificial film and the second exposed by the first trench And removing the sacrificial film to form a second trench, and forming a conductive film in the second trench.

Specific details of other embodiments are included in the detailed description and drawings.

1 is an exemplary circuit diagram for describing a semiconductor memory device in accordance with some embodiments of the present invention.
2 is a plan view illustrating one of a plurality of stacked structures included in a semiconductor memory device according to some embodiments of the present invention.
3 is a cross-sectional view taken along line A-A' of FIG. 2.
4 is an enlarged view of region S of FIG. 3.
5 is a cross-sectional view taken along line B-B' of FIG. 2.
6 is a cross-sectional view taken along line A-A' of FIG. 2.
7 is a cross-sectional view taken along line A-A' of FIG. 2.
8 is a cross-sectional view taken along line A-A' of FIG. 2.
9 to 15 are intermediate stage diagrams for describing a semiconductor memory device in accordance with some embodiments of the present invention.
16 is an intermediate step diagram illustrating a semiconductor memory device in accordance with some other embodiments of the present invention.
17 is an intermediate step diagram illustrating a semiconductor memory device in accordance with some other embodiments of the present invention.

1 is an exemplary circuit diagram for describing a semiconductor memory device in accordance with some embodiments of the present invention.

Referring to FIG. 1, a memory cell array of a semiconductor memory device according to some embodiments of the present invention includes a common source line (CSL), a stacked structure (ST), a plurality of bit lines (BL), and a plurality of cell strings (CSTR).

The stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 disposed on the first stacked structure ST1. The first stacked structure ST1 may include a ground selection line GSL and a plurality of lower word lines WL11 to WL1n and DWL1. The second stacked structure ST2 may include a plurality of upper word lines DWL2, WL21 to WL2n, and a string selection line SSL. Although two stacked structures ST1 and ST2 are shown in this figure, the present invention is not limited thereto, and may include three or more stacked structures.

A plurality of cell strings CSTR may be connected to each of the bit lines BL in parallel. The plurality of cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and one common source line CSL. The plurality of common source lines CSL may be arranged two-dimensionally. The same voltage may be applied to the common source lines CSL or may be controlled separately by applying different voltages.

Each cell string CSTR includes, for example, a ground select transistor GST connected to a common source line CSL, a string select transistor SST connected to each of a plurality of bit lines BL, and ground. A plurality of memory cell transistors MCT disposed between the selection transistor GST and the string selection transistor SST may be included. That is, the ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series. Each of the memory cell transistors MTC may include a data storage element.

In addition, each cell string CSTR may further include dummy cell transistors DMCT1 and DMCT2 connected between the string select transistor SST and the memory cell transistor MCT. Although not shown in the figure, the dummy cell transistors DMCT1 and DMCT2 may be connected between the ground select transistor GST and the memory cell transistor MCT. In addition, a gate induced drain leakage (GIDL) transistor connected between the common source line CSL and the ground selection line GSL may be further included.

The common source line CSL may be commonly connected to the sources of the ground selection transistors GST. Further, a plurality of gate electrodes (eg, a ground selection line GSL), a plurality of word lines WL1-WLn, and a string selection line between each of the common source line CSL and the bit lines BL. (SSL)).

The ground select line GSL may be used as the gate electrode of the ground select transistor GST, and the plurality of word lines WL11-WL1n, DWL1, DLW2, WL21-WL2n may be gate electrodes of the memory cell transistors MCT. The string select line SSL may be used as a gate electrode of the string select transistor SST.

2 is a plan view illustrating one of a plurality of stacked structures included in a semiconductor memory device according to some embodiments of the present invention. 3 is a cross-sectional view taken along line A-A' of FIG. 2. 4 is an enlarged view of region S of FIG. 3. 5 is a cross-sectional view taken along line B-B' of FIG. 2.

2 to 5, a semiconductor memory device according to some embodiments of the present invention includes a substrate 100, a common source plate 110, a supporting semiconductor layer 120, a stacked structure (ST), and a sacrificial channel structure (SCS), channel structures CS1 and CS2, and bit lines 193.

The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or other materials, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimony, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide, or It may include gallium antimony, but is not limited thereto.

The common source plate 110 may be disposed on the substrate 100. The common source plate 110 may serve as the common source line CSL of FIG. 1.

The common source plate 110 may include at least one of a conductive semiconductor film, a metal silicide film, and a metal film. When the common source plate 110 includes a conductive semiconductor film, the common source plate 110 is, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium Arsenic (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof. The common source plate 110 may have a crystal structure including at least one selected from single crystal, amorphous and polycrystalline. The common source plate 110 may include at least one of p-type impurities, n-type impurities, and carbon included in the semiconductor film.

The stacked structure ST may be disposed on the common source plate 110. The stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 disposed on the first stacked structure ST1. The stacked structure ST extends in the second direction DR2 from the cell region CR, the first cell contact region CNR1 extending from the cell region CR in the first direction DR2, and the cell region CR from the cell region CR. It may include a second cell contact area (CNR2).

The first stacked structure ST1 may include a plurality of first conductive films GSL, WL11-WL1n, and DWL1 stacked in the third direction DR3 and a plurality of first insulating films 132. The plurality of first conductive films GSL, WL11-WL1n, and DWL1 and the plurality of first insulating films 132 may be alternately stacked in the third direction DR3. The plurality of first conductive layers GSL, WL11-WL1n, and DWL1 may include a ground selection line GSL, a plurality of first word lines WL11-WL1n, and a first dummy word line DWL1. The ground selection line GSL, the plurality of first word lines WL11 to WL1n, and the first dummy word line DWL1 may be sequentially stacked on the substrate 100.

The second stacked structure ST2 may be disposed on the first insulating layer 132 disposed on the top of the plurality of first insulating layers 132. The first insulating layer 132 disposed on the top of the plurality of first insulating layers 132 may cover the stepped first conductive layers GSL, WL11-WL1n, and DWL1. The thickness of the first insulating layer 132 disposed on the top of the plurality of first insulating layers 132 may be thicker than the thickness of other first insulating layers 132.

The second stacked structure ST2 may include a plurality of second conductive films DWL2, WL21-WL2n, and SSL stacked in the third direction DR3 and a plurality of second insulating films 162. The plurality of second conductive films DWL2, WL21-WL2n, and SSL, and the plurality of second insulating films 162 may be alternately stacked in the third direction DR3. The plurality of second conductive layers DWL2, WL21-WL2n, and SSL may include a second dummy word line DWL2, a plurality of second word lines WL21-WL2n, and a string selection line SSL. The second dummy word line DWL2, the plurality of second word lines WL21-WL2n and the string selection line SSL may be sequentially stacked on the substrate 100.

Although one first dummy word line DWL1 and one second dummy word line DWL2 are illustrated in the drawing, the present invention is not limited thereto, and may further include a plurality of dummy word lines. Alternatively, when the cell string CSTR of FIG. 1 does not include the dummy cell transistors DMCT1 and DMCT2, the first and second dummy word lines DWL1 and DWL2 are the first and second word lines WL11 to WL1n, WL21-WL2n).

The first and second conductive films (GSL, WL11-WL1n, DWL1, DWL2, WL21-WL2n, SSL) may include metals such as tungsten (W), cobalt (Co), nickel (Ni), for example. However, the type of metal is not limited thereto. In the drawings, the first and second conductive films (GSL, WL1 -WL1n, DWL1, DWL2, WL21-WL2n, and SSL) are shown as being formed as a single film, but are for convenience of description and are not limited thereto. . The metallic lines (GSL, WL ₀ -WL _n , DWL) may further include a barrier conductive layer. The barrier conductive layer may include at least one of metal, metal nitride, metal carbonitride, and two-dimensional (2D) material. For example, the two-dimensional material can be a metallic material and/or a semiconducting material. The 2D material may include a 2D allotrope or a 2D compound.

The first and second conductive layers GSL, WL11-WL1n, DWL1, DWL2, WL21-WL2n, and SSL may be stacked in a stepwise fashion. The first and second conductive layers GSL, WL11-WL1n, DWL1, DWL2, WL21-WL2n, and SSL may be stacked in a stepwise manner in the first direction DR2 and the second direction DR2.

The first and second insulating layers 132 and 162 are, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), FOX (Flowable Oxide), TOSZ (Tonen SilaZene), USG ( Undoped Silica Glass (BSG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), BoroPhosphoSilica Glass (PSG), Plasma Enhanced Tetra Ethyl Ortho Silicate (PETEOS), Fluoride Silicate Glass (FSG), Carbon Doped Silicon Oxide (CDO), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, or a combination thereof, but the technical idea of the present invention is not limited thereto. .

As shown in the figure, the first and second conductive layers (GSL, WL11-WL1n, DWL1, DWL2, WL21-WL2n, SSL) and the sacrificial channel structure (SCS), the first and second information storage patterns 170, A horizontal insulation pattern may be further disposed between 180). The horizontal insulating pattern may include, for example, silicon oxide or a high-k material (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )).

The stacked structure ST may include an electrode separation region ESR. The electrode separation area ESR may extend in the second direction DR2. The length of at least a portion of the electrode separation region ESR in the second direction DR2 may be smaller than the width of the stacked structure ST in the second direction DR2. For example, the electrode separation area ESR may separate the cell area CR in the first direction DR1.

The electrode isolation region ESR may pass through the first and second interlayer insulating layers 166 and 186, the stacked structure ST, and the supporting semiconductor layer 120. The electrode separation region ESR extends in the third direction DR3 to cut the stacked structure ST and the supporting semiconductor layer 120. The first trench T1 may cut the first and second conductive layers GSL, WL11-WL1n, DWL1, DWL2, WL21-WL2n, SSL, and the first and second insulating layers 132 and 162.

The electrode separation region ESR may fill the first trench T1. The electrode separation region ESR may include, for example, an insulating material filling the first trench T1. The electrode separation region ESR may include, for example, silicon oxide.

Alternatively, as illustrated, the electrode separation area ESR may include a liner formed along a sidewall of the first trench T1 and a peeling film on the liner filling the first trench T1. For example, the liner can include an insulating material, and the peeling film can include a conductive material. Alternatively, the liner may include a conductive material, and the peeling film may include an insulating material.

Referring to FIG. 3, the cell region CR may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be regions adjacent to each other or regions separated from each other. The positions of the first region R1 and the second region R2 are not limited except that the first region R1 and the second region R2 are formed on the cell region CR.

The first area R1 may mean an area other than the second area R2. The second region R2 may be a region defined as needed. The second area R2 may mean, for example, a guide area for alignment of the channel structures CS1 and CS2 to be described later.

The first and second stacked structures ST1 and ST2 of the first region R1 may include the first channel structure CS1.

The first channel structure CS1 may penetrate the first interlayer insulating layer 166 and the first and second stacked structures ST1 and ST2. The first channel structure CS1 may extend in the third direction DR3. The first channel structure CS1 may fill the first and third channel holes CH1 and CH3.

The first channel structure CS1 may include a first information storage pattern 170, a first channel layer 174, a first channel filling layer 175, and a bit line pad 177.

The first information storage pattern 170 may be disposed on the first and third channel holes CH1 and CH3. The first information storage pattern 170 may extend along side and bottom surfaces of the first and third channel holes CH1 and CH3.

The first information storage pattern 170 may include, for example, at least one of a high dielectric constant material having a higher dielectric constant than silicon oxide, silicon nitride, silicon oxynitride, and silicon oxide. The high dielectric constant materials include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, and lanthanum hafnium oxide. oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

Alternatively, the first information storage pattern 170 may include a plurality of films. For example, as illustrated in FIG. 4, the first information storage pattern 170 is a blocking insulating layer 171 and a charge storage layer 172 that are sequentially stacked on the first and third channel holes CH1 and CH3. And the tunnel insulating layer 173 may be sequentially arranged.

The blocking insulating layer 171 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). The charge storage layer 172 may include, for example, silicon nitride. The tunnel insulating layer 173 may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )).

The first channel layer 174 may be disposed on the first information storage pattern 170. The first channel layer 174 may extend along side surfaces and bottom surfaces of the first information storage pattern 170. The first channel layer 174 may be connected to the common source plate 110. For example, the first channel layer 174 used as a channel region of the memory cell among the first channel layers 174 may be electrically connected to the common source plate 110.

The first channel layer 174 may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. Alternatively, the first channel layer 174 may include a metal oxide semiconductor material.

The first channel filling layer 175 may be disposed on the first channel layer 174. The first channel filling layer 175 may extend along side surfaces and bottom surfaces of the first channel layer 174. The first channel filling layer 175 may fill the first and third channel holes CH1 and CH3. The first channel filling layer 175 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The bit line pad 177 may be disposed on the first channel filling layer 175. The bit line pad 177 may include a conductive material. The bit line pad 177 may include, for example, a semiconductor material doped with n-type impurities.

Meanwhile, the blocking insulating layer 171, the charge storage layer 172, and the tunnel insulating layer 173 may be separated under the first channel structure CS1. The support semiconductor layer 120 may be disposed between the separated blocking insulating layer 171, the charge storage layer 172, and the tunnel insulating layer 173. The support semiconductor layer 120 may electrically connect the common source plate 110 and the first channel layer 174. The support semiconductor layer 120 may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof.

Alternatively, as shown in the figure, when the supporting semiconductor layer 120 is not disposed, the blocking insulating layer 171, the charge storage layer 172, and the tunnel insulating layer 173 are bottom surfaces of the first channel structure CS1. Can be separated from. That is, the sidewalls of the first channel layer 174 are not exposed, and the bottom surface of the first channel layer 174 may be exposed. The first channel layer 174 may be electrically connected to the common source plate 110 through the bottom surface of the exposed first channel layer 174.

The first and second stacked structures ST1 and ST2 of the second region R2 may include the sacrificial channel structure SCS and the second channel structure CS2.

The sacrificial channel structure SCS may penetrate the first stacked structure ST1. The sacrificial channel structure SCS may extend in the third direction DR3. The sacrificial channel structure SCS may fill the second channel hole CH2.

The sacrificial channel structure CSC may include a first channel sacrificial layer 141, a second channel sacrificial layer 143, an adhesive layer 151 and a metal layer 153.

The first channel sacrificial layer 141 may be disposed in the second channel hole CH2. The first channel sacrificial layer 141 may fill at least a portion of the second channel hole CH2. The second channel sacrificial layer 143 may be disposed on the first channel sacrificial layer 141. The second channel sacrificial layer 143 may be conformally formed along the side surface of the second channel hole CH2 and the top surface of the first channel sacrificial layer 141.

The second channel sacrificial layer 143 may include, for example, the same material as the first channel sacrificial layer 141. The first and second channel sacrificial layers 141 and 143 may include, for example, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

The adhesive layer 151 may be formed along the profile of the second channel sacrificial layer 143. The adhesive layer 151 may include, for example, titanium (Ti).

The metal layer 153 may be disposed on the adhesive layer 151. The metal layer 153 may fill the second channel hole CH2. The metal layer 153 may be disposed in the center of the sacrificial channel structure (SCS), for example. The width of the metal layer 153 in the first direction DR1 may be, for example, about 1/3 times the width of the sacrificial channel structure SCS in the first direction DR1. For example, the width of the metal layer 153 in the first direction DR1 may be about 40 nm, and the width of the sacrificial channel structure SCS in the first direction DR1 may be about 120 nm.

The metal layer 153 may include a metal material, for example, tungsten (W).

The second channel structure CS2 may penetrate the first interlayer insulating layer 166 and the second stacked structure ST2. The second channel structure CS2 may extend in the third direction DR3. The second channel structure CS2 may fill the fourth channel hole CH4. The second channel structure CS2 may be disposed on the sacrificial channel structure SCS. A portion of the second channel structure CS2 may be disposed in the upper portion of the sacrificial channel structure SCS.

The second channel structure CS2 may include a second information storage pattern 180, a second channel layer 184, a second channel filling layer 185, and a capping layer 187.

The second information storage pattern 180 may be disposed on the fourth channel hole CH4. The second information storage pattern 180 may extend along side and bottom surfaces of the fourth channel hole CH4. The second information storage pattern 180 is not separated from the first information storage pattern 170 and may be conformally formed on the fourth channel hole CH4. Therefore, the second channel layer 184 may not be electrically connected to the common source plate 110.

The second channel layer 180 may be disposed on the second information storage pattern 180. The second channel layer 180 may extend along side surfaces and bottom surfaces of the second information storage pattern 180. The second channel filling layer 185 may be disposed on the second channel layer 180. The second channel filling layer 185 may fill the fourth channel hole CH4.

In addition, each of the second information storage pattern 180, the second channel film 184, the second channel filling film 185, and the capping film 187 includes a first information storage pattern 170 and a first channel film ( 174), the first channel peeling film 175 and the bit line pad 177 may have similar or identical characteristics.

In addition, referring to FIG. 5, the second cell contact region CNR2 may include a sacrificial channel structure SCS and a second channel structure CS2 on the sacrificial channel structure SCS.

The first interlayer insulating layer 166 may be disposed on the first stacked structure ST1. The first interlayer insulating layer 166 may cover the step portion of the second stacked structure ST2. The second and third interlayer insulating films 186 and 196 may be sequentially disposed on the first interlayer insulating film 166.

The first to third interlayer insulating films 166, 186, and 196 may include, for example, at least one of silicon oxide, silicon oxynitride, and a low dielectric constant material, but are not limited thereto.

The bit line BL may be disposed on the third interlayer insulating layer 196. The bit line BL may be extended in the first direction DR1. The bit line BL may be electrically connected to at least one of the first channel layers 174. The bit line BL may be electrically connected to the bit line pad 177 through the bit line contact 191 penetrating the second and third interlayer insulating layers 186 and 196.

The cell contact 195 may penetrate the first and/or second stacked structure ST2 in the second cell contact region CNR2. The ground selection line GSL, the first and second word lines GSL, WL11-WL1n, and WL21-WL2n, and the string selection line SSL are electrically connected to the word line wiring 197 through the cell contact 195. Can. The first and second dummy word lines DWL1 and DWL2 are connected to the cell contact 195, but may not be connected to the word line wiring 197.

The cell contact 195, the bit line BL, and the word line wiring 197 may include, for example, a conductive material.

6 is a cross-sectional view taken along line A-A' of FIG. 2. For convenience of description, description will be made focusing on differences from those described with reference to FIGS. 2 to 5.

Referring to FIG. 6, in a semiconductor memory device according to some other embodiments of the present invention, a first dummy word line DWL1 may be disposed on the top of the first stacked structure ST1. The second stacked structure ST2 may be disposed on the first dummy word line DWL1. The first conductive layers GSL, WL11-WL1n, and DWL1 and the second conductive layers DWL2, WL21-WL2n, and SSL may be continuously arranged in the third direction DR3.

7 is a cross-sectional view taken along line A-A' of FIG. 2. For convenience of description, description will be made focusing on differences from those described with reference to FIGS. 2 to 5.

Referring to FIG. 7, in a semiconductor memory device according to some other embodiments of the present invention, a center of each of the third and fourth channel holes CH3 and CH4 is a first and second channel hole CH1 and CH2, respectively. May not be aligned with the center of. The center of each of the third and fourth channel holes CH3 and CH4 may be disposed to be offset from the center of each of the first and second channel holes CH1 and CH2, respectively.

The bottom surface CH2_bs of the second channel hole CH2 may be disposed in the sacrificial channel structure SCS. At least a portion of both side walls of the second channel structure CS2 connected to the bottom surface CH2_bs of the second channel hole CH2 may be disposed in the sacrificial channel structure SCS.

8 is a cross-sectional view taken along line A-A' of FIG. 2. For convenience of description, description will be made focusing on differences from those described with reference to FIGS. 2 to 5.

Referring to FIG. 8, a semiconductor memory device according to some other exemplary embodiments of the present invention may include a peripheral logic structure PS and a cell array structure CS.

The peripheral logic structure PS may include a peripheral circuit PTR, a lower connection wiring body PW, and a peripheral logic insulating layer 101.

The peripheral circuit PTR may be formed on the substrate 100. The peripheral circuit PTR may be circuits operating the cell array structure CS.

The peripheral logic insulating layer 101 may be formed on the substrate 100. The peripheral logic insulating layer 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials.

The lower connection wiring body 102 may be formed in the peripheral logic insulating layer 101. The lower connection wiring body 102 may be connected to the peripheral circuit PTR.

The cell array structure CS may be disposed on the peripheral logic structure PS. The cell array structure CS may include first and second stacked structures ST1 and ST2, an electrode separation area ESR, and a bit line BL.

The common source plate 110 may extend along the upper surface of the peripheral logic structure PS.

9 to 15 are intermediate stage diagrams for describing a semiconductor memory device in accordance with some embodiments of the present invention.

Referring to FIG. 9, a common source plate 110 and a free supporting semiconductor layer 120a may be formed on the substrate 100.

A first pre-stacked structure ST1a in which the first sacrificial films GSLa, WL11a-WL1na, and DWL1a and the first insulating layer 132 are alternately stacked may be formed on the pre-supported semiconductor layer 120a. The first insulating layer 132 may be disposed on the top of the first pre-stacked structure ST1a.

Subsequently, first and second channel holes CH1 and CH2 penetrating the pre-supporting semiconductor layer 120a and the first pre-stacked structure ST1a in the third direction DR3 may be formed. The first and second channel holes CH1 and CH2 may be spaced apart in the first direction DR1. The first and second channel holes CH1 and CH2 may extend into the common source plate 110.

Subsequently, the first channel sacrificial layer 141 may be formed in the first and second channel holes CH1 and CH2. An upper portion of the first channel sacrificial layer 141 may be etched, and the first channel sacrificial layer 141 may fill a portion of the first and second channel holes CH1 and CH2.

Referring to FIG. 10, a second channel sacrificial layer 143 may be formed on the first channel sacrificial layer 141. The second channel sacrificial layer 143 may be conformally formed on the first channel sacrificial layer 141. Accordingly, the second channel sacrificial layer 143 may define a recess R.

Referring to FIG. 11, an adhesive layer 151 may be formed on the second channel sacrificial layer 143. The adhesive layer 151 may be conformally formed on the second channel sacrificial layer 143.

The metal layer 153 may be formed on the adhesive layer 151. The metal layer 153 may fill the recess R. The metal layer 153 may fill the first and second channel holes CH1 and CH2.

Referring to FIG. 12, the second channel sacrificial layer 143, the adhesive layer 151 and the metal layer 153 may be etched by a planarization process. The upper surfaces of the second channel sacrificial layer 143, the adhesive layer 151 and the metal layer 153 may be disposed on the same plane as the upper surfaces of the first pre-stacked structure ST1a. Accordingly, sacrificial channel structures SCS' and SCS may be formed in the first channel hole CH1 of the first region R1 and the second channel hole CH2 of the second region R2, respectively.

Referring to FIG. 13, a second pre-stack structure ST2a in which second sacrificial films DWL2a, WL21a-WL2na, and SSLa and a second insulating film 162 are alternately stacked on the first pre-stack structure ST1a. Can be formed. The first interlayer insulating layer 166 may be formed on the second pre-stacked structure ST2a.

Subsequently, third and fourth channel holes CH4 penetrating the first interlayer insulating layer 166 and the second pre-layered structure ST2a may be formed. The third and fourth channel holes CH4 may be spaced apart in the first direction DR1.

The third and fourth channel holes CH3 and CH4 may be formed on the sacrificial channel structures SCS' and SCS formed in the first and second channel holes CH1 and CH2, respectively. The third and fourth channel holes CH3 and CH4 may extend into the sacrificial channel structures SCS' and SCS formed in the first and second channel holes CH1 and CH2, respectively. The bottom surfaces CH3_bs and CH4_bs of the third and fourth channel holes CH3 and CH4 may be disposed in the sacrificial channel structures SCS' and SCS respectively formed in the first and second channel holes CH1 and CH2, respectively. have.

The third and fourth channel holes CH4 according to some embodiments of the present invention may be formed by, for example, dry etching. At this time, the ions 10 used in the dry etching process may be collected in the metal layer 153 by the lightning rod phenomenon. Accordingly, each of the third and fourth channel holes CH4 may be aligned on the first and second channel holes CH1 and CH2, respectively.

Referring to FIG. 14, the sacrificial channel structure SCS' in the first channel hole CH1 may be removed.

Referring to FIG. 15, a first information storage pattern 170, a first channel layer 174 inside a second channel hole CH2 from which the first channel hole CH1 and the sacrificial channel structure SCS' are removed, The first channel filling layer 175 and the bit line pad 177 may be formed. A second information storage pattern 180, a second channel layer 180, a second channel filling layer 185 and a capping layer 187 may be formed in the fourth channel hole CH4. Accordingly, the first channel structure CS1 may be formed in the first and second channel holes CH1 and CH2, and the second channel structure CS2 may be formed in the fourth channel hole CH4.

Subsequently, a second interlayer insulating layer 186 covering the bit line pad 177 and the capping layer 187 may be formed on the first interlayer insulating layer 166.

Subsequently, a first trench T1 passing through the first and second interlayer insulating layers 186 may be formed. The first trench T1 may cut the first and second free stacked structures ST1a and ST2a. The first trench T1 may expose the pre-supported semiconductor layer 120a and the first and second sacrificial films GSLa, WL11a-WL1na, DWL1a, DWL2a, WL21a-WL2na, and SSLa.

Next, referring to FIG. 3, the pre-supported semiconductor layer 120a exposed by the first trench T1 may be removed.

For example, while the pre-supported semiconductor layer 120a is removed, a portion of the first information storage pattern 170 is removed, so that the first channel layer 174 may be exposed. Alternatively, after the pre-supporting semiconductor layer 120a is removed, a portion of the first information storage pattern 170 is removed, so that the first channel layer 174 may be exposed.

The support semiconductor layer 120 may be formed in a space in which the free support semiconductor layer 120a is removed.

In addition, the first and second sacrificial films GSLa, WL11a-WL1na, DWL1a, DWL2a, WL21a-WL2na, and SSLa exposed by the first trench T1 may be removed. First and second conductive films GSL, WL11-WL1n, DWL1, DWL2, WL21 in the spaces in which the first and second sacrificial films GSLa, WL11a-WL1na, DWL1a, DWL2a, WL21a-WL2na, and SSLa are removed, respectively. -WL2n, SSL) may be formed. That is, the first and second sacrificial films (GSLa, WL11a-WL1na, DWL1a, DWL2a, WL21a-WL2na, SSLa) are first and second through a replacement metal gate process using the first trench T1. The second conductive layer (GSL, WL11-WL1n, DWL1, DWL2, WL21-WL2n, SSL) may be replaced. Accordingly, the first and second stacked structures ST1 and ST2 may be formed.

Subsequently, a bit line contact 191 and a third interlayer insulating film 196 may be formed on the second interlayer insulating film 186 and the electrode isolation region ESR. A bit line BL may be formed on the third interlayer insulating layer 196.

In the semiconductor memory device according to some embodiments of the present invention, the third and fourth channel holes CH3 and CH4 may be aligned with the first and second channel holes CH1 and CH2 by the metal layer 153, respectively. . Accordingly, the number of dummy word lines due to misalignment of the first and second stacked structures ST1 and ST2 can be reduced.

In addition, the junctions of the first and second stacked structures ST1 and ST2 may have a height in consideration of the misalignment of the first and second stacked structures ST1 and ST2. However, in the semiconductor memory device according to some other embodiments of the present invention, since the first and second stacked structures are aligned by the metal layer 153, the height of the junction of the first and second stacked structures according to misalignment is reduced. I can do it.

16 is an intermediate step diagram illustrating a semiconductor memory device in accordance with some other embodiments of the present invention. For convenience of description, description will be made focusing on differences from those described with reference to FIG. 9.

Referring to FIG. 16, a first pre-stacked structure ST1a in which first sacrificial films GSLa, WL11a-WL1na, and DWL1a and a first insulating layer 132 are alternately stacked on the pre-supported semiconductor layer 120a. Can be formed. The first sacrificial films GSLa, WL11a-WL1na, and DWL1a and the first insulating film 132 may be stacked continuously. The first sacrificial layer DWL1a may be disposed on the top of the first pre-stacked structure ST1a.

Subsequently, a semiconductor memory device according to some other embodiments of the present invention illustrated in FIG. 6 may be manufactured by the manufacturing method described with reference to FIGS. 10 to 15.

17 is an intermediate step diagram illustrating a semiconductor memory device in accordance with some other embodiments of the present invention. For convenience of description, description will be made focusing on differences from those described with reference to FIGS. 9 to 13.

Referring to FIG. 17, the third and fourth channel holes CH3 and CH4 may be formed on the sacrificial channel structures SCS' and SCS formed in the first and second channel holes CH1 and CH2, respectively. At this time, the ions 10 used in the dry etching process may be collected in the metal layer 153 by the lightning rod phenomenon. That is, the bottom surfaces CH3_bs and CH4_bs of the third and fourth channel holes CH3 and CH4 are to be disposed in the sacrificial channel structures SCS' and SCS formed in the first and second channel holes CH1 and CH2, respectively. Can be. Therefore, the lower portions of the third and fourth channel holes CH3 and CH4 may be aligned on the sacrificial channel structures SCS' and SCS formed in the first and second channel holes CH1 and CH2, respectively.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments and may be manufactured in various different forms, and having ordinary knowledge in the technical field to which the present invention pertains. It will be understood that a person can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 110: common source plate
120: support semiconductor layer 132, 162: first and second insulating film
141, 143: first and second channel sacrificial layer
151: adhesive layer 153: metal layer
166, 186, 196: first to third interlayer insulating films
170, 180: first and second information storage pattern
174, 184: first and second channel film 175, 185: first and second channel film
177: bit line pad 187: capping film
191: bit line contact 195: cell contact
197: Word line wiring
ST1, ST2: First and second laminated structures
ESR: electrode separation area
GSL, WL11-WL1n, DWL1: first conductive film
DWL2, WL21-WL2n, SSL: Second conductive film
CS1, CS2: first and second channel structures
CSC: sacrificial channel structure BL: bit line

Claims (10)

A first stacked structure on which a plurality of first conductive films are stacked on a substrate;
A second stacked structure on which a plurality of second conductive films are stacked on the first stacked structure;
A first channel structure penetrating the first and second stacked structures and including a channel film; And
Passing through the first stacked structure and non-penetrating the second stacked structure, including a sacrificial channel structure including a metal layer,
The first stacked structure includes different first and second regions,
The first channel structure is disposed in the first region,
The sacrificial channel structure is a semiconductor memory device disposed in the second region. According to claim 1,
The sacrificial channel structure,
A channel sacrificial layer disposed along the profile of the channel hole passing through the first stacked structure, and an adhesive layer disposed on the channel sacrificial layer,
The metal layer is disposed on the adhesive layer to fill the channel hole. According to claim 1,
Further comprising a second channel structure passing through the second stacked structure, and disposed on the sacrificial channel structure,
The bottom surface of the second channel structure is a semiconductor memory device disposed in the sacrificial channel structure. A first channel hole penetrating the first stacked structure is formed in a first stacked structure in which a first insulating film and a first sacrificial film are alternately stacked,
A sacrificial channel structure including a metal layer and a channel sacrificial layer surrounding the metal layer is formed in the first channel hole, wherein the top surface of the metal layer is disposed on the same plane as the top surface of the channel sacrificial layer,
On the first stacked structure, a second stacked structure in which a second insulating film and a second sacrificial film are alternately stacked,
On the sacrificial channel structure, a second channel hole penetrating the second stacked structure is formed,
A channel structure filling the second channel hole is formed in the second channel hole,
Forming a first trench spaced apart from the channel structure and penetrating the first stacked structure and the second stacked structure,
Removing the first sacrificial layer and the second sacrificial layer exposed by the first trench to form a second trench,
A method of manufacturing a semiconductor memory device, comprising forming a conductive film in the second trench. The method of claim 4,
The channel sacrificial layer includes a first channel sacrificial layer and a second channel sacrificial layer,
Forming the channel sacrificial layer,
Forming the first channel sacrificial layer filling at least a portion of the first channel hole in the first channel hole,
A second channel sacrificial layer defining a recess is formed on the first channel sacrificial layer, wherein at least a part of the recess is disposed in the first channel hole,
And forming the metal layer filling the recess. The method of claim 5,
Forming the metal layer,
A method of manufacturing a semiconductor memory device further comprising forming an adhesive layer along the profile of the recess. The method of claim 4,
The first stacked structure includes a cell region and a cell extension region,
During the formation of the first trench, the sacrificial channel structure remains in the cell extension region. The method of claim 4,
A method of manufacturing a semiconductor memory device in which a portion of the second channel hole extends into the sacrificial channel structure. The method of claim 4,
Forming the channel structure,
The metal layer and the channel sacrificial layer formed in the first channel hole are removed,
And forming the channel structure filling the first and second channel holes in the first and second channel holes. The method of claim 4,
Between the substrate and the first stacked structure, further comprising forming a common source plate,
A portion of the first channel hole extends into the common source plate,
The channel structure is a method of manufacturing a semiconductor memory device that is electrically connected to the common source plate.

Images