KR20200081231A - Integrated circuit package and method - Google Patents

Abstract

Disclosed are a packaged semiconductor device including an integrated passive device-containing package component disposed between a power module and an integrated circuit-containing package and a method of forming the same. In an embodiment, a device comprises: a first package component including a first integrated circuit die, a first encapsulant at least partially surrounding the first integrated circuit die, and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, wherein the second package component includes an integrated passive device and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component through the second package component.

Description

Integrated circuit package and method {INTEGRATED CIRCUIT PACKAGE AND METHOD}

Priority claims and cross-references

This application claims the priority of U.S. Provisional Application No. 62/785,133, filed December 26, 2018, which is incorporated herein by reference.

The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). For most parts, an improvement in integration density is the result of repeated reductions in minimum feature size, which allows more components to be integrated within a given area. As the demand to shrink electronic devices has increased, the need for smaller and more productive packaging technologies for semiconductor dies has emerged. An example of such a packaging system is PoP (Package-on-Package) technology. In PoP devices, the upper semiconductor package is stacked on top of the lower semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with small footprints and enhanced functionality on printed circuit boards (PCBs).

A packaged semiconductor device comprising an integrated passive component-comprising package component disposed between an integrated circuit-comprising package and a power module and a method of forming the same are disclosed. In an embodiment, a device includes, as a first package component, a first integrated circuit die; A first encapsulant surrounding at least partially the first integrated circuit die; The first package component on the first encapsulant and including a redistribution structure coupled to the first integrated circuit die; A second package component bonded to the first package component, comprising: an integrated passive element; A second package component comprising a second encapsulant at least partially surrounding the integrated passive element; And a power module attached to the first package component through the second package component.

Aspects of the present disclosure are best understood when viewed in conjunction with the accompanying drawings from the following detailed description. It should be noted that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may have been arbitrarily increased or decreased to clarify the description.
1 to 4, 5A, 5B, 6 to 15, 16A to 16C, 17A to 17C, 18A to 18E are in the process of forming a first package according to some embodiments Intermediate steps are illustrated.
19-24 illustrate cross-sectional views of an intermediate step in a process for forming a system-on-wafer (SoW) package in accordance with some embodiments.
25-32 illustrate cross-sectional views of an intermediate step in a process for forming a packaged device in accordance with some embodiments.
33 and 38 illustrate top-down views of a packaged device according to some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and configurations are described below to simplify the present disclosure. These, of course, are merely examples and are not intended to be limiting. For example, in the following description, forming the first feature on or over the second feature may include embodiments in which the first and second features are formed in direct contact, and the first and second Also included are embodiments in which additional features may be formed between the first feature and the second feature so that the features do not come into direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself dictate the relationship between the various embodiments and/or configurations described.

In addition, spatially relative terms such as “below”, “below”, “bottom”, “above”, “top”, etc., are one component(s) or another component(s) of a feature, as illustrated in the figure. It can be used herein for ease of explanation to describe the relationship to feature(s). The spatially relative terms are intended to encompass different orientations of the device being used or in operation in addition to the orientation depicted in the figures. The device can be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein can likewise be interpreted accordingly.

Although embodiments are described in detail below, a general description of the present disclosure is provided herein. In general, the embodiment described herein includes integrated passive device (IPD) packages between a power module (sometimes referred to as a socket) and an integrated fan-out (InFO) structure. By stacking on, IPD provides a package that is packaged and integrated into a system-on-wafer (SoW) package (eg, an ultra-large fan-out wafer scale package). The SoW package of an embodiment may include any combination of interconnected functional dies in a package area of 10,000 mm ² or more. For example, interconnected functional dies in a SoW package provide each component of a completed electrical system, such as high performance computing (HPC) in data center applications, server applications, etc. (eg, artificial intelligence (AI; AI); artificial intelligence) server accelerometer, cloud computing system, edge computing system, etc.). The power module can be connected to the functional die of the SoW package through the IPD package. Each power module can provide power management for a single function die or multiple function dies within a SoW package.

Advantageous features of some or all of the embodiments described herein may include a shorter distance between the IPD and the functional die, which may enhance power distribution network (PDN) performance. Some embodiments may provide integration of 3D stacked IPD with InFO process, thus making adoption of the embodiments feasible. In some embodiments, 3D stacking of IPDs eliminates the need to remove the ball grid array (BGA) connector from the socket landscape (eg, the footprint of the package) and increases the current handling. The area (eg, more BGA connectors) enables improved current handling.

1-16C illustrate cross-sectional views of intermediate steps during a process for forming a first package component 100 in accordance with some embodiments. The first package component 100 is an IPD package including one or more IPDs, which may include modules (eg, the module 160 illustrated in FIGS. 17A to 17C) and SoW packages (eg, FIG. 24, according to various embodiments). It may be implemented between the illustrated SoW package (400). 1 illustrates a first package area 101A and a second package area 101B, in which one or more IPDs, such as IPD 50A, described below with reference to FIG. 4, can be packaged.

In FIG. 1, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 can be a wafer, so that multiple packages can be formed on the carrier substrate 102 simultaneously.

The release layer 104 can be formed of a polymer-based material, which can be removed together with the carrier substrate 102 from the above structures to be formed in a later step. In some embodiments, release layer 104 is an epoxy-based heat-release material, which loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In another embodiment, the release layer 104 may be a UV glue that loses its adhesive properties when exposed to ultra-violet (UV) light. The release layer 104 can be dispensed as a liquid and cured, can be a laminate film deposited over the carrier substrate 102, or the like. The top surface of the release layer 104 can be planarized and have a high level of co-planarity.

In FIG. 2, a back-side redistribution structure 106 may be formed on the release layer 104. In the illustrated embodiment, back redistribution structure 106 includes dielectric layer 108, metallization pattern 110 (often referred to as a redistribution layer or redistribution line) and dielectric layer 112. Rear redistribution structure 106 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on release layer 104 instead of back redistribution structure 106.

Dielectric layer 108 may be formed on release layer 104. The lower surface of dielectric layer 108 may be in contact with the upper surface of release layer 104. In some embodiments, dielectric layer 108 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In other embodiments, dielectric layer 108 may include nitride, such as silicon nitride; Oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), and boron-doped phosphosilicate glass (BSG); And the like. Dielectric layer 108 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, or a combination thereof.

The metallization pattern 110 can be formed on the dielectric layer 108. As an example, the metallization pattern 110 may be formed by first forming a seed layer over the dielectric layer 10. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, and the like. Subsequently, portions of the seed layer on which the conductive material is not formed and photoresist are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, the exposed portion of the seed layer is removed using an acceptable etching process such as wet or dry etching. The remaining portion of the seed layer and the conductive material form a metallization pattern 110.

Dielectric layer 112 may be formed on metallization pattern 110 and dielectric layer 108. In some embodiments, dielectric layer 112 is formed of a polymer that can be a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a lithography mask. In other embodiments, dielectric layer 112 may include nitride, such as silicon nitride; Oxides such as silicon oxide, PSG, BSG, and BPSG; And the like. Dielectric layer 112 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 112 can be patterned to form an opening 114 exposing a portion of the metallization pattern 110. Patterning can be performed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material, or by etching using, for example, anisotropic etching. In embodiments where dielectric layer 112 is a photosensitive material, dielectric layer 112 may be developed after exposure to light.

It should be noted that the back redistribution structure 106 can include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are formed, the steps and processes described above can be repeated. The metallization pattern can include conductive lines and conductive vias. Conductive vias can be formed by forming a seed layer and a conductive material of the metallization pattern in the opening of the underlying dielectric layer during formation of the metallization pattern. Conductive vias can interconnect and electrically couple the various conductive lines of the metallization pattern.

In FIG. 3, a through via 116 is formed in the opening 114 and over the topmost dielectric layer of the backside redistribution structure 106 (eg, dielectric layer 112 in the embodiment illustrated in FIG. 3 ). Extend. As an example, the through via 116 first forms a seed layer over the backside redistribution structure 106, such as a portion of the metallization pattern 110 exposed by the opening 114 and the dielectric layer 112. Can be formed by. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In certain embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of photoresist corresponds to the through via 116. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, and the like. Portions of the seed layer and photoresist on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, the exposed portion of the seed layer is removed using an acceptable etching process such as wet or dry etching. The remaining portion of the seed layer and the conductive material form a through via 116.

In FIG. 4, die 50 comprising IPD 50A, discrete passive element 50B, and active element die 50C is adhered to dielectric layer 112 by adhesive 118. A desired type and amount of die 50 is adhered to each of the first package area 101A and the second package area 101B. In various embodiments, passive elements such as IPD 50A and discrete passive element 50B may occupy an area greater than 50 percent in each of first package area 101A and second package area 101B. . In the illustrated embodiment, multiple dies 50 are bonded adjacent to each other. The IPD 50A and the active device die 50C are respectively described in more detail below with respect to FIGS. 5A and 5B, respectively.

Discrete passive element 50B may include, for example, one or more discrete capacitors, inductors, combinations thereof, and the like. When a plurality of discrete passive elements 50B are disposed in each of the first package area 101A and the second package area 101B, the discrete passive elements 50B are bonded together or in a stacked configuration (as illustrated). Alternatively, it may be directly arranged side by side on the rear redistribution structure 106. As illustrated in FIG. 4, each of the discrete passive elements 50B includes a semiconductor substrate 52B, a through via 53B extending through the semiconductor substrate 52B, a semiconductor substrate 52B, and a through via 53B. It may include a pad 62B disposed above, a semiconductor substrate 52B and a passivation layer 64B disposed on the pad 62B, and a die connector 66B extending through the passivation layer 64B. Discrete passive element 50B and active element die 50C are optional, and in some embodiments, discrete passive element 50B and/or active element die 50C may include first package area 101A and/or second package. It can be omitted from the region 101B.

IPD 50A, discrete passive element 50B, and active element die 50C can have different sizes (eg, different heights and/or surface areas), or have the same size (eg, same height and/or surface area). Can have The space available for the through via 116 in the first package area 101A and the second package area 101B can be limited, in particular the IPD 50A, the discrete passive element 50B, and the active element die 50C ) When including a device with a large footprint, such as an SoC. The use of the back redistribution structure 106 enables improved interconnect arrangement when the first package area 101A and the second package area 101B have limited space available for the through via 116.

The adhesive 118 is on the back of the IPD 50A, the discrete passive element 50B, and the active element die 50C, and the IPD 50A, the discrete passive element 50B, and the active element die 50C. It is adhered to a backside redistribution structure 106, such as a dielectric layer 112. The adhesive 118 can be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 118 may be applied to the back of the IPD 50A, discrete passive element 50B, and active element die 50C, or may be applied over the surface of the dielectric layer 112 on the carrier substrate 102. have. For example, the adhesive 118 can be IPD 50A, discrete passive element 50B, before singulating to separate IPD 50A, discrete passive element 50B, and active element die 50C, And an active device die 50C.

5A illustrates IPD 50A in accordance with some embodiments. The IPD 50A may include a wide variety of passive components such as baluns, couplers, splitters, filters, diplexers, inductors, capacitors, resistors, and the like. In some embodiments, IPD 50A may be a multi-layer ceramic capacitor (MLCC), coil inductor, film resistance, or the like. According to some embodiments, IPD 50A has no active elements such as transistors or diodes.

IPD 50A can be formed on a wafer that can include different device regions that are individualized in subsequent steps to form a plurality of IPDs 50A. IPD 50A can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the IPD 50A can include a semiconductor substrate 52A, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52A includes other semiconductor materials such as germanium; Compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; Alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; Or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The semiconductor substrate 52A has an active surface, often referred to as a front-side (eg, an upward facing surface in FIG. 5A), and an inactive surface, often referred to as a back (eg, a downward facing surface in FIG. 5A).

An inter-layer dielectric (ILD) 56A is formed on the front surface of the semiconductor substrate 52A. The ILD 56A may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (PSG), undoped silicate glass (USG), and the like.

Interconnect structure 60A is included over ILD 56A. The interconnect structure 60A can be used to interconnect various passive elements included in the IPD 50A. The interconnect structure 60A may further define various passive elements included in the IPD 50A. For example, area 70A of interconnect structure 60A can define a resistor, area 70B of interconnect structure 60A can define a capacitor, and area of interconnect structure 60A 70C can define an inductor. However, each of the regions 70A, 70B, and 70C can define any passive element of the IPD 50A.

The interconnect structure 60A can be formed, for example, by a metallization pattern in the dielectric layer on the ILD 56A. The metallization pattern includes metal lines and vias formed in one or more low k dielectric layers. The metallization pattern of interconnect structure 60A is electrically coupled to the passive elements of IPD 50A.

The IPD 50A further includes a pad 62A, such as an aluminum pad, to which external connection is made. The pad 62A is on the front side of the IPD 50A, such as on the interconnect structure 60A and/or on the interconnect structure 60A. One or more passivation films 64A are on IPD 50A, such as on interconnect structure 60A and a portion of pad 62A. The opening extends through the passivation film 64A to the pad 62A. A die connector 66A, such as a conductive pillar (for example formed of a metal such as copper), extends through the opening in the passivation film 64A, and physically and electrically to each pad of the pad 62A. Is coupled to. The die connector 66A can be formed, for example, by plating or the like. The die connector 66A electrically couples each passive element of the IPD 50A to an external device.

Optionally, solder regions (eg, solder balls or solder bumps) can be disposed on the pad 62A. The solder ball can be used to perform chip probe (CP) testing on the IPD 50A. CP testing may be performed on IPD 50A to determine whether IPD 50A is a known good die (KGD). Therefore, only the IPD 50A, which is the KGD, is packaged through subsequent processing, and the die that failed CP testing is not packaged. After testing, solder regions may be removed in a subsequent processing step.

Dielectric layer 68A can be included on the front side of IPD 50A, such as on passivation film 64A and die connector 66A. Dielectric layer 68A encapsulates die connector 66A laterally, and dielectric layer 68A is laterally in contact with IPD 50A. Initially, the dielectric layer 68A can fill the die connector 66A such that the top surface of the dielectric layer 68A is over the top surface of the die connector 66A. In some embodiments where solder regions are disposed on die connector 66A, dielectric layer 68A may also fill the solder regions. Alternatively, solder regions can be removed prior to forming dielectric layer 68A.

The dielectric layer 68A may include polymers such as PBO, polyimide, BCB, and the like; Nitrides, such as silicon nitride; Oxides such as silicon oxide, PSG, BSG, and BPSG; Other or a combination thereof. Dielectric layer 68A may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, die connector 66A is exposed through dielectric layer 68A during formation of IPD 50A. In some embodiments, die connector 66A remains buried and is exposed during a subsequent process to package IPD 50A. Exposing die connector 66A can remove any solder areas that may be present on die connector 66A.

In some embodiments, IPD 50A may be a stacked device comprising a plurality of semiconductor substrates 52A. In this embodiment, IPD 50A includes a plurality of semiconductor substrates 52A interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates 52A may have an interconnect structure 60A.

5B illustrates an active device die 50C in accordance with some embodiments. The active device die 50C will be packaged in subsequent processing to form an integrated circuit package. The active device die 50C includes a logic die (eg, a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory Dies (eg dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, high bandwidth memory (HBM) dies, etc.), input/output (I/O) interface dies, power management dies (eg PMIC (power management integrated circuit) die, radio frequency (RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die, etc.) , Front end die (eg, analog front-end (AFE) die, etc.), etc., or a combination thereof.

The active device die 50C can be formed on a wafer, which can include different device regions that are individualized in subsequent steps to form a plurality of active device dies. The active element 50C can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the active element 50C includes a semiconductor substrate 52C, such as silicon, doped or undoped, or an active layer of an SOI substrate. The semiconductor substrate 52C includes other semiconductor materials such as germanium; Compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; Alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; Or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The semiconductor substrate 52C has an active surface, often referred to as the front side (eg, an upward facing surface in FIG. 5B), and an inactive surface, often referred to as a back side (eg, a downward facing surface in FIG. 5B).

The device 54 can be formed on the front surface of the semiconductor substrate 52. Device 54 may be an active element (eg, transistor, diode, etc.), capacitor, resistor, or the like. An interlayer dielectric (ILD) 56C is formed on the front surface of the semiconductor substrate 52C. ILD 56C may surround and cover device 54. The ILD 56C may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (PSG), undoped silicate glass (USG), and the like.

Conductive plug 58 extends through ILD 56C to electrically and physically couple device 54. For example, when device 54 is a transistor, conductive plug 58 can couple the gate and source/drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or a combination thereof. Interconnect structure 60C is included over ILD 56C and conductive plug 58. Interconnect structure 60C interconnects devices 54 to form an integrated circuit. Interconnect structure 60C may be formed, for example, by a metallization pattern in a dielectric layer on ILD 56C. The metallization pattern includes metal lines and vias formed in one or more low k dielectric layers. The metallization pattern of interconnect structure 60C is electrically coupled to device 54 by conductive plug 58.

The active element die 50C further includes a pad 62C, such as an aluminum pad, to which an external connection is made. The pad 62C is on the active side of the active element die 50C, such as on the interconnect structure 60C and/or on the interconnect structure 60C. One or more passivation films 64C are on the active device die 50C, such as on the interconnect structure 60C and a portion of the pad 62C. The opening extends through the passivation film 64C to the pad 62C. A die connector 66C, such as a conductive pillar (for example formed of a metal such as copper), extends through the opening in the passivation film 64C, and physically and electrically couples to each pad of the pad 62C do. The die connector 66C can be formed, for example, by plating or the like. The die connector 66C electrically couples the respective integrated circuit of the active element die 50C.

Optionally, solder regions (eg, solder balls or solder bumps) can be disposed on the pad 62C. Solder balls can be used to perform chip probe (CP) testing on the active device die 50C. CP testing may be performed on the active device die 50C to confirm whether the active device die 50C is a known good die (KGD). Therefore, only the active element die 50C, which is the KGD, is packaged through subsequent processing, and the die that failed CP testing is not packaged. After testing, solder regions may be removed in a subsequent processing step.

Dielectric layer 68C may be on the front side of active element die 50C, such as on passivation film 64C and die connector 66C. Dielectric layer 68C encapsulates die connector 66C laterally, dielectric layer 68C laterally abuts active element die 50C. Initially, the dielectric layer 68C can fill the die connector 66C such that the top surface of the dielectric layer 68C is above the top surface of the die connector 66C. In some embodiments where the solder area is disposed on the die connector 66C, the dielectric layer 68C may also fill the solder area. Alternatively, solder regions can be removed prior to forming dielectric layer 68C.

The dielectric layer 68C may include polymers such as PBO, polyimide, BCB, and the like; Nitrides, such as silicon nitride; Oxides such as silicon oxide, PSG, BSG, and BPSG; Other or a combination thereof. Dielectric layer 68C may be formed, for example, by spin coating, lamination, CVD, or the like. In some embodiments, die connector 66C is exposed through dielectric layer 68C during formation of active element die 50C. In some embodiments, die connector 66C remains buried and is exposed during a subsequent process to package active element die 50C. Exposing the die connector 66C can remove any solder areas that may be present on the die connector 66C.

In some embodiments, active element die 50C is a stacked device that includes a plurality of semiconductor substrates 52C. For example, the active element die 50C may be a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, and the like, including a plurality of memory dies. In this embodiment, the active element die 50C includes a plurality of semiconductor substrates 52C interconnected by TSVs. Each of the semiconductor substrates 52C may have an interconnect structure 60C.

In FIG. 6, encapsulant 120 is formed surrounding die 50 and through via 116. After formation, encapsulant 120 encapsulates through via 116, IPD 50A, discrete passive element 50B, and active element die 50C. The encapsulant 120 may be a molding compound, epoxy, or the like. The encapsulant 120 may be applied by compression molding, transfer molding, or the like, and carriers such that the through via 116 and/or the IPD 50A, the discrete passive element 50B, and the active element die 50C are embedded or covered. It may be formed on the substrate 102. The encapsulant 120 is further formed in a gap region between the IPD 50A, the discrete passive element 50B, and the active element die 50C. The encapsulant 120 may be applied in a liquid or semi-liquid form and then cured.

In FIG. 7, a planarization process is performed on encapsulant 120 to expose through vias 116 and die connectors 66A, 66B, and 66C. The planarization process may also include through connectors 116, dielectric layers 68A and 68C, and/or die connectors 66A, 66B, and until die connectors 66A, 66B, and 66C and through vias 116 are exposed. 66C) can be removed. Following the planarization process, the top surfaces of through vias 116, die connectors 66A, 66B, and 66C, dielectric layers 68A and 68C, and encapsulant 120 may be flush with each other (eg, coplanar) ). The planarization process may be, for example, a chemical-mechanical polish (CMP) process, a grinding process, an etchback process, or the like. In some embodiments, the planarization process can be omitted, for example, if the through vias 116 and/or die connectors 66A, 66B, and 66C have already been exposed.

In FIGS. 8-11, front redistribution structure 122 (see FIG. 11) includes encapsulant 120, through via 116, IPD 50A, discrete passive element 50B, and active element die 50C. ) Is formed on top. Front redistribution structure 122 includes dielectric layers 124, 128, 132, and 136, and metallization patterns 126, 130, and 134. The metallization pattern may also be referred to as a redistribution layer or redistribution line. The front redistribution structure 122 illustrated in FIG. 11 includes three layers of metallization patterns and four layers of dielectric layers, but more or fewer metallization patterns and dielectric layers are front redistribution structures 122 Can be included in If fewer dielectric layers and metallization patterns are formed, the steps and processes described below can be omitted. If more dielectric layers and metallization patterns are formed, the steps and processes described below can be repeated.

In FIG. 8, dielectric layer 124 is deposited on encapsulant 120, through via 116 and die connectors 66A, 66B, and 66C. In some embodiments, dielectric layer 124 is formed of a photosensitive material such as PBO, polyimide, BCB, and the like, which can be patterned using a lithography mask. Dielectric layer 124 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. Then, dielectric layer 124 is patterned. The patterning forms an opening exposing a portion of the through via 116 and die connectors 66A, 66B, and 66C. Patterning can be accomplished by an acceptable process, such as by exposing the dielectric layer 124 to light when the dielectric layer 124 is a photosensitive material, or by etching using, for example, anisotropic etching. When the dielectric layer 124 is a photosensitive material, the dielectric layer 124 can be developed after exposure.

Then, a metallization pattern 126 is formed. The metallization pattern 126 includes a line portion (also referred to as a conductive line) extending along it on the major surface of the dielectric layer 124. The metallization pattern 126 extends through the dielectric layer 124 to physically and electrically couple the through via 116 and IPD 50A, the discrete passive element 50B, and the active element die 50C. It further includes a via portion (also referred to as a conductive via). For example, the metallization pattern 126 can be formed by first forming a seed layer over the dielectric layer 124 and in openings extending through the dielectric layer 124. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 126. Patterning forms openings through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the bottom portion of the seed layer forms a metallization pattern 126. Portions of the seed layer and photoresist on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, the exposed portion of the seed layer is removed using an acceptable etching process such as wet or dry etching.

In FIG. 9, dielectric layer 128 is deposited on metallization pattern 126 and dielectric layer 124. Dielectric layer 128 may be formed in a similar manner to dielectric layer 124, and may be formed of a material similar to that of dielectric layer 124.

Then, a metallization pattern 130 is formed. The metallization pattern 130 includes a line portion extending along it on the main surface of the dielectric layer 128. The metallization pattern 130 further includes a via portion extending through the dielectric layer 128 to physically and electrically couple the metallization pattern 126. The metallization pattern 130 may be formed in a manner similar to the metallization pattern 126, and may be formed of a material similar to the material of the metallization pattern 126. In some embodiments, metallization pattern 130 has a different size than metallization pattern 126. For example, the conductive lines and/or vias of the metallization pattern 130 may be wider or thicker than the conductive lines and/or vias of the metallization pattern 126. Further, the metallization pattern 130 may be formed at a larger pitch than the metallization pattern 126.

In FIG. 10, dielectric layer 132 is deposited over metallization pattern 130 and dielectric layer 128. Dielectric layer 132 may be formed in a similar manner to dielectric layer 124 and may be formed of a material similar to that of dielectric layer 124.

Then, a metallization pattern 134 is formed. The metallization pattern 134 includes a line portion extending along it on the major surface of the dielectric layer 132. The metallization pattern 134 further includes a via portion extending through the dielectric layer 132 to physically and electrically couple the metallization pattern 130. The metallization pattern 134 may be formed in a manner similar to the metallization pattern 126, and may be formed of a material similar to the material of the metallization pattern 126. The metallization pattern 134 is the top metallization pattern of the front redistribution structure 122. Thus, all intermediate metallization patterns of front redistribution structure 122 (eg, metallization patterns 126 and 130) are metallization pattern 134 and IPD 50A, discrete passive elements 50B, and active elements. It is disposed between the dies 50C. In some embodiments, metallization pattern 134 has a different size than metallization patterns 126 and 130. For example, the conductive lines and/or vias of the metallization pattern 134 may be wider or thicker than the conductive lines and/or vias of the metallization patterns 126 and 130. Also, the metallization pattern 134 may be formed at a larger pitch than the metallization pattern 130.

In FIG. 11, dielectric layer 136 is deposited over metallization pattern 134 and dielectric layer 132. Dielectric layer 136 may be formed in a similar manner to dielectric layer 124 and may be formed of a material similar to that of dielectric layer 124. Dielectric layer 136 is the top dielectric layer of front redistribution structure 122. Thus, all metallization patterns of front redistribution structure 122 (eg, metallization patterns 126, 130, and 134) include dielectric layer 136 and IPD 50A, discrete passive elements 50B, and active elements. It is disposed between the dies 50C. In addition, all intermediate dielectric layers of front redistribution structure 122 (e.g., dielectric layers 124, 128, 132) include dielectric layer 136 and IPD 50A, discrete passive elements 50B, and active element die. (50C).

In FIG. 12, under bump metallurgies (UBM) 138 are formed for external connection to the front redistribution structure 122. The UBM 138 has a bump portion extending along it on the major surface of the dielectric layer 136, and a via portion extending through the dielectric layer 136 to physically and electrically couple to the metallization pattern 134. Have As a result, UBM 138 is electrically coupled to through via 116 and IPD 50A, discrete passive element 50B, and active element die 50C. The UBM 138 may be formed of the same material as the metallization pattern 126. In some embodiments, UBM 138 may have a different size than metallization patterns 126, 130 and 134.

In FIG. 13, a conductive connector 150 is formed on the UBM 138. The conductive connector 150 includes a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, an electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bump Etc. The conductive connector 150 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof. In some embodiments, the conductive connector 150 is formed by first forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, and the like. If a solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 150 includes a metal pillar (eg, copper pillar) formed by sputtering, printing, electrolytic plating, electroless plating, CVD, or the like. The metal pillars can be lead-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed by a plating process.

In FIG. 14, the structure of FIG. 13 is flipped and placed on tape 149, and carrier substrate 102 is de-bonded from back redistribution structure 106, such as dielectric layer 108. According to some embodiments, bonding separation projects light, such as laser light or UV light, onto the release layer 104 so that the release layer 104 can be decomposed under the heat of light to remove the carrier substrate 102. Includes. The structure is then flipped and placed on tape 149.

Also in FIG. 14, the front redistribution structure 122 may be pre-cut. The front redistribution structure 122 in the scribe line area between the first package area 101A and the second package area 101B so that the cutting device forms a recess (not separately illustrated) in the front redistribution structure 122. Can be partially cut. In some embodiments, the cutting device for the precut process is a laser. The precut process can prevent peeling of the front redistribution structure 122 and its layers during subsequent individualization processes (see, eg, FIGS. 16A-16C ).

In FIG. 15, opening 151 is formed through dielectric layer 108 to expose a portion of metallization pattern 110. The opening 151 may be formed using, for example, laser drilling or etching.

16A to 16C, various external connectors are formed in the opening 151 to form the first package component 100 in the first package area 101A and the second package area 101B. In FIG. 16A, a conductive connector 152 is formed on the metallization pattern 110 in the opening 151, and the first package component 100A in the first package region 101A and the second package region 101B. To form. The conductive connector 152 includes a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, an electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bump Etc. The conductive connector 152 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 152 is formed by initially forming a solder layer through this commonly used method such as evaporation, electroplating, printing, solder transfer, ball placement, and the like. If a solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape.

In FIG. 16B, a pad 154 is formed on the metallization pattern 110 in the opening 151, and the first package component 100B is applied to the first package area 101A and the second package area 101B. To form. The pad 154 is used to couple to the conductive connector 156 and may be referred to as UBM 154. In the illustrated embodiment, a pad 154 is formed in the opening 151 through the dielectric layer 108 to the metallization pattern 110.

As an example, pad 154 may be formed by first forming a seed layer over dielectric layer 108 and in opening 151 extending through dielectric layer 108. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using PVD or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of photoresist corresponds to pad 154. Patterning forms openings through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, and the like. In some embodiments, the pad 154 may include alloys such as electroless nickel, electroless palladium, immersion gold (ENEPIG), electroless nickel, immersion gold (ENIG), and the like. The combination of the conductive material and the bottom portion of the seed layer forms the pad 154. Portions of the seed layer and photoresist on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, the exposed portion of the seed layer is removed using an acceptable etching process such as wet or dry etching.

Next, a conductive connector 156 is formed over the pad 154. The conductive connector 156 may be formed in a similar manner to the conductive connector 152, and may be formed of a material similar to that of the conductive connector 152.

16C shows that the pad 154 is formed without the conductive connector being formed on the pad 154, and the first package component 100C is formed in the first package region 101A and the second package region 101B. Illustrate an example. The pad 154 can be formed of a material and in a similar manner as described with respect to FIG. 16B.

In FIGS. 17A-C, module 160 is bonded to rear redistribution structure 106. The module 160 may be a power supply module, a memory module, a voltage regulator module, or an integrated passive device (IPD) module. In some embodiments, module 160 may include flip chip bonding, wire bonding, and the like. The module 160 may be chip-scale packages (CSP), multi-chip modules (MCM), or the like. The module 160 may be a PCB module including discrete integrated circuits and passive elements according to some embodiments.

17A illustrates the module 160A bonded to the first package component 100A illustrated in FIG. 16A. As illustrated in FIG. 17A, module 160A may include pad 162, and conductive connector 158 is formed on pad 162. The pad 162 may be formed in a manner similar to the pad 154, and may be formed of a material similar to the material of the pad 154. The conductive connector 158 may be formed in a similar manner to the conductive connector 152, and may be formed of a material similar to that of the conductive connector 152. The module 160A may be disposed in the first package area 101A and the second package area 101B using a pick and place machine or the like. Once the module 160A is placed, the conductive connector 152 and the conductive connector 158 can be reflowed to bond the module 160A to the rearrange redistribution structure 106.

An underfill 164 may be formed to fill the gap between module 160A and back redistribution structure 106. The underfill 164 may be formed by a capillary flow process after the module 160A is attached, or may be formed by a suitable deposition method before the module 160A is attached.

17B illustrates a module 160A bonded to the first package component 100B illustrated in FIG. 16B. The pad 162 may be formed in a manner similar to the pad 154, and may be formed of a material similar to the material of the pad 154. The module 160A may be disposed in the first package area 101A and the second package area 101B using a pick-and-place machine or the like. Once the module 160A is placed, the conductive connector 152 can be reflowed to bond the module 160A to the backside redistribution structure 106.

An underfill 164 may be formed to fill the gap between the module 160A and the back redistribution structure 106. The underfill 164 may be formed by a capillary flow process after module 160A is attached, or it may be formed by a suitable deposition method before module 160A is attached.

17C illustrates the module 160B electrically coupled to the first package component 100C illustrated in FIG. 16C. As illustrated in FIG. 17C, module 160B may include a spring-type contact 166. The module 160B may be disposed on the first package component 100C using a pick and place machine or the like such that the spring-type contact 166 is disposed on the pad 154. The module 160B can then be attached to the first package component 100B using a fastener, such as a fastener 450 described below with respect to FIGS. 30 and 32. The spring-type contact 166 may be formed of a material such as copper, copper alloy, plated beryllium copper (e.g., beryllium copper (BeCu) plated with nickel (Ni) and then plated with gold (Au)), combinations thereof, and the like. Can be. The spring type contact 166 can be formed by a cold forming process or the like. Including the spring-type contact 166 allows the module 160B to be mechanically fastened to the first package component 100C without requiring a bonding or bonding process, and the module 160B This makes it easy to replace. As illustrated in FIG. 17C, in an embodiment where a spring-type contact 166 is used to attach the module 160B to the back redistribution structure 106, the underfill material is the module 160B and the back redistribution structure 106. ).

18A to 18E, the first package component 100 in the first package region 101A and the second package region 101B is individualized, and the first package component 100 with or without the attached module 160 is shown. ) Are disposed in the tray 170. The first package component 100 can be individualized using a dicing process such as sawing, laser drilling, and the like. 18A-18E, the first package component 100 includes a front redistribution structure 122, an encapsulated die 50, a back redistribution structure 106, and optional conductive connectors 152, Pad 154 and a conductive connector 156. The first package 200 includes a module 160 bonded to the first package component 100. After the first package component 100 is individualized, each of the first packages 200 is removed from the tape 149 and placed in the tray 170. The tray 170 remains until the first package 200 is placed during a subsequent 3D packaging process (eg, the process used to attach the first package 200 to the SoW package 400, illustrated in FIG. 25 ). It can be used to provide protection to the first package 200. Placing the first package 200 in the tray 170 can improve the reliability and yield of the package produced by the method of the present application.

18A illustrates a first package 200A that includes a module 160A bonded to a first package component 100A. The module 160A is bonded to the first package component 100A by a solder bond between the conductive connector 152 and the conductive connector 158. Module 160A is coupled to die 50 of first package component 100A through pad 162, conductive connector 158, conductive connector 152, and back redistribution structure 106. 18B illustrates a first package 200B that includes a module 160A bonded to the first package component 100B. The module 160A is bonded to the first package component 100B by solder bonding between the conductive connector 156 and the pad 162. Module 160A is coupled to die 50 of first package component 100B via pad 162, conductive connector 156, pad 154, and back redistribution structure 106. 18C illustrates the first package 200C including the module 160B bonded to the first package component 100C. The module 160B is disposed on the first package component 100C with a spring-type contact 166 disposed on the pad 154. As described with respect to FIG. 30, the module 160b may then be secured to the first package component 100C using a mechanical brace 450A or the like. Module 160B is coupled to die 50 of first package component 100C through spring-type contact 166, pad 154, and back redistribution structure 106. 18D shows the individualized first package component 100C, including the pad 154 without a conductive connector thereon, disposed on the tray 170 without the module 160 attached to the first package component 100C. For example.

18E illustrates the first package 200D including the module 160C bonded to the first package component 100B. Module 160C may include a conductive pad (not illustrated separately) that is flush with its surface. The conductive connector 156 is bonded to the conductive pad of the module 160C. Module 160C may be bonded to first package component 100B using a process similar to the process used to bond module 160A to first package component 100B, described above with respect to FIG. 17B. have. Module 160C is coupled to die 50 of first package component 100B through conductive connector 156, pad 154, and back redistribution structure 106.

19-24 illustrate cross-sectional views of an intermediate step in a process for forming a system-on-wafer (SoW) package 400A in accordance with some embodiments. In FIG. 19, a carrier substrate 402 is provided, and an integrated circuit die 405 is attached to the carrier substrate 402. A release layer 404 can be formed on the carrier substrate 402. The carrier substrate 402 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 402 can be a wafer, so that multiple packages can be formed on the carrier substrate 402 simultaneously. The release layer 404 can be removed together with the carrier substrate 402 from the above structures to be formed in a later step. In some embodiments, release layer 404 is any suitable adhesive, epoxy, die attach film (DAF), or the like, and is applied over the surface of carrier substrate 402.

The integrated circuit die 405 is attached to the carrier substrate 402 using a release layer 404. The desired type and amount of integrated circuit die 405 can be attached to the carrier substrate 102. The integrated circuit die 405 can be the same or similar to the active device die 50C. For example, each of the integrated circuit die 405 includes a logic die (eg, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), Microcontroller, etc.), memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, high bandwidth memory (HBM) die, etc.), input/output (I/O) interface die, power Management die (eg, power management integrated circuit (PMIC) die, etc.), radio frequency (RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (eg, digital (DSP) signal processing (die), etc.), front end die (eg, analog front-end (AFE) die, etc.), etc., or a combination thereof.

As illustrated in FIG. 19, the integrated circuit die 405 can include the same components as the active device die 50C. For example, the integrated circuit die includes a semiconductor substrate 52C, a device 54 on the semiconductor substrate 52C, an ILD 56C surrounding the device 54, and an interconnect structure 60C over the ILD 56C. , A pad 62C on the interconnect structure 60C, a passivation film 64C on the interconnect structure 60C and the pad 62C, a die connector 66C coupled to the pad 62C, and a die connector Dielectric layer 68C surrounding 66C.

In FIG. 20, encapsulant 406 is formed over release layer 404 and surrounds integrated circuit die 405. After formation, encapsulant 406 encapsulates integrated circuit die 405. The encapsulant 406 may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The encapsulant 406 may be applied in a liquid or semi-liquid form and then cured. In some embodiments, encapsulant 406 is formed over carrier substrate 402 such that integrated circuit die 405 is embedded or covered, and then a planarization process is performed on encapsulant 406. The planarization process can planarize the dielectric layer 68C of the integrated circuit die, as well as the encapsulant 406, and expose the die connector 66C of the integrated circuit die 405. The top surfaces of encapsulant 406, die connector 66C, and dielectric layer 68 may be flush with each other after the planarization process. The planarization process can be, for example, chemical-mechanical polish (CMP).

In FIGS. 21-23, a redistribution structure 430 (see FIG. 23) having a fine-featured portion 414 and a coarse-featured portion 426 (see FIG. 23) is encapsulant 406 ) And an integrated circuit die 405. Redistribution structure 430 includes a metallization pattern, a dielectric layer, and UBM. The metallization pattern may also be referred to as a redistribution layer or redistribution line. Redistribution structure 430 is shown as an example with four metallization pattern layers. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 430. If fewer dielectric layers and metallization patterns are formed, the steps and processes described below can be omitted. If more dielectric layers and metallization patterns are formed, the steps and processes described below can be repeated. The fine features 414 and roughly features 426 of the redistribution structure 430 include different sized metallization patterns and dielectric layers.

In FIG. 21, fine features 414 of redistribution structure 430 are formed. The fine features 414 of the redistribution structure 430 include dielectric layers 408 and 411, and metallization patterns 410 and 412. In some embodiments, dielectric layers 408 and 411 are formed from the same dielectric material and are formed from the same thickness. Likewise, in some embodiments, the conductive features of metallization patterns 410 and 412 are formed of the same material and are formed of the same thickness. Specifically, the dielectric layers 408 and 411 have a first thickness T ₁ , which is small, eg, in the range of about 5 μm to about 40 μm, and the conductive features of the metallization patterns 410 and 412 have a second thickness T ₂ . And is small in the range of about 1 μm to about 25 μm.

As an example of forming the fine features 414 of the redistribution structure 430, a dielectric layer 408 is deposited over the encapsulant 406, dielectric layer 68C, and die connector 66C. In some embodiments, dielectric layer 408 is formed of a photosensitive material, such as PBO, polyimide, BCB, etc., that can be patterned using a lithography mask. Dielectric layer 408 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 408 is then patterned. The patterning forms an opening exposing a portion of the die connector 66C. Patterning can be accomplished by an acceptable process, such as by exposing the dielectric layer 408 to light when the dielectric layer 408 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 408 is a photosensitive material, the dielectric layer 408 can be developed after exposure.

Then, a metallization pattern 410 is formed. The metallization pattern 410 has a line portion (also referred to as a conductive line or trace) extending along it on the major surface of the dielectric layer 408, and is physically attached to the die connector 66C of the integrated circuit die 405. And a via portion (also referred to as a conductive via) that extends through dielectric layer 408 to electrically couple. By way of example, metallization pattern 410 can be formed by forming a seed layer over dielectric layer 408 and in openings extending through dielectric layer 408. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, using physical vapor deposition (PVD) or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 410. Patterning forms openings through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the bottom portion of the seed layer forms a metallization pattern 410. Portions of the seed layer and photoresist on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, the exposed portion of the seed layer is removed using an acceptable etching process such as wet or dry etching.

Then, a dielectric layer 411 is deposited over the metallization pattern 410 and the dielectric layer 408. Dielectric layer 411 may be formed in a similar manner to dielectric layer 408, and may be formed of a material similar to that of dielectric layer 408. Then, a metallization pattern 412 is formed. The metallization pattern 412 has a line portion extending along it on the major surface of the dielectric layer 411 and vias extending through the dielectric layer 411 to physically and electrically couple to the metallization pattern 410 Have a part. The metallization pattern 412 may be formed in a manner similar to the metallization pattern 410, and may be formed of a material similar to that of the metallization pattern 410. The fine features 414 are illustrated as including two dielectric layers and two metallization patterns, however any number of dielectric layers and metallization patterns can be formed in the fine features 414.

In FIG. 22, roughly feature 426 of redistribution structure 430 is formed. Roughly feature 426 of redistribution structure 430 includes dielectric layers 416, 420 and 424, and metallization patterns 418 and 422. In some embodiments, dielectric layers 416, 420 and 424 are formed of the same dielectric material and are formed of the same thickness. Likewise, in some embodiments, the conductive features of the metallization patterns 418 and 422 are formed of the same material and are formed of the same thickness. Specifically, dielectric layers 416, 420, and 424 have a third thickness T ₃ , which is large, for example, in the range of about 5 μm to about 40 μm, and the conductive features of the metallization patterns 418 and 422 have a fourth thickness T ₄ , which is large in the range of about 1 μm to about 25 μm. In various embodiments, the third thickness T ₃ may be greater than the first thickness T ₁ (see FIG. 21 ), and the fourth thickness T ₄ may be greater than the second thickness T ₂ (see FIG. 21 ).

Dielectric layer 416 may be deposited on metallization pattern 412 and dielectric layer 411 to form approximately features 426 of redistribution structure 430. Dielectric layer 416 may be formed in a similar manner to dielectric layer 408, and may be formed of a material similar to that of dielectric layer 408. Then, a metallization pattern 418 is formed. The metallization pattern 418 has a line portion extending along it on the major surface of the dielectric layer 416 and vias extending through the dielectric layer 416 to physically and electrically couple to the metallization pattern 412. Have a part. The metallization pattern 418 may be formed in a manner similar to the metallization pattern 410, and may be formed of a material similar to the material of the metallization pattern 410.

Dielectric layer 420 is then deposited on metallization pattern 418 and dielectric layer 416. Dielectric layer 420 may be formed in a similar manner to dielectric layer 408, and may be formed of a material similar to that of dielectric layer 408. Then, a metallization pattern 422 is formed. The metallization pattern 422 has a line portion extending along it on the major surface of the dielectric layer 420 and vias extending through the dielectric layer 420 to physically and electrically couple to the metallization pattern 418. Have a part. The metallization pattern 422 may be formed in a manner similar to the metallization pattern 410, and may be formed of a material similar to the material of the metallization pattern 410.

A dielectric layer 424 is then deposited on the metallization pattern 422 and dielectric layer 420. Dielectric layer 424 may be formed in a similar manner to dielectric layer 408, and may be formed of a material similar to that of dielectric layer 408. Although roughly feature 426 is illustrated as including three dielectric layers and two metallization patterns, any number of dielectric layers and metallization patterns may be formed in roughly feature 426. In some embodiments, fine features 414 and roughly features 426 can include three dielectric layers and three metallization patterns, respectively.

Coarse feature 426 may have a lower resistance compared to fine feature 414 due to the thickness of the metallization pattern included in coarse feature 426 and fine feature 414. Roughly feature 426 can be used to route the power line due to the lower resistance. The fine features 414 can be used to route signal lines that do not require lower resistance. Including both roughly feature 426 and fine feature 414 minimizes the thickness of redistribution structure 430 while allowing power and signal lines to be routed.

In FIG. 23, UBM 428 is formed for external connection to redistribution structure 430. The UBM 428 has a bump portion extending along it on the major surface of the dielectric layer 424, and a via portion extending through the dielectric layer 424 to physically and electrically couple to the metallization pattern 422. Have As a result, UBM 428 is electrically coupled to integrated circuit die 405. The UBM 428 can be formed in a similar manner to the metallization pattern 410 and from a similar material. In some embodiments, UBM 428 has a different size than metallization patterns 410, 412, 418 and 422.

In FIG. 24, a conductive connector 432 is formed on the UBM 428, forming a SoW package 400A. The conductive connector 432 includes a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, an electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bump , ENIG (electroless nickel-immersion gold technique) formed bumps, and the like. The conductive connector 432 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 432 is formed by first forming a solder layer or solder paste through evaporation, electroplating, printing, solder transfer, ball placement, and the like. If a solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape.

In FIG. 25, the first package 200A and the external connector 434A including the module 160A bonded to the first package component 100A are bonded to the SoW package 400A. In various embodiments, SoW package 400A may be a very large fanout wafer level package with an area of 10,000 mm ² or greater. The first package 200A may be disposed on the SoW package 400A using a pick-and-place machine or the like. When the first package 200A is disposed, the conductive connector 432 and the conductive connector 150 may be reflowed to bond the first package 200A to the SoW package 400A. 25 illustrates the first package 200A attached to the SoW package 400A, the first package 200B or the first package 200C may alternatively or additionally be attached to the SoW package 400A.

In addition, an external connector 434A is attached to the SoW package 400A. The external connector 434A is an electrical and physical interface for the SoW package 400A to other SoW packages 400A, other external systems, and the like. For example, when SoW package 400A is installed as part of a larger external system, such as a data center, external connector 434A can be used to couple SoW package 400A to an external system. Examples of external connectors 434A include large wire bonds, receptors for ribbon cables, flexible printed circuits, and the like. The external connector 434A includes a pad 438 that can be similar to the UBM 428. The external connector 434A can include different components such as chassis, pad 438, and external connection pins, which can include different materials. External connector 434A also includes a conductive connector 436 on pad 438, which can be similar to conductive connector 432. Pad 438 and conductive connector 432 are used for physical and electrical connections to SoW package 400A. Attaching the external connector 434A places the external connector 434A on the SoW package 400A using a pick-and-place machine or the like, and then physically and electrically couples the pad 438 and the UBM 428. It may include reflowing the conductive connector 436 and the conductive connector 432 to ring.

An underfill 440 may be formed to fill the gap between the first package 200A and the SoW package 400A. The underfill 440 may be formed by a capillary flow process after the first package 200A is attached, or may be formed by a suitable deposition method before the first package 200A is attached.

In FIG. 26, the carrier substrate 402 is separated from the encapsulant 406 and the integrated circuit die 405 to form a packaged device 500A. According to some embodiments, bonding separation projects light, such as laser light or UV light, onto the release layer 404 so that the release layer 404 can be decomposed under heat of light to remove the carrier substrate 402. It includes doing.

FIG. 27 illustrates an embodiment in which the first package component 100C is bonded to the SoW package 400A, rather than the first package 200A bonded to the SoW package as illustrated in FIG. 25. The first package component 100C may be disposed on the SoW package 400A using a pick and place machine or the like. When the first package component 100C is disposed, the conductive connector 432 and the conductive connector 150 may be reflowed to bond the first package component 100C to the SoW package 400A. The external connector 434A, which includes the pad 438 and the conductive connector 436, is also bonded to the SoW package 400A using the same method as described above with respect to FIG.

An underfill 440 may be formed to fill the gap between the first package component 100C and the SoW package 400A. The underfill 440 can be formed by a capillary flow process after the first package component 100C is attached, or can be formed by a suitable deposition method before the first package component 100C is attached.

In FIG. 28, the carrier substrate 402 is bonded separated from the encapsulant 406 and the integrated circuit die 405, and a bolt hole 442 is formed through the SoW package 400A. According to some embodiments, bonding separation projects light, such as laser light or UV light, onto the release layer 404 so that the release layer 404 can be decomposed under heat of light to remove the carrier substrate 402. It includes doing. The bolt hole 442 may be formed by a drilling process such as laser drilling or mechanical drilling. The bolt hole 442 can be formed by drilling the outline for the bolt hole 442 using a drilling process, and then removing the material separated by the outline.

In FIG. 29, a module 160B including a spring-type contact 166 is disposed on the first package component 100C to form the first package 200C. Module 160B may be similar or identical to module 160B described above with respect to FIG. 17C, and spring type contact 166 may be identical to spring type contact 166 described above with respect to FIG. 17C. Or similar. The module 160B may be disposed on the first package component 100C using a pick and place machine or the like.

In FIG. 30, a mechanical brace 450A is installed to secure the module 160B to the first package component 100C and the SoW package 400A, forming a packaged device 500B. The mechanical brace 450A is a rigid support that can be formed of a high-rigidity material such as metal, which may include steel, titanium, cobalt, and the like. The mechanical brace 450A is physically engaged with a portion of the module 160B. Using the mechanical brace 450A to clamp the module 160C to the first package component 100C and the SoW package 400A can reduce any warpage in the packaged device 500B. .

The module 160C is fastened with a bolt 452A between the first package component 100C and the mechanical brace 450A. The bolt 452A is threaded through the bolt hole 442 of the SoW package 400 and through the corresponding bolt hole in the mechanical brace 450A. The fastener 454A is screwed to the bolt 452A and is tightened to clamp the module 160C between the first package component 100C and the mechanical brace 450A. The fastener 454A may be, for example, a nut that is threaded to the bolt 452A. The fastener 454A can be tightened on the bolt 452A so that the spring-type contact 166 is compressed. After attachment, a portion of the mechanical brace 450A is disposed between the module 160C and the external connector 434A. The embodiment illustrated in FIG. 30 may not include an underfill disposed between the module 160B and the first package component 100C, and a portion of the module 160B may include a first package component ( 100C).

31 shows, according to an embodiment, the first package 200B (including the module 160A bonded to the first package component 100B), the first package 200D (bonding to the first package component 100B) Packaged device 500C including the module 160C) and the SoW package 400B. The SoW package 400B may be formed in a similar manner to the SoW package 400A, and may be formed of a material similar to the material of the SoW package 400A, but the two regions to which the first packages 200B and 200D are bonded. It may include. In various embodiments, the SoW package 400B may be a very large fanout wafer level package with an area of 10,000 mm ² or more. The first package 200B may be spaced apart from the second package 200D by a distance of about 0.05 mm to about 10 mm, such as about 0.5 mm.

The first packages 200B and 200D may be disposed on the SoW package 400B using a pick and place machine or the like. When the first packages 200B and 200D are disposed, the conductive connectors 432 and the conductive connectors 150 may be reflowed to bond the first packages 200B and 200D to the SoW package 400B. 31 illustrates the first packages 200B and 200D attached to the SoW package 400B, but any combination of the first packages 200A-200D may alternatively or additionally be attached to the SoW package 400B. have. An underfill 440 may be formed to fill the gap between the first package 200B and 200D and the SoW package 400B. The underfill 440 may be formed by a capillary flow process after the first packages 200B and 200D are attached, or may be formed by a suitable deposition method before the first packages 200B and 200D are attached. .

In addition, an external connector 434B is attached to the SoW package 400B. The external connector 434B is an electrical and physical interface for the SoW package 400B to other SoW packages 400B, other external systems, and the like. For example, when SoW package 400B is installed as part of a larger external system, such as a data center, external connector 434B can be used to couple SoW package 400B to an external system. Examples of external connectors 434B include large wire bonds, receptors for ribbon cables, flexible printed circuits, and the like. The external connector 434B includes a pad 438 that can be similar to the UBM 428. The external connector 434B can include different components such as chassis, pad 438 and external connection pins, which can include different materials. The external connector 434B also includes a conductive connector 436 on the pad 438, which can be similar to the conductive connector 432. Pad 438 and conductive connector 432 are used for physical and electrical connections to SoW package 400B. Attaching the external connector 434B uses a pick-and-place machine or the like to place the external connector 434B on the SoW package 400B, then physically and electrically couples the pads 438 and UBM 428. It may include reflowing the conductive connector 436 and the conductive connector 432 to ring.

A mechanical brace 450B is installed to fix the thermal module 460 on the back side of the SoW package 400B. The heat module 460 may be a heat sink, heat spreader, cooling plate, or the like. The mechanical brace 450B is a rigid support that can be formed of a high-rigidity material such as metal, which may include steel, titanium, cobalt, and the like. The mechanical brace 450B is physically engaged with a portion of the SoW package 400B. Using mechanical brace 450B to clamp thermal module 460 to SoW package 400B can reduce any warpage in SoW package 400B.

The thermal module 460 is fastened to the back of the SoW package 400B using bolts 452B. The bolt 452B is screwed through the bolt hole 442 formed in the SoW package 400B and through the corresponding bolt hole in the mechanical brace 450B. The fastener 454B is screwed to the bolt 452B, and tightened to clamp the thermal module 460 to the SoW package 400B, the SoW package 400B between the mechanical brace 450B and the thermal module 460 Is placed. The fastener 454B may be, for example, a nut screwed to the bolt 452B. After being attached, a portion of the mechanical brace 450B is disposed between the first package 200B and the first package 200B and outside the outer connector 434B.

Before fixing the thermal module 460 and the SoW package 400B together, a thermal interface material (TIM) 462 can be dispensed on the back side of the SoW package 400B, and the thermal module 460 is a SoW package. Physically and thermally coupled to (400B). In some embodiments, TIM 462 is formed from a film comprising indium, thermal grease, thermal sheet, phase change material, combinations thereof, and the like. During fastening, the fastener 454B is tightened to increase the mechanical force applied to the SoW package 400B by the thermal module 460 and the mechanical brace 450B. Fastener 454B is tightened until thermal module 460 applies the desired amount of pressure to TIM 462.

32 illustrates a packaged device 500D comprising a module 160B, a first package component 100C, a mechanical brace 450C, a mechanical brace 450B, a thermal module 460 and a SoW package 400C. do. The SoW package 400C may be formed in a manner similar to the SoW package 400A, and may be formed of a material similar to the material of the SoW package 400A, but the two regions to which the first package component 100C is bonded are formed. It can contain. In various embodiments, the SoW package 400C may be a very large fanout wafer level package with an area of 10,000 mm ² or more.

Each of the first package components 100C may be disposed on the SoW package 400C using a pick-and-place machine or the like. When the first package component 100C is disposed, the conductive connector 432 and the conductive connector 150 may be reflowed to bond the first package component 100C to the SoW package 400C. 25 illustrates first packages 200B and 200D attached to SoW package 400B, any combination of first packages 200A-200D may alternatively or additionally be attached to SoW package 400B. . An underfill 440 may be formed to fill the gap between the first package component 100C and the SoW package 400C. The underfill 440 can be formed by a capillary flow process after the first package component 100C is attached, or can be formed by a suitable deposition method before the first package component 100C is attached.

In addition, an external connector 434B is attached to the SoW package 400C. The external connector 434B is an electrical and physical interface for the SoW package 400C to other SoW packages 400C, other external systems, and the like. For example, when the SoW package 400C is installed as part of a larger external system such as a data center, the external connector 434B can be used to couple the SoW package 400C to the external system. Examples of external connectors 434B include large wire bonds, receptors for ribbon cables, flexible printed circuits, and the like. The external connector 434B includes a pad 438 that can be similar to the UBM 428. The external connector 434B can include different components such as chassis, pad 438 and external connection pins, which can include different materials. The external connector 434B also includes a conductive connector 436 on the pad 438, which can be similar to the conductive connector 432. Pad 438 and conductive connector 432 are used for physical and electrical connections to SoW package 400C. Attaching the external connector 434B uses a pick-and-place machine or the like to place the external connector 434B on the SoW package 400C, then physically and electrically couples the pads 438 and UBM 428. It may include reflowing the conductive connector 436 and the conductive connector 432 to ring.

Each of the modules 160B may be disposed on the respective first package component 100C using a pick and place machine or the like. Then, a mechanical brace 450C is installed to secure each of the modules 160B to their respective first package components 100C, forming the first package 200C. The mechanical brace 450C is a rigid support that can be formed of a high-rigidity material such as metal, which may include steel, titanium, cobalt, and the like. The mechanical brace 450C is physically engaged with a portion of the module 160B. Using the mechanical brace 450C to clamp the module 160B to the first package component 100C and the SoW package 400C can reduce any warpage in the packaged device 500D.

The module 160B is fastened with a bolt 452C between the first package component 100C and the mechanical brace 450C. The bolt 452C is screwed through the bolt hole 442 of the SoW package 400C and through the corresponding bolt hole in the mechanical brace 450C. The fastener 454C is screwed to the bolt 452C and is tightened to clamp the module 160B between the first package component 100C and the mechanical brace 450C. The fastener 454C may be, for example, a nut screwed to the bolt 452C. The fastener 454C can be tightened on the bolt 452C such that the spring-type contact 166 is compressed. After attachment, a portion of the mechanical brace 450C is disposed between the first package component 100C and between the first package component 100C and the external connector 434B.

A mechanical brace 450B is installed to secure the thermal module 460 to the back of the SoW package 400C. The mechanical brace 450C can also secure the thermal module to the back of the SoW package 400C. The heat module 460 may be a heat sink, heat spreader, cooling plate, or the like. The mechanical brace 450B is a rigid support that can be formed of a high-rigidity material such as metal, which may include steel, titanium, cobalt, and the like. The mechanical brace 450B is physically engaged with a portion of the SoW package 400C. Using mechanical brace 450B to clamp thermal module 460 to SoW package 400C can reduce any warpage in SoW package 400C.

The thermal module 460 is fastened to the back of the SoW package 400C using bolts 452B. The bolt 452B is screwed through the bolt hole 442 formed in the SoW package 400C and through the corresponding bolt hole in the mechanical brace 450B. The fastener 454B is screwed to the bolt 452B, tightened to clamp the thermal module 460 to the SoW package 400C, and the SoW package 400C is between the mechanical brace 450B and the thermal module 460. Is placed. The fastener 454B may be, for example, a nut screwed to the bolt 452B. After attachment, a portion of the mechanical brace 450A is placed outside the external connector 434B.

Before fastening the thermal module 460 and the SoW package 400C together, a thermal interface material (TIM) 462 may be dispensed on the back side of the SoW package 400C, and the thermal module 460 is SoW. It is physically and thermally coupled to the package 400C. In some embodiments, TIM 462 is formed from a film comprising indium, thermal grease, thermal sheet, phase change material, combinations thereof, and the like. During fastening, fasteners 454B and 454C are tightened to increase the mechanical force applied to SoW package 400C by thermal module 460 and mechanical braces 450B and 450C. Fasteners 454B and 454C are tightened until thermal module 460 applies the desired amount of pressure to TIM 462.

33-38 illustrate top-down views of SoW package 400 according to various embodiments. In the embodiment illustrated in FIGS. 33-35, the SoW package 400 has a circular shape. The SoW package 400 illustrated in FIGS. 33-35 may be an intermediate structure, which may be sawed, diced, etc. to form the SoW package 400 illustrated in FIGS. 36-38. The SoW package 400 includes various integrated circuit dies 405, such as a computing die 405A, a memory die 405B, and an input/output (I/O) die 405C. In some embodiments, the computing die 405A may include a central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like. The memory die 405B may include a high-bandwidth memory (HBM) die, a dynamic random access memory (DRAM) die, a hybrid memory cube (HMC), and the like.

In the embodiment illustrated in FIG. 33, a first package 200 is provided over each of the integrated circuit die 405. The first package 200 may be any first package among the first packages 200A-200E described above. In the embodiment illustrated in FIG. 34, each pair of two memory dies 405B share the first package 200, and each set of four computing dies 405A share the first package 200. do. In the embodiment illustrated in FIG. 35, two of the first packages 200 may be provided for each of the I/O dies 405C, and four first packages 200 of each of the computing dies 405A Can be provided against. Other configurations are possible, and any number of first packages 200 can be provided for any number of integrated circuit dies 405. SoW package 400 further includes an external connector 434.

In the embodiment illustrated in Figures 36-38, SoW package 400 has an octagonal shape. This may allow interconnected SoW packages 400 to be more densely arranged with each other. The SoW package 400 includes various integrated circuit dies 405, such as a computing die 405A, a memory die 405B, and an input/output (I/O) die 405C. In the embodiment illustrated in FIG. 36, a first package 200 is provided on each of the integrated circuit die 405. The first package 200 may be any first package among the first packages 200A-200E described above. In the embodiment illustrated in Figure 37, each pair of two memory dies 405B shares the first package 200, and each set of four computing dies 405A shares the first package 200. do. In the embodiment illustrated in FIG. 38, two of the first packages 200 may be provided for each of the I/O dies 405C, and four first packages 200 of each of the computing dies 405A Can be provided against. Other configurations are possible, and any number of first packages 200 can be provided for any number of integrated circuit dies 405. SoW package 400 further includes an external connector 434.

Providing a packaged device 500 including a first package component 100 (including a die 50 disposed therein) disposed between the module 160 and the SoW package 400 is a first The distance between the IPD included in the package component 100 and the functional die included in the SoW package 400 is reduced. This enhances the power distribution network (PDN) performance. The various embodiments described above include high performance computing (HPC) in data center applications, server applications, etc. (e.g., accelerometers of artificial intelligence (AI) servers, cloud computing systems, edge computing systems, etc.) It may be applicable to.

Other features and processes may also be included. For example, a test structure may be included to assist in 3D packaging or verification testing of 3DIC devices. The test structure can include, for example, a test pad formed on a redistribution layer or on a substrate, which enables 3D packaging or testing of 3DIC, use of probes and/or probe cards, and the like. Verification tests can be performed on the final structure as well as the intermediate structure. In addition, the structures and methods disclosed herein can be used with test methods that incorporate intermediate verification of known good die to increase yield and reduce cost.

According to an embodiment, a device comprises: a first package component, comprising: a first integrated circuit die; A first encapsulant surrounding at least partially the first integrated circuit die; The first package component on the first encapsulant and including a redistribution structure coupled to the first integrated circuit die; A second package component bonded to the first package component, comprising: an integrated passive element; A second package component comprising a second encapsulant at least partially surrounding the integrated passive element; And a power module attached to the first package component through the second package component. In an embodiment, the device further comprises an electrical connector coupled to the redistribution structure, the electrical connector surrounding the second package component. In an embodiment, the second package does not include active elements disposed on the second encapsulant. In an embodiment, the power module is bonded to the second package component using solder bonds. In an embodiment, the power module is coupled to the second package using a spring-type contact. In an embodiment, the device further comprises a mechanical brace extending through the first package component, the mechanical brace contacting the power module, and the mechanical brace connecting the power module to the second Attach to the package component. In an embodiment, the device further includes a thermal module attached to the first package component, the second package component is disposed on a first side of the first package component, and the second package The component is disposed on the second side of the first package component, opposite the first side. In an embodiment, the device further comprises a thermal interface material (TIM) disposed between the thermal module and the first package component, and a mechanical brace attaches the thermal module to the first package component.

According to another embodiment, a method includes forming a first package component, the method comprising: attaching a first integrated passive element to a first redistribution structure; Sealing the first integrated passive element with an encapsulant; Forming a first redistribution structure on the first integrated passive element and the encapsulant, wherein the first package component is formed; Attaching a power module to the second redistribution structure; And bonding the first redistribution structure to a third redistribution structure of a second package component, wherein the second package component includes a first integrated circuit die coupled to the third redistribution structure. . In an embodiment, the method comprises singulating the first package component after attaching the power module to the first package component and before bonding the first package component to the second package component. It further includes. In an embodiment, the power module is attached to the first package component after the first package component is bonded to the second package component. In an embodiment, attaching the power module to the first package comprises placing the power module on the first package component using a pick-and-place machine, and using the mechanical brace And fastening the power module to one package component, the mechanical brace including a bolt extending through the second package component. In an embodiment, the power module includes a spring-type contact, and the mechanical brace applies pressure to the spring-type contact to compress the spring-type contact. In an embodiment, the method further comprises depositing a first underfill material between the power module and a first side of the first package component, and between a second side of the first package component and the second package component. 2 further comprising depositing the underfill material.

According to another embodiment, a device includes a first package comprising a plurality of integrated circuit dies; A plurality of power modules on the first package, each of the power modules being disposed directly above the integrated circuit die in a direction perpendicular to the main surface of the first package; And a plurality of package components interposed between the integrated circuit die and the power module, and each of the package components includes an integrated passive device (IPD). In an embodiment, one of the power modules and one of the package components are disposed on each of the integrated circuit die. In an embodiment, more than one of the power modules and more than one of the package components are disposed on each of the integrated circuit die. In an embodiment, one of the power modules and one of the package components is disposed on more integrated circuit dies than one of the integrated circuit dies. In an embodiment, each of the package components includes a front redistribution structure, wherein the IPD is disposed on the front redistribution structure; An encapsulant disposed on the front redistribution structure and surrounding the IPD; A through via extending through the encapsulant and coupled to the front redistribution structure; And a rear redistribution structure on the through via, the IPD, and the encapsulant, and the rear redistribution structure is coupled to the front redistribution structure through the through via. In an embodiment, the first package has an octagonal shape in a top-down view.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to accomplish the same objectives and/or achieve the same advantages as the embodiments introduced herein. do. Those skilled in the art should also appreciate that such equivalent constructions are not departed from the true meaning and scope of the present disclosure, and various changes, substitutions, and alternatives can be made without departing from the true meaning and scope of the present disclosure.

Example

Example 1. In a device,

As a first package component,

A first integrated circuit die;

A first encapsulant surrounding at least partially the first integrated circuit die;

A redistribution structure on the first encapsulant and coupled to the first integrated circuit die

Including, The first package component;

As a second package component bonded to the first package component,

An integrated passive element;

A second encapsulant at least partially surrounding the integrated passive element

Including, The second package component; And

Power module attached to the first package component through the second package component

Device comprising a.

Embodiment 2 The device of embodiment 1, further comprising an electrical connector coupled to the redistribution structure, the electrical connector surrounding the second package component.

Embodiment 3 The device of embodiment 2, wherein the second package does not include an active element disposed in the second encapsulant.

Embodiment 4 The device of embodiment 1, wherein the power module is bonded to the second package component using a solder bond.

Embodiment 5 The device of embodiment 1, wherein the power module is coupled to the second package using a spring-type contact.

Embodiment 6 The method of Embodiment 5, further comprising a mechanical brace extending through the first package component, wherein the mechanical brace contacts the power module, and the mechanical brace contacts the power module. A device that is attached to a second package component.

Embodiment 7 In Embodiment 1, further comprising a thermal module attached to the first package component, the second package component is disposed on a first side of the first package component, and the first A device in which two package components are disposed on a second side of the first package component, opposite the first side.

Embodiment 8. The method of Embodiment 7, further comprising a thermal interface material (TIM) disposed between the thermal module and the first package component, wherein a mechanical brace attaches the thermal module to the first package component. Device.

Example 9. In a method,

Forming a first package component,

Attaching the first integrated passive element to the first redistribution structure;

Sealing the first integrated passive element with an encapsulant;

Forming a second redistribution structure on the first integrated passive element and the encapsulant

Including, The first package component forming step;

Attaching a power module to the second redistribution structure; And

Bonding the first redistribution structure to a third redistribution structure of a second package component, wherein the second package component comprises a first integrated circuit die coupled to the third redistribution structure. How to be.

Embodiment 10. In Embodiment 9, after attaching the power module to the first package component and before bonding the first package component to the second package component, singulate the first package component. The method further comprising the step of.

Embodiment 11. The method of embodiment 9, wherein the power module is attached to the first package component after the first package component is bonded to the second package component.

Embodiment 12. In Embodiment 11, attaching the power module to the first package comprises placing the power module on the first package component using a pick-and-place machine and mechanically And fastening the power module to the first package component using a brace, wherein the mechanical brace comprises a bolt extending through the second package component.

Example 13. The method of example 12, wherein the power module comprises a spring-type contact, and the mechanical brace applies pressure to the spring-type contact to compress the spring-type contact.

Embodiment 14. The method of embodiment 9, comprising depositing a first underfill material between the power module and the first side of the first package component and between the second side of the first package component and the second package component. Further comprising depositing a second underfill material.

Example 15. In a device,

A first package comprising a plurality of integrated circuit dies;

A plurality of power modules on the first package, each of the power modules being disposed directly above the integrated circuit die in a direction perpendicular to the main surface of the first package; And

And a plurality of package components interposed between the integrated circuit die and the power module, each of the package components comprising an integrated passive device (IPD).

Embodiment 16 The device of embodiment 15, wherein one of the power modules and one of the package components are disposed on each of the integrated circuit die.

Embodiment 17 The device of embodiment 15, wherein more than one of the power modules and more than one of the package components are disposed on each of the integrated circuit die.

Embodiment 18. The device of embodiment 15, wherein one of the power modules and one of the package components are disposed on more integrated circuit dies than one of the integrated circuit dies.

Embodiment 19. In Embodiment 15, each of the package components,

A front redistribution structure, wherein the IPD is disposed on the front redistribution structure;

An encapsulant disposed on the front redistribution structure and surrounding the IPD;

A through via extending through the encapsulant and coupled to the front redistribution structure; And

And a rear redistribution structure on the through via, the IPD, and the encapsulant, wherein the rear redistribution structure is coupled to the front redistribution structure through the through via.

Embodiment 20. The device of embodiment 15, wherein the first package has an octagonal shape in a top-down view.

Claims (10)

In the device,
As a first package component,
A first integrated circuit die;
A first encapsulant surrounding at least partially the first integrated circuit die;
A redistribution structure on the first encapsulant and coupled to the first integrated circuit die
Including, The first package component;
As a second package component bonded to the first package component,
An integrated passive element;
A second encapsulant at least partially surrounding the integrated passive element
Including, The second package component; And
Power module attached to the first package component through the second package component
Device comprising a. The device of claim 1, further comprising an electrical connector coupled to the redistribution structure, the electrical connector surrounding the second package component. The device of claim 2, wherein the second package does not include active elements disposed on the second encapsulant. The device of claim 1, wherein the power module is bonded to the second package component using a solder bond. The device of claim 1, wherein the power module is coupled to the second package using a spring-type contact. The method according to claim 5, further comprising a mechanical brace (mechanical brace) extending through the first package component, the mechanical brace is in contact with the power module, the mechanical brace is the power module to the second package component Device to attach. The method according to claim 1, further comprising a thermal module attached to the first package component, the second package component is disposed on the first side of the first package component, the second package component is the A device that is disposed on a second side of the first package component, opposite the first side. The device of claim 7, further comprising a thermal interface material (TIM) disposed between the thermal module and the first package component, wherein a mechanical brace attaches the thermal module to the first package component. In the way,
Forming a first package component,
Attaching the first integrated passive element to the first redistribution structure;
Sealing the first integrated passive element with an encapsulant;
Forming a second redistribution structure on the first integrated passive element and the encapsulant
Including, The first package component forming step;
Attaching a power module to the second redistribution structure; And
Bonding the first redistribution structure to a third redistribution structure of a second package component, wherein the second package component comprises a first integrated circuit die coupled to the third redistribution structure. How to be. In the device,
A first package comprising a plurality of integrated circuit dies;
A plurality of power modules on the first package, each of the power modules being disposed directly above the integrated circuit die in a direction perpendicular to the main surface of the first package; And
And a plurality of package components interposed between the integrated circuit die and the power module, each of the package components comprising an integrated passive device (IPD).

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