KR20200081180A - Flash memory storage device and operating method thereof - Google Patents

Abstract

A flash memory storage device according to an embodiment of the present invention comprises: a compressor compressing input data to generate first data; a pattern generator coupling specific pattern data to the first data to generate second data; an ECC encoder generating a parity code by using the second data; a memory cell array storing the second data and the parity code therein; an ECC decoder correcting an error of the second data provided from the memory cell array; a pattern canceller cancelling specific pattern data of the second data whose error has been corrected; and a compression canceller cancelling the compression of data, from which the specific pattern is removed, to generate data which is to be output. An embodiment of the present invention can enhance reliability of the flash memory storage device by correcting the error after data compression and data reconfiguration.

Description

FLASH MEMORY STORAGE DEVICE AND OPERATING METHOD THEREOF}

An embodiment relates to a flash memory storage device storage device and a driving method for improving the error correction capability of data.

In order to use the flash memory as a storage device, a separate error correction technique is required. This means that the flash memory stores data by trapping or emptying electrons in the floating gate between the oxide layers, but when the number of electrons in the floating gate changes due to the leakage of electrons in the floating gate or the influence of adjacent cells at an unintended point, This is because the existing data may be damaged.

Flash memory storage devices generally correct data errors using an ECC having a fixed error correction capability. ECC's error correction capability is determined by considering the BER (Bit Error Rate) that can occur until the P/E (Program/Erase) cycle of the flash memory reaches a limit in the product design stage.

However, in order to use a flash memory in a system requiring high reliability, a robust error correction technique capable of correcting unpredictable data errors occurring in exceptional situations is required.

An object of the present invention is to provide a flash memory storage device capable of correcting a data error exceeding the ECC error correction capability and a method of driving the same.

The flash memory storage device according to an embodiment compresses the input data to generate first data, a pattern generator to generate second data by combining specific pattern data with the first data, and the second data. An ECC encoder for generating a parity code by using, a memory cell array for storing the second data and the parity code, an ECC decoder for correcting errors in the second data provided from the memory cell array, and correcting the error It may include a pattern decompressor to remove the specific pattern data of the second data, and a decompressor to decompress the data from which the specific pattern data is removed to generate data to be output.

The size of the specific pattern data may be determined by a difference between the input unit of the ECC encoder and the compressed first data.

The specific pattern data may include a fixed pattern such as 0,1 or an adaptive pattern that minimizes cell interference according to a data pattern of surrounding data cells.

The location where the specific pattern data is combined may include a front, back or intermediate point of the first data.

The specific pattern data may be combined with the first data at a plurality of points.

The specific pattern data may be combined at a location where a frequency of error occurrence is high.

The memory cell array may include a data cell area storing the second data and a parity cell area storing the parity code.

The ECC decoder may remove errors in the specific pattern data before correcting errors in the second data.

The specific pattern data may be overwritten with the second data to eliminate errors in the specific pattern data.

The ECC decoder may correct an error remaining in the second data by using the parity code after removing an error of specific pattern data existing in the second data.

In addition, the data storage method of the flash memory storage device according to an embodiment may include compressing input data to generate first data, and combining the compressed first data with specific pattern data to generate second data. And generating a parity code using the second data, and storing the second data and the parity code.

The size of the specific pattern data may be determined by a difference in size between the input unit of the ECC encoder and the compressed second data.

The specific pattern data may be combined with the first data at a plurality of points.

The specific pattern data may be combined at a location where a frequency of error occurrence is high.

In addition, a method of reading data from a flash memory storage device according to an embodiment includes reading compressed data and parity codes combined with specific pattern data from a memory cell array, and correcting errors in compressed data provided from the memory cell array. The method may include removing specific pattern data of the compressed data in which the error is corrected, and removing and outputting compressed data from which the specific pattern data is removed.

And overwriting the specific pattern data before correcting the error of the data.

After the step of overwriting the specific pattern data, an error remaining in the data may be corrected using the parity code.

The embodiment has an effect of improving reliability of a flash memory storage device by correcting errors after data compression and data reconstruction.

In addition, the embodiment has an effect of maximizing the error correction effect by allowing the error in the data to be corrected in two steps.

In addition, the embodiment removes the primary error using specific pattern data, and then uses all of the error correction capabilities to correct errors in the remaining data, thereby improving the reliability of error correction.

1 is a block diagram schematically illustrating a flash memory storage device according to an embodiment.
2 is a diagram illustrating a structure in which specific pattern data of a flash memory storage device according to an embodiment is disposed.
3 is a flowchart illustrating a data storage method of a flash memory storage device according to an embodiment.
4 is a view for explaining FIG. 3.
5 and 6 are flowcharts illustrating a method of reading data from a flash memory storage device according to an embodiment.
7 is a view for explaining FIG. 5.

The present invention can be applied to various changes and can have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each drawing, similar reference numerals are used for similar components.

Terms such as first, second, A, and B can be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from other components. For example, the first component may be referred to as a second component without departing from the scope of the present invention, and similarly, the second component may be referred to as a first component. The term and/or includes a combination of a plurality of related described items or any one of a plurality of related described items.

When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but there may be other components in between. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle.

The terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “include” or “have” are intended to indicate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, and that one or more other features are present. It should be understood that the existence or addition possibilities of fields or numbers, steps, operations, components, parts or combinations thereof are not excluded in advance.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms, such as those defined in a commonly used dictionary, should be interpreted as having meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application. Does not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a flash memory storage device according to an embodiment, and FIG. 2 is a view showing a structure in which specific pattern data of a flash memory storage device according to an embodiment is disposed.

The flash memory storage device of the embodiment may include a solid state drive (SSD), an embedded multimedia card (eMMC), or universal flash storage (UFS). However, the flash memory storage device of the present embodiment is not limited to the devices listed above, and it can be understood that the flash memory storage device may be various types of storage devices based on flash memory.

The flash memory storage device of the embodiment may have a structure in which new data is generated using compressed data and specific pattern data, and errors are removed using the generated new data using specific pattern data and parity codes. From this, the flash memory storage device of the embodiment can improve error correction capability and improve reliability.

Hereinafter, a flash memory storage device according to an embodiment will be described in more detail.

Referring to FIG. 1, a flash memory storage device according to an embodiment includes a compressor 110, a pattern generator 120, an ECC encoder (encoder, 130), a memory cell array 140, an ECC decoder (150), and a pattern A decompressor 160 and a decompressor 170 may be included.

The compressor 110 serves to compress data input to the flash memory storage device. The compressor 110 compresses the size of the input data to a predetermined size, thereby generating first data having a size smaller than the input data.

The pattern generator 120 serves to generate second data rules using the compressed first data. The pattern generator 120 may generate second data by combining specific pattern data with the compressed first data. That is, the second data may be data including first data and specific pattern data. The size of the specific pattern data can be determined by Equation (1).

In the specific pattern data, all bits may be formed in a fixed pattern such as 0,1. As for the specific pattern data, an adaptive pattern in which interference between cells can be minimized may be selected according to the data pattern of neighboring data cells.

As shown in FIG. 2A, the specific pattern data PD may be combined before or after the first data D1. Alternatively, as illustrated in FIG. 2B, the specific pattern data PD may be formed of a plurality of patterns, and the plurality of patterns may be combined with the first data D1. Alternatively, as illustrated in FIG. 2C, the specific pattern data PD may be combined with the first data D1 at an intermediate point of the first data D1.

The location of the specific pattern data PD is not limited to this, and may be formed at various locations. The combined position of the specific pattern data PD may be arranged in a region in which an error occurrence frequency is high. Areas with a high frequency of errors can be determined by empirical experimentation.

When a specific pattern data PD is formed in an area in which an error is frequently generated, an area in which errors can be removed from the entire data is reduced, so that error correction can be effectively performed. That is, the ECC decoder 150 can use all of the error correction capabilities to correct errors existing in the second data area other than the specific pattern data DP, thereby improving the reliability of error correction.

The ECC encoder 130 serves to encode (or encode) the input data. The ECC encoder 130 may include a plurality of input terminals and a plurality of output terminals.

The ECC encoder 130 may form a parity code using the second data generated from the pattern generator 120. The ECC encoder 130 may generate parity codes corresponding to the second data. The parity code generated by the ECC encoder 130 can be used to detect and correct errors generated in the process of writing data to or reading data from the memory cell array. The parity code may be formed in a 1-bit size, for example, but is not limited thereto.

The parity code may include, for example, a plurality of parity codes. The plurality of parity codes may include codes having different error correction capabilities and error correction rates. For example, any one of the plurality of parity codes may be a code having a relatively high error correction capability and a relatively slow error correction rate. On the other hand, any one of the plurality of parity codes may be a code having a relatively low error correction capability and a relatively fast error correction rate.

The memory cell array 140 may store software and/or programs. The program may include a kernel, middleware, application, programming interface (API), and/or application program. At least a portion of the kernel, middleware or API may be referred to as an operating system (OS).

The memory cell array 140 may include a data cell 141 storing second data. The data cell 141 may include a plurality of cells. The memory cell array 140 may include parity cells 142 that store parity codes. The parity cell 142 may include a plurality of cells.

The ECC decoder 150 may decode (or decode) second data stored in the memory cell array 140. The ECC decoder 150 may include a plurality of input terminals and a plurality of output terminals. The ECC decoder 150 may detect an error included in the second data and correct the detected error using the parity code stored in at least one of the memory cell arrays 140.

The ECC decoder 150 according to an embodiment may remove errors in specific pattern data before correcting errors in the second data by the parity code.

The ECC decoder 150 may overwrite the second pattern with specific pattern data by using the information, size, and location information of the specific pattern data generated from the pattern generator 120. When there is an error formed in the specific pattern data included in the second data, when the specific pattern data is overwritten in the second data as described above, the error in the specific pattern data may be eliminated.

The ECC decoder 150 can use all of the error correction capabilities to correct errors existing in the remaining area of the second data other than specific pattern data, thereby improving the error correction capability.

The pattern canceller 160 serves to remove specific pattern data. The pattern canceller 160 may remove specific pattern data of the second data from which the error has been removed. The pattern canceller 160 may generate only the first data from which the specific pattern data is removed by removing the specific pattern data from the second data. The pattern releaser 160 may receive specific pattern data information and size locations from the pattern generator 120 to remove specific pattern data.

The decompressor 170 may decompress the first data to generate data to be output. Due to this, the data to be output may be larger than the size of the first data.

Hereinafter, a data storage method of a flash memory storage device according to an embodiment will be described in more detail with reference to the drawings.

3 is a flowchart illustrating a data storage method of a flash memory storage device according to an embodiment, and FIG. 4 is a diagram for describing FIG. 3.

3 and 4, a method of storing data in a flash memory storage device according to an embodiment is a step of compressing input data (S110) and a second pattern of a new pattern by combining the compressed first data and specific pattern data. Step S120 of generating data and step S130 of generating a parity code using the second data may be performed.

First, when data is input, step S110 of compressing the input data may be performed. The step of compressing the input data ID may be performed in the compressor. The input data ID may store software and/or programs. The program may include a kernel, middleware, application, programming interface (API), and/or application program. The size of the compressed first data D1 may be smaller than the size of the input data ID.

Subsequently, a step (S120) of generating the second data D2 by combining the first data D1 and the specific pattern data PD may be performed. The step of generating the second data D2 may be performed in the pattern generator.

In the specific pattern data PD, all bits may be formed in a fixed pattern such as 0, 1 or an adaptive pattern. The specific pattern data PD may be combined with the first data D1 between the back of the first data D1 and the first data D1. The location where the specific pattern data PD is formed may be a region in which an error occurrence frequency is high.

Accordingly, the second data D2 may be a structure in which the first data D1 and the specific pattern data PD are combined. Here, the size of the specific pattern data PD may be determined by a difference between the input unit of the ECC encoder and the compressed first data D1.

Subsequently, a step of generating a parity code (PC) using the second data D2 may be performed. The generation of the parity code (PC) may be performed by the ECC encoder.

The parity code PC may be inserted at the end of the second data D2 to determine whether the second data D2 is correct. The parity code PC may be formed, for example, in a size of 1 bit.

As described above, when the parity code PC is generated, the generated second data D2 and the parity code PC may be stored in the memory cell array. The second data D2 may be stored in a data cell of the memory cell array, and the parity code PC may be stored in a parity cell of the memory cell array.

5 and 6 are flowcharts for explaining a method of reading data from a flash memory storage device according to an embodiment, and FIG. 7 is a diagram for describing FIG. 5.

Referring to FIG. 5, a method of reading data from a flash memory storage device according to an embodiment includes reading data from a memory cell array (S210), and correcting errors in data provided from the memory cell array (S220), The step of removing the specific pattern data of the error corrected data (S230) and the step of outputting the data by removing the compression of the compressed data from which the specific pattern data is removed may be performed (S240).

First, a step (S210) of reading data from the memory cell array may be performed. The step of reading data may be performed by the ECC decoder. The data may include second data and parity codes. The second data may be a structure in which compressed first data and specific pattern data are combined.

Subsequently, a step (S220) of correcting an error in data may be performed. The ECC decoder may perform the step of correcting data errors. Data errors can be corrected in two steps.

6 and 7, correcting an error in data (S220) includes removing an error in specific pattern data (S221) and removing an error in data (S222 ). Can be.

As shown in FIG. 7A, when errors e1 and e2 occur in the second data D2, the second data D2 is generated using information, size, and location information of specific pattern data provided by the pattern generator. A specific pattern data DP can be overwritten by a specified position and size.

Accordingly, the error e1 generated in the specific pattern data DP is removed to remove the error (S211 ).

As illustrated in FIG. 7B, when the error e1 of the specific pattern data DP is removed, the error e2 is still present in the remaining second data D2 area. The ECC decoder corrects an error existing in the second data D2 area remaining all of the error correction capabilities of the parity code (PC). Accordingly, as illustrated in FIG. 7C, all errors of the second data can be eliminated.

Returning to FIG. 5, when the step of correcting an error in the data is completed, a step (S230) of removing specific pattern data may be performed. The pattern canceller may perform the removal of specific pattern data. In order to remove the specific pattern data, the position and size data of the specific pattern data may be provided from the pattern generator to remove the specific pattern data included in the second data.

Subsequently, a step (S240) of outputting the decompressed data may be performed. The decompressor may perform the step of outputting the decompressed data. The size of data to be output may be larger than the size of compressed data.

As described above, when the compression is decompressed, the decompressed data can be output.

The embodiment has an effect of improving reliability of the flash memory by correcting errors after data compression and data reconstruction.

In addition, the embodiment has an effect of maximizing the error correction effect by allowing the error in the data to be corrected in two steps.

In addition, the embodiment removes the primary error using specific pattern data, and then uses all of the error correction capabilities to correct errors in the remaining data, thereby improving the reliability of error correction.

110: compressor
120: pattern generator
130: ECC encoder
140: memory cell array
150: ECC decoder
160: pattern releaser

Claims (17)

A compressor that compresses the input data to generate first data;
A pattern generator that generates second data by combining specific pattern data with the first data;
An ECC encoder for generating a parity code using the second data;
A memory cell array storing the second data and the parity code;
An ECC decoder to correct errors in the second data provided from the memory cell array;
A pattern canceler to remove specific pattern data of the second data in which the error is corrected; And
And a decompressor that generates data to be output by removing compression of the data from which the specific pattern data is removed. According to claim 1,
The size of the specific pattern data is determined by a difference in size between the input unit of the ECC encoder and the compressed first data. According to claim 1,
The specific pattern data is a flash memory storage device including a fixed pattern such as 0, 1 or an adaptive pattern that minimizes cell interference according to a data pattern of surrounding data cells. According to claim 1,
The location where the specific pattern data is combined includes a front, back or intermediate point of the first data. According to claim 4,
The specific pattern data is a flash memory storage device that is combined with the first data at a plurality of points. According to claim 1,
The specific pattern data is a flash memory storage device that is coupled to a location with a high frequency of errors. According to claim 1,
The memory cell array includes a data cell area for storing the second data and a parity cell area for storing the parity code. The method according to any one of claims 1 to 7,
The ECC decoder removes errors in the specific pattern data before correcting errors in the second data. The method of claim 8,
A flash memory storage device that removes errors in the specific pattern data by overwriting the specific pattern data with the second data. The method of claim 9,
The ECC decoder is a flash memory storage device that corrects an error remaining in the second data using the parity code after removing an error of specific pattern data existing in the second data. Compressing the input data to generate first data;
Generating second data by combining the compressed first data with specific pattern data;
Generating a parity code using the second data; And
And storing the second data and the parity code. The method of claim 11,
The size of the specific pattern data is determined by the difference between the input unit of the ECC encoder and the size of the compressed second data. The method of claim 12,
The specific pattern data is a data storage method of a flash memory storage device that is combined with the first data at a plurality of points. The method of claim 13,
The specific pattern data is a data storage method of a flash memory storage device that is coupled to a location with a high frequency of errors. Reading compressed data and parity codes combined with specific pattern data from the memory cell array;
Correcting an error in compressed data provided from the memory cell array;
Removing specific pattern data of the compressed data in which the error is corrected; And
And decompressing the compressed data from which the specific pattern data has been removed, and outputting the compressed data. The method of claim 15,
And overwriting the specific pattern data before correcting the error in the data. The method of claim 16,
A method of reading data from a flash memory storage device that corrects an error remaining in data using the parity code after the step of overwriting the specific pattern data.

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