KR20200068387A - Stdp learning hardware - Google Patents

Abstract

Disclosed is an STDP learning hardware. The STDP learning hardware, according to an embodiment of the present invention, comprises: a pre-neuron; a post-neuron; an NVM circuit that transmits a signal from the pre-neuron to the post-neuron and changes conductance based on a recording pulse; an STDP time generator outputting a first output signal reflecting a metastability time determined according to a voltage difference between the voltage of the pre-neuron and the voltage of the post-neuron; and a control signal and recording pulse generator for generating the recording pulse whose pulse width is variable according to the first output signal, and applying the recording pulse to the NVM circuit.

Description

STDP LEARNING HARDWARE

The present invention relates to STDP learning hardware capable of performing STDP learning using meta-stability of a comparator.

The brains of organisms contain neurons as billions of units of neurons, which form a complex neural network. The neurons exert their intellectual abilities as creatures by sending and receiving signals through synapses with thousands of other neurons.

The neuron is a structural and functional unit of the nervous system and a basic unit of information transmission. A synapse refers to a junction between the neurons and refers to a region where axons of one neuron and dendrites of another neuron are connected. Neuromorphic hardware is a semiconductor circuit created by simulating the information processing method processed by the brain by producing an artificial nervous system that simulates these biological neural networks at the neuron level. These neuromorphic hardware can be manufactured as electronic circuits using semiconductors.

The neuromorphic hardware, like the brain of a living creature, can be effectively used to implement an intelligent system that can adapt itself to an unspecified environment. For example, it can be applied as an interface for performing recognition and estimation, such as text recognition, speech recognition, risk recognition, real-time high-speed signal processing, and eventually, computers, robots, home appliances, small mobile devices, security, and It can be applied to fields such as surveillance systems and intelligent vehicles.

Among the neuromorphic hardware, the Spiking Neural Network (SNN) hardware reads the information transmitted to each layer in the form of spikes or pulses, and reads the synapse weight. ) Or a kind of artificial neural network hardware that can be written.

On the other hand, in order to train a Spiking Neural Network (SNN), an algorithm capable of updating a synaptic weight for a spike or pulse signal of a neuron is required.

On the other hand, non-volatile memory (NVM), which is a memory device that can function as a synapse in a Spiking Neural Network (SNN), is mainly based on a Spike Time Dependent Plasticity (STDP) learning rule. The conductance is updated. Here, updating the conductance of the non-volatile memory (NVM) may correspond to updating the weight of the synapse.

In STDP, on the other hand, according to the spike time difference between the pre-neuron and post-neuron, the conductance, that is, how much the weight of the synapse will be updated is determined.

On the other hand, the characteristics of the Spiking Neural Network (SNN), compared to the Artificial Neural Network (ANN), can process a large amount of computation with higher energy efficiency in a more similar way to the biological brain.

In particular, learning of a Spiking Neural Network (SNN) using a Spike Time Dependent Plasticity (STDP) learning rule is different from that of an artificial neural network (ANN). information), it is more efficient than back-propagation-based learning in the artificial neural network.

In addition, in Spiking Neural Network (SNN), non-volatile memory (NVM) devices having memristor characteristics such as ReRAM and PCM are STDP (SDP) rather than conventional digital memory such as SRAM. Spike Time Dependent Plasticity) may be suitable for implementing learning rules.

In this case, the non-volatile memory (NVM) device used as a synapse device is mainly written with a programming pulse, and the number of applied pulses or the pulse width The amount of change in conductance can be adjusted with (pulse-width).

On the other hand, in the Spike Time Dependent Plasticity (STDP) learning rule, the amount of change in the weight of the spike or pulse time information according to the STDP (Spike Time Dependent Plasticity) learning rule It requires calculation and operation to convert to (Δw).

Currently, research is being conducted on learning algorithms, such as the Spiking Neural Network (SNN), which can learn Spike Time Dependent Plasticity (STDP) learning rules, but studies that implement STDP with hardware Each is not standardized, and has some disadvantages in implementing the advantages of a Spiking Neural Network (SNN).

Specifically, in the first prior literature (Bruno U. Pedroni, et al., “Forward Table-based Presynaptic Event-triggered Spike-timing-dependent Plasticity”, 2016 IEEE Biomedical Circuits and Systems, 2016), using Configuration memory , Creating a look-up table for STDP timing, and discloses the application of the Δw value according to Δt.

And the second prior document (US 2017/0185890 A1, Jun. 29, 2017) discloses a neuromorphic system that implements digital STDP.

However, in the same manner as in the first prior document, since the amount of weight update according to STDP is digitally determined, a lookup table defining the amount of weight update according to spike time Since this is necessary, there is a disadvantage that an additional digital memory must be used.

In addition, the same method as the second prior literature also has a problem in that a timer for measuring spike time and an additional memory for storing the timer are required.

Meanwhile, the third prior literature (Jose M. Cruz-Albrecht, et al., “Energy efficient Neuron, Synapse and STDP Integrated Circuit”, IEEE Transactions on Biomedical Circuits and Systems, Vol. 6, pp.246-256, 2012.) And in the fourth prior literature (S. Mitra, et al., “Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI, Vol. 3, pp.32-42, 2009.) Analogue STDP circuit is implemented using ΔV according to the difference in pulse time between -neuron and post-neuron.

When Δw is determined in an analog manner such as the third and fourth publications, many circuits such as an amplifier having high power consumption are required to calculate Δw according to spike timing. Therefore, there is a disadvantage that the power consumption of the circuit is large, and additional time for updating the weight is required.

Meanwhile, S. Kim, et al., “NVM Neuromorphic Core with Phase Change Memory Synaptic Array with On-chip Neuron Circuits for Continuous In-situ Learning, 2015 International Electron Devices Meeting (IEDM) pp.17.1.1 -17.1.4, 2015.) designed and applied the STDP pulse shape to have the STDP behavior in order to train the ReRAM device according to the STDP learning rules.

Meanwhile, in the sixth prior document (US 2010/0299296A1, Nov. 25, 2010), in order to program an inactive memory device, two spikes having correlations are generated and applied to both ends of the device to implement STDP.

Also, the seventh precedent literature (S. Kim, et al., “On Spike-timing-dependent-plasticity, Memristive Devices, and Building a Self-learning Visual Cortex, Frontier Neuroscience, Vol. 4, pp.26, 2011.) And in the eighth prior literature (US 2013/0311415 A1, Nov. 21, 2013), in order to train the memristor element according to the STDP learning rule, a spike circuit that creates an STDP pulse shape is a neuron circuit. I am designing with.

In the case of implementing the STDP by the spike method as in the fifth prior document, the sixth prior document, the seventh prior document, and the eighth prior document, the spike capable of making the STDP must be implemented, and when it is implemented in a circuit There was a problem in that an additional spike generator circuit was required for the Integrate and Fire neuron.

The present invention is intended to solve the above-mentioned problems, and an object of the present invention relates to STDP learning hardware capable of performing STDP learning in a simple manner using meta-stability of a comparator.

STDP learning hardware according to an embodiment of the present invention, a pre-neuron, a post-neuron, an NVM circuit that transmits a signal from a pre-neuron to a post-neuron and changes conductance based on a recording pulse, the voltage of the pre-neuron and the post-neuron STDP time generator for outputting a first output signal reflecting a metastable time (metastability time) determined according to the voltage difference of the voltage, and, the pulse width is varied according to the first output signal to generate the recording pulse , A control signal for applying the write pulse to the NVM circuit and a write pulse generator.

1 is a circuit diagram for explaining STDP learning hardware according to an embodiment of the present invention.
2 to 4 are diagrams for explaining the operation of the dynamic comparator 410 according to an embodiment of the present invention.
5 to 7 are diagrams for explaining the operation of the STDP time generator 400 in more detail.
8 is a diagram showing a detailed configuration of a control signal and a recording pulse generator.
9 is a diagram showing a time diagram of control signals and signals generated by the recording pulse generator.
10 is a view for explaining the operation of the NVM circuit according to the output of the write pulse, the first switch signal, and the second switch signal.
FIG. 11 is a diagram comparing conventional STDP learning with STDP learning using a meta-stability time proposed in the present invention.
FIG. 12 shows that the STDP curve is approximated by a curve plotting the quasi-stability time of the dynamic comparator with respect to the difference of the input voltage.
13 to 15 are views showing simulation results according to an embodiment of the present invention.

Hereinafter, exemplary embodiments disclosed herein will be described in detail with reference to the accompanying drawings, but the same or similar elements will be given the same reference numbers regardless of the reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed only considering the ease of writing the specification, and do not have meanings or roles that are distinguished from each other. In addition, in describing the embodiments disclosed in this specification, detailed descriptions of related well-known technologies are omitted when it is determined that the gist of the embodiments disclosed herein may obscure the subject matter. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed in the specification is not limited by the accompanying drawings, and all modifications included in the spirit and technical scope of the present invention , It should be understood to include equivalents or substitutes.

Terms including ordinal numbers such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from other components.

When an element is said to be "connected" to or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but may exist in the middle. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle.

Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as "comprises" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts or combinations thereof described in the specification, but one or more other features. It should be understood that the existence or addition possibilities of fields or numbers, steps, operations, components, parts or combinations thereof are not excluded in advance.

Prior to presenting an embodiment of the invention, a learning algorithm is introduced. The Spike-Timing-Dependent Plasticity (STDP) algorithm is an algorithm that can implement both supervised learning algorithms and unsupervised learning algorithms, and it can update weights using the time difference of spikes without using complex operations.

1 is a circuit diagram for explaining STDP learning hardware according to an embodiment of the present invention.

The STDP learning hardware may include a pre-neuron 100, a post-neuron 200, an NVM circuit 300, an STDP time generator 400 and a control signal and write pulse generator 500.

The NVM circuit 300 may include an inactive memory element 310, a first switch unit, and a second switch unit. Here, the inactive memory device 310 corresponds to a synapse in an actual neural network, and the inactive memory device 310 may be a non-volatile memory (NVM) device having memristor characteristics.

Neurons (Neuron) (100, 200) is a configuration that corresponds to neurons in a real neural network, and may be connected to each other by the NVM circuit 300, such as neurons in a real neural network are connected to each other by synapses.

In this case, the pre-neuron (Pre-Neuron) 100 may be disposed in front of the NVM circuit 300 and connected to the NVM circuit 300, and the post-neuron (Post-Neuron) 200 of the NVM circuit 300 It can be disposed at the rear end and connected to the NVM circuit 300.

In this case, the output terminal of the pre-neuron 100 is connected to one end of the NVM circuit 300, and the input terminal of the post-neuron 200 can be connected to the other end of the NVM circuit 300. .

Pre-Neuron (100) and post-neuron (Post-Neuron) (200) may be composed of an integrator. It can be understood that when a pulse is applied to the integrator for a predetermined time, the output voltage from the integrator continues to increase, and when the output voltage increases to a certain level or more, a neuron is turned on. It may be said that this is fired.

On the other hand, the pre-neuron (Pre-Neuron) 100 and the post-neuron (Post-Neuron) 200 is expressed only as an integrator for simplification, but is not limited thereto.

In this case, the signal output from the free neuron may be transmitted to the post neuron by the NVM circuit 300.

The Spike Time Dependent Plasticity (STDP) learning rule is the most used learning algorithm for learning the Spiking Neural Network (SNN). To implement STDP learning on hardware, spikes of free and post neurons It is necessary to update the weight according to the time difference.

This process can be expressed as the following equation.

(W+: maximum weight value, W-: minimum weight value, τ+: time window to determine the weight update ratio of long-term potentiation (LTP), τ-: long-term depression ( LTD) time window to determine the weight update rate (time window)

Meanwhile, the conductance of the inactive memory device 310 may be changed by an applied voltage or current. Specifically, the conductance of the inactive memory device 310 may be controlled by the number of write pulses applied to both ends of the inactive memory device 310 or the width of the write pulses applied. have.

In this case, write pulses are set write pulses that apply a set voltage to both ends of the inactive memory element 310 and resets both ends of the inactive memory element 310. ) A reset write pulse for applying a voltage may be included.

When a set write pulse is applied to one terminal while a specific voltage is biased to the other terminal, conductance may increase. On the other hand, if a reset write pulse is applied to one terminal while a specific voltage is biased to the other terminal, conductance may decrease.

As described above, the recording operation of the inactive memory device updating the conductance using the time information of the recording pulse, learning of a Spiking Neural Network (SNN) by a Spiking Time Dependent Plasticity (STDP) learning rule Can be useful for

The STDP time generator 400 may output a first output signal reflecting a quasi-stable time determined according to a voltage difference between a voltage of a pre-neuron and a voltage of a post-neuron.

In this case, the STDP time generator 400 is a dynamic comparator 410 and a voltage of a pre-neuron and a voltage of a post-neuron are input, and receives a comparator clock signal CLCK to output a second output signal and a third output signal. The logic gate 420 may output a first output signal by performing logical operation on the second output signal and the third output signal.

In addition, the output terminal of the pre-neuron may be connected to the first input terminal of the dynamic comparator 410, and the output terminal of the post-neuron may be connected to the second input terminal of the dynamic comparator 410.

In addition, the first output terminal and the second output terminal of the dynamic comparator 410 may be connected to the control signal and the recording pulse generator 500.

Also, the first output terminal and the second output terminal of the dynamic comparator 410 may be connected to the input terminal of the logic gate 420, and the output terminal of the logic gate 420 may be a control signal and a write pulse generator 510 of the write pulse generator 500. ).

The control signal and write pulse generator 500 may include a write pulse generator 510 and a control block 520.

Here, the write pulse generator 510 may generate a write pulse using the comparator clock signal and the first output signal and output the write pulse to the memory element 310.

Also, the control block 520 may generate a switch control signal for controlling a switch element in the NVM circuit 300 and output it to the NVM circuit 300.

Meanwhile, the write pulse generator 510 is connected to one end of the inactive memory element 310 so that the write pulse generated by the write pulse generator 510 can be applied to the inactive memory element 310.

Meanwhile, the control block 520 is connected to the first switch unit disposed at the front end of the inactive memory element 310 and the second switch unit disposed at the rear end of the inactive memory element 310, so that the first switch unit and the second switch The switching operation of the switches in the unit can be controlled.

Meanwhile, two external signals may be input to the STDP learning hardware. Specifically, a reset signal for resetting the initial state of the digital circuit and a comparator clock signal CLKC for controlling the operation of the dynamic comparator may be input to the STDP learning hardware.

In this case, a reset signal may be generated by the reset signal generator and input to the control signal and the recording pulse generator 500.

Also, the comparator clock signal CLKC may be generated by the comparator clock signal generator and input to the dynamic comparator 410 and the control signal and write pulse generator 500.

Meanwhile, the frequency of the comparator clock signal CLKC may be adjusted by the control of the comparator clock signal generator, or may be controlled by the control of the control signal and the write pulse generator 500.

2 to 4 are diagrams for explaining the operation of the dynamic comparator 410 according to an embodiment of the present invention.

The present invention is to implement STDP learning by using the metastability time of the dynamic comparator 410.

The dynamic comparator 410 has metastability characteristics. The metastability characteristic means a characteristic in which the output is determined late due to the latch time characteristic of the dynamic comparator even though the comparator clock CLKC of the dynamic comparator is high.

As shown in Figure 2, the dynamic comparator includes a latch circuit.

In addition, when the comparator clock signal CLKC becomes high, currents In and Ip flow through the first transistor Min and the second transistor Mip, respectively, and output voltage of the latch circuit. Depending on the input voltage pair (Vin, Vip), it can be pulled to ground at different rates.

Here, the input voltage pair may be a voltage of a free neuron (ie, a membrane potential of a free neuron) and a voltage of a post neuron (ie, a membrane potential of a post neuron).

This operation can maintain the dynamic comparator in a meta-stable state in which the output of the comparator has not been determined, even though the comparator clock signal CLKC is high.

That is, the metastability time may mean a time in which the dynamic comparator is in a meta-stable state according to a difference between input voltages.

And, referring to FIG. 3, the time that the dynamic comparator is present in the meta-stabilized section changes according to the difference between the two input voltages of the dynamic comparator.

That is, as shown in FIG. 3A, the larger the input voltage difference, the shorter the meta-stability time is, and as shown in FIG. 3B, the smaller the input voltage difference, the lower the meta-stability time is. ) Indicates a longer property.

The meta-stability time (Tcomp) may be determined by the following equation according to the difference between the circuit parameters and the input voltage.

Co: Output capacitance of the dynamic comparator

gm_latch: Transconductance of the latch transistor

gm_in: Transconductance of input transistors M1 and M2

VDD: supply voltage

Vin: difference of input voltage

On the other hand, the meta-stability time (Tcomp) curve for the difference (Vin) of the input voltage shows a non-linear curve characteristic as shown in FIG. 4.

Therefore, a nonlinear STDP learning algorithm can be implemented using a nonlinear quasi-stable time curve. That is, Tcomp can replace the weight update in STDP learning.

That is, both the transfer curve in the conventional transfer curve of STDP learning and the quasi-stable time curve in the dynamic comparator of the present invention have a common characteristic that exhibits nonlinear characteristics.

On the other hand, the difference is that in the conventional STDP learning, the difference in the spike time is used, whereas in the present invention, the weight is updated based on the voltage difference between the membrane potentials of the free and post neurons instead of the time information of the spikes. In the present invention, the conductance of the inactive memory is updated by generating a write pulse having a variable pulse width in order to follow the STDP learning rule.

5 to 7 are diagrams for explaining the operation of the STDP time generator 400 in more detail.

The STDP time generator 400 reflects a first output signal reflecting a metastability time determined according to a voltage difference between the voltage Vpre of the pre-neuron 100 and the voltage Vpost of the post-neuron 200. Can print

Specifically, the voltage Vpre of the pre-neuron 100 and the voltage Vpost of the post-neuron 200 may be input to the dynamic comparator. The difference between the voltage Vpre of the pre-neuron 100 and the voltage Vpost of the post-neuron 200 is caused by the conductance of the inactive memory device, and it is possible to determine the quasi-stable time of the dynamic comparator.

Meanwhile, two output terminals of the dynamic comparator 410 may be connected to the input terminals of the logic circuit 420. Also, two output load capacitors Co may be connected to two output terminals of the dynamic comparator 410, respectively.

Meanwhile, the dynamic comparator 410 may receive the comparator clock signal CLKC and output the second output signal Vcoutp and the third output signal Vcoutn through two output terminals.

On the other hand, the logic circuit 420 may output the first output signal Vcoutp/n by logically calculating the second output signal Vcoutp and the third output signal Vcoutn.

Specifically, the logic circuit 420 may be a NAND gate, and the first output signal Vcoutp/ which becomes high when the second output signal Vcoutp or the third output signal Vcoutn becomes low. n). In this case, the first output signal Vcoutp/n may remain high until the comparator clock signal CLKC becomes low.

The two output load capacitors (Co) can be designed to control the quasi-stable time according to system specifications and device conditions.

The output load capacitor Co is a variable capacitor, and the capacitance of the output load capacitor Co can be varied. In this case, as illustrated in FIG. 7, it can be adjusted to meet various requirements of the memory device.

8 is a diagram showing a detailed configuration of a control signal and a recording pulse generator, and FIG. 9 is a diagram showing a time diagram of signals generated by the control signal and the recording pulse generator.

The control signal and the recording pulse generator 500 may generate a recording pulse having a variable pulse width according to the first output signal, and apply the recording pulse to the NVM circuit.

The control signal and write pulse generator 500 includes a first clock divider 810, a second clock divider 820, a first flip flop 830, a second flip flop 840 and a second logic gate 850. It can contain.

The first clock divider 810 may generate a first clock signal STDP_phase having a frequency of half (1/2) of the comparator clock signal CLKC.

Also, the second clock divider 820 may generate a second clock signal CLKwrite having a frequency of a quarter (1/4) of the comparator clock signal CLKC.

Meanwhile, the control signal and the recording pulse generator 500 may receive the first output signal and generate a recording pulse corresponding to the quasi-stable time using the comparator clock signal and the first output signal.

Specifically, the first flip-flop 830 receives the comparator clock signal CLKC as a clock signal, and receives the first output signal Vcoutp/n as a reset signal, thereby generating a write pulse equal to the quasi-stable time (write_pulse). Can print

Meanwhile, the time Δt indicated by the pulse width of the write pulse write_pulse may mean quasi-stability time.

Specifically, the time Δt indicated by the pulse width of the write pulse (write_pulse) may mean a time difference (t _Vcoutp/n -t _CLKC ) between the first output signal Vcoutp/n and the comparator clock signal CLKC.

Meanwhile, the control signal and the write pulse generator 500 may operate in two steps, determining the polarity of the output of the dynamic comparator and writing to the inactive memory device.

Specifically, during one period of the first clock signal STDP_phase, the dynamic comparator may compare the voltage Vpre of the pre-neuron and the voltage Vpost of the post-neuron twice.

Then, the first half cycle of the first clock signal STDP_phase, that is, the operation in a state where the first clock signal STDP_phase is high will be described.

The first flip-flop 830 receives the comparator clock signal CLKC as a clock signal, and receives the first output signal Vcoutp/n as a reset signal, thereby outputting a write pulse (write_pulse) equal to the quasi-stable time. Can be.

Also, in a period in which the first clock signal STDP_phase is high, the dynamic comparator may determine the polarity of the difference of the input voltage.

In this case, the second flip-flop 840 that receives the second output signal Vcoutp and the third output signal Vcoutn as a clock signal and receives the first clock signal STDP_phase as a reset signal depends on the determined polarity. On the basis of this, the fourth output signal Pp or the fifth output signal Pn may be output high.

On the other hand, when the fourth output signal Pp and the fifth output signal Pn become high, the high may be maintained until one period of the first clock signal STDP_phase ends.

The following describes the second half cycle of the first clock signal STDP_phase, that is, the operation in a state where the first clock signal STDP_phase is low.

The first flip-flop 830 receives the comparator clock signal CLKC as a clock signal, and receives the first output signal Vcoutp/n as a reset signal, whereby a write pulse equal to the quasi-stable time (write_pulse) 910 Can output

Meanwhile, the second logic gate 850 may logically calculate the write pulse (write_pulse) 910 and the fourth output signal Pp to output the first switch signal SWp. Specifically, the 2-1 logic gate 850a is an AND gate, and the 2-1 logic gate 850a is high in a section in which the fourth output signal Pp is high and the write pulse (write_pulse) 910 is present. The first switch signal SWp in the state can be output.

Also, the second logic gate 850 may logically calculate the write pulse (write_pulse) 910 and the fifth output signal Pn to output the second switch signal SWp. Specifically, the 2-2 logic gate 850b is an AND gate, and the 2-2 logic gate 850b is high in a section in which the fifth output signal Pn is high and the write pulse (write_pulse) 910 is present. The second switch signal SWn in the state can be output.

In addition, as the first switch signal SWp or the second switch signal SWn is output while the first clock signal STDP_phase is low, a write pulse write 910 is applied to the inactive memory device. And the conductance of the inactive memory device can be updated.

10 is a view for explaining the operation of the NVM circuit according to the output of the write pulse, the first switch signal, and the second switch signal.

This will be described with reference to FIG. 9 together.

According to FIG. 10A, the NVM circuit 300 includes an inactive memory element 310, a first switch portion 1010 disposed at the front end of the inactive memory element, and a second switch portion 1020 disposed at the rear end of the memory element. can do.

One end of the inactive memory element 310 may be connected to a free neuron to receive a signal output from the free neuron. In addition, one end of the inactive memory device 310 may be connected to the control signal and write pulse generator 500 to receive a write pulse (write_pulse) 910 output from the control signal and write pulse generator 500.

Meanwhile, the first-first switch 1011 of the first switch unit 1010 can control whether a write pulse (write_pulse) 910 is applied to the memory element 310, and remove the first switch unit 1010. The 1-2 switch 1012 may control the signal output from the pre-neuron to be applied to the memory element 310.

Meanwhile, the other end of the inactive memory device 310 may be connected to a post neuron to transmit a signal output from the free neuron to the post neuron. In addition, the other end of the inactive memory device 310 may be connected to a first reference voltage generator that generates a first reference voltage Vrefp to receive a first reference voltage. In addition, the other end of the inactive memory device 310 may be connected to a second reference voltage generator that generates a second reference voltage Vrefn to receive a second reference voltage.

Meanwhile, the 2-1 switch 1021 of the second switch unit 1020 may control that the first reference voltage Vrefp is applied to the memory element 310, and the second of the second switch unit 1020. The -2 switch 1022 may control whether the second reference voltage Vrefn is applied to the memory element 310.

Specifically, the 2-1 switch 1021 may output the first reference voltage Vrefp to the memory device 310 when the first switch signal SWp is high, and the 2-2 switch 1022 may When the second switch signal SWn is high, the second reference voltage Vrefn may be output to the memory element 310.

In addition, the 2-3 switch 1023 of the second switch unit 1020 may control the signal output from the pre-neuron to be transmitted to the post-neuron through the memory element 310.

A period in which the second clock signal CLKwrite is low may be an integration period.

Specifically, the 1-2 switch 1012 and the 2-3 switch 1023 may be closed when the second clock signal CLKwrite is low. Accordingly, both ends of the memory element 310 are connected to the output terminal of the free neuron and the input terminal of the post neuron, and the current generated by the conductance of the memory element may be integrated by the integrator of the post neuron.

Meanwhile, a section in which the second clock signal CLKwrite is high may be an STDP learning section.

Specifically, when the second clock signal CLKwrite is high, the first-first switch 1011 may be closed, and accordingly, the write pulse 910 may be applied to the memory element 310.

In addition, as the first switch signal SWp or the second switch signal Swn is output together with the write pulse 910, the first reference voltage Vrefp or the second reference voltage Vrefn together with the write pulse 910 is output. It may be applied to the memory element 310.

Meanwhile, referring to FIG. 10B, when the first switch signal SWp is high, a voltage difference between a write pulse (write_pulse) and a first reference voltage (Vrefp) is applied to the memory element 310 at both terminals of the memory element 310. It can be input as a set voltage. Accordingly, the conductance of the memory element increases, and the weight can be updated.

On the other hand, when the second switch signal SWn is high, the voltage difference between the write pulse (write_pulse) and the second reference voltage Vrefn is reset to the memory element 310 at both terminals of the memory element 310. Can be entered as Accordingly, the conductance of the memory device is reduced, and the weight can be updated.

FIG. 11 is a diagram comparing conventional STDP learning with STDP learning using a meta-stability time proposed in the present invention.

In conventional STDP learning, there are long-term depression (LTD), a region in which the weight of synapses decreases, and long-term potentiation (LTP), a region in which the weights increase.

On the other hand, the STDP learning hardware proposed in the present invention determines whether a write pulse applied to the inactive memory element is a set pulse or a reset pulse according to the polarity of the comparator output.

FIG. 12 shows that the STDP curve is approximated by a curve plotting the quasi-stability time of the dynamic comparator with respect to the difference of the input voltage.

As described above, quasi-stability time is defined by Equation 2, and conventional STDP learning is defined by Equation 1, and there are four parameters in Equation 2 and Equation 1, respectively.

The STDP learning hardware proposed in the present invention can be designed according to the specifications of STDP learning required by the system, and various STDP learning curves can be implemented by adjusting circuit parameters (parameters of Equation 2).

That is, in order to compare the quasi-stability time of the dynamic comparator with the STDP learning rule, the STDP learning rule can be approximated using the quasi-stability time, and the parameter of the equation defining the quasi-stability time together with the parameters of the equation of STDP learning. By adjusting, various STDP learning curves can be implemented.

13 to 15 are views showing simulation results according to an embodiment of the present invention.

A NVM model implemented in software was used to verify the learning performance of the STDP learning hardware, and simulation results of STDP learning are introduced.

The conductance response model can be defined by the following equation.

Here, G(m) and w may be the standardized conductance of the NVM and the pulse width of the recording pulse. The range of w is from 0 to Max(w), which may be the maximum pulse width of the recording pulse. Also, the value of Max(w) can be determined by the unique characteristics of the recording pulse.

Fig. 13 shows the conductance response curve of the NVM having various values of β (the conductance response model of the NVM to the pulse width of the recording pulse).

In LTP, the conductance increases as the pulse width (top x-axis) increases, whereas in LTD, the conductance decreases as the pulse width (bottom x-axis) increases.

In addition, the NVM model has a linear conductance response when β is 1, and as the β value is changed, the linearity of the conductance update can be adjusted to generate various conductance response curves.

On the other hand, by modeling the conductance response to the pulse width of a memory device, STDP learning proposed in the present invention can be applied.

In FIG. 14, when STDP learning proposed in the present invention is applied, a weight change amount of a memory device according to a difference in input voltage in a comparator is illustrated.

And FIG. 14 shows the SPICE simulation results of the STDP learning generated by the STDP learning hardware proposed in this specification and various conductance response curves of the NVM model.

Conductance responses of LTP and LTD pairs with β of 1, 2, 0.5, 3 and 0.33 were applied to the simulation, respectively.

The implemented transfer curves of STDP learning can be compared with mathematical STDP, and parameters used in mathematical STDP and parameters used in STDP implemented in the present invention are illustrated in FIG. 15.

In conclusion, the STDP learning hardware proposed in the present invention is based on a dynamic comparator in a spike-based neuromorphic system that implements weight using an inactive memory device. The STDP learning rule may be implemented using meta-stability time information, and the weight of an inactive memory device may be learned according to the STDP learning rule.

While the existing STDP learning hardware requires an additional memory or a spike generating circuit of a complex structure, the present invention implements STDP learning by using the quasi-stable characteristics of the comparator.

Therefore, the present invention has an advantage in that an additional digital memory is not required because the lookup table is not used when determining the amount of weight update according to the STDP, as compared to the conventional digital method.

In addition, the present invention, compared to the conventional analog method, does not require an amplifier that consumes a fixed power to calculate the weight update amount according to the spike time (spike timing). That is, STDP learning rules using low power can be implemented only with a dynamic comparator and flip-flop.

In addition, the present invention has an advantage that the STDP learning rule can be implemented using only a single pulse having a pulse width conforming to the STDP, without separately implementing a spike for STDP learning.

In addition, the present invention has an advantage of generating a recording pulse capable of automatically updating the conductance while determining the update amount of the weight according to the STDP learning rule.

The present invention described above can be embodied as computer readable codes on a medium on which a program is recorded. The computer-readable medium includes all types of recording devices in which data readable by a computer system is stored. Examples of computer-readable media include a hard disk drive (HDD), solid state disk (SSD), silicon disk drive (SDD), ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage device. There is this. In addition, the computer may include a control unit 180 of the terminal. Accordingly, the above detailed description should not be construed as limiting in all respects, but should be considered illustrative. The scope of the invention should be determined by rational interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

100: free neuron 200: post neuron
300: NVM circuit 400: STDP time generator
500: control signal and record pulse generator

Claims (11)

Free neurons;
Post neurons;
An NVM circuit that transfers a signal from the pre-neuron to the post-neuron and changes conductance based on the recording pulse;
An STDP time generator outputting a first output signal reflecting a metastability time determined according to a voltage difference between the voltage of the pre-neuron and the voltage of the post-neuron; And
And a control signal and a write pulse generator for generating the write pulse whose pulse width is variable according to the first output signal, and applying the write pulse to the NVM circuit.
STDP learning hardware. According to claim 1,
The STDP time generator,
A dynamic comparator in which the voltage of the pre-neuron and the voltage of the post-neuron are input, and receives a comparator clock signal and outputs a second output signal and a third output signal; And
And a logic gate for logically calculating the second output signal and the third output signal to output the first output signal.
STDP learning hardware. According to claim 1,
The control signal and recording pulse generator,
Receiving the first output signal, and using the comparator clock signal and the first output signal to generate the recording pulse corresponding to the metastable time
STDP learning hardware. According to claim 3,
The control signal and recording pulse generator,
And a first flip-flop receiving the comparator clock signal as a clock signal and receiving the first output signal as a reset signal to generate the write pulse equal to the quasi-stable time.
STDP learning hardware. The method of claim 4,
The control signal and recording pulse generator,
And a first clock divider for generating a first clock signal of 1/2 frequency of the comparator clock signal,
The dynamic comparator,
Determining the polarity of the voltage difference in the section where the first clock signal is high
STDP learning hardware. The method of claim 5,
The control signal and recording pulse generator,
A second receiving the second output signal and the third output signal as a clock signal, receiving the first clock signal as a reset signal, and outputting a fourth output signal or a fifth output signal based on the determined polarity Which includes flip-flops
STDP learning hardware. The method of claim 6,
The control signal and recording pulse generator,
And a second logic gate performing a logical operation on the write pulse and the fourth output signal to output a first switch signal, and performing a logical operation on the write pulse and the fifth output signal to output a second switch signal.
STDP learning hardware. The method of claim 7,
The control signal and recording pulse generator,
And a second clock divider for generating a second clock signal of 1/4 frequency of the comparator clock signal,
The NVM circuit,
And an inactive memory element, a first switch portion disposed at the front end of the inactive memory element, and a second switch portion disposed at the rear end of the memory element,
The first switch unit,
Outputting the write pulse to the memory element in a period in which the second clock signal is high
STDP learning hardware. The method of claim 8,
The second switch unit,
When the first switch signal is high, a first reference voltage is output to the memory element,
When the second switch signal is high, outputting a second reference voltage to the memory element
STDP learning hardware. The method of claim 9,
On both ends of the memory element
When the first switch signal is high, a voltage difference between the write pulse and the first reference voltage is input as the set voltage of the memory element,
When the second switch signal is high, a voltage difference between the write pulse and the second reference voltage is input as a reset voltage of the memory element.
STDP learning hardware. According to claim 2,
The STDP time generator,
Including a variable capacitor connected to the output terminal of the dynamic comparator
STDP learning hardware.

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