KR20200064557A - 3-Level DC-DC Converter Including multi-phase - Google Patents

Abstract

The present invention relates to a technology related to a three-level direct current (DC)-DC converter. The three-level DC-DC converter comprises: a first converting unit including a capacitor and a plurality of switches for charging and discharging the capacitor; a second converting unit connected to an output node of the first converting unit and including an inductor and a switching unit selectively supplying or discharging an output voltage of the first converting unit to the inductor; and an output unit connected to the second converting unit. The first converting unit is composed of a single unit, and the second converting unit is composed of a plurality, thereby allowing the three-level DC-DC converter to include one capacitor.

Description

3-Level DC-DC Converter Including multi-phase

The present invention relates to a power conversion system, and more particularly, to a three-level DC-DC converter having multiple phases.

A DC-DC converter is a device that converts a direct current (DC) voltage source from one voltage level to another. Such a DC-DC converter can be mainly used to convert a power supply voltage to a relatively low operating voltage as the integration density of semiconductor devices decreases. The DC-DC converter is a buck DC-DC converter that generates a low output voltage for a high input voltage, as described above, as well as a boost DC-DC that generates a high output voltage compared to an input voltage. And a buck-boost DC-DC converter that generates a high or low output voltage for the converter and/or input voltage.

A typical DC-DC converter has a disadvantage in that power efficiency is lowered when the ratio of the input voltage to the output voltage is high. Accordingly, a 3-level DC-DC converter has been proposed. The 3-level DC-DC converter may be composed of a phase including a plurality of power switches, flying capacitors, and inductors. By the way, for the voltage conversion operation, a conduction loss and a switching loss may occur due to the driving of the plurality of power switches. Also, in the process of supplying the power voltage to the phase , Output voltage abnormalities and output voltage ripple problems such as overshoot/undershoot may occur. Accordingly, in order to provide a high-quality output voltage, a structure in which a plurality of three-level DC-DC converters use the phases has been proposed.

However, in the case of a multi-phase 3-level DC-DC converter, since a capacitor is provided for each phase, the area of the 3-level DC-DC converter is not only increased, but also due to a mismatch in the charge amount of the capacitor. , There is a problem that the output current difference of the inductor occurs. The difference in output current of the inductor causes a reduction in the power efficiency of the DC-DC converter.

The present invention provides a three-level DC-DC converter capable of improving the area and power efficiency.

A 3-level DC-DC converter according to an embodiment of the present invention is connected to a first converting unit including a capacitor and a plurality of switches for charging and discharging the capacitor, and to an output node of the first converting unit, A second converting unit including an inductor and a switching unit selectively supplying or discharging the output voltage of the first converting unit to the inductor, and an output unit connected to the second converting unit, wherein the first converting unit comprises a single unit The second converting unit is composed of a plurality.

In addition, the 3-level DC-DC converter according to another embodiment of the present invention is a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor sequentially connected in series between an input power supply and a ground power supply. A first converting unit including a flying capacitor connected in parallel with the first NMOS transistor and the upper second PMOS transistor; A plurality of second converting units connected in parallel to the output node of the first converting unit and including an inductor and a switching unit selectively supplying an output voltage of the first converting unit to the inductor; An output unit connected to the second converting unit to provide a load; And a control circuit block for controlling the transistors of the first converting unit and the switching unit of the second converting unit, and the plurality of second converting units are sequentially driven with a phase difference.

According to this embodiment, the first converting unit including the flying capacitor occupying a relatively large area is implemented in a single number, and the second converting unit including the inductor is implemented in a plurality of phases. Accordingly, the area occupied by the converter can be reduced, and the conduction loss can be reduced, thereby improving power efficiency.

In addition, the voltage swing level can be reduced by alternately connecting the PMOS transistor and the NMOS transistor for charging and discharging the flying capacitor in series between the input power supply and the ground power supply.

1 is a circuit diagram showing a 3-level DC-DC converter according to an embodiment of the present invention.
2 is a block diagram showing a control circuit block of a 3-level DC-DC converter according to an embodiment of the present invention.
3 is a view showing output waveforms of modulated signals according to an embodiment of the present invention.
4 is a circuit diagram for explaining the driving of the first converting unit according to an embodiment of the present invention.
5 is a circuit diagram showing a typical three-level DC-DC converter structure.
6A to 6C are timing diagrams of output voltages for each phase of the 3-level DC-DC converter.
7 is a table showing the effective resistance of the charge mode and the discharge mode according to the duty ratio for each phase
8 is a table showing an average resistance according to each duty ratio according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and the ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity of explanation. The same reference numerals refer to the same components throughout the specification.

1 is a circuit diagram showing a DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 1, the DC-DC converter 100 may include a first converting unit 110, a second converting unit 120, and an output unit 130.

The first converting unit 110 may include switches connected in series between the input power Vin and the ground power. For example, the first converting unit 110 includes a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3 sequentially connected between an input power source Vin and a ground power source, and A second NMOS transistor M4 may be included. The first PMOS transistor M1, the first NMOS transistor M2, the second PMOS transistor M3, and the second NMOS transistor M4 are driven by the first to fourth control signals Gsc1, Gsc2, Gsc3, and Gsc4. Optionally turned on. The first to fourth control signals Gsc1, Gsc2, Gsc3, and Gsc4 may be provided in a control circuit block to be described below.

The first PMOS transistor M1, the first NMOS transistor M2, the second PMOS transistor M3, and the second NMOS transistor M4 may have the same mobility characteristics, such that the first PMOS transistor M1 ) And the second PMOS transistor M3 may be formed to have an area of 4N, respectively, and the first NMOS transistor M2 and the second NMOS transistor M4 may be formed to have an area of 2N, respectively. At this time, the first and second PMOS transistors M1 and M3 having an area of 4N and the first and second NMOS transistors M2 and M4 having an area of 2N may each have resistances corresponding to R. In this case, R and N may be positive rational numbers.

Also, the first converting unit 110 may include a flying capacitor (Cfly). The flying capacitor Cfly may be charged by a voltage corresponding to 0.5 times the input voltage Vin. Here, the flying capacitor Cfly may be connected between the connection node of the first PMOS transistor M1 and the first NMOS transistor M2 and the connection node of the second PMOS transistor M3 and the second NMOS transistor M4. . The first converting unit 110 of this embodiment is provided as a single piece. Therefore, only one flying capacitor Cfly is provided in the three-level DC-DC converter 100, thereby reducing the area of the three-level DC-DC converter 100.

As described above, the first converting unit 110 of the present embodiment is between the input power source Vin and the ground power source, the first PMOS transistor M1, the first NMOS transistor M2, and the second PMOS transistor M3. And the second NMOS transistor M4 is alternately connected in series. Accordingly, the output node of the first converting unit 110 may correspond to a connection node of the first NMOS transistor M2 and the second PMOS transistor M3.

The switches of the first converting unit 110 are alternately connected to the PMOS transistor and the NMOS transistor between the input power Vin and the ground power. Accordingly, control signals Gsc1 and Gsc2 for driving the first PMOS transistor and the first NMOS transistor M1 and M2 are swinged in the range of Vin to Vin/2, and the second PMOS transistor and the second 2 NMOS transistor The control signals Gsc3 and Gsc4 for driving (M3, M4) can be swinged at Vin/2 to Vss. In addition, the first converting unit 110 selectively selects the first and second PMOS transistors M1 and M3 so that the flying capacitor Cfly preserves a constant charge to provide a constant output voltage Vsc. Or selectively drive the first and second NMOS transistors M2 and M4. Therefore, the first PMOS transistor M1, the first NMOS transistor M2, the second PMOS transistor M3, and the second NMOS transistor M4 constituting the first converting unit 110 are not operated at the same time. , No shoot-through occurs from the input voltage Vin to the ground voltage Vss. As will be described again below, the first converting unit 110 is used for selective operation of the first PMOS transistor M1, the first NMOS transistor M2, the second PMOS transistor M3, and the second NMOS transistor M4. Accordingly, the voltage Vin-Vf or the capacitor voltage Vf obtained by subtracting the capacitor voltage Vf from the input power supply Vin can be repeatedly output. At this time, since the capacitor voltage Vf corresponds to 0.5 times the input voltage, the first converting unit 110 can continuously output a voltage corresponding to 0.5 times the input power Vin.

The second converting unit 120 may be connected between the output node of the first converting unit 110 and the output unit 130. The second converting unit 120 is configured to include an inductor L, and may be composed of a plurality. The plurality of second converting units 120 may be operated in multiple phases (PH1, PH2, PH3, PH4) to reduce conduction loss and switching loss. The second converting unit 120 driven in multiple phases may be connected in parallel to the output node of the first converting unit 110. The plurality of second converting units 120 may be driven to have, for example, four phase differences, for example, a position difference of 0°, 45°, 90°, and 135°. In addition, the second converting unit 120 in order to switch and discharge the output voltage (Vsc) of the first converting unit 110, between the output node of the first converting unit 110 and the inductor (L), It may include a switching unit (SW). The switching unit SW of the second converting unit 120 may include a third PMOS transistor Mp1 and a third NMOS transistor Mn1. The third PMOS transistor Mp1 includes a drain connected to the output node of the first converting unit 110, a gate receiving the fifth control signal Gp1, and a drain connected to the third NMOS transistor Mn1. Can be. The third NMOS transistor Mn1 may include a drain connected to the drain of the third PMOS transistor Mp1, a gate receiving the sixth control signal Gn1, and a source connected to a ground power supply. In the figure, Vx designates a node to which the drain of the third PMOS transistor Mp1, the drain of the third NMOS transistor Mn1, and the inductor L are connected.

The third PMOS transistor Mp1 and the third NMOS transistor Mn1 may be simultaneously or selectively turned on by the fifth control signal Gp1 and the sixth control signal Gn1. Accordingly, the output voltage Vsc of the first converting unit 110 may be switched to the inductor L as it is, or the ground voltage may be transmitted to the inductor L. The fifth and sixth control signals Gp1 and Gn1 may be generated in the control circuit block similarly to the first to fourth control signals Gsc1 to Gsc4.

The third PMOS transistor Mp1 of the second converting unit 120 may be formed with an area of 2N to have a resistance corresponding to 2R, and the third NMOS transistor Mn1 may have an area of N to have a resistance corresponding to 2R. It can be formed as.

The output unit 130 may be a load including an output capacitor Co, an output resistor R, and a current source Ic. The output capacitor Co and the output resistor R may be connected in series between the output node of the output unit 130 and the ground power supply. The current source Ic can also be connected between the output node and the ground power supply.

The voltage of the output node of the output unit 130 (Vout, hereinafter the output voltage of the DC-DC converter) may be calculated by the following equation.

<Equation 1>

Vout= Duty *Vin *0.5

Accordingly, the duty ratio of the output signal of the 3-level DC-DC converter may be obtained as D=Vout/Vin * 200.

2 is a block diagram showing a control circuit block of a 3-level DC-DC converter according to an embodiment of the present invention. 3 is a view showing output waveforms of modulated signals according to an embodiment of the present invention. 4 is a circuit diagram for explaining the driving of the first converting unit according to an embodiment of the present invention.

Referring to FIG. 2, the control circuit block 200 of the 3-level DC-DC converter 100 includes the phase control unit 140 and the first converting unit 110 that control the driving of the second converting unit 120. It may include a switching control unit 150 for controlling the operation of the switch.

The phase controller 140 may include a signal generator 142 and a driver 144.

The signal generator 142 may be a time-based PID (proportional integral Derivative) device. The PID may include a regulator to output by varying the output voltage Vout according to a change in the load current Iload of the output unit. Also, the signal generator 142 may receive the output voltage Vout and the reference voltage Vref to generate the output clock CKout and the reference clock CKref. The signal generator 142 may generate a plurality of modulated signals PWMs by dividing the reference clock CKref based on the output clock CKout.

Referring to FIG. 3, the signal generation unit 142 is divided into four divided modulation signals (PWM 0°, PWM 45°, PWM 90°, PWM 135°) synchronized with the output clock CKout and the reference clock CKref. Can generate The modulation signals (PWM 0°, PWM 45, PWM 90°, PWM 135°) each have a phase difference of 45° and can be sequentially enabled. For example, it may be a gate signal Gp1 of the third PMOS transistor Mp1 input to each phase PH1 to PH4. In addition, the signal generator 142 inverts the gate signal Gp1 of the third PMOS transistor Mp1 to generate the gate signal Gn1 of the third NMOS transistor Mn1 of each phase PH1 to PH4. Can be.

The driver 144 buffers the modulation signals PWMs output from the signal generator 142 to a level suitable for driving the MOS transistor. The driver 144 may provide the buffered modulated signals to each phase PH1 to PH4, that is, the plurality of second converting units 120. Accordingly, the switches of the plurality of second converting units 120 may be sequentially turned on by buffered modulation signals (PWMs).

The switching control unit 150 may include a division unit 152, a preliminary control signal generation unit 154, and a control signal generation unit 156.

The dividing circuit unit 152 may receive the output clock CKout provided from the signal generator 142 and divide the output clock CKout by 4 to generate a control clock (Fsc, see FIG. 3 ).

The selection circuit unit 154 may receive the control clock Fsc and modulate the control clock Fsc to generate a preliminary control signal pre_S. The preliminary control signal pre_S may include, for example, signals for driving the PMOS transistor and signals for driving the NMOS transistor.

The control signal generation unit 156 receives the preliminary control signal pre_S and level shifts the preliminary control signal pre_S to be in the range of Vin to Vin/2 and Vin/2 to Vss. The control signal generation unit 156 may output the level shifted preliminary control signal pre_S and signals inverted as the first to fourth control signals Gsc1, Gsc2, Gsc3, and Gsc4.

For example, as illustrated in FIGS. 3 and 4, when the control clock Fsc is a high period (①), the preliminary control signal generator 154 and the control signal generator 156 are first and first. The first and fourth control signals Gsc1, Gsc2, Gsc3, and Gsc4 may be generated such that the 2 PMOS transistors M1 and M3 are turned on and the first and second NMOS transistors M2 and M4 are turned off. .

As described above, when the first and second PMOS transistors M1 and M3 are turned on, and the first and second NMOS transistors M2 and M4 are turned off, the first converting unit 110 outputs the capacitor voltage Vf from the input voltage Vin as the limit voltage Vin-Vf as the output voltage Vsc. Since the capacitor voltage Vf corresponds to 0.5 times the input voltage Vin, the first converting unit 110 may substantially output the capacitor voltage Vf.

On the other hand, when the control clock (Fsc) is a low period (②), the preliminary control signal generator 154 and the control signal generator 156 turn off the first and second PMOS transistors M1 and M3, The first to fourth control signals Gsc1, Gsc2, Gsc3, and Gsc4 may be generated to turn on the first and second NMOS transistors M2 and M4. Accordingly, since the first converting unit 1110 turns off the first and second PMOS transistors M1 and M3, and the first and second NMOS transistors M2 and M4 are turned on, the capacitor voltage Vf. Is output as the output voltage Vsc.

As a result, the first converting unit 110 is 0.5 times the capacitor voltage (Vf) of the flying capacitor (Cfly), that is, the input power supply (Vin) of both the high section (①) and the low section (②) of the control clock (Fsc) By outputting the voltage corresponding to, it is possible to maintain auto balancing.

5 is a circuit diagram showing a typical three-level DC-DC converter structure.

Referring to FIG. 5, a typical three-level DC-DC converter 10 includes a plurality of converting units (a plurality of power switches M11, M12, M13, and M14), a flying capacitor (Cfly), and an inductor (L). 20) and a plurality of converting units 20 may be connected to the output unit 30. The plurality of converting units 20 are driven with different phase differences, and may be referred to as a plurality of phases.

The power switch is connected to the first PMOS transistor M11, the second PMOS transistor M12, the first NMOS transistor M13 and the second NMOS transistor M14 sequentially connected between the input power Vin and the ground power. It may be. The first and second PMOS transistors M11 and M12 may be formed with a 2N area to have a resistance of 2R. The first and second NMOS transistors M13 and M14 may be formed with an N area to have a resistance corresponding to 2R.

Table 1 below shows the effective resistance in the charging and discharging modes of the 3-level DC-DC converter 100 according to the embodiment of the present invention (FIG. 1), and the general 3-level DC-DC shown in FIG. A table comparing the effective resistances of the charging and discharging modes of the converter 10.

Effective resistance when charging Cfly1 in Figure 5 Effective resistance when discharging Cfly1 of Figure 5 Effective resistance when charging Cfly of Figure 1 Effective resistance when discharging Cfly of Figure 1 Single phase selection 4R 4R 4R 2R 2 phase selection 2R 2R 3R R 3 phase selection 4R/3 4R/3 8R/3 2R/3

Referring to Table 1, while one of the converting units 20 of FIG. 5 is driven and the flying capacitor Cfly1 is charged, the first and second PMOS transistors M11 of the DC-DC converter 10 of FIG. 5 ,M12) should be turned on. Accordingly, the 3-level DC-DC converter 10 of FIG. 5 has an effective resistance (2R+2R) of 4R.

Meanwhile, one of the second converting units 120 of the 3-level DC-DC converter 100 of FIG. 1 according to an embodiment of the present invention is selectively driven, and the flying capacitor Cfly of the first converting unit 110 In order to be charged, both the first and second PMOS transistors M1 and M3 of the first converting unit 110 and the third PMOS transistor Mp1 of the selected second converting unit 10 must be turned on. Accordingly, the DC-DC converter 100 according to the present embodiment has an effective resistance (R+R+2R) of 4R.

In addition, if one of the converting units 20 of the 3-level DC-DC converter 10 of FIG. 5 is selectively driven and the flying capacitor Cfly1 is discharged, the 3-level DC-DC converter 10 of FIG. 5 The first and second NMOS transistors M13 and M14 of should be turned on. At this time, the 3-level DC-DC converter 10 of FIG. 5 has an effective resistance (2R+2R) of 4R.

Meanwhile, in the three-level DC-DC converter 100 of FIG. 1 in this embodiment, one of the second converting units 120 is selectively driven, and the flying capacitor of the first converting unit 110 is discharged, that is, When the 3-level DC-DC converter 100 needs to output the voltage of the ground power level, the third NMOS transistor Mn1 of the selected second converting unit 120 regardless of driving of the first converting unit 110 ) Only needs to be turned on. Accordingly, the 3-level DC-DC converter 100 of FIG. 1 has a substantially 2R effective resistance (effective resistance of the third NMOS transistor).

In addition, in the 3-level DC-DC converter 10 of FIG. 5, when two converting units 20 are selected with a phase difference, and the flying capacitor Cfly1 is charged, the first and second of the two converting units 20 are charged. Since the second PMOS transistors M11 and M12 are driven at the same time, they have an effective resistance (4R/2, parallel resistance value) of 2R.

Meanwhile, in the 3-level DC-DC converter 100 of FIG. 1 according to the present embodiment, two second converting units 120 connected in parallel are simultaneously selected with a phase difference, and the flying of the first converting unit 110 is performed. When the capacitor Cfly needs to be charged, the first and second PMOS transistors M1 and M3 of the first converting unit 110 are driven, and the third PMOS transistor of the two second converting units 120 ( Mp1) is driven simultaneously. Accordingly, the 3-level DC-DC converter 100 of this embodiment has an effective resistor (R+R+(2R/2)) corresponding to 3R.

In the 3-level DC-DC converter 10 of FIG. 5, when two converting units 20 are selected with a phase difference, and the flying capacitor Cfly1 is discharged, the first of the two converting units 20 connected in parallel And since the second NMOS transistors M13 and M14 are driven respectively, they have an effective resistance of 4R/2R.

Meanwhile, in the 3-level DC-DC converter 100 of FIG. 1 according to the present embodiment, two second converting units 120 connected in parallel are simultaneously selected with a phase difference, and the flying of the first converting unit 110 is performed. To discharge the capacitor Cfly, the third NMOS transistor Mn1 of the two selected second converting units 120 is driven, and the DC-DC converter 100 has an effective resistance of R(2R/2). .

If three of the converting units 20 of the 3-level DC-DC converter 10 of FIG. 5 are selected with a phase difference, and the flying capacitor Cfly1 needs to be charged, the three converting units 20 in parallel Since the first and second PMOS transistors M11 and M12 are driven respectively, the DC-DC converter 10 has an effective resistance of 4R/3.

Meanwhile, in the three-level DC-DC converter 100 of FIG. 1 according to the present embodiment, three second converting units 120 connected in parallel are selected at the same time, and the flying capacitor Cfly of the first converting unit 110 ), the first and second PMOS transistors M1 and M3 of the first converting unit 110 and the third PMOS transistor Mp1 of the three second converting units 120 connected in parallel are simultaneously Turns on. Accordingly, the 3-level DC-DC converter 100 of FIG. 1 has an effective resistor (R+R+(2R/3)) corresponding to 8R/3.

When three of the converting units 20 of the DC-DC converter 10 of FIG. 5 are simultaneously selected with a phase difference and the flying capacitor Cfly1 needs to be discharged, the DC-DC converter 10 of FIG. 5 is in parallel. Since the first and second NMOS transistors M13 and M14 of the three connected converting units 20 are simultaneously driven, they have an effective resistance of 4R/3.

Meanwhile, in the DC-DC converter 100 of FIG. 1 according to the present exemplary embodiment, three second converting units 120 connected in parallel are simultaneously selected, and the flying capacitor Cfly of the first converting unit 110 is discharged. When it is to be done, the third NMOS transistor Mn1 of the three second converting units 120 connected in parallel is simultaneously driven. Accordingly, the DC-DC converter 100 of FIG. 1 according to the present embodiment has an effective resistance of 2R/3.

6A to 6C are timing diagrams of output voltage for each phase of the DC-DC converter. 7 is a table showing the effective resistance of the charge mode and the discharge mode according to the duty ratio for each phase.

6A shows that when the duty ratio of the output voltage is 25% or less, the first second converting unit (PH1: 0°, or less first phase), the second second converting unit (PH2: 45° or less, second phase), It is a timing diagram showing the output voltage Vout of the third second converting unit (PH3: 90°, below, third phase) and the fourth second converting unit (PH4: 135°, below, fourth phase).

Referring to FIG. 6A, when the dubi ratio D of the output voltage Vout is 25% or less, the first phase PH1 is enabled at a high level, and thus corresponds to the charging mode C of the flying capacitor Cfly , Since the remaining second to fourth phases PH2 to PH4 are disabled at a low level, they correspond to the discharge mode DI of the flying capacitor Cfly.

Referring to FIG. 7, when the duty ratio D of the output voltage Vout is 25% or less, the charging mode of the 3-level DC-DC converter 10 of FIG. 5 and the DC-DC converter 100 of FIG. 1 The effective resistors of (C) are single phase selected, respectively, as described in Table 1 above, and may correspond to 4R, which is an effective resistor when the flying capacitor Cfly is charged.

In addition, when the duty ratio D of the output voltage Vout is 25% or less, the discharge mode of the 3-level DC-DC converter 10 of FIG. 5 and the 3-level DC-DC converter 100 of FIG. 1 ( Each of the effective resistors of DI) has effective resistors of 4R/3 and 2R/3, which are the effective resistors when three phases are selected simultaneously and the flying capacitor Cfly is discharged (see Table 1).

FIG. 6B shows the first phase (PH1: 0°), the second phase (PH2: 45°), the third phase (90°:PH3) and the fourth phase (when the duty ratio of the output voltage is greater than 25% and less than 50%) This is a timing chart showing the output voltage (Vout) of PH4:135°.

Referring to FIG. 6B, when the output voltage Vout has a duty ratio D of more than 25% and less than 50%, the first phase PH1 and the second phase PH2 are enabled high, so charging It corresponds to the mode (C), the third phase (PH3) and the fourth phase (PH4) is a discharge mode (DI) because it is disabled low.

Accordingly, referring to FIG. 7, when the duty ratio D of the output voltage Vout is greater than 25% and less than 50%, the 3-level DC-DC converter 10 of FIG. 5 and the DC-DC converter of FIG. 1 The effective resistance of the charging mode (C) of (100) corresponds to the effective resistance values of 2R and 3R when the flying capacitor Cfly is charged while the two phases of Table 1 are simultaneously selected.

When the duty ratio D of the output voltage Vout is greater than 25% and less than 50%, the discharge mode of the 3-level DC-DC converter 10 of FIG. 5 and the 3-level DC-DC converter 100 of FIG. 1 The effective resistance of (DI) corresponds to 2R and R, which are effective resistance values when the flying capacitors are discharged while two phases of Table 1 are simultaneously selected.

6C, when the duty ratio of the output voltage Vout is greater than 50% and less than 75%, the first phase (PH1: 0°), the second phase (PH2: 45°), the third phase (PH3: 90°) and the first It is a timing chart showing the output voltage of 4 phases (PH4:135°).

Referring to FIG. 6C, when the output voltage Vout has a duty ratio D of more than 50% and 75% or less, the first phase PH1 to the third phase PH3 are enabled and charged, It corresponds to the mode (C), and the fourth phase (PH4) is a discharge mode (DI) because it is disabled low.

Referring to FIG. 7, when the duty ratio D of the output voltage Vout is greater than 50% and less than 75%, the 3-level DC-DC converter 10 of FIG. 5 and the 3-level DC-DC converter of FIG. 1 As shown in Table 1, the effective resistance of the charging mode (C) of (100) corresponds to 4R/3 and 8R/3, which are effective resistances when the flying capacitor Cfly is charged while three phases are simultaneously selected. .

Meanwhile, when the duty ratio D of the output voltage Vout is greater than 50% and less than 75%, the 3-level DC-DC converter 10 of FIG. 5 and the 3-level DC- of FIG. 1 The effective resistances of the discharge mode DI of the DC converter 100 have effective resistances of 4R and 2R, which are effective resistance values when the flying capacitor Cfly is discharged while a single phase is driven (see Table 1).

8 is a table showing an average resistance according to each duty ratio according to an embodiment of the present invention.

Referring to FIG. 8, in the case of a duty ratio of 25% or less, the average resistance of the 3-level DC-DC converter 10 of FIG. 5 is 4R, which is the effective resistance value of the charging mode, and 4R/3, which is the effective resistance value of the discharge mode. Corresponds to the parallel resistance value of (4R ∥ 4R/3), the 3-level DC-DC converter 100 according to the present embodiment is the effective resistance value of 4R in the charging mode and the effective resistance value of 2R/3 in the discharge mode. Has a parallel resistance value of (4R∥4R/3). Accordingly, compared with the general three-level DC-DC converter 10, the average resistance of the three-level DC-DC converter 100 of this embodiment is reduced by about 40% in a duty ratio section of 25% or less. .

In the case of a duty ratio of more than 25% and less than 50%, the average resistance of the 3-level DC-DC converter 10 in FIG. 5 is a parallel resistance value of 2R, which is an effective resistance value of the charging mode and 2R, which is an effective resistance value of the discharge mode ( 2R∥2R), and the 3-level DC-DC converter 100 according to the present embodiment has a parallel resistance value of 3R, which is an effective resistance value in the charging mode and R, which is an effective resistance value in the discharge mode (3R∥R) Corresponds to Accordingly, compared with the general three-level DC-DC converter 10, the three-level DC-DC converter 100 of the present embodiment has an average resistance of about 25% in a Dubi ratio section of more than 25% and less than 50% It is reduced.

On the other hand, in the case of a duty ratio of more than 50% and 75% or less, the average resistance of the DC-DC converter 10 of FIG. 5 is a parallel resistance value of 4R/3, which is an effective resistance value of the charging mode and 4R, which is an effective resistance value of the discharge mode. Corresponding to (4R/3∥4R), the DC-DC converter 100 of FIG. 1 according to this embodiment has a parallel resistance value of 8R/3, which is an effective resistance value in the charging mode, and 2R, which is an effective resistance value in the discharge mode. It corresponds to (8R/3∥2R). Accordingly, when compared with the general DC-DC converter 10, the average resistance of the DC-DC converter 100 of this embodiment may increase by about 12% in a duty ratio period of more than 50% and less than 75%. .

At this time, the conduction loss of the 3-level DC-DC converter may be expressed by the following equation.

<Equation 2>

Conduction loss = I ₀ ² * average resistance (I ₀ is output current)

Accordingly, when the 3-level DC-DC converter 100 is implemented as in the embodiment of the present invention, since the effective resistance value is reduced by 25% or more in a duty ratio section of 50% or less, the conduction loss can be reduced. .

According to this embodiment, the first converting unit including the flying capacitor occupying a relatively large area is implemented in a single number, and the second converting unit including the inductor is implemented in a plurality of phases. Accordingly, the area occupied by the converter can be reduced, and the conduction loss can be reduced, thereby improving power efficiency.

In addition, the voltage swing level can be reduced by alternately connecting the PMOS transistor and the NMOS transistor for charging and discharging the flying capacitor in series between the input power supply and the ground power supply.

The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical spirit of the present invention. Do.

100: 3-level DC-DC converter 110: first converting unit
120: second converting unit 130: output unit

Claims (18)

A first converting unit including a capacitor and a plurality of switches for charging and discharging the capacitor;
A second converting unit connected to the output node of the first converting unit and including an inductor and a switching unit selectively supplying or discharging the output voltage of the first converting unit to the inductor; And
And an output part connected to the second converting part,
The first converting unit is composed of a single,
The second level converter is a three-level DC-DC converter consisting of a plurality. According to claim 1,
The first converting unit,
A first PMOS transistor, a first NMOS transistor, a second PMOS transistor and a second NMOS transistor connected in series between the input power supply and the ground power supply,
The capacitor is connected between the connection node of the first PMOS transistor and the first NMOS transistor and the connection node of the second PMOS transistor and the second NMOS transistor,
The first and second PMOS transistors are turned on by a voltage swinging from a voltage corresponding to 0.5 times the input power level to a voltage level of the capacitor,
The first and second NMOS transistors are three-level DC-DC converters that are turned on by a voltage swinging from the capacitor voltage level to the ground power level. According to claim 1,
The first and second PMOS transistors are formed with an area of 4N to have a resistance corresponding to R (where R and N are positive rational numbers).
The first and second NMOS transistors are three-level DC-DC converters formed with an area of 2N to have a resistance corresponding to the R. According to claim 1,
A three-level DC selectively driving the first and second PMOS transistors and the first and second NMOS transistors so as to conserve the charge of the capacitor so that the output signal of the first converting unit continuously outputs a constant voltage. -DC converter. The method of claim 4,
The first converting unit is a three-level DC-DC converter configured to selectively output a voltage of 0.5 times the voltage of the input power or the capacitor voltage. The method of claim 4,
A third-level DC-DC converter further comprising a switching control unit generating first to fourth control signals for driving the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor. . The method of claim 6,
The switching control unit,
A divider configured to divide the output clock generated based on the output voltage of the output portion to generate a control clock;
A selection circuit unit for modulating the control clock to generate a preliminary control signal for selecting the first and second PMOS transistors and a preliminary control signal for selecting the first and second NMOS transistors; And
The first control signal for driving the first PMOS transistor by adjusting the operation level of the preliminary control signals, the second control signal for driving the second PMOS transistor, and the third control signal for driving the first NMOS transistor And a control signal generator for generating a fourth control signal for driving the second NMOS transistor. According to claim 1,
The switching unit of the second converting unit,
A third PMOS transistor connected to the output node of the first converting unit; And
And a third NMOS transistor connected between the third PMOS transistor and a connection node of the inductor and the ground power supply. The method of claim 8,
The switching units of the plurality of second converting units are sequentially driven with a predetermined phase difference, respectively, a three-level DC-DC converter. The method of claim 9,
Each of the switching units of the plurality of second converting units is a 3-level DC-DC converter sequentially driven with a phase difference of 45°. The method of claim 8,
The third PMOS transistor is formed with an area of 2N to have a resistance corresponding to 2R,
The third NMOS transistor is a 3-level DC-DC converter formed of an area of N to have a resistance corresponding to the 2R. The method of claim 8,
A third-level DC-DC converter further comprising a phase control unit for generating fifth and sixth control signals for driving the third PMOS transistor and the fourth NMOS transistor. The method of claim 12,
Signal generation by receiving the output voltage and reference voltage of the output unit, generating an output clock and a reference clock, dividing the output clock and the reference clock, and generating a plurality of modulated signals sequentially enabled with a phase difference part; And
A 3-level DC-DC converter including a driver for buffering the modulated signals and providing them to the plurality of second converters. According to claim 1,
The output unit includes a capacitor connected to the output node of the second converting unit, a resistor connected between the capacitor and the ground power supply, and a 3-level including a current source connected between the output node of the second converting unit and the ground power supply DC-DC converter. A first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor connected in series between the input power supply and the ground power supply, and the first NMOS transistor and the second PMOS transistor connected in parallel. A first converting unit including a flying capacitor;
A plurality of second converting units connected in parallel to the output node of the first converting unit and including an inductor and a switching unit selectively supplying an output voltage of the first converting unit to the inductor;
An output unit connected to the second converting unit to provide a load; And
And a control circuit block controlling transistors of the first converting unit and a switching unit of the second converting unit,
The plurality of second converters are three-level DC-DC converters sequentially driven with a phase difference. The method of claim 15,
The switching unit of the second converting unit,
A third PMOS transistor connected to the output node of the first converting unit; And
And a third NMOS transistor connected between the third PMOS transistor and a connection node of the inductor and the ground power supply. The method of claim 15,
The control circuit block,
A switching control block generating first to fourth control signals such that the first and second PMOS transistors are selectively operated or the first and second NMOS transistors are selectively operated; And
A three-level DC-DC converter including a phase control block for generating a control signal, so that the switching portion of the plurality of second converting portions are sequentially turned on with a phase difference. The method of claim 17,
The switching control block and the phase control block are three-level DC-DC converters configured to generate the first to fourth control signals and the control signals based on the output voltage of the output unit.

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