KR20200057658A - Anti-fuse memory cell - Google Patents

Abstract

The present disclosure relates to an anti-fuse memory cell operated by light which comprises: a photodiode that receives light and generates current; an anti-fuse including an insulating layer; a switch provided between the photodiode and the anti-fuse in order to prevent high current from flowing or not flowing through the anti-fuse; and an output unit outputting an output signal according to the state of the anti-fuse. When a high current flows through the anti-fuse, the anti-fuse breaks the insulating layer due to the high current.

Description

Anti-fuse memory cell {ANTI-FUSE MEMORY CELL}

The present disclosure relates to an anti-fuse memory cell as a whole, in particular to an anti-fuse memory cell having a simple circuit without external circuitry and programming.

Here, background technology is provided in connection with the present disclosure, and this does not necessarily mean prior art.

1 is a view showing an example of a non-volatile anti-fuse memory cell proposed in Japanese Patent Publication No. 5997711.

Disclosed is a nonvolatile anti-fuse memory cell. In one embodiment, the memory cell is comprised of a one-time programmable N-channel diode connectable transistor. In this example, the polysilicon gate of the transistor has two parts. One portion is highly doped in the second portion of the gate. The impurity used in this example is an N-type impurity. The transistor further has a source with two parts, so that one part of the source is highly doped in the second part of the source. In this example, the source is also doped using N-type impurities.

In this embodiment, a portion physically close to the source of the gate is lighter doped than the other portions of the polysilicon gate. The portion of the source that is physically close to the lightly doped portion of the polysilicon gate is lightly doped with respect to the other portion of the source. When the transistor is programmed (e.g. by applying 6 volts to the gate and 0 volts to the source), rupture in the oxide is most likely to occur in the heavily doped portion of the polysilicon gate.

When the gate is uniformly doped, rupture can occur even near the source. When rupture occurs near the source, word lines and bit lines may be shorted. In this example, by shorting the word line to the bit line, the cell becomes inoperable, thereby increasing the gain and power used on the integrated circuit on which the transistor is placed. Defects of this kind are described in further detail below.

FIG. 1 (a) illustrates one embodiment of four programmable nonvolatile anti-fuse memory cells. Each memory cell (110, 112, 114, 116) includes a one-time programmable N-channel diode connectable transistor (102, 104, 106, 108). The sources of the transistors 102 and 106 are electrically connected to the bit line BL1, and the sources of the transistors 104 and 108 are electrically connected to the bit line BL2. The gates of transistors 102 and 104 are electrically connected to word line WL1, and the gates of transistors 106 and 108 are electrically connected to word line WL2. The one-time programmable N-channel diode connectable transistors 102, 104, 106, and 108 shown in Fig. 1A are not programmed. Since these are not programmed, transistors 102, 104, 106 and 108 have no drain.

1 (b) is a schematic diagram of one embodiment of four non-volatile anti-fuse memory cells in which two memory cells are programmed. In this example, memory cells 110 and 116 are programmed. Memory cells can be programmed by applying high voltage pulses not encountered during normal operation at the gate of the transistor to break down the insulating layer (eg, oxide) between the gate and the substrate. (3.5 nm thick oxide, about 6V). The positive voltage on the transistor gate forms an inverted channel in the substrate under the gate, passing a tunneling current through the insulating layer. This current creates an additional trap in the oxide, increasing the current through the insulating layer, and finally melting the insulating layer, forming a conductive channel from the gate to the substrate. The current required to form the drain diode is about 100 μA / 100 nm2, and breakdown occurs at about 100 μs.

FIG. 2 is a diagram showing an example of an anti-fuse OTP memory cell having performance improvement and a manufacturing method and a method of manufacturing the memory, as disclosed in Japanese Patent No. 6096237.

The nonvolatile memory is a memory that retains the stored information even when the power supply is cut off. Non-volatile memory is classified into read-only memory (ROM), one-time programmable memory (OTP memory), and rewritable memory. In addition, with advances in semiconductor memory technology, non-volatile memory can be mounted with a process such as a complementary metal oxide semiconductor (CMOS) device.

The above-described OTP memory can be divided into a fuse type and an anti-fuse type. The fused OTP memory is short circuited before it is programmed and open circuit after it is programmed. Conversely, an anti-fuse type OTP memory is an open circuit before it is programmed, and a short circuit after it is programmed. In addition, based on the characteristics of a metal-oxide semiconductor (MOS) device in the CMOS manufacturing process, an anti-fuse type OTP memory can be integrated into the CMOS manufacturing process.

In addition, the OTP memory unit forms a permanent conductive path in the ruptured gate oxide layer. In addition, the location of the formation of permanent conductive paths is changed by changes in the manufacturing process. For this reason, the operation method of the OTP memory unit usually makes a wrong judgment according to the formation position where the conductive path is different.

When programming the selected memory cell M1, the voltage Vp1 applied to the word line WL0 turns on the channel of the selection transistor. Therefore, the voltage Vp2 applied to the bit line BL0 reaches the lower portion of the anti-fuse gate through the channel of the selection transistor. Then, the anti-fuse layer bursts according to a voltage difference between the voltage Vp3 applied to the anti-fuse gate line AF0 and the voltage Vp2 applied to the bit line BL0, and programs the selected memory cell M1.

The voltage Vp1 is, for example, about 0.7 to 3.5 kV; the voltage Vp2 is, for example, about 0 V; the voltage Vp3 is, for example, about 4.5 to 12 V; the voltage Vp4 is, for example, about 0.7 to 3.5 km. During programming operation, for unselected memory cells M3 sharing word line WL0 and anti-fuse gate line AF0 with memory cell M1, the voltage Vp4 and word applied to bit line BL1 coupled to unselected memory cell M3 Since the voltage difference of the voltage Vp1 applied to the line WL0 is not sufficient to turn on the selection transistor corresponding to the unselected memory cell M3, programming of the unselected memory cell M3 is suppressed.

In FIG. 1, it will be described that the insulating layer is melted through a tunneling current by a positive voltage on the gate, and a conductive channel is formed.

In addition, in FIGS. 1 to 2, circuits and memory cells for making an inactive memory using an anti-fuse are manufactured. In FIG. 1 to FIG. 2, a separate circuit or an external input device is required to use a memory and a memory cell using an anti-fuse.

In addition, in most inactive memories using anti-fuses, addresses are generated in the wafer process and separated into chips, and addresses cannot be modified automatically because addresses are generated automatically on the program or addresses are generated on the wafer. There was a problem in that the size of the circuit for operation was large.

On the other hand, in the present disclosure, the size is small using a simple circuit, the address can be flexibly assigned only as necessary to the completed device, and the address can be assigned when the user desires.

This will be described at the end of 'Details for the Invention'.

Here, an overall summary of the present disclosure is provided, and this should not be understood as limiting the appearance of the present disclosure (This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).

According to an aspect of the present disclosure (According to one aspect of the present disclosure), an anti-fuse memory cell operated by light, comprising: a photodiode that receives light and generates a current; An anti-fuse including an insulating layer; A switch provided between the photodiode and the anti-fuse, to prevent high current from flowing or not flowing through the anti-fuse; And, according to the state of the anti-fuse, including an output unit for outputting an output signal; When a high current flows in the anti-fuse, the anti-fuse is provided with an anti-fuse memory cell in which the insulating layer is destroyed by the high current.

This will be described at the end of 'Details for the Invention'.

1 is a view showing an example of a nonvolatile anti-fuse memory cell proposed in Japanese Patent Publication No. 5,971,711;
FIG. 2 is a diagram showing an example of an anti-fuse OTP memory cell having performance improvement and a manufacturing method and an operation method of the memory, as disclosed in Japanese Patent No. 6096237,
3 is a diagram illustrating an example of an anti-fuse memory cell according to the present disclosure;
4 is a view illustrating the structure and breakdown of an anti-fuse according to the present disclosure;
5 is a view for explaining the connection of the anti-fuse and switch according to the present disclosure,
6 illustrates another example of an anti-fuse memory cell according to the present disclosure.

Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings (The present disclosure will now be described in detail with reference to the accompanying drawing (s)).

3 is a diagram illustrating an example of an anti-fuse memory cell according to the present disclosure.

In the anti-fuse memory cell 200 operated by light, the anti-fuse memory cell 200 includes a photodiode 210, an anti-fuse 230, a switch 250; M1, and a resistance ( 290) and an output unit 270.

The photodiode 210 receives light and generates a current. The current flows in the direction of the arrow by the light. The photodiode 210 has a PN junction or PIN structure. When the light of sufficient photon energy strikes the photodiode 210, electrons are generated because mobile electrons and positive charge holes are generated. If it is absorbed in the depletion region of the junction, the carrier flows through the erected field of the depletion layer to generate a photocurrent.

The photodiode 210 operates only when it receives light, and if it does not receive light, no current is generated in the photodiode 210. Then, the switch 250 and the anti-fuse 230 do not operate.

The anti-fuse 230 is, for example, Mosfet (see FIG. 4), and includes an insulating layer 234 (see FIG. 4). The insulating layer 234 may be oxide. Although not shown in FIG. 3, one of the plurality of n-wells 233 (see FIG. 4) formed on the substrate 231 (see FIG. 4) is the source s2 and the other is the drain d2. The metal layer 235 (see FIG. 4) may be the gate g2. The insulating layer 234 is provided with an insulating layer 234 between the substrate 231 and the gate g2 so that the source s2 and the drain d2 are formed with the substrate 231 and the gate g2 insulated. The anti-fuse 230 is set so that the source s2 and the drain d2 have the same voltage in order to prevent flowing from the source s2 to the drain d2 or from the drain d2 to the source s2. If the same voltage is not applied, only one side can be broken, and only one side can be connected.

In general, the fuse is shorted in the normal state, and then, if necessary, a high voltage is applied to break the insulating layer 234 between the conductors, thereby electrically opening. In contrast to the fuse, the anti-fuse is opened in a normal state and short-circuited when a high voltage is applied.

The switch 250 is provided between the photodiode 210 and the anti-fuse 230, and the switch 250 prevents high current from flowing or not flowing through the anti-fuse 230. The switch 250 may be a Mosfet like the anti-fuse 230. Like the anti-fuse 230, the switch 250 is not shown, but may include a gate (g1; see FIG. 5), a source (s1; see FIG. 5) and a drain (d1; see FIG. 5). When a sufficient voltage is applied to the gate g1 of the switch 250, a current flows between the source s1 and the drain d1.

The output unit 270 outputs an output signal according to the state of the anti-fuse 230. The output unit 270 is provided between the switch 250 and the anti-fuse 230. The output signals can be output as 0 and 1. When the anti-fuse 230 is permanently connected, 1 may be output. For details, the operation of the anti-fuse memory cell 200 will be described below.

The anti-fuse memory cell 200 is provided with a resistor 290, and the voltage applied to the gate g1 of the switch 250 can be adjusted by the resistor 290. The voltage applied to the gate g1 should be such that the transistor can stably generate a sufficient current. Here, this voltage should be above the transistor driving threshold voltage, and should be sufficient to operate in the saturation region. The transistor basically functions to amplify and induce a current by adjusting the voltage. The resistor 290 is connected in parallel with the switch 250 to adjust the voltage across the resistor 290 to adjust the voltage across the gate g1 of the anti-fuse 230.

It includes a high voltage (Vdd) and a ground (GND), one side of the resistor 290 is connected to the ground (GND), the other side may be connected to the photodiode 210 and the switch 250. The resistor 290 is adjusted to have a sufficient voltage value to allow current to flow through the drain d1 and the source s1 at the gate g1 of the switch 250. The power supply Vdd may be any power supply that is generally used, and may be, for example, 3.3V.

The drain d1 of the switch 250 is connected to the gate g2 of the anti-fuse 230. When a voltage sufficient to operate the switch 250 is applied, a high current is induced to the gate g2 and the source s2 and the drain d2 of the anti-fuse 230.

To describe an example of the operation of the anti-fuse memory cell 200, first, when light is shined on the photodiode 210, current flows and the resistor 290 and the gate g1 of the switch 250 immediately below it flow. ) To increase the voltage. When a voltage sufficient to operate the n-mosfet of the switch 250 is applied to the gate g1, a high current is induced between the gate g2 of the anti-fuse 230 and the source s2 and the drain d2. . When the current exceeds the threshold, the insulating layer (oxide; see FIG. 4) between the metal layer (metal (see FIG. 4)) is destroyed, and the gate (g2) and the source (s2) and drain (d2) are connected to the metal. As can be seen in the circuit diagram, the output unit 270 is connected between the drain d1 of the switch 250 and the anti-fuse 230 to be connected to the next circuit. When the anti-fuse 230 is short-circuited, the high voltage (HV) above will be output as '1', which is digital data, and vice versa. The digital data '1' is the size of Vdd and is generally equal to the voltage driving the system. In this example, '1', which is digital data, has a value of 3.3V, whereas in the case of '0', it has a value of 0V as a GND value. Digital data distinguishes 1 and 0 based on Vdd / 2 by a digital circuit. The farther from the reference point, the higher the accuracy and reliability of the data. In the case of 3.3V, if it is 3 or more, 1 is calculated inside the circuit.

4 is a view illustrating the structure and breakdown of an anti-fuse according to the present disclosure.

The anti-fuse 230 may have an N-Mosfet structure as shown in FIG. 4 (a). For example, a plurality of N-wells 233 are formed on the P-type substrate 231, and an insulating layer 234 is formed on the N-wells 233 and a metal layer 235 is formed on the insulating layer 234. The P-type substrate 231 and the N-well 233 are insulated from the metal layer 235 by the insulating layer 234.

4 (b) is a view showing a phenomenon in which the insulating layer 234 provided in the anti-fuse 230 is destroyed.

Referring to FIG. 4 (a), the anti-fuse 200 is basically a type in which an insulating layer 234 is provided between the two conductive metal layers 235 and the substrate 231.

There are two main principles of the breakdown of the insulating layer 234, the voltage applied to the conductive layer is high, and silicon or the like in an amorphous form is changed to polycrystalline, resulting in low resistance, or an insulating layer due to the tunneling effect. As a permanent strong breakdown occurs in 234, the metal of the metal layer 234 is introduced into the insulating layer 234, resulting in a lower resistance and formed like a short circuit.

5 is a view illustrating connection of an anti-fuse and a switch according to the present disclosure.

The drain d1 of the switch 250 is connected to the gate g2 of the anti-fuse 230. The source s2 and the drain d2 of the anti-fuse 230 are connected to each other to have the same voltage. Therefore, the current flows from the source s2 and the drain d2 of the anti-fuse 230 in the direction of the gate g2 by the flow of the current formed by the switch 250. Since the source s2 and the drain d2 are connected, current does not flow between the source s2 and the drain d2.

6 is a diagram illustrating another example of an anti-fuse memory cell according to the present disclosure.

An example in which a plurality of anti-fuse memory cells 200 are provided is illustrated. At this time, the place where the photodiode 210 is provided generates an address desired by the user by illuminating light and not illuminating each photodiode 210 exposed in the anti-fuse memory cell 200. Addresses can be generated by combining the values of d0 to d4. When light is shined on the photodiode 210, 1 is output from the output unit 270, and 0 is output if the light is not shined.

Subsequently, after generating the address, a material that blocks light from entering the photodiode 210 may be covered so that no light enters the photodiode 210.

The anti-fuse memory cell 200 occupies a small space compared to a complicated circuit or a memory for programming. For example, one anti-fuse memory cell 200 has a size of 20umX20um. Here, the size of the photodiode 210 is 10umX10um, and the size depends on the performance of the photodiode 210, and even if it is made smaller, if the performance is good, the size can be further reduced.

Hereinafter, various embodiments of the present disclosure will be described.

(1) An anti-fuse memory cell operated by light, comprising: a photodiode that receives light and generates current; An anti-fuse including an insulating layer; A switch provided between the photodiode and the anti-fuse, to prevent high current from flowing or not flowing through the anti-fuse; And, according to the state of the anti-fuse, including an output unit for outputting an output signal; When a high current flows through the anti-fuse, the anti-fuse is an anti-fuse memory cell in which the insulating layer is destroyed by high current.

(2) A resistor connected to the photodiode; is provided, the switch includes a gate, and an anti-fuse memory cell that adjusts the voltage across the gate of the switch by a resistor.

(3) An anti-fuse memory cell comprising a source and a drain, and the insulating layer is destroyed so that the source and drain are permanently connected.

(4) The output signal is 0 and 1 anti-fuse memory cell.

(5) An anti-fuse memory cell that outputs 1 when the anti-fuse is short-circuited.

(6) An anti-fuse memory cell that includes a power supply and ground, one side of the resistor is connected to ground, and the other side is connected to a photodiode and a switch.

(7) The switch includes a drain, and the anti-fuse includes a gate, and the drain of the switch and the gate of the anti-fuse are connected to an anti-fuse memory cell.

(8) An anti-fuse memory cell having a source and a drain, and the source and drain having the same voltage.

(9) An anti-fuse memory cell having a source and a drain, and the source and drain are connected.

(10) Resistor and switch are anti-fuse memory cells connected in parallel.

According to one anti-fuse memory cell according to the present disclosure, it is possible to operate with light.

According to another anti-fuse memory cell according to the present disclosure, it is possible to manufacture in a general CMOS process.

According to another anti-fuse memory cell according to the present disclosure, it is possible to design using a 1.2V / 3.3V CMOS process. It is common for anti-fuse to break down when it takes more than 5V, and such devices are in line with the current trend of demanding devices with low power and high density by allowing high current to flow at the same time as high voltage is applied to reliably destroy the oxide layer. In the field, a simple non-volatile memory can be implemented without using a dc-dc converter to generate a high voltage.

200: anti-fuse memory cell 210: photodiode 230: anti-fuse 250: switch
270: output 290: resistance 231: substrate 233: n-well
234: insulating layer 235: metal layer

Claims (10)

In the light-operated anti-fuse memory cell,
A photodiode that receives light and generates current;
An anti-fuse including an insulating layer;
A switch provided between the photodiode and the anti-fuse, to prevent high current from flowing or not flowing through the anti-fuse; And,
In accordance with the state of the anti-fuse, an output unit for outputting an output signal; includes,
When a high current flows through the anti-fuse, the anti-fuse is an anti-fuse memory cell in which the insulating layer is destroyed by the high current. The method according to claim 1,
A resistor connected to the photodiode; is provided,
The switch includes a gate,
An anti-fuse memory cell that adjusts the voltage across the switch's gate by a resistor. The method according to claim 1,
The anti-fuse memory cell includes a source and a drain, and an insulating layer is destroyed to permanently connect the source and the drain. The method according to claim 3,
Anti-fuse memory cells with output signals 0 and 1. The method according to claim 3,
An anti-fuse memory cell that outputs 1 when the anti-fuse is shorted. The method according to claim 1,
Includes power and ground,
One side of the resistor is connected to ground,
The other side is an anti-fuse memory cell connected to a photodiode and a switch. The method according to claim 1,
The switch includes a drain,
Anti-fuse includes a gate,
An anti-fuse memory cell to which the drain of the switch and the gate of the anti-fuse are connected. The method according to claim 1,
The anti-fuse memory cell has a source and a drain, and the source and drain have the same voltage. The method according to claim 1,
The anti-fuse memory cell has a source and a drain, and the source and drain are connected. The method according to claim 2,
Anti-fuse memory cells with resistors and switches connected in parallel.

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