KR20200037102A - Mram fabrication and device - Google Patents

Abstract

The present invention relates to an MRAM manufacturing and device. In MRAM manufacturing, a top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

Description

MRAM FABRICATION AND DEVICE

Priority claims and cross-references

This application is filed on September 28, 2018, and enjoys the advantages of U.S. Provisional Application No. 62 / 738,681 entitled "MRAM Fabrication and Device", the entire contents of this U.S. patent. By is included here.

Semiconductor memories are used in integrated circuits for electronic applications, including, for example, radios, televisions, cell phones, and personal computing devices. One type of semiconductor memory device requires spin electronics that combines semiconductor technology with magnetic materials and devices. The spin of an electron is used to represent the bit through its magnetic moment rather than the charge of the electron.

One such electronic device is a magnetoresistive random access memory (MRAM) array, which includes conductive lines (word lines and bit lines) positioned vertically to each other in different directions, such as different metal layers. The conductive lines sandwich a magnetic tunnel junction (MTJ) to function as a magnetic memory cell.

An embodiment is a method comprising forming a bottom electrode over a via, wherein the via is electrically coupling the bottom electrode to a control line for a magnetoresistive random access memory device (MRAM). A magnetic tunnel junction (MTJ) is formed on the bottom electrode. An upper electrode is formed on the MTJ, and the material of the upper electrode is formed of a first material having an oxidation temperature higher than 450 ° C in 10 seconds or less.

Another embodiment is a method comprising forming a bottom electrode of a magnetoresistive random access memory device (MRAM). The magnetic tunnel junction (MTJ) is formed on the bottom electrode, and the MTJ includes an antiferromagnetic layer, a pinning layer, and a free layer. The upper electrode is formed over the MTJ, the upper electrode is physically coupled to the free layer of MTJ, and contains titanium nitride.

Another embodiment is a magnetoresistive random access memory (MRAM) cell comprising a titanium nitride film and including an upper electrode comprising a crystal orientation 111 as a dominant crystal orientation concentration. The MRAM cell further includes a magnetic tunnel junction (MTJ) disposed under the upper electrode and a bottom electrode disposed under the MTJ.

Another embodiment is a magnetoresistive random access memory (MRAM) device that includes a bottom electrode connected to a metal feature of the bottom substrate by bottom electrode vias. The MRAM device further includes a magnetic tunnel junction (MTJ) disposed over the bottom electrode, and an upper electrode disposed over the MTJ and comprising a material having an oxidation temperature of 450 ° C. in 10 seconds or less.

Aspects of the present disclosure are best understood when reading the detailed description below in conjunction with the accompanying drawings. Note that according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of explanation.
1-7 illustrate intermediate steps for a process flow forming a magnetoresistive random access memory (MRAM) device in accordance with some embodiments.
8A and 8B illustrate a deposition chamber usable to form an upper electrode of an MRAM device in accordance with some embodiments.
9A and 9B illustrate top electrode films of MRAM devices in accordance with some embodiments.
10 and 11 illustrate various characteristics of an MRAM device in accordance with some embodiments.
12 illustrates an intermediate step in a process flow forming an MRAM device in accordance with some embodiments.
13 is a cross-sectional view of an MRAM device, in accordance with some embodiments.
14 illustrates various characteristics of an MRAM device in accordance with some embodiments.

The disclosure below presents several different embodiments or examples for implementing different features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples, and are not intended to be limiting. For example, in the following description, the formation of the first feature on the second feature or on the second feature may include embodiments in which the first and second features are formed in direct contact with the first feature. It may also include embodiments in which other features can be formed between the first feature and the second feature such that the second feature cannot be in direct contact. In addition, the present disclosure may repeat reference signs and / or characters in various examples. This repetition is for brevity and clarity, and does not represent relationships between the various embodiments and / or configurations described by itself.

Moreover, spatial relative terms such as “beneath”, “below”, “lower”, “above”, “upper”, etc., are as illustrated herein in the drawings. It can be used for convenience of description describing the relationship of one element or feature to another element (s) or feature (s). Spatial relative terms are intended to encompass different orientations of the device in use or in process as well as orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or oriented in a different orientation), and the spatially relative descriptors used herein can be interpreted accordingly.

In forming a magnetoresistive random access memory (MRAM) device, after forming the upper electrode, subsequent processing steps include patterning the layers into individual cells. Oxidation of the top electrode and / or bottom layer during patterning can cause problems for the magnetic tunnel junction (MTJ) process of MRAM cells. In particular, oxygen can suppress electron spin in MTJ and magnetic reversibility of the free layer of MTJ. The process of the embodiment utilizes a deposition technique to form the top electrode, reducing oxygen contamination that can be attributed to subsequent processing. The crystal orientation of the upper electrode reduces oxygen contamination in the lower layer. For example, as will be described in more detail below, a single layer top electrode formed of titanium nitride, having a crystal orientation of (111) (face-centered cubic structure), is used to suppress oxygen for the lower layer including the free layer of MTJ in the MRAM cell. Characteristics can be provided. A single layer made of other materials or a multilayer made of titanium nitride and other materials may also be used. Titanium nitride also has the advantage of having a relatively high oxidation temperature above about 450 ° C in these processes.

1 to 13 illustrate an intermediate step of manufacturing the MRAM device 10. In Fig. 1, a substrate 90 is illustrated. In some embodiments, the substrate 90 is a carrier substrate, and the MRAM device 10 is formed on a carrier substrate. The MRAM device 10 may include a plurality of MRAM cell regions including the MRAM cell 20 and the MRAM cell 25. After each layer of the MRAM cell is formed of the MRAM device 10, the cells are patterned into individual MRAM cells.

In some embodiments, the substrate 90 may be formed of a semiconductor material such as silicon, silicon germanium, or the like. In some embodiments, the substrate 90 is a crystalline semiconductor substrate, such as a crystalline silicon substrate, a crystalline silicon carbon substrate, a crystalline silicon germanium substrate, a III-V compound semiconductor substrate, and the like. In an embodiment, the substrate 90 may include an active layer of a bulk silicon, doped or undoped, or silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material, such as silicon, germanium, silicon germanium, or a combination of these, such as Silicon Germanium On Insulator (SGOI). Other substrates that can be used are multilayer substrates, gradient substrates, or hybrid orientation substrates.

In some embodiments, substrate 90 may be part of an interconnect or redistribution structure. The substrate 90 can be formed of an insulating material, such as a dielectric. In some embodiments, the substrate 90 may include an Inter-Metal Dielectric (IMD) layer or an Inter-Layer Dielectric (ILD) layer, such as less than 3.8, less than about 3.0, or about 2.5 It may include a dielectric material having a dielectric constant less than (k value) and having conductive features formed therein. The insulating material of the substrate 90 is PSG (PhosphoSilicate Glass), BSG (BoroSilicate Glass), BPSG (Boron-doped PhosphoSilicate Glass), FSG (Fluorine-doped Silicate Glass), TEOS (TetraEthyl OrthoSilicate), Black Diamond (Black Diamond) (Registered trademark of Applied Materials Inc.), a low dielectric constant dielectric material containing carbon, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), and the like.

Layer 100 is formed over substrate 90. In some embodiments, layer 100 may be formed of a semiconductor material such as silicon, silicon germanium, or the like. In some embodiments, layer 100 is a crystalline semiconductor, such as crystalline silicon, crystalline silicon carbon, crystalline silicon germanium substrate, group III-V compound semiconductor, and the like. In an embodiment, the layer 100 may include an active layer of bulk silicon, doped or undoped, or silicon on insulator (SOI) substrates.

In some embodiments, layer 100 may be part of an interconnect or redistribution structure. Layer 100 may be formed of an insulating material, such as a dielectric material. In some embodiments, layer 100 may include an IMD layer or ILD layer having a dielectric constant (k value) of, for example, less than 3.8, less than about 3.0, or less than about 2.5, and conductive features such as conductive features 105. You can. The insulating material of the layer 100 may be formed of PSG, BSG, BPSG, FSG, TEOS, black diamond (registered trademark of Applied Materials Inc.), low dielectric constant dielectric material containing carbon, HSQ, MSQ, and the like.

The conductive feature 105 can be coupled to an active or passive device (eg, transistor or other electrical element) that can be embedded in the substrate 90 or layer 100. The conductive features 105 may include, for example, source / drain regions of transistors, gate electrodes, contact pads, portions of vias, portions of metal lines, and the like. Active devices can include a wide variety of active devices, such as transistors, and passive devices can include devices such as capacitors, resistors, inductors, and the like, which can be used together to form desired structural and functional components. The active device can be formed in the substrate 90 or layer 100 or in other portions on the substrate or layer using any suitable method.

Conductive features 105 formed in layer 100 may include contacts or metal lines that may be formed of, for example, copper or a copper alloy. In some embodiments, conductive features 105 are MRAM devices 10 It may be part of an interconnect that provides addressing for the MRAM cell to be formed in. In the above-described embodiment, the conductive feature 105 may be a control line such as a bit line or word line. In some embodiments, conductive features 105 may include other conductive materials, such as tungsten, aluminum, and the like. Moreover, the conductive feature 105 can be positioned below the conductive feature 105 and surrounded by a conductive diffusion barrier layer (not shown) surrounding the conductive feature. The conductive diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

The conductive feature 105 can be formed by any suitable process. For example, by a patterning and plating process in which an opening corresponding to the conductive feature 105 is formed, a conductive diffusion barrier layer (if used) is deposited on the opening, followed by a seed layer. Next, the conductive feature 105 is formed by any suitable process, such as a plating process including electroplating or electroless plating. Following formation of the conductive feature 105, any excess material along the excess seed layer and conductive diffusion barrier layer may be removed by a polishing process, such as a suitable etching and / or chemical mechanical polishing (CMP) process. You can. Other suitable processes can be used to form the conductive features 105.

In some embodiments, one or more etch stop layers such as etch stop layer 110 and / or etch stop layer 120 may be deposited over layer 100. In some embodiments, the etch stop layer 110 and the etch stop layer 120 may include nitride, oxide, carbon doped oxide, and / or combinations thereof. In some embodiments, the etch stop layer 110 and the etch stop layer 120 may also include metal or semiconductor materials such as oxides, nitrides, or carbides or semiconductor materials of metal. Examples of the above materials include aluminum nitride, aluminum oxide, silicon nitride, and silicon carbide. The etch stop layer 110 may be formed of a different material or the same material as the etch stop layer 120. In one embodiment, the etch stop layer 110 may be formed of aluminum nitride, and the etch stop layer 120 may be formed of aluminum oxide. The etch stop layer 110 and the etch stop layer 120 can be any suitable method such as plasma enhanced chemical vapor deposition (PECVD) or high-density plasma CVD (HDPCVD), atomic layer It may be formed by other methods such as atomic layer deposition (ALD), low pressure CVD (LPCVD), physical vapor deposition (PVD), or the like. According to some embodiments, the etch stop layer 110 and / or the etch stop layer 120 may also be utilized as a diffusion barrier layer that prevents undesirable elements, such as copper, from diffusing into the subsequently formed layer. In some embodiments, each of the etch stop layer 110 and / or etch stop layer 120 may include one or more separate layers. The etch stop layer 110 and / or the etch stop layer 120 may be deposited to a total thickness of about 30 mm 2 to about 100 mm 2, such as 50 mm 2, respectively.

The etch stop layer 120 (or the etch stop layer 110 if the etch stop layer 120 is omitted) is deposited, followed by the dielectric layer 130 using any suitable material for any suitable forming process. It can be formed by. In one embodiment, dielectric layer 130 may include a silicon oxide network, such as silicon oxide formed by tetraethyl orthosilicate (TEOS) or from TEOS. Dielectric layer 130 may be formed by any suitable process, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma (HDP) deposition, and the like. Other silicate oxides such as TetraMethylOrthoSilicate (TMOS) can be used instead of TEOS. In some embodiments, dielectric layer 130 may include silicon carbide, silicon oxynitride, and the like.

In some embodiments, following dielectric layer 130 formation, a nitrogen-free anti-reflective coating (NF-ARC) 140 may be formed, which will contribute to the subsequent photo patterning process. You can. NF-ARC 140 can be formed using any acceptable process, and can include any suitable oxide. In some embodiments, dielectric layer 130 may be used as NF-ARC rather than including separate layers.

Next, the bottom electrode vias 145 can be formed by any suitable method. For example, the NF-ARC 140, dielectric layer 130, etch stop layer 120 and etch are etched by any suitable process, such as a photo-patterning process, using a patterned photoresist (not shown). It may be formed on the stop layer 110. The pattern of patterned photoresist can be transferred to each layer by an appropriate etching process using an etchant that is selective for the material of each layer. In some embodiments, NF-ARC 140 can act as a hardmask. In another embodiment, a separate hardmask (not shown) can be deposited over the NF-ARC 140 prior to etching the opening for the bottom electrode via 145. After the conductive features 105 are exposed by these openings, the openings are filled with conductive material to form bottom electrode vias 145.

In some embodiments, a conductive barrier layer (not shown) may first be formed in the opening. The conductive barrier layer can be similar to that described above for the conductive feature 105. In some embodiments, the conductive material of the bottom electrode via 145 can overfill the via opening, and a planarization process, such as a chemical mechanical polishing (CMP) process, removes excess conductive material of the bottom electrode via 145 and , It can be used to planarize the top of the bottom electrode via 145 and the top of the NF-ARC 140. In embodiments that use a conductive barrier layer to line the via opening, an excess portion of the conductive barrier layer that may be formed on the NF-ARC 140 may also be removed through a planarization process.

The conductive material of the bottom electrode via 145 can be formed by any suitable film deposition process, such as electroplating, electroless plating, CVD, PVD, and the like. The conductive material of the bottom electrode via 145 can include any suitable conductive material, such as titanium nitride, copper, aluminum, and the like.

Referring to FIG. 2, the bottom electrode 170 of the MRAM device 10 may be formed. In some embodiments, the bottom electrode 170 may include a single layer, and in other embodiments, the bottom electrode 170 may include multiple distinct layers of the same material or separate materials. In some embodiments, the bottom electrode 170 may include a single layer of titanium nitride, tantalum nitride, nitrogen, titanium, tantalum, tungsten, cobalt, copper, and the like. In some embodiments, the bottom electrode 170 includes titanium nitride, titanium and titanium nitride; Tantalum nitride, tantalum and tantalum nitride; Tantalum, tantalum nitride and tantalum; Titanium, titanium nitride and titanium; Tantalum and titanium nitride; Titanium and tantalum nitride; Titanium nitride and tantalum nitride; Titanium nitride and tungsten; Tantalum nitride and tungsten; And the like. In summary, in embodiments where the bottom electrode 170 has a multi-layered formation, the layers can include two or more layers of a single layer material.

The bottom electrode 170 can be formed using any suitable process including DC PVD, RFDC PVD, CVD, ALD, pulsed DC, and the like. The bottom electrode 170 may be formed to a thickness of about 50 mm2 to about 3000 mm2, but other thicknesses may be considered and used.

For example, the first layer 150 of the bottom electrode 170 may include tantalum nitride or be composed of tantalum nitride, and may be of about 50 Å to about 3000 의해 by DC PVD, RFDC PVD, CVD, ALD, pulsed DC, etc. It can be deposited to a thickness. In some embodiments, following the deposition of the first layer 150, a planarization process may be used to thin and / or flatten the first layer 150.

Referring to FIG. 3, following the formation of the first layer 150, the second layer 160 of the bottom electrode 170 may include titanium nitride or be composed of titanium nitride, and DC PVD, RFDC PVD, CVD , ALD, pulsed DC or the like can be formed to a thickness of about 50 Å to about 3000 Å. In some embodiments, the second layer 160 of the bottom electrode 170 may include titanium nitride, and the second layer is an upper electrode 190 (see FIG. 7) to achieve a predominant crystal orientation 111. It is formed according to the process described for.

Referring to FIG. 4, subsequent to the deposition of the second layer 160, a planarization process, such as a CMP process, can be used to thin and / or planarize the second layer 160. Following the formation of the bottom electrode 170, the total thickness of the bottom electrode 170 may be from about 50 mm 2 to about 3000 mm 2, but other thicknesses are contemplated and can be used.

Referring to FIG. 5, following formation of the bottom electrode 170 of the MRAM device 10, a magnetic tunnel junction (MTJ) structure 180 may be formed. MTJ structure 180 may include any suitable configuration for MTJ of an MRAM device, such as MRAM device 10. Various configurations for the MTJ structure 180 are described with respect to FIGS. 6A, 6B and 6C.

6A, 6B and 6C, various exemplary configurations of MTJ structures in accordance with some embodiments are illustrated. It should be understood that any suitable structure can be used for MTJ structure 180.

In FIG. 6A, layers of the MTJ structure 180 may include an antiferromagnetic layer 182, a pinning layer 184, and a free layer 188. 6B and 6C, the MTJ structure 180 may also include one or more layers of tunnel barrier 186. In FIG. 6B, the tunnel barrier layer 186 is disposed between the pinning layer 184 and the free layer 188. In FIG. 6C, the tunnel barrier layer 186 is disposed between the antiferromagnetic layer 182 and the pinning layer 184. The tunnel barrier layer 186 may be disposed at each of the locations illustrated in FIG. 6C. Additionally, more layers of MTJ structures 180 may be included in the MRAM device 10, including additional tunnel barrier layers, antiferromagnetic layers, pinning layers, and free layers.

The antiferromagnetic layer 182 is formed on the bottom electrode 170, the pinning layer 184 is formed on the antiferromagnetic layer 182, and the free layer 188 is formed on the pinning layer 184. However, other configurations of the MTJ structure 180 are also contemplated. For example, the layers can be formed in reverse order. The antiferromagnetic layer 182, the pinning layer 184, and the free layer 188 may be sequentially formed.

The pinning layer 184 may be formed of, for example, platinum manganese (PtMn). The antiferromagnetic layer 182 is, for example, iridium manganese (IrMn), platinum manganese (PtMn), iron manganese (FeMn), ruthenium manganese (RuMn), nickel manganese (NiMn), and palladium platinum manganese (PdPtMn), or alloys thereof. It can be formed as. The free layer 188 may be formed of cobalt-iron-boron (CoFeB). The tunnel barrier layer 186 may be formed of manganese oxide (MgO) when included in the MTJ structure 180. It should be understood that the various layers of MTJ structure 180 can be formed of different materials. The antiferromagnetic layer 182, pinning layer 184, free layer 188, and tunnel barrier layer 186 may be any suitable process, such as by DC PVD, RFDC PVD, CVD, ALD, pulsed DC, etc. Can be formed.

Referring to FIG. 7, an upper electrode 190 is formed following the formation of the MTJ structure 180. The upper electrode 190 may be formed of a single layer or a multi-layer structure made of titanium nitride rather than a multi-layer structure made of tantalum nitride, tantalum, and tantalum nitride, which is easily oxidized. Using a single layer of titanium nitride for the top electrode 190 of the MRAM device 10 advantageously simplifies the process of forming the top electrode 190. In addition, the crystal orientation 111 of the upper electrode 190 contributes to preventing oxygen from diffusing into the MTJ structure 180. An appropriate deposition process using titanium nitride for the material of the upper electrode 190 can form the dominant crystal orientation 111 of the upper electrode 190. Instead of titanium nitride, other materials may also be used, including a multilayer, which may or may not include titanium nitride as one or more of the multilayers of upper electrode 190. Crystal orientation 111 may be achieved with other materials listed below, but may not be the predominant orientation. As such, in an embodiment in which a material other than titanium nitride is used to form the upper electrode 190, the thicker the upper electrode 190, the better the oxidation of the MTJ structure 180 can be prevented.

In some embodiments, the upper electrode 190 may include a single layer made of titanium nitride, tantalum nitride, titanium, tantalum, tungsten, cobalt, copper, and the like. In some embodiments, the upper electrode 190 includes titanium nitride, titanium and titanium nitride; Tantalum nitride, tantalum and tantalum nitride; Tantalum, tantalum nitride and tantalum; Titanium, titanium nitride and titanium; Tantalum and titanium nitride; Titanium and tantalum nitride; Titanium nitride and tantalum nitride; Titanium nitride and tungsten; Tantalum nitride and tungsten; And the like. In summary, the upper electrode 190 having a multi-layer configuration may include two or more layers of a single layer material.

In embodiments in which the upper electrode 190 includes titanium nitride, the upper electrode 190 may be deposited to a thickness of about 50 mm 2 to about 3000 mm 2, such as about 1000 mm 2, but other thicknesses may also be considered and used. . In embodiments where the upper electrode 190 contains a material that does not contain titanium nitride, the predominant crystal orientation 111 may not appear. In the above embodiment, the upper electrode may be deposited to a thickness of about 200 mm 2 to about 5000 mm 2, such as 2000 mm 2, or about 1000 mm to about 5000 mm 2, such as about 2000 mm 2, but other thicknesses are contemplated and used Can be. In general, the thicker the upper electrode 190, the better the ability to suppress oxygen penetration, but by using the upper electrode 190 formed of titanium nitride having a predominant crystal orientation 111, the upper electrode 190 The thickness can be reduced to achieve the same oxygen suppression effect as the thick upper electrode 190 that does not contain titanium nitride with a predominant crystal orientation 111. In some embodiments, the thickness of the upper electrode 190 formed of titanium oxide having the predominant crystal orientation 111 is from about 25% to about the thickness of the top electrode formed of a material that does not contain titanium nitride in the predominant crystal orientation 111. It may be about 60%. This advantageously forms a thinner film stack. In forming the upper electrode 190, the workpiece (eg, the MRAM device 10) can be preheated by a lamp heater or the like by any allowable tool including a heating control element located on the electrostatic chuck. have. In some embodiments, before and after depositing the upper electrode 190, a pre-cleaning process including plasma treatment, heating, nitrogen treatment, and the like may be used.

8A and 8B, the upper electrode 190 may be formed using any suitable process including DC PVD, bias DC PVD, RFDC PVD and RFDC PVD by magnetron. For DC PVD and bias DC PVD, an exemplary deposition chamber is illustrated in FIG. 8A. For RFDC PVD and RFDC PVD by magnetron, an exemplary deposition chamber is illustrated in FIG. 8B. The workpiece 11 to be formed of the MRAM device 10 is positioned on the same chuck as the electrostatic chuck 810. The target 830 is positioned in the chamber as a source for the material to be deposited on the workpiece 11. Cathode 820 may be biased using voltage and / or radio frequency (RF). The distance D1 between the workpiece 11 and the target is controllable. In FIG. 8B, a magnetron 835 can be used, can be positioned over the target, and the distance D2 between the magnetron 835 and the target 830 is controllable.

The target 830 is made of a material deposited on the workpiece 11. In forming the upper electrode 190 of the MRAM device 10, the material to be formed for each of the one or more layers of the upper electrode 190 may include a metal such as titanium or tantalum. In an embodiment using a multi-layered top electrode 190, the target 830 can be changed from one material to another for each layer. When target 830 is priced by the plasma generated in the chamber, material will be transferred from target 830 to the workpiece. When titanium nitride is formed, the target may be formed of titanium or titanium nitride. In an embodiment in which the target is formed of titanium, when the titanium is transferred from the target to the workpiece 11, a process gas 840 containing nitrogen may directly nitride the titanium before or during deposition, thereby allowing the workpiece to be nitrided. A titanium nitride layer is formed on the piece 11. The target 830 may be larger than the size of the work piece 11 to improve the uniformity of the deposited film. The shape of the target 830 may be defined as circular, rectangular, oval, oval, square, triangular, regular or irregular polygons, and the like. In some embodiments, the shape of the target 830 may be the same shape as the workpiece 11 (eg, MRAM device 10). The process gas 840 may also include an inert gas flowing between the workpiece 11 and the target 830. Argon (Ar) may be used, but it is understood herein that in some applications other gases that are inert or non-inert may be employed in addition to or instead of argon as process gas 840. For example, a mixture of argon and nitrogen can be used to deposit titanium nitride from a titanium target.

8A, the bias DC PVD process is first described. In the bias DC PVD process, a DC voltage is applied between the workpiece 11 and the target 830. For example, a negative DC bias can be applied to the target 830 relative to the workpiece 11. Therefore, the target 830 is a cathode, and the workpiece 11 is an anode. As a result of applying the DC voltage, an electric field is formed between the workpiece 11 and the target 830. Workpiece 11 may be grounded and target 830 may provide a negative bias with respect to ground. Under the influence of the electric field, electrons leave the target 830 and are accelerated toward the workpiece 11. Upon collision with an atom of a process gas 840, such as an inert process gas, the electrons ionize the atoms of the process gas 840, forming new free electrons and inert gas ions. Since the inert gas ions are positively charged, they are attached to the negatively biased target 830. The inert gas ions collide with the target 830 and emit target atoms of the target 830 material away from the target 830. The target atom sits on the workpiece 11 (eg, the MRAM device 10), contributing to the formation of the upper electrode 190. Here, it is understood that the aforementioned single ionization event is an exemplary property, and that in fact, many ionization events involving many electrons and inert gas atoms occur. Moreover, in addition to the electrons leaving the target 830, the electrons generated in the ionization event are also accelerated towards the workpiece 11 and can ionize additional inert gas atoms of the process gas 840. In this way, a plasma containing many electrons and ions is formed between the target 830 and the workpiece 11, so that many atoms from the target 830 are sputtered and formed as the upper electrode 190.

When bias DC PVD is used when the upper electrode 190 includes titanium nitride, when the DC output range is from about 1 kW to 30 kW, such as about 10 kW, titanium nitride may be formed to have an appropriate crystal orientation. , Other output values can also be used. The DC bias voltage can be from about 200 V to about 900 V, such as about 500 V, but other values can also be considered and used. The current control can be from about 5 A to about 35 A, such as about 10 A, but other values can also be considered and used. The process gas can include nitrogen (N ₂ ) and argon (Ar) and can flow at a flow rate of about 10 to 1000 sccm, such as about 400 sccm, but other flow rates can also be used. The process gas can be provided at a pressure of about 10 to 400 mTorr, such as about 50 mTorr, but other pressures can also be used. The workpiece 11 (eg, MRAM device 10) may be heated to about 200 ° C. to about 450 ° C., such as about 300 ° C., but other temperatures may also be used.

With continued reference to FIG. 8A, DC PVD can also be used without bias. In DC PVD, plasma is generated from process gas 840 without using bias control. Plasma forms radicals and ions of the process gas 840 that expand in all directions, including hitting the target 830 and releasing material from the target 830. The transfer of energy from radicals and ions to the material causes the material to accelerate in various directions, including towards the work piece 11, so that many atoms from the target 830 are sputtered and formed as the upper electrode 190.

When DC PVD is used when the upper electrode 190 includes titanium nitride, when the DC output range is about 1 kW to 30 kW, such as about 10 kW, titanium nitride can be formed to have an appropriate crystal orientation. Process gas 840 may include nitrogen (N ₂ ) and argon (Ar), and may flow at a flow rate of about 10 to 1000 sccm, such as about 400 sccm, but other flow rates may also be used. Process gas 840 may be provided at a pressure of about 1 to 100 mTorr, such as about 50 mTorr, but other pressures may also be used. The workpiece 11 (including the MRAM device 10) can be heated to about 200 ° C to about 450 ° C, such as about 300 ° C, but other temperatures can also be used.

Referring to FIG. 8B, RF PVD and RFDC PVD processes will be described. Both RF PVD and RFDC PVD technology operate in a similar way to the bias DC process. However, in the RF PVD process, an RF voltage (ie, AC) bias can be applied instead of the DC output. In the RFDC PVD process, both RF voltage bias and DC bias are applied. Includes RF bias, and any positive charge collected on the target 830 during each half cycle is canceled out over the next half cycle, preventing significant charge buildup over time.

When the upper electrode 190 includes titanium nitride, when using bias RF PVD or RFDC PVD, when the RF bias frequency is greater than about 40 MHz, about 13.56 MHz or more, titanium nitride is formed to have an appropriate crystal orientation. Can be. The AC bias output can be controlled from about 100 W to about 1000 W, such as about 500 W, but other values can also be used. When DC bias is also used (RFDC PVD), the DC output range can be from about 1 kW to 30 kW, such as about 5 kW, and other values can also be used. The DC bias voltage can be from about 200 V to about 900 V, such as about 500 V, but other values can also be considered and used. DC current control can be from about 15 A to about 25 A, such as from about 5 A to about 35 A or from about 20 A, such as about 10 A, but other values can also be considered and used. Process gas 840 may include nitrogen (N ₂ ) and argon (Ar), and may flow at a flow rate of about 10 to 1500 sccm, such as about 400 sccm, but other flow rates may also be used. Process gas 840 may be provided at a pressure of about 10 to 400 mTorr, such as about 50 mTorr, but other pressures may also be used. The workpiece 11 (eg, MRAM device 10) may be heated to about 200 ° C. to about 450 ° C., such as about 300 ° C., but other temperatures may also be used. The separation distance D1 between the workpiece (eg, MRAM device 10) and the target may be about 55 to 65 mm, such as about 60 mm, but other values may also be used.

In some embodiments, a magnetron 835 may be used as illustrated in FIG. 8B. Any of the deposition techniques described above, including DC PVD, bias DC PVD, RF PVD and RFDC PVD, can use the magnetron 835. The efficiency of the deposition process can be improved through the use of a magnetron configuration. In a magnetron PVD deposition system, magnets can be used to create a magnetic field near the target 830. The direction of the resulting magnetic field is approximately perpendicular to the electric field across most of the target 830. The electrons are substantially blocked in these intersecting fields, so that substantially the plasma is concentrated near the target 830. Such containment reduces the likelihood of harmful collisions between the electron and the workpiece 11 and increases the efficiency of the deposition process. The separation distance D2 between the target 830 and the magnetron 835 may be about 38 to 46 mm, such as about 42 mm, but other values may also be used.

In some embodiments, pulsing can be used. Multiple deposition cycles may be performed in a pulsing process under vacuum with or without process gas 840. In other embodiments, other deposition techniques, such as ALD, CVD, etc., can be used.

Obtaining the desired crystalline film to mitigate the oxygen effect in subsequent processing of the MRAM device 10 can be achieved through growth of the crystalline film with strong crystal orientation 111. Growing oriented grains can be achieved by using low energy deposition techniques. In low-energy deposition technology, electronic energy is more controlled than in high-energy deposition. Using bias control provides the ability to use lower ionic energy while maintaining high strength. RF bias also provides strong strength, but may also have increased ionic energy. By using the magnetron 835, it is possible to cancel and control some of the excess energy of the ions having more energy than desired. When the ions of the target material impact the workpiece 11, the ions are low in energy, so there is less likelihood of removing, replacing or damaging other atoms already deposited on the workpiece 11. Lost electrons can accumulate and deionize ions of the target material, forming a (111) oriented crystalline structure.

9A and 9B, exemplary top electrode 190 layers using two different film deposition techniques are illustrated. In FIG. 9A, DC bias is used to form a strong oriented crystalline film. The top of the film is also very smooth. In contrast, the upper surface of the tantalum nitride is rougher than the upper surface of the titanium nitride film illustrated in FIG. 9A. In an embodiment comprising a tantalum nitride layer and a titanium nitride layer, the top surface of the titanium nitride layer will be smoother than the top surface of the tantalum nitride layer. The upper electrode 190 shown in FIG. 9A can better prevent oxygen penetration in subsequent processing forming the MRAM device 10. In Fig. 9b, no bias is used. As a result, the particles are not highly oriented, and the upper surface is rougher.

Referring to FIG. 10, in some embodiments, the upper electrode 190 may be formed to exhibit a strong crystal orientation 111. The graph 1010 illustrates that the strength of the crystal orientation 111 at the marker 1020 is the largest of the lattice planes proven in different process conditions. Graph 1010 illustrates that the strength of crystal orientation 200 at marker 1030 is the second largest of the lattice surfaces proven under different process conditions. The strength of the crystal orientation of (111) may be about 25% to about 100% greater than the strength of the crystal orientation of (200).

Referring to FIG. 11, the upper electrode 190 may be formed to control film stress. In some embodiments, the tensile stress of the upper electrode 190 can be controlled to be greater than about 400 Mpa, but other values can also be considered and used. Controlling the stress of the film of the upper electrode 190 greater than about 400 Mpa also contributes to preventing oxygen from penetrating the MTJ structure 180. As shown in the graph 1110 of FIG. 11, the film stress can be increased at different substrate temperatures when the AC bias is increased. In some embodiments, the upper electrode 190 may be doped with a suitable dopant, such as carbon or silicon, to enhance and / or further control film stress. Carbon can be doped at a concentration of about 1.0 x 10 ²² cm ^-3 to 1.0 x 10 ²⁴ cm ^-3 . The silicon can be doped to a concentration of about 1.0 x 10 ²² cm ^-3 to 1.0 x 10 ²⁴ cm ^-3 . Silicon or carbon may be doped in situ while forming the upper electrode 190, or may be doped by subsequent ion implantation. The higher the concentration of the dopant, the greater the stress of the upper electrode 190. Selecting carbon and / or silicon to have a doping concentration in the above range provides tunable film stress without adversely affecting the conductive properties of the upper electrode 190. Other dopant concentrations are also contemplated and can be used instead.

Referring to FIG. 12, following formation of the upper electrode 190, the upper electrode 190 may be thinned to a desired thickness. Thinning can be done by any suitable process. In some embodiments, an ion beam etch cleaning process may be performed to thin the upper electrode 190 to a desired thickness. In other embodiments, wet etching may be used. In another embodiment, a chemical mechanical polishing (CMP) process can be used.

Referring to FIG. 13, a cross-sectional view of the MRAM device 10 after patterning into separate MRAM cells such as the MRAM cell 20, MRAM cell 30 and MRAM cell 40 is illustrated. The cross section of FIG. 13 is a cross section of the MRAM device 10 perpendicular to the cross section illustrated in FIG. 12.

Each of the MRAM cells can be patterned using any suitable technique, such as photo-patterning technique. During patterning, oxygen penetration into the MTJ structure 180 is reduced or eliminated due to the strong crystal orientation 111 of the upper electrode 190. Choosing titanium nitride as the material of the upper electrode 190 also contributes to reducing or eliminating oxygen penetration into the MTJ structure 180. After patterning the MRAM device 10 into an MRAM cell, a protective dielectric layer 210 is deposited on the sidewall of the MTJ structure, thereby preventing the MTJ structure from being oxidized through the sidewall surface. The protective dielectric layer 210 can include silicon nitride or other suitable material formed by any suitable technique, such as PVD, CVD, and the like. Dielectric layer 215 may be deposited over multiple MRAM cells of the MRAM device. Dielectric layer 215 may include silicon nitride or other suitable material formed by any suitable technique, such as PVD, CVD, or the like. The resulting MRAM cell 20 of the MRAM device 10 may have an interface between the upper electrode 190 and the MTJ structure 180, where the bottom surface of the upper electrode 190 and the MTJ structure 180 The upper surface of the is matched in its lateral range over the entire surface, that is, between the sidewalls, so that either the bottom surface of the upper electrode 190 and the upper surface of the MTJ structure 180 are lateral to the MJT structure. It does not extend beyond the upper electrode. That is, the MTJ structure 180 and the upper electrode 190 may have a shared interface in their respective lateral ranges.

Since the upper electrode 190 is oxidized at a relatively high temperature and is formed of a material having a crystal orientation 111, the upper surface of the upper electrode 190 is in an unprotected state during the formation of the protective dielectric layer 210 and the dielectric layer 215 Can be maintained. Formation of these conventional materials may require a separate protective / oxygen blocking layer, but since the upper electrode 190 may include titanium nitride and has a crystal orientation 111, the upper electrode 190 is subjected to subsequent processing. It is possible to block the penetration of oxygen at the stage. Following formation of the dielectric layer 215, a cell gap filling material layer 220 can be formed over each group of MARM cells, such as the MARM device 10. The cell gap filling material layer 220 can be made of any suitable film, such as silicon oxide, polyimide, PBO, PSG, BSG, BPSG, FSG, TEOS, etc., using any suitable deposition technique such as CVD, PVD, ALD, flowable CVD, etc. It can be formed of a material.

Following formation of the cell gap filling material layer 220, a device gap filling material layer 230 may be formed over all die, including the MRAM device 10 and adjacent MRAM devices formed on the same workpiece. The device gap filling material layer 230 may be formed using materials and techniques similar to those described above for the cell gap filling material layer 220. Following formation of the device gap filling material layer 230, the device gap filling material layer 230 may be planarized by, for example, a CMP process, or other suitable process to flatten the top surface of the device gap filling material layer 230. You can.

After flattening the device gap filling material layer 230, an optional mask layer 240 and an optional mask layer 250 may be deposited over the device gap filling material layer 230. The optional mask layers 240 and 250 may be used as an etch stop layer, and may be formed using materials and processes similar to those described above for each of the etch stop layer 110 and the etch stop layer 120.

Next, an isolation layer 260 may be formed over the optional mask layer 250. The isolation layer 260 may be formed of polymer, polyimide, PSG, BSG, BPSG, FSG, TEOS, black diamond (registered trademark of Applied Materials Inc.), low dielectric constant dielectric material containing carbon, HSQ, MSQ, and the like. Isolation layer 260 may be any suitable method such as spin-on coating, plasma enhanced chemical vapor deposition (PECVD) or high density plasma CVD (HDPCVD), atomic layer deposition (ALD), low pressure CVD (LPCVD) , And other methods such as physical vapor deposition (PVD).

The contact 270 may be formed by patterning the isolation layer 260 to form an opening corresponding to the contact 270 therein. The opening can be formed using any acceptable patterning technique, such as using a photoresist mask over the isolation layer 260. In some embodiments, the opening is formed using a self-aligning process. The bottom of the opening can expose almost all of the top electrode 190 for each MRAM cell. Contact 270 may be formed using a process and material similar to that described above for conductive feature 105 of FIG. 1.

After contact 270 is formed, by any suitable process, a first interconnect (not shown) can be formed over isolation layer 260, and a second interconnect (eg, layer 100 and conductive features ( 105) may be formed below the layer 100. The first interconnect and the second interconnect may provide addressing capabilities, such as bit lines and word lines, to each MRAM cell, such that each MRAM cell is individually addressable.

Referring to FIG. 14, graph 1410 illustrates an exemplary voltage flow for changing the electron spin of MTJ structure 180. The rectangular shape of the flow indicates that electron spin inversion works. Those skilled in the art will understand that the example in FIG. 14 is given for illustrative purposes and is not intended to be limiting. In this example, when the electron spin is unidirectional, the resistance value across the MTJ structure 180 may be about 190 Ω to about 200 Ω. When the electron spin is reversed, the resistance value across the MTJ structure 180 may be about 250 Ω to about 285 Ω. To change the electron spin, a positive voltage of about 1.25 V is applied across the MTJ structure 180 (1), the voltage is removed (2), and then a negative voltage of about -1.25 V is applied to the MTJ structure ( 180) (3). The voltage can be removed (4). To change the voltage spin back, a positive voltage can be applied across the MTJ structure 180 (5), and then the voltage can be removed (6).

In some embodiments, wafer yield and acceptance testing can be performed to test electron spin reversibility. The process used to form the upper electrode 190 increases yield, because more MRAM cells contain functional electron spin reversibility than when using conventional processes and materials. .

From the foregoing, it should be understood that the MRAM device 10 has several advantages. For example, the material and formation of the upper electrode 190 is selected and formed to prevent the possibility of oxygen penetration into the MTJ structure 180 in a subsequent processing step. In particular, the structure of the upper electrode 190 has a peak concentration of crystals oriented with a (111) face-centered cube, and controlled stress characteristics to provide a film subjected to a stress greater than about 400 Mpa. The material of the upper electrode 190 may also include titanium nitride in some embodiments, which also has a relatively high temperature at which oxidation occurs in these processes (eg, greater than about 450 ° C. for a short duration of less than 10 seconds or 70 For longer durations of more than seconds, greater than about 1000 ° C.) has advantages. Since titanium nitride is resistant to oxidation, diffusion of oxygen from the oxidized titanium nitride particles to the MTJ structure 180 is unlikely to occur. As such, diffusion or penetration of oxygen into the MTJ structure 180 is mitigated or prevented, thereby preventing the MTJ structure 180 from failing electron reversibility.

Additionally, wafer acceptance testing and circuit probe yield of the MRAM device 10 are improved over conventional devices. Further, the process flow for the MRAM device 10 can be shortened, for example, the cost of the protective mask (s) for the upper electrode 190 can be reduced.

An embodiment is a method comprising forming a bottom electrode over a via, wherein the via is electrically coupling the bottom electrode to a control line for a magnetoresistive random access memory device (MRAM). A magnetic tunnel junction (MTJ) is formed on the bottom electrode. An upper electrode is formed on the MTJ, and the material of the upper electrode is formed of a first material having an oxidation temperature higher than 450 ° C in 10 seconds or less.

Another embodiment is a method comprising forming a bottom electrode of a magnetoresistive random access memory device (MRAM). The magnetic tunnel junction (MTJ) is formed on the bottom electrode, and the MTJ includes an antiferromagnetic layer, a pinning layer, and a free layer. The upper electrode is formed over the MTJ, the upper electrode is physically coupled to the free layer of MTJ, and contains titanium nitride.

Another embodiment is a magnetoresistive random access memory (MRAM) cell comprising a titanium nitride film and an upper electrode comprising a crystal orientation 111 as the predominant crystal orientation concentration. The MRAM cell further includes a magnetic tunnel junction (MTJ) disposed under the upper electrode and a bottom electrode disposed under the MTJ.

Another embodiment is a magnetoresistive random access memory (MRAM) device that includes a bottom electrode connected to a metal feature of the bottom substrate by bottom electrode vias. The MRAM device further includes a magnetic tunnel junction (MTJ) disposed over the bottom electrode, and an upper electrode disposed over the MTJ and comprising a material having an oxidation temperature of 450 ° C. in 10 seconds or less.

The preceding description outlines features of multiple embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for constructing or modifying other processes and structures that fulfill the same objectives of the embodiments introduced herein and / or achieve the same advantages of the above embodiments. Only. Those skilled in the art should also understand that such equivalent configurations are not departed from the spirit and scope of the present disclosure, and various changes, replacements, and modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure.

<Bookkeeping>

1. As a method,

Forming a bottom electrode over the via, wherein the via is electrically coupling the bottom electrode to a control line for a magnetoresistive random access memory (MRAM) device;

Forming a magnetic tunnel junction (MTJ) on the bottom electrode; And

Forming an upper electrode on the MTJ, wherein the material of the upper electrode is formed of a first material having an oxidation temperature higher than 450 ° C. in 10 seconds or less.

How to include.

2. The method of claim 1, wherein forming the MTJ

Forming a ferromagnetic layer;

Forming a pinning layer on the ferromagnetic layer; And

Forming a free layer over the pinning layer

How to include.

3. The method of claim 2, wherein forming the MTJ further comprises forming a tunnel barrier layer between the ferromagnetic layer and the pinning layer or between the pinning layer and the free layer.

4. The method of claim 1, wherein the first material comprises titanium nitride.

5. The method of claim 1, wherein the first material is a crystalline structure with a maximum number of crystals with a lattice plane orientation of (111).

6. The method of paragraph 1,

Forming the upper electrode and the MTJ into a tapered shape; And

Forming a protective dielectric layer over the sidewalls of the upper electrode and the sidewalls of the MTJ

And further comprising no protective dielectric layer on the top surface of the top electrode and no protective dielectric layer on the top surface of the MTJ.

7. The method of paragraph 1,

Forming a dielectric material over the upper electrode; And

Forming a conductive via through the dielectric material

And further comprising, the bottom surface of the conductive via completely covering the top surface of the top electrode.

8. A magnetoresistive random access memory (MRAM) cell,

An upper electrode comprising a titanium nitride film and comprising crystal orientation (111) as a dominant crystal orientation concentration;

A magnetic tunnel junction (MTJ) disposed under the upper electrode; And

Bottom electrode placed under MTJ

MRAM cell comprising a.

9. The method of claim 8, wherein the MTJ

An antiferromagnetic layer coupled to the bottom electrode;

A pinning layer over the antiferromagnetic layer; And

Free layer above the pinning layer

MRAM cell comprising a.

10. The MRAM cell of claim 9, wherein the MTJ further comprises a tunnel barrier layer disposed between the antiferromagnetic layer and the pinning layer or between the pinning layer and the free layer.

11. The MRAM cell of claim 8, wherein the MTJ and the upper electrode have a shared interface in their respective lateral ranges.

12. The MRAM cell of claim 8, wherein the upper electrode further comprises a second film comprising tantalum.

13. The MRAM cell of claim 12, wherein the second film is tantalum nitride, and the upper surface of the upper electrode is smoother than the upper surface of the second film.

14. The MRAM cell of claim 8, wherein the top electrode has a tensile stress in excess of about 400 Mpa.

15. A magnetoresistive random access memory (MRAM) device,

A bottom electrode connected to a metal feature of the lower substrate by a bottom electrode via;

A magnetic tunnel junction (MTJ) disposed on the bottom electrode; And

An upper electrode disposed over the MTJ, the upper electrode comprising a material having an oxidation temperature higher than 450 ° C. in 10 seconds or less.

MRAM device comprising a.

16. The method of claim 15, wherein the MTJ

A ferromagnetic layer coupled to the bottom electrode;

A pinning layer over the ferromagnetic layer; And

Free layer above the pinning layer

MRAM device comprising a.

17. The MRAM device of claim 16, wherein the MTJ further comprises a tunnel barrier layer disposed between the ferromagnetic layer and the pinning layer or between the pinning layer and the free layer.

18. The method of claim 15,

A MRAM device further comprising a protective dielectric layer disposed on the sidewall of the MTJ and the sidewall of the top electrode, wherein the top surface of the MTJ and the top surface of the top electrode are free of the protective dielectric layer.

19. The method of claim 15,

A MRAM device further comprising a conductor coupled to the upper electrode and extending through the dielectric layer, wherein the bottom surface of the conductor completely covers the upper surface of the upper electrode.

20. The MRAM device of claim 15, wherein there is no dielectric on the top surface of the top electrode.

Claims (10)

As a method,
Forming a bottom electrode over the via, wherein the via is electrically coupling the bottom electrode to a control line for a magnetoresistive random access memory (MRAM) device;
Forming a magnetic tunnel junction (MTJ) on the bottom electrode; And
Forming an upper electrode on the MTJ, wherein the material of the upper electrode is formed of a first material having an oxidation temperature higher than 450 ° C. in 10 seconds or less.
How to include. A magnetoresistive random access memory (MRAM) cell,
An upper electrode comprising a titanium nitride film and comprising crystal orientation (111) as a dominant crystal orientation concentration;
A magnetic tunnel junction (MTJ) disposed under the upper electrode; And
Bottom electrode placed under MTJ
MRAM cell comprising a. The method of claim 2, wherein the MTJ
An antiferromagnetic layer coupled to the bottom electrode;
A pinning layer over the antiferromagnetic layer; And
Free layer above the pinning layer
MRAM cell comprising a. 4. The MRAM cell of claim 3, wherein the MTJ further comprises a tunnel barrier layer disposed between the antiferromagnetic layer and the pinning layer or between the pinning layer and the free layer. 3. The MRAM cell of claim 2, wherein the MTJ and the upper electrode have a shared interface in their respective lateral ranges. 3. The MRAM cell of claim 2, wherein the upper electrode further comprises a second film comprising tantalum. A magnetoresistive random access memory (MRAM) device,
A bottom electrode connected to a metal feature of the lower substrate by a bottom electrode via;
A magnetic tunnel junction (MTJ) disposed on the bottom electrode; And
An upper electrode disposed over the MTJ, the upper electrode comprising a material having an oxidation temperature higher than 450 ° C. in 10 seconds or less.
MRAM device comprising a. The method of claim 7,
A MRAM device further comprising a protective dielectric layer disposed on the sidewall of the MTJ and the sidewall of the upper electrode, wherein the upper surface of the MTJ and the upper surface of the upper electrode are free of the protective dielectric layer. The method of claim 7,
A MRAM device further comprising a conductor coupled to the upper electrode and extending through the dielectric layer, wherein the bottom surface of the conductor completely covers the upper surface of the upper electrode. The MRAM device of claim 7, wherein the upper surface of the upper electrode is free of dielectric material.

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