KR20200029328A - Image sensor incuding cmos image sensor pixel and dynamic vision sensor pixel - Google Patents

Abstract

Disclosed is an image sensor. The image sensor includes a CMOS image sensor (CIS) pixel, a dynamic vision sensor (DVS) pixel, and an image signal processor. The CIS pixel includes a photoelectric conversion element accumulating charges corresponding to incident light and a readout circuit generating an output voltage corresponding to the accumulated charges. The DVS pixel outputs an event signal by sensing a change in incident light intensity based on the accumulated charges and does not include a separate photoelectric conversion element. The image signal processor controls the photoelectric conversion element to be connected to the readout circuit or the DVS pixel. Therefore, a size of the image sensor may be reduced.

Description

Image sensor including CIS pixel and DVS pixel {IMAGE SENSOR INCUDING CMOS IMAGE SENSOR PIXEL AND DYNAMIC VISION SENSOR PIXEL}

The present invention relates to an image sensor, and more particularly, to an image sensor including two types of pixels of different types.

Typical examples of image sensors include a complementary metal-oxide semiconductor (CMOS) image sensor and a dynamic vision sensor. The CMOS image sensor has an advantage of providing the captured image as it is to the user, but has a disadvantage that the amount of data to be processed is large. Since the dynamic vision sensor detects and provides only the event in which the light intensity changes, it has an advantage that the amount of data to be processed is small, but has a disadvantage that the size is larger than the CMOS image sensor.

Compared to these differences, there is a commonality that both CMOS image sensors and dynamic vision sensors require photoelectric conversion elements to sense light. However, since the photoelectric conversion element generally occupies a considerable size of an image sensor, when a CMOS image sensor and a dynamic vision sensor are simultaneously implemented in one device, the size of the device may increase. Therefore, it is becoming an important issue to reduce the size of the image sensor and provide an architecture that can lower the manufacturing cost of the image sensor.

The technical idea of the present disclosure provides an architecture for a CMOS image sensor and a dynamic vision sensor that share a photoelectric conversion element with each other.

More specifically, the technical idea of the present disclosure provides an architecture in which a dynamic vision sensor uses a photoelectric conversion element included in a CMOS image sensor.

An image sensor according to an exemplary embodiment of the present disclosure includes a CIS pixel including a photoelectric conversion element generating charges corresponding to incident light and a lead-out circuit generating an output voltage corresponding to the generated charges, the generation DVS pixels outputting an event signal by detecting the intensity change of the incident light based on the charged charges, and the first path or the generated charges set by the readout circuit to generate the output voltage are the DVS And an image signal processor that controls the second path provided to the pixel.

An image sensor according to another exemplary embodiment of the present disclosure includes a photoelectric conversion element generating charges corresponding to incident light, a driving transistor having a gate electrode connected to a floating diffusion node to which the generated charge is transferred, and the floating diffusion node A CIS pixel including a reset transistor for resetting, a DVS pixel including a log current source, and outputting an event signal by detecting a change in intensity of the incident light based on the accumulated charges, and a gate electrode of the reset transistor And an image signal processor controlling one end of the driving transistor to be connected to the log current source.

In an image sensor according to another embodiment of the present disclosure, a CIS pixel array including a plurality of CIS pixels is formed, and each CIS pixel is a photoelectric conversion element generating charges corresponding to incident light and the generated charges A DVS pixel array including a plurality of DVS pixels is formed, the first substrate comprising a lead-out circuit generating an output voltage corresponding to each DVS pixel, and each DVS pixel is based on the generated charges. Charges generated by at least some of the second substrate and the photoelectric conversion elements, including DVS pixels outputting an event signal by detecting a change in intensity of the, are provided as one CIS pixel of the plurality of CIS pixels It includes an image signal processor to control the path.

According to exemplary embodiments of the present disclosure, the dynamic vision sensor uses a photoelectric conversion element included in a CMOS image sensor.

As a result, not only can the size of the image sensor be reduced, but also the manufacturing cost can be reduced.

1 shows an image sensor according to an example embodiment of the present disclosure.
FIG. 2 shows an exemplary configuration of the CMOS image sensor of FIG. 1.
3 is a circuit diagram showing an exemplary configuration of the CIS pixel of FIG. 2.
FIG. 4 shows an exemplary configuration of the dynamic vision sensor of FIG. 1.
FIG. 5 is a circuit diagram showing an exemplary configuration of DVS pixels constituting the pixel DVS pixel array of FIG. 4.
FIG. 6 shows an exemplary configuration of the DVS pixel back-end circuit of FIG. 5.
7 conceptually illustrates that CIS pixels and DVS pixels share photoelectric conversion elements (PSDs) according to an embodiment of the present disclosure.
8 shows a cross-sectional view of an image sensor in accordance with an exemplary embodiment of the present disclosure.
9 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
FIG. 10 shows operation in the first mode of the image sensor of FIG. 9.
FIG. 11 shows the operation of the image sensor of FIG. 9 in a second mode.
12 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
13 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
14 shows a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
15 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
16 is a circuit diagram showing an exemplary configuration of the CIS pixel of FIG. 2.
17 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
18 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
19 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
20 shows the operation of the image sensor of FIG. 19 in the first mode.
FIG. 21 shows operation in the second mode of the image sensor of FIG. 19.
22 shows a circuit diagram of an image sensor according to an example embodiment of the present disclosure.
23 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.
24 shows a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person having ordinary knowledge in the technical field of the present invention can easily implement the present invention.

The functional blocks shown in the drawings and components described with reference to terms such as a part or a unit, a module, a block, and ~ or (~ er) used in the detailed description It may be implemented in the form of software, hardware, or a combination thereof. Illustratively, the software can be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive elements, or combinations thereof. . Furthermore, in the present specification, the connection of the first component to the second component includes a case in which two components are connected with the third component interposed therebetween.

1 shows an image sensor 1000 according to an exemplary embodiment of the present disclosure. The image sensor 1000 includes an image signal processor 1100, a complementary metal oxide semiconductor (CMOS) image sensor 1200, and a dynamic vision sensor (DVS) 1300.

The image signal processor 1100 may generate an image (IMG) by processing signals output from the CMOS image sensor 1200 and / or the dynamic vision sensor 1300. In an embodiment, the image signal processor 1100 may process the frame-based image data received from the CMOS image sensor 1200 to generate an image IMG. Alternatively, the image signal processor 1100 may generate an image IMG by processing packet-based or frame-based image data received from the dynamic vision sensor 1300.

The image signal processor 1100 may perform various processes on image data received from the CMOS image sensor 1200. For example, the image signal processor 1100 includes color interpolation, color correction, auto white balance, gamma correction, color saturation correction, Various processes such as formatting, bad pixel correction, and hue correction may be performed.

The image signal processor 1100 may perform various processes on image data received from the dynamic vision sensor 1300. For example, the image signal processor 1100 uses a temporal correlation of the timestamp values of adjacent pixels constituting the dynamic vision sensor 1300 to generate noise pixels and hot pixels. Alternatively, the timestamp value of the dead pixel may be corrected.

The CMOS image sensor 1200 includes a plurality of CMOS image sensor (CIS) pixels, each of which includes a photoelectric conversion device (PSD). On the other hand, each DVS pixel constituting the dynamic vision sensor 1300 does not include a photoelectric conversion element. Instead, the dynamic vision sensor 1300 uses a photoelectric conversion element (PSD) of the CMOS image sensor 1200. That is, the CMOS image sensor 1200 and the dynamic vision sensor 1300 share a photoelectric conversion element with each other.

In an embodiment, when the CMOS image sensor 1200 is operating, a path connecting a photoelectric conversion element (PSD) and a DVS pixel is blocked. Conversely, when the dynamic vision sensor 1300 is operating, the photoelectric conversion element PSD and the DVS pixel are electrically connected. In an embodiment, the image signal processor 1100 may change the operation mode of the image sensor 1000. For example, the image signal processor 1100 may control switching between operation modes by generating at least one control signal for changing the operation mode. By configuring the CMOS image sensor 1200 and the dynamic vision sensor 1300 to share a photoelectric conversion element, the size and manufacturing cost of the image sensor 1000 can be reduced. The specific configuration will be described later in detail.

Meanwhile, in this specification, CIS pixels and DVS pixels sharing a photoelectric conversion element will be disclosed, but the present invention can be applied to other types of pixels. For example, the present invention can be applied between a CCD (Charge Coupled Device) type pixel and a CIS pixel. Furthermore, the present invention can also be applied between CCD type pixels and DVS pixels. Furthermore, the present invention can be applied to an image sensor including all CIS pixels, DVS pixels, and CCD pixels.

FIG. 2 shows an exemplary configuration of the CMOS image sensor 1200 of FIG. 1.

The CMOS image sensor 1200 is configured to generate image data for the subject 10 incident through the lens 1201. The CMOS image sensor 1200 includes a CIS pixel array 1210, a row decoder 1220, a CDS circuit 1230, an ADC circuit 1240, an output buffer 1250, a timing controller 1260, and a lamp generator 1270. It includes.

The CIS pixel array 1210 may include a plurality of CIS pixels PXs arranged in rows and columns. In an embodiment, each CIS pixel may have a 3TR pixel structure composed of 3 transistors, a 4TR pixel structure composed of 4 transistors, or a 5TR pixel structure composed of 5 transistors. Alternatively, at least two CIS pixels of the CIS pixels constituting the CIS pixel array 1210 may share the same floating diffusion region (FD) (or floating diffusion node). However, the structure of the CIS pixel is not limited to the above-described configuration.

The row decoder 1220 may select and drive a row of the CIS pixel array 1210. In an embodiment, the row decoder 1210 decodes row addresses and / or control signals output from the timing controller 1260 to generate control signals for selecting and driving a row of the CIS pixel array 1210. For example, the row decoder 1220 may generate a selection signal VSEL, a reset signal VRST, and a transmission signal VTG, and transmit them to pixels corresponding to the selected row.

The Correlated-Double Sampler (CDS) 1230 sequentially samples and holds a reference signal and a set of image signals provided through column lines CL1 to CLn from the CIS pixel array 1210 (Sampling and Holding) )can do. In other words, the correlated double sampler 1230 samples and maintains the level of the reference signal and the video signal corresponding to each of the columns. The correlated double sampler 1230 may provide a set of reference signals and image signals of each of the sampled columns to the analog-to-digital converter 1240 under the control of the timing controller 1260.

The analog-to-digital converter 1240 may convert a correlated double sampling signal corresponding to each column output from the correlated double sampler 1230 into a digital signal. In an embodiment, the analog-to-digital converter 1240 may compare the correlated double-sampled signal with the ramp signal output from the ramp generator 1270, and generate a digital signal corresponding to the comparison result.

The output buffer 1250 may temporarily store and output digital signals provided from the analog-to-digital converter 1240.

The timing controller 1260 operates at least one of a CIS pixel array 1210, a row decoder 1220, a correlated double sampler 1230, an analog-to-digital converter 1240, an output buffer 1250, and a ramp generator 1270. Can be controlled.

The ramp signal generator 1270 may generate a ramp signal and provide it to the analog-to-digital converter 1240.

For example, at least some of the row decoder 1220, the correlated double sampler 1230, the analog-to-digital converter 1340, the output buffer 1250, the timing controller 1260, and the ramp generator 1270 described above are CIS Can be referred to as peripheral circuitry.

3 is a circuit diagram showing an exemplary configuration of the CIS pixel 1211 of FIG. 2. For example, the CIS pixel 1211 may have a 4TR structure composed of four transistors. The CIS pixel 1211 may include photoelectric conversion elements (PSDs), a transfer transistor (TG), a reset transistor (RT), a driving transistor (DT), and a selection transistor (ST).

The photoelectric conversion element PSD may generate photoelectrons (hereinafter referred to as charges) in response to incident light. That is, the photoelectric conversion element (PSD) may generate a photocurrent (IP) by converting an optical signal into an electrical signal. For example, the photoelectric defense or device (PSD) may include a photodiode, a photo transistor, a pinned photodiode, or similar device.

The transfer transistor TG may transfer charges generated by the photoelectric conversion element PCD to the floating diffusion region FD. For example, one end of the transfer transistor TG may be connected to the photoelectric conversion element PSD, and the other end may be connected to the floating diffusion region FD. The transmission transistor TG may be turned on or off under the control of the transmission signal VTG received from the row decoder (FIGS. 2 and 1220).

The floating diffusion region FD has a function of detecting charges corresponding to the amount of incident light. During the time when the transmission signal VTG is activated, charges provided from the photoelectric conversion element PCD may accumulate in the floating diffusion region FD. The floating diffusion region FD may be connected to a gate terminal of the drive transistor DT driven by a source follower amplifier. The floating diffusion region FD may be reset by the power supply voltage VDD provided when the reset transistor RT is turned on.

The reset transistor RT is turned on by the reset signal VRST to provide a power supply voltage VDD to the floating diffusion region FD. As a result, charges accumulated in the floating diffusion region FD move to the power supply voltage VDD stage, and the voltage of the floating diffusion region FD may be reset. Although the power supply voltage VDD is used as the voltage applied to the floating diffusion region FD, it should be understood that various levels of voltage (ie, reset voltage) for resetting the floating diffusion region FD are used.

The driving transistor DT may operate as a source follower amplifier. The driving transistor DT may amplify a change in the electrical potential of the floating diffusion region FD, and output the corresponding output voltage VOUT through the first column line CL1. For example, the CIS pixel 1211 is shown connected to the first column line CL1.

The selection transistor ST is driven by the selection signal VSEL to select a pixel to be read in units of rows. When the selection transistor ST is turned on, the potential of the floating diffusion region FD is amplified through the driving transistor DT and transferred to the drain electrode of the selection transistor ST.

For example, the driving transistor DT and the selection transistor ST may be referred to as a readout circuit. That is, the lead-out circuit may generate an output voltage VOUT corresponding to the charge accumulated in the floating diffusion region FD.

4 shows an exemplary configuration of the dynamic vision sensor 1300 of FIG. 1.

The dynamic vision sensor 1300 may include a DVS pixel array 1310, a column address event representation (AER) circuit 1320, a row AER circuit 1330, and an output buffer 1340. The dynamic vision sensor 1300 detects an event in which the light intensity changes (hereinafter referred to as an 'event'), determines the type of the event (that is, whether the event increases or decreases the light intensity) ), A value corresponding to the event can be output. For example, an event can occur mainly on the outline of a moving object. Unlike the CMOS image sensor (FIGS. 1 and 1200), the dynamic vision sensor 1300 outputs only a value corresponding to light whose intensity changes, so the dynamic vision sensor 1300 and / or the image signal processor (FIGS. 1 and 1100) ) Can significantly reduce the amount of data processed.

The DVS pixel array 1310 may include a plurality of DVS pixels arranged in a matrix form along a plurality of rows and a plurality of columns. The DVS pixel 1311, which detects an event among a plurality of pixels constituting the DVS pixel array 1310, generates a signal (column request; CR) indicating that an event of increasing or decreasing the light intensity occurs in a column AER circuit. (1320).

The column AER circuit 1320 may transmit a response signal ACK to the pixel in response to the column request CR received from the pixel detecting the event. The pixel receiving the response signal ACK may transmit the polarity information Pol of the generated event to the low AER circuit 1330. The column AER circuit 1320 may generate a column address (C_ADDR) of the pixel detecting the event based on the column request (CR) received from the pixel detecting the event.

The row AER circuit 1330 may receive polarity information Pol from a pixel detecting an event. The row AER circuit 1330 may generate a timestamp including information on the time at which the event occurred, based on the polarity information (Pol). For example, the timestamp may be generated by a time stamper 1332 provided in the row AER circuit 1330. For example, the time stamper 1332 may be implemented using a timetick generated in units of several tens to tens of microseconds. The low AER circuit 1330 may transmit a reset signal RST to the DVS pixel 1311 in which an event occurs in response to the polarity information Pol. The reset signal RST may reset the DVS pixel 1311 in which an event has occurred. Furthermore, the row AER circuit 1330 may generate the row address R_ADDR of the DVS pixel 1311 where the event has occurred.

The low AER circuit 1330 may control a cycle in which a reset signal RST is generated. For example, the row AER circuit 1330 may control a period in which a reset signal RST is generated so that an event does not occur for a specific period to prevent the workload from increasing due to too many events. That is, the row AER circuit 1330 may control a refractory period of event generation.

The output buffer 1340 may generate a packet based on a time stamp, a column address (C_ADDR), a row address (R_ADDR), and polarity information (Pol). The output buffer 1340 may add a header indicating the start of the packet to the front end of the packet and a tail indicating the end of the packet to the rear end.

For example, at least some of the column AER 1320, row AER 1330, and output buffer 1340 described above may be referred to as DVS peripheral circuitry.

FIG. 5 is a circuit diagram showing an exemplary configuration of DVS pixels constituting the pixel DVS pixel array of FIG. 4. The DVS pixel 1311 includes a photoreceptor 1313, and a DVS pixel back-end circuit 1315.

The optical receiver 1313 may include a logarithmic amplifier (LA) and a feedback transistor (FB). However, the optical receiver 1313 does not include a photoelectric conversion element (PSD), unlike a typical DVS pixel. The photoelectric conversion element (PSD) illustrated in the drawing may be a component of CIS pixels (FIGS. 3 and 1211). The log amplifier LA amplifies a voltage corresponding to the photo current IPD generated by at least one photoelectric conversion element PSD of the CIS pixel. The logarithmic voltage (VLOG) of the logarithmic scale can be output. The feedback transistor FB may be isolated from the photoreceptor 1313 and the differentiator 1316.

The DVS pixel back-end circuit 1315 may perform various processes for the log voltage VLOG. In an embodiment, the DVS pixel back-end circuit 1315 amplifies the log voltage (VLOG) and compares the amplified voltage with a reference voltage to increase or decrease the intensity of light incident on the photoelectric conversion element (PSD). It is possible to determine whether it is light, and output an event signal (that is, on-event or off-event) corresponding to the determined value. After the DVS pixel back-end circuit 1315 outputs an on-event or an off-event, the DVS pixel back-end circuit 1315 may be reset by a reset signal RST.

FIG. 6 shows an exemplary configuration of the DVS pixel back-end circuit of FIG. 5. The DVS pixel back-end circuit 1315 may include a differentiator 1316, a comparator 1317, and a read circuit 1318.

The differentiator 1316 may be configured to amplify the voltage VLOG to generate the voltage VDIFF. For example, the differentiator 1316 may include capacitors C1 and C2, a differential amplifier DA, and a switch SW operated by a reset signal RST. For example, the capacitors C1 and C2 may store electrical energy generated by at least one photoelectric conversion element PSD. For example, the capacitances of the capacitors C1 and C2 may be appropriately selected in consideration of the shortest time between two events that may occur continuously in one pixel (ie, a refractory period). . When the switch SW is switched on by the reset signal RST, the pixel may be initialized. The reset signal RST may be received from a low AER circuit (eg, 3, 1330).

The comparator 1317 can compare the level of the output voltage VDIFF and the reference voltage Vref of the differential amplifier DA to determine whether an event detected in the pixel is an on-event or an off-event. When an event of increasing light intensity is detected, the comparator 1317 may output a signal ON indicating that it is an on-event, and when an event of decreasing light intensity is detected, the comparator 1317 is off-event It can output a signal (OFF) indicating that.

The read circuit 1318 may transmit information regarding an event occurring in a pixel. The information related to the event output from the read circuit 1318 may include information (eg, a bit) as to whether the generated event is an on-event or an off-event. The information related to the event output from the read circuit 1318 may be referred to as polarity information (FIG. 4, Pol). Polarity information may be transmitted to the row AER circuit (FIGS. 4, 1330).

On the other hand, the configuration of the pixel illustrated in this embodiment is exemplary, and the present invention will also be applied to DVS pixels of various configurations configured to determine the type of event by sensing the intensity of light that changes.

7 conceptually illustrates that CIS pixels and DVS pixels share photoelectric conversion elements (PSDs) according to an embodiment of the present disclosure.

For example, four CIS pixels may correspond to one DVS pixel in a plan view (ie, a view of pixels in the Z-axis direction). This is usually due to the size of DVS pixels being larger than the size of CIS pixels. However, the number of DVS pixels corresponding to one DVS pixel may vary depending on the size of the pixel, and is not limited to that shown in the figure.

The photoelectric conversion element PSD of each CIS pixel 1211 may be connected to the DVS pixel 1311 through an interconnector IC. In an embodiment, when the image sensor (FIGS. 1 and 1000) operates in the DVS mode, only the photoelectric conversion element (PSD) among the components of the CIS pixel 1211 may operate. The charge generated by the photoelectric conversion element (PSD) is transferred to the DVS pixel 1311 through the interconnector (IC). In an embodiment, the interconnector (IC) may mean various configurations for electrically connecting the CIS pixel 1211 and the DVS pixel 1311. For example, the interconnector (IC) may include at least one of electrical wiring, wire, solder ball, bump, and through silicon via (TSV).

8 shows a cross-sectional view of an image sensor in accordance with an exemplary embodiment of the present disclosure. Referring to FIGS. 3 and 5 together, a case where the image sensor 1000 operates in the DVS mode will be described.

The image sensor 1000 includes a CIS pixel array 1210 including CIS pixels 1211 and a DVS pixel array 1310 including DVS pixels 1311. Lenses 1201 may be disposed on the CIS pixel array 1210. The CIS pixel array 1210 and the DVS pixel array 1310 may be formed on different substrates, respectively.

In an embodiment, the first substrate including the CIS pixel array 1210 and the second substrate including the DVS pixel array 1310 may be electrically connected in a flip-chip bonding manner through the solder ball 5. . Alternatively, the first substrate including the CIS pixel array 1210 may be electrically connected through a wire on the second substrate including the DVS pixel array 1310. Alternatively, the first substrate including the CIS pixel array 1210 and the second substrate including the DVS pixel array 1310 may be electrically connected through TSV. Alternatively, the first substrate including the CIS pixel array 1210 and the second substrate including the DVS pixel array 1310 may be electrically connected through Cu-to-Cu bonding. However, these methods are exemplary, and the present invention is not limited to the above-described techniques.

The CIS pixel 1211 includes a photoelectric conversion element (PSD) composed of a first impurity implantation region 2 and a second impurity implantation region 3. The first impurity implantation region 2 and the second impurity implantation region 3 may be doped with different impurities. In an embodiment, the first impurity implantation region 2 may be doped with P-type impurities, and the second impurity implantation region 3 may be doped with N-type impurities. When light enters the photoelectric conversion element (PSD) through the lenses 1201, electron-hole pairs (EHPs) corresponding to the absorbed light intensity are generated.

The CIS pixel 1211 includes a transfer transistor TG and a floating diffusion region FD. Although not illustrated for the sake of simplicity, the CIS pixel 1211 may further include a reset transistor RT, a driving transistor DT, and a selection transistor ST. When the transfer signal VTG is applied to the gate electrode of the transfer transistor TG and the transfer transistor TG is turned on, charges generated in the first impurity implantation region 2 and the second impurity implantation region 3 are It moves to the floating diffusion region FD. The charges of the floating diffusion region FD are transferred to the DVS pixel 1311 through the internal wirings 4, the solder ball 5, and the internal wirings 6.

The DVS pixel 1311 includes an optical receiving end 1313 and a DVS pixel back-end circuit 1315. Exemplarily, one DVS pixel 1311 is based on charges received from a plurality of photoelectric conversion elements (PSDs), and whether the generated event is an event of increasing light intensity or an event of decreasing light intensity It can be determined whether or not. Information regarding the determined event may be transmitted to the outside (eg, the image signal processor 1100 of FIG. 1, a CIS peripheral circuit, a DVS peripheral circuit, etc.) through internal wirings 7.

On the other hand, in this embodiment, the CIS pixel array 1210 and the DVS pixel array 1310 are illustrated as being directly electrically connected as upper and lower layers, respectively, but may be different in other embodiments. That is, at least one of an image signal processor 1100, a CIS peripheral circuit, and a DVS peripheral circuit may be disposed between the CIS pixel array 1210 and the DVS pixel array 1310. However, even in this case, a configuration for transferring charges of the floating diffusion region FD to the DVS pixel 1311 (ie, internal wirings such as the internal wirings 4, 5, and 6) is provided similarly to FIG. 8. Will be.

Referring back to FIG. 8, as shown in FIG. 8, the size of the photoelectric conversion element composed of the first impurity implantation region 2 and the second impurity implantation region 3 is significant, which increases the size of the chip size. It is a factor. However, according to an exemplary embodiment of the present disclosure, the DVS pixel 1311 shares photoelectric conversion elements of a plurality of CIS pixels 1211. Therefore, not only can the size of the image sensor be reduced, but also the manufacturing cost can be reduced.

9 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure. The image sensor 1000 includes CIS pixels 1211 and DVS pixels 1311. For example, it is illustrated that four CIS pixels 1211 are commonly connected to one DVS pixel 1311.

The CIS pixel 1211 is configured to output an output voltage VOUT corresponding to the charge accumulated in the floating diffusion region FD. Since the specific configuration and operation of the CIS pixel 1211 has been described in FIG. 3, a detailed description is omitted. However, unlike FIG. 3, the floating diffusion region FD of the CIS pixel 1211 may be connected to the DVS pixel 1311 through a reset transistor RT. More specifically, the floating diffusion region FD may be connected to a configuration (ie, SW1 and / or SW2) for changing the operation mode of the image sensor 1000 through the reset transistor RT. That is, depending on the operation mode, the CIS pixel 1211 may be selectively connected to the power supply voltage VDD or the feedback transistor FD.

The DVS pixel 1311 is configured to determine whether an event is an on-event or an off-event through charges generated by the photoelectric conversion element (PSD) of the CIS pixel 1211. The detailed configuration and operation of the DVS pixel 1311 has been described in FIGS. 5 and 6. However, unlike shown in FIGS. 5 and 6, the DVS pixel 1311 further includes a configuration (eg, first and second switches SW1 and SW2) for changing the operation mode of the image sensor 1000. can do. The first and second switches SW1 and SW2 may be controlled by the image signal processor 1100 or the switch control signal SWC generated by the low AER (FIGS. 4 and 1330).

In an embodiment, the first and second switches SW1 and SW2 may not be simultaneously switched on / off in the same section. For example, when the first switch SW1 is composed of an NMOS transistor, the second switch SW2 may be composed of a PMOS transistor. In this case, the first and second switches SW1 and SW2 may be controlled by one switch control signal SWC.

In an embodiment, the first and second switches SW1 and SW2 may be composed of the same type of switch. For example, both the first and second switches SW1 and SW2 may be composed of NMOS transistors or PMOS transistors. In this case, a configuration (eg, an inverter, etc.) for inverting the switch control signal SWC such that the first and second switches SW1 and SW2 are simultaneously switched-on or not switched-off in the same section may be further provided. have. For example, the switch control signal SWC may be applied to the first switch SW1, and the inverted switch control signal (not shown) may be applied to the second switch SW2.

In an embodiment, the first and second switches SW1 and SW2 may be composed of the same type of switch. For example, a plurality of control signals for controlling the first and second switches SW1 and SW2, respectively, may be applied to the first and second switches SW1 and SW2, respectively.

Meanwhile, the first and second switches SW1 and SW2 are exemplary. That is, in other embodiments, various configurations for selectively connecting the CIS pixels 1211 to the power supply voltage VDD or the feedback transistor FB may be adopted. And, unlike shown in the drawing, in other embodiments, the first and second switches SW1 and SW2 may be provided outside the DVS pixel 1311 and may be provided inside the CIS pixel 1211. have. That is, the configuration and arrangement of the first and second switches SW1 and SW2 shown in the drawings are not intended to limit the present invention. The configuration and operation of the above-described first and second switches SW1 and SW2 will be equally / similarly applied to the embodiments described below.

FIG. 10 shows operation in the first mode of the image sensor of FIG. 9.

In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 is switched on by the switch control signal SWC, and the second switch SW2 is switched off. As a result, the power supply voltage VDD is applied to the drain electrode of the reset transistor RT through the interconnector IC. In the period of resetting the CIS pixel 1211, when the reset transistor RT is turned on by the reset signal VRST, the floating diffusion region FD is reset by the power supply voltage VDD. Instead, in the first mode, other components except the first and second switches SW1 and SW2 do not operate.

FIG. 11 shows the operation of the image sensor of FIG. 9 in a second mode.

In the second mode, the image sensor 1000 may operate in the DVS mode. The first switch SW1 is switched off by the switch control signal SWC, and the second switch SW2 is switched on. When the transfer transistor TG is turned on, the charges generated by the photoelectric conversion element PSD move to the floating diffusion region FD. Then, when the reset transistor RT is turned on by the reset signal VRST, charges accumulated in the floating diffusion region FD are input to the log amplifier LA. That is, in the second mode, among the components of the CIS pixel 1211, other components except the photoelectric conversion element (PSD), the transfer transistor (TG), and the reset transistor (RT) do not operate. Finally, the photocurrent (IP) is generated by the movement of charges, so that the DVS pixel (1311) will operate.

12 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.

The configuration and operation of the image sensor 1000 is generally similar to that described through FIGS. 9 to 11. However, unlike the embodiments of FIGS. 9 to 11, the CIS pixel 1211 may further include a switch transistor SW2. In addition, the DVS pixel 1311 may include only the first switch SW1. In an embodiment, the image signal processor (FIGS. 1 and 1100) or the row decoder (FIGS. 2 and 1220) may generate a DVS enable signal EN_DVS for controlling the switch transistor SW2.

In the first mode, the image sensor 1000 may operate in the CIS mode. Under the control of the switch control signal SWC, the switch transistor SW2 is turned off, and other components of the CIS pixel 1211 operate similarly to the normal CIS pixel. Also, the DVS pixel 1311 does not operate.

In the second mode, the image sensor 1000 may operate in the DVS mode. Under the control of the DVS enable signal EN_DVS, the switch transistor SW2 is turned on. Among the components of the CIS pixel 1211, components other than the photoelectric conversion element PSD and the switch transistor SW2 do not operate. Then, the first switch SW1 is also switched on under control of the switch control signal SWC. The photocurrent IP is generated by the movement of charges generated by the photoelectric conversion element PSD. As the photocurrent IP is input to the log amplifier LA, the DVS pixel 1311 will operate.

13 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure. This embodiment is similar to the embodiment of FIG. 13 in that the CIS pixel 1311 includes the first switch SW1 and the DVS pixel 1311 includes the switch transistor SW2. However, the switch transistor SW2 may be connected to a node such as the floating diffusion region FD.

In the first mode, the image sensor 1000 may operate in the CIS mode. Under the control of the switch control signal SWC, the switch transistor SW2 is turned off, and other components of the CIS pixel 1211 operate similarly to the normal CIS pixel. Also, the DVS pixel 1311 does not operate. That is, the operation of the CIS pixel 1211 in the first mode is the same as the embodiment of FIG. 13.

In the second mode, the image sensor 1000 may operate in the DVS mode. Under the control of the DVS enable signal EN_DVS, the switch transistor SW2 is turned on. Among the components of the CIS pixel 1211, other components except the photoelectric conversion element (PSD), the transfer transistor (TG), and the switch transistor (SW2) do not operate. That is, it differs from the embodiment of FIG. 13 in that the transfer transistor TG operates. Then, the first switch SW1 is also switched on by the switch control signal SWC. The photoelectric current IP is generated by the movement of charges generated by the photoelectric conversion element PSD, so that the DVS pixel 1311 will operate.

14 shows a circuit diagram of an image sensor 1000 according to an exemplary embodiment of the present disclosure.

The CIS pixel 1211 may include a photoelectric conversion element (PSD), a reset transistor (RT), a driving transistor (DT), and a selection transistor (ST). That is, unlike the previous embodiments, the CIS pixel 1211 includes three transistors and does not include a transfer transistor (eg, TG in FIG. 9).

In the first mode, the image sensor 1000 may operate in the CIS mode. Under the control of the switch control signal SWC, the first switch SW1 is switched on and the second switch SW2 is switched off. The charges generated by the photoelectric conversion element PSD may be directly transferred to the floating diffusion region FD. When the selection transistor ST is turned on by the selection signal VSEL, the process of outputting the output voltage VOUT corresponding to the charge of the floating diffusion region FD is similar to that described in the embodiment of FIG. 3 above. Do.

In the second mode, the image sensor 1000 may operate in the DVS mode. Under the control of the switch control signal SWC, the first switch SW1 is switched off and the second switch SW2 is switched on. Then, under the control of the reset signal VRST, the reset transistor RT is turned on. The photocurrent IP is generated by the charges generated by the photoelectric conversion element PSD, and the DVS pixel 1311 will operate.

15 is a circuit diagram of an image sensor 1000 according to an exemplary embodiment of the present disclosure.

The CIS pixel 1211 may include a photoelectric conversion element (PSD), a transfer transistor (TG), a reset transistor (RT), a first selection transistor (ST1), and a second selection transistor (ST2). That is, the CIS pixel 1211 may have a 5TR structure. The second selection transistor ST2 is turned on by the selection signal VSEL and is configured to transfer the transmission signal VTG to the gate electrode of the transmission transistor TG. The gate electrodes of the first and second selection transistors ST1 and ST2 may be connected to each other to receive the selection signal VSEL.

In the first mode, the image sensor 1000 may operate in the CIS mode. Under the control of the switch control signal SWC, the first switch SW1 is switched on and the second switch SW2 is switched off. In order to transfer the charges generated by the photoelectric conversion element PSD to the floating diffusion region FD, the selection signal VSEL may be applied to the first and second selection transistors ST1 and ST2. The second selection transistor ST2 is turned on, the transfer signal VTG is applied to the transfer transistor TG, and the transfer transistor TG is turned on. As a result, charges are transferred to the floating diffusion region FD. The operation of the CIS pixel 1211 is similar to the embodiment of FIGS. 9 to 11, except that the second select transistor ST2 is added.

In the second mode, the image sensor 1000 may operate in the DVS mode. The second selection transistor ST2 is turned on by the selection signal VSEL. The transfer signal VTG is applied to the gate electrode of the transfer transistor TG, so that the transfer transistor TG is turned on. The reset transistor RT is turned on by the reset signal VRST. Then, under the control of the switch control signal SWC, the first switch SW1 is switched off and the second switch SW2 is switched on. The photocurrent IP is generated by the movement of charges generated by the photoelectric conversion element PSD, and the DVS pixel 1311 is operated by the photocurrent IP.

16 is a circuit diagram showing an exemplary configuration of the CIS pixel of FIG. 2.

The CIS pixel 1211 may include photoelectric conversion elements PSD1 to PSD4, transfer transistors TG1 to TG4, reset transistor RT, driving transistor RT, and selection transistor ST. The first photoelectric conversion element PSD1, the first transfer transistor TG1, the reset transistor RT, the driving transistor RT, and the selection transistor ST constitute the first sub CIS pixel 1211a. Although FIG. 16 shows that the first sub CIS pixel 1211a surrounds only the first photoelectric conversion element PSD1 and the first transfer transistor TG1, this is for simplicity of illustration. Similarly, the second photoelectric conversion element PSD2, the second transfer transistor TG2, the reset transistor RT, the driving transistor RT, and the selection transistor ST constitute the second sub CIS pixel 1211b. . The same applies to the third sub CIS pixel 1211c and the fourth sub CIS pixel 1211d.

The first to fourth sub CIS pixels 1211a, 1211b, 1211c, and 1211d may share the floating diffusion region FD. For example, the first sub CIS pixel 1211a may include a green filter, the second sub CIS pixel 1211b may include a blue filter, and the third sub CIS pixel 1211c may include a red filter. In addition, the fourth sub CIS pixel 1211d may include a green filter. The red filter can pass light in the red wavelength band, the green filter can pass light in the green wavelength band, and the blue filter can pass light in the blue wavelength band.

In an embodiment, the first to fourth sub CIS pixels 1211a, 1211b, 1211c, and 1211d may operate sequentially. For example, when the first transmission transistor TG1 is turned on by the first transmission signal VTG1 during operation of the first sub CIS pixel 1211a, the first photoelectric conversion element PSD1 generates Electric charges are transferred to the floating diffusion region FD. When the selection transistor ST is turned on by the selection signal VSEL, an output voltage VOUT corresponding to the charge of the floating diffusion region FD is output. In addition, the floating diffusion region FD is reset by turning on the reset transistor RT by the reset signal VRST.

After the operation of the first sub CIS pixel 1211a, the second sub CIS pixel 1211b will operate similarly to the first sub CIS pixel 1211a described above. The same applies to the third sub CIS pixel 1211c and the fourth sub CIS pixel 1211d.

However, the color filter arrangement within the aforementioned pixel group, the number of CIS pixels commonly connected to the floating diffusion region FD, the configuration of the pixel group, the operation of the pixel group, etc. are exemplary. The present invention is not limited to this, and the present invention can be applied to CIS image sensors of various configurations in which a plurality of photoelectric conversion elements share a floating diffusion region (FD).

17 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure.

The CIS pixel 1211 shown in FIG. 17 is substantially the same as the CIS pixel 1211 in FIG. 16. Therefore, the components of FIG. 17 may be referred to as first to fourth sub CIS pixels 1211a, 1211b, 1211c, and 1211d as in FIG. 16. For example, the first photoelectric conversion element PSD1, the first transfer transistor TG1, the reset transistor RT, the driving transistor RT, and the selection transistor ST are referred to as first sub CIS pixels. The second to fourth sub CIS pixels are also called similarly. For the sake of simplicity, reference numerals 1211a, 1211b, 1211c, and 1211d shown in FIG. 16 are omitted in FIG. 17.

In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 is switched on by the switch control signal SWC, and the second switch SW2 is switched off. Since the operation of the sub CIS pixels constituting the CIS pixel 1211 in the CIS mode has been described with reference to FIG. 16, a detailed description is omitted.

In the second mode, the image sensor 1000 may operate in the DVS mode. The transfer signals VTG1 to VTG4 are applied to the gate electrodes of the transfer transistors TG1 to TG4, respectively, and the transfer transistors TG1 to TG4 are turned on. The reset transistor RT is turned on by the reset signal VRST. Then, under the control of the switch control signal SWC, the first switch SW1 is switched off and the second switch SW2 is switched on. The photocurrent IP is generated by the movement of charges generated by the photoelectric conversion elements PSD1 to PSD4, and the DVS pixel 1311 will operate by the photocurrent IP.

In an embodiment, only a portion of the transmission transistors TG1 to TG4 may be turned on to adjust the sensitivity (or intensity) of the received light. Unlike the previous embodiments, in this embodiment, 16 CIS pixels are connected to one DVS pixel. Therefore, to adjust the sensitivity (or intensity) of the received light or to reduce the power consumption of the image sensor 1000, only some of the 16 transmission transistors can be turned on.

18 shows a circuit diagram of an image sensor 1000 according to an exemplary embodiment of the present disclosure.

The image sensor 1000 includes a plurality of photoelectric conversion elements (PSDs), a first transistor T1, a second transistor T2, a log current source ILOG, and a DVS pixel back-end circuit 1315. In an embodiment, FIG. 18 shows only components related to generation of an event signal among all components of the image sensor. That is, the components shown in FIG. 18 show only the components operating in the DVS mode among the components of the image sensor, and some components of the CIS pixel are not illustrated.

Briefly describing the operation of the components shown in the drawing, the second transistor T2 may be turned on by the photocurrent IP generated by the charges generated by the photoelectric conversion elements PSD. In addition, the first transistor T1 may be turned on by the log voltage VLOG based on the log current source ILOG. Here, the magnitude of the log voltage VLOG may have a log scale value. For example, a node through which the current of the log current source ILOG is output may be referred to as a log voltage node.

In an embodiment, the log current source ILOG may be a component of DVS pixels. In addition, the first and second transistors T1 and T2 and the photoelectric conversion elements PSD may be components of a CIS pixel. According to this embodiment, not only does the DVS pixel not include a photoelectric conversion element (PSD), but also does not include other components (ie, the first and second transistors T1 and T2). Therefore, it is possible to further reduce the size than a typical DVS pixel. The structure of the image sensor in which DVS pixels share some of the components of a CIS pixel will be described in detail below in FIG. 19.

19 is a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure. In an embodiment, FIG. 19 shows an image sensor 1000 for implementing the circuit diagram of FIG. 18. The image sensor 1000 includes CIS pixels 1211 and DVS pixels 1311. For example, it is illustrated that four CIS pixels 1211 are commonly connected to one DVS pixel 1311.

The CIS pixel 1211 is configured to output an output voltage VOUT corresponding to the charge accumulated in the floating diffusion region FD. The configuration and operation of the CIS pixel 1211 is substantially the same as described in FIG. 9. However, there is a difference in the connection between the CIS pixel 1211 and the DVS pixel 1311. More specifically, the gate electrode of the reset transistor RT may be connected to a configuration (ie, SW1 and / or SW2) for changing the operation mode of the image sensor 1000 through the first interconnect IC1. Further, one end of the driving transistor DT may be connected to a configuration (ie, SW2 and / or SW3) for changing the operation mode of the image sensor 1000 through the second interconnector IC2.

The DVS pixel 1311 is configured to determine whether an event is an on-event or an off-event through charges generated in the photoelectric conversion element PSD of the CIS pixel 1211. However, the DVS pixel 1311 of the present exemplary embodiment does not include a photoelectric conversion element (PSD), and the DVS pixel 1311 of the present exemplary embodiment does not include transistors (eg, T1 and T2 of FIG. 18). Instead, the DVS pixel 1311 may further include a configuration (eg, first to third switches SW1 to SW3) for changing the operation mode of the image sensor 1000. The first to third switches SW1 to SW2 may be controlled by the image signal processor 1100 or the switch control signal SWC generated by the low AER (FIGS. 4 and 1330).

Meanwhile, the image sensor 1000 may include a fourth switch SW4 for selectively providing a power supply voltage VDD applied to the driving transistor DT in the CIS mode. For example, the fourth switch SW4 is connected to the second interconnector IC2 to selectively provide a power supply voltage VDD to the driving transistor DT. For example, the first to fourth switches SW1 to SW4 may be referred to as switching circuits.

20 shows the operation of the image sensor of FIG. 19 in the first mode.

In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 may be switched-on or switched-off by the switch control signal SWC. In more detail, when the floating diffusion region FD is to be reset, the first switch SW1 will be switched on. The second and third switches SW2 and SW3 are switched off. Then, the fourth switch SW4 may be switched on.

FIG. 21 shows operation in the second mode of the image sensor of FIG. 19.

In the second mode, the image sensor 1000 may operate in the DVS mode. The first and fourth switches SW1 and SW4 are switched off by the switch control signal SWC, and the second and third switches SW2 and SW3 are switched on. That is, the gate electrode of the reset transistor RT and the drain electrode of the driving transistor DT may be connected to a log voltage node. Then, the transfer transistor TG is turned on by the transfer signal VTG.

The source electrode of the selection transistor ST to which the output voltage VOUT is output may be grounded. Although not shown for the sake of simplicity, a configuration (eg, switch) for selectively connecting the source electrode of the selection transistor ST to the ground electrode or the column line (eg, CL1 in FIG. 3) may be further provided.

When comparing the circuit diagram according to the switching state of FIG. 21 with FIG. 18, it can be seen that the image sensor 1000 of FIG. 18 and the image sensor 1000 of FIG. 21 are identical to each other. That is, the first and second transistors T1 and T2 of FIG. 18 correspond to the reset transistor RT and the driving transistor DT of FIG. 22, respectively.

22 shows a circuit diagram of an image sensor according to an example embodiment of the present disclosure.

This embodiment is substantially similar to the embodiment of FIGS. 19 to 21. However, compared with the embodiments of FIGS. 19 to 21, this embodiment differs in configuration and arrangement of the switches SW1 to SW4. In an embodiment, the third switch SW3 may be selectively connected to the power supply voltage VDD or the log current source ILOG according to the operation mode. For example, the third switch SW3 may be connected to the power supply voltage VDD in the first mode and may be connected to the log current source ILOG in the second mode.

However, in the first mode, the reset signal VRST is applied to the gate electrode of the reset transistor RT, the power supply voltage VDD is applied to the driving transistor DT, and the gate of the reset transistor RT is applied in the second mode. The configuration for applying the log current source ILOG to the electrode and the driving transistor DT is not limited to this. That is, in addition to the embodiments of FIGS. 19 to 22, switches of various configurations for implementing the circuit diagram of FIG. 18 may be employed.

23 is a circuit diagram of an image sensor 1000 according to an exemplary embodiment of the present disclosure.

The image sensor 1000 includes a plurality of photoelectric conversion elements (PSDs), a first transistor T1, a second transistor T2, a log current source ILOG, and a DVS pixel back-end circuit 1315. In an embodiment, FIG. 23 shows only components related to generation of an event signal among all components of the image sensor. That is, the components shown in FIG. 23 show only components operating in the DVS mode among the components of the image sensor, and some components of the CIS pixel are not shown.

The circuit diagram of FIG. 23 is largely similar to the circuit diagram of FIG. 18. However, the first transistor T1 has been replaced with a PMOS transistor, and one end of the first transistor T1 is connected to a log voltage node through which a log current source ILOG is output. The log current source ILOG may be a component of the DVS pixel, and the first and second transistors T1 and T2, and the photoelectric conversion elements PSD may be components of the CIS pixel. The second transistor T2 may be turned on by the photocurrent IP generated by the charges generated by the photoelectric conversion elements PSD. The first transistor T1 may be turned on by a separate voltage V. The log voltage node may have a logarithmic scale voltage value.

24 shows a circuit diagram of an image sensor according to an exemplary embodiment of the present disclosure. In an embodiment, FIG. 24 shows an image sensor 1000 for implementing the circuit diagram of FIG. 23. The image sensor 1000 includes CIS pixels 1211 and DVS pixels 1311.

The configuration of the CIS pixel 1211 is substantially similar to that of FIG. 19. However, the reset transistor RT may be implemented as a PMOS transistor. One end of the reset transistor RT may be connected to a configuration (ie, SW1 and / or SW2) for changing the operation mode of the image sensor 1000 through the first interconnector IC1. Further, one end of the driving transistor DT may be connected to a configuration (ie, SW2 and / or SW3) for changing the operation mode of the image sensor 1000 through the second interconnector IC2.

The configuration of the DVS pixel 1311 is the same as that of FIG. 19 except that the power supply voltage VDD is provided to the CIS pixel 1211 through the first switch SW1. Therefore, detailed description is omitted.

In the first mode, the image sensor 1000 may operate in the CIS mode. When the floating diffusion region FD is to be reset, the first switch SW1 will be switched on by the switch control signal SWC, and the first switch SW1 will be switched off in the other period. will be. The second and third switches SW2 and SW3 are switched off. Then, the fourth switch SW4 may be switched on.

In the second mode, the image sensor 1000 may operate in the DVS mode. The first and fourth switches SW1 and SW4 are switched off by the switch control signal SWC, and the second and third switches SW2 and SW3 are switched on. That is, one end of the reset transistor RT and one end of the driving transistor DT may be connected to a log voltage node. Then, the transfer transistor TG is turned on by the transfer signal VTG. The reset transistor RT is turned on by the reset signal VRST.

According to the embodiments disclosed above, the DVS pixel of the present disclosure does not include a photoelectric conversion element. Instead, DVS pixels use the photoelectric conversion elements of CIS pixels to determine the type of event. Furthermore, in some embodiments, DVS pixels do not include photoelectric conversion elements, but do not include some transistors, and use transistors of CIS pixels. Therefore, with the proposed architectures, the size of the image sensor can be reduced, and the manufacturing cost can be lowered.

The above are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will also include techniques that can be easily modified and implemented using embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined not only by the claims to be described later but also by the claims and equivalents of the present invention.

1000: image sensor
1100: image signal processor
1200: CMOS image sensor
1300: dynamic vision sensor

Claims (20)

A CIS (CMOS Image Sensor) pixel including a photoelectric conversion element generating charges corresponding to the incident light, and a lead-out circuit generating an output voltage corresponding to the generated charges;
A DVS (Dynamic Vision Sensor) pixel outputting an event signal by detecting a change in intensity of the incident light based on the generated charges; And
And an image signal processor for controlling the first path in which the readout circuit is set to generate the output voltage or the second path in which the generated charges are provided to the DVS pixel. According to claim 1,
The CIS pixels are:
In a first mode and a second mode, a transfer transistor for transferring the generated charges to a floating diffusion node;
A reset transistor that resets the floating diffusion node in the first mode and connects the floating diffusion node to the DVS pixel in the second mode;
A driving transistor generating the output voltage corresponding to the voltage of the floating diffusion node in the first mode; And
In the first mode, further comprising a selection transistor for selecting the CIS pixel so that the output voltage is output outside the CIS pixel,
The driving transistor and the selection transistor constitute the image sensor. According to claim 1,
The CIS pixels are:
In a first mode, a transfer transistor transfers the generated charges to a floating diffusion node;
A reset transistor for resetting the floating diffusion node in the first mode;
A driving transistor generating an output voltage corresponding to the voltage of the floating diffusion node in the first mode;
A selection transistor for selecting the CIS pixel such that the output voltage is output outside the CIS pixel in the first mode; And
In a second mode, further comprising a switch transistor for transferring the generated charges to the DVS pixel,
The driving transistor and the selection transistor constitute the image sensor. According to claim 1,
The CIS pixels are:
In a first mode and a second mode, a transfer transistor for transferring the generated charges to a floating diffusion node;
A reset transistor for resetting the floating diffusion node in the first mode;
A driving transistor generating the output voltage corresponding to the voltage of the floating diffusion node in the first mode;
A selection transistor for selecting the CIS pixel such that the output voltage is output outside the CIS pixel in the first mode; And
And a switch transistor for transferring charges of the floating diffusion node to the DVS pixel in the second mode,
The driving transistor and the selection transistor constitute the image sensor. According to claim 1,
The CIS pixels are:
A reset transistor that resets a floating diffusion node in a first mode and transfers the charges of the floating diffusion node to the DVS pixel in a second mode;
A driving transistor generating the output voltage corresponding to the voltage of the floating diffusion node in the first mode; And
In the first mode, further comprising a selection transistor for selecting the CIS pixel so that the output voltage is output outside the CIS pixel,
The driving transistor and the selection transistor constitute the image sensor. According to claim 1,
The CIS pixels are:
In a first mode and a second mode, a transfer transistor for transferring the generated charges to a floating diffusion node;
A reset transistor that resets the floating diffusion node in the first mode and connects the floating diffusion node to the DVS pixel in the second mode;
A driving transistor generating the output voltage corresponding to the voltage of the floating diffusion node in the first mode;
A first selection transistor for selecting the CIS pixel such that the output voltage is output outside the CIS pixel in the first mode; And
In the first mode and the second mode, further comprising a second selection transistor for transmitting a transmission signal for turning on the transfer transistor to the transfer transistor,
The driving transistor and the selection transistor constitute the image sensor. According to claim 1,
The photoelectric conversion element is a first photoelectric conversion element,
The CIS pixels are:
A second photoelectric conversion element that accumulates charges corresponding to the incident light;
In the first mode and the second mode, first and second transfer transistors respectively transferring charges generated by the first and second photoelectric conversion elements to a floating diffusion node;
A reset transistor that resets the floating diffusion node in the first mode and connects the floating diffusion node to the DVS pixel in the second mode;
A driving transistor generating the output voltage corresponding to the voltage of the floating diffusion node in the first mode; And
In the first mode, further comprising a selection transistor for selecting the CIS pixel so that the output voltage is output outside the CIS pixel,
The driving transistor and the selection transistor are image sensors constituting the readout circuit. According to claim 1,
The DVS pixels are:
An optical receiver outputting a log voltage based on the photocurrent caused by the accumulated charges;
And a DVS pixel back-end circuit for amplifying the log voltage, comparing the amplified voltage with a comparison voltage to determine a change in the intensity of the incident light, and outputting the event signal corresponding to the determined value. Image sensor. According to claim 1,
In the operation of the DVS pixel, the DVS pixel is an image sensor that receives electric charges from photoelectric conversion elements of a plurality of CIS pixels including the CIS pixel. According to claim 1,
A first substrate on which a CIS pixel array including the CIS pixels is formed and a second substrate on which a DVS pixel array containing the DVS pixels is formed are connected by a copper-to-Cu bonding method. Image sensor. According to claim 1,
The DVS pixel is an image sensor that does not include a photoelectric conversion element. CIS (CMOS Image) including a photoelectric conversion element generating charges corresponding to the incident light, a driving transistor having a gate electrode connected to a floating diffusion node to which the generated charge is transferred, and a reset transistor to reset the floating diffusion node Sensor) pixel;
A DVS (Dynamic Vision Sensor) pixel including a log current source and detecting an intensity change of the incident light based on the accumulated charges and outputting an event signal; And
And an image signal processor that controls one end of the gate electrode and the driving transistor of the reset transistor to be connected to the log current source. The method of claim 12,
In the first mode, configured to selectively apply a reset signal to the gate electrode of the reset transistor, and to apply a power supply voltage to the one end of the drive transistor; And
In the second mode, the image sensor further comprises a switching circuit configured to connect the gate electrode of the reset transistor and the one end of the driving transistor with the log current source. The method of claim 13,
The CIS pixels are:
A transfer transistor transferring the generated charges to the floating diffusion node; And
And a selection transistor for selecting the CIS pixel such that an output voltage output from the other end of the driving transistor is output to the outside of the CIS pixel in the first mode. The method of claim 12,
The DVS pixel is an image sensor that does not include a photoelectric conversion element. A CIS pixel array including a plurality of CMOS image sensor (CIS) pixels is formed, each CIS pixel generating a photoelectric conversion element generating charges corresponding to incident light and an output voltage corresponding to the generated charges A first substrate comprising a readout circuit; And
A DVS pixel array including a plurality of Dynamic Vision Sensor (DVS) pixels is formed, and each DVS pixel detects a change in intensity of the incident light based on the generated charges and outputs an event signal (DVS). Sensor) a second substrate comprising pixels; And
And an image signal processor that controls a path in which charges generated by at least some of the photoelectric conversion elements are provided to one of the plurality of CIS pixels. The method of claim 16,
Each CIS pixel is:
In a first mode and a second mode, a transfer transistor transferring the accumulated charges to a floating diffusion node;
A reset transistor that resets the floating diffusion node in the first mode and connects the floating diffusion node to the DVS pixel in the second mode;
A driving transistor generating an output voltage corresponding to the voltage of the floating diffusion node in the first mode; And
In the first mode, the image sensor further comprises a selection transistor for selecting the CIS pixel such that the output voltage is output outside the CIS pixel. The method of claim 16,
Each DVS pixel is:
An optical receiver outputting a log voltage based on the photocurrent caused by the accumulated charges;
And a DVS pixel back-end circuit for amplifying the log voltage, comparing the amplified voltage with a comparison voltage to determine a change in the intensity of the incident light, and outputting the event signal corresponding to the determined value. Image sensor. The method of claim 16
The DVS pixel is an image sensor that does not include a photoelectric conversion element. The method of claim 16,
The first substrate and the second substrate is an image sensor connected by a copper-copper bonding (Cu-to-Cu bonding) method.

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