KR20200028697A - Control method of memory using priority of master bus - Google Patents

Abstract

The present invention relates to a bus system. Specifically, provided is a method for giving different priorities in accordance with characteristics of masters, which is a memory control method considering priority of a master bus which can improve data transmission efficiency by managing memories connected to the master. In addition, a fixed priority method is applied between master groups grouped in at least one master performing the same function, and the memory control method capable of evenly distributing bus usage authorities between masters in each group is applied.

Description

Memory control method considering the priority of the master bus {CONTROL METHOD OF MEMORY USING PRIORITY OF MASTER BUS}

The present invention relates to a bus system, and in particular, to a method of assigning different priorities according to characteristics of the masters, by managing memories connected to the master, memory considering the priority of the master bus that can improve data transmission efficiency It relates to a control method.

In addition, a fixed priority method is applied between master groups grouped into at least one master that performs the same function, and a memory control method in which bus usage rights can be evenly distributed among masters in each group is applied. It is characterized by.

In another embodiment, the present invention relates generally to a semiconductor memory system, device, and method included in a master device, and more particularly, to a memory control method considering priority of a master bus.

Recently, studies on memory have been actively conducted for fast processing of computers and the like. In particular, volatile memory has been used as the main memory in the related art, but research on non-volatile memory is actively conducted to overcome the limitations of volatile memory.

Non-volatile memory is a memory having a characteristic that does not lose data despite the power off. In such a non-volatile memory, a memory cell is non-volatile by itself, and is capable of accessing addresses in bytes at a high speed.

Meanwhile, research on how to manage various types of memory used as the main memory is also being conducted.

Memory devices are generally provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain the information, and may include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide information permanently by maintaining stored information even when there is no power input, in particular, NAND flash memory, NOR flash memory, ROM (read only memory), EEPROM (Electrically Erasable) Programmable ROM (EPROM), Erasable Programmable ROM (EPROM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), such as spin torque transfer random access memory (STT) ).

External interfaces connected to peripheral devices and personal computers to transmit and receive data have been used. Examples of such external interfaces include Universal Serial Bus (USB), Inter-IC bus (I2C), Serial Peripheral Interface (SPI), and Universal Asynchronous Receiver / Transmitter (UART).

Since the above-described conventional buses operate according to a fixed priority, there is a problem of repeating inefficient operation even when the situation changes.

KR10-2004-0042321A (2004.05.20)

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Technical problem to be achieved by the present invention relates to a method of assigning different priorities according to characteristics of masters, and managing memories connected to the master, thereby controlling memory in consideration of the priority of the master bus that can improve data transmission efficiency. Methods are provided.

The present invention is to provide a memory control system that can communicate and process data at high speed and a memory interface method using the same.

Overcoming the above disadvantages In the present application, 1) data including at least one of the presence or absence of bursts of data to be transmitted / received from the master through the bus, the size of the data, the number of requests to use the bus, and the waiting time for bus use. Receiving information; 2) grouping masters into the data information; 3) selecting a priority for the use of the bus of the master according to the presence or absence of the burst and the size of the data; 4) selecting a high priority for the use of the master's bus for the master group having a large number of the bus use requests; 5) allocating the priority in proportion to the number of use requests; 6) if the priority is different from the previously assigned priority, applying the priority by averaging the priority to be allocated and the existing priority; 7) When the use of the bus by the master is completed with the assigned priority, re-assigning the priority by initializing the priority stored in a plurality of memory devices that specify the priority and restarting from step 1) for priority assignment. It will be solved by the memory control method considering the priority of the master bus containing;.

In addition, the memory devices are configured in parallel or sequentially, and each of the plurality of memory devices has respective chain inputs, and whether to configure in parallel or sequentially is based on a programmable option.

In another embodiment, the present invention applies a fixed priority method between master groups grouped into at least one master performing the same function, and bus usage rights can be evenly distributed among masters in each group. It is characterized by applying a bus arbitration method.

In another embodiment, the present invention is to temporarily select a priority for bus use of the specific master as a priority when the waiting time of a bus use request of one of the masters exceeds a preset time. Characterized in that it further comprises.

In another embodiment, the present invention further includes the step of temporarily selecting a priority for the bus use of the specific master as a priority when the waiting time of a specific master bus use request exceeds a preset time. It is characterized by.

In another embodiment, the present invention is characterized in that the bus arbitration method in which the bus usage authority is evenly distributed is one of the round robin, TDMA, and rotary bus methods.

In another embodiment, the present invention is characterized in that the master groups are composed of masters having the same or similar bus requests.

In another embodiment, the present invention is characterized in that when the number of bus use requests of the masters is changed, the priorities of the masters constituting the master group are initialized according to the number of bus use requests.

According to a memory control system and method according to an embodiment of the present invention has the following effects.

First, the present invention can give different priorities according to the characteristics of the masters.

Second, the present invention can improve data transmission efficiency by managing memories connected to masters.

Third, it is possible to efficiently manage the main memory connected to the master device by controlling the memory in consideration of the priority of the master bus.

1 is a block diagram illustrating a memory control system according to an embodiment of the present invention.
2 is a block diagram illustrating a memory control system according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. In the drawings, parts not related to the description are omitted in order to clearly describe the present invention, and the same reference numerals are attached to the same or similar elements throughout the specification.

Throughout the specification, when a part “includes” a certain component, it means that the component may further include other components, not to exclude other components, unless otherwise stated.

In addition, the terms "… unit" and "... module" described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software.

In this application, in order to manage the memory connected to an efficient bus master, 1) information on at least one of the presence or absence of bursts of data to be transmitted and received through the bus from the master, the size of the data, the number of requests to use the bus, and the waiting time for bus use. Receiving data information including; 2) grouping masters according to the data information; 3) selecting a priority for the use of the bus of the master according to the presence or absence of the burst and the size of the data; 4) selecting a high priority for the use of the master's bus for the master group having a large number of the bus use requests; 5) allocating the priority in proportion to the number of use requests; 6) if the priority is different from the previously assigned priority, applying the priority by averaging the priority to be allocated and the existing priority; 7) When the use of the bus by the master is completed with the assigned priority, re-assigning the priority by initializing the priority stored in a plurality of memory devices that specify the priority and restarting from step 1) for priority assignment. It characterized in that it contains a.

In addition, the memory devices are configured in parallel or sequentially, and each of the plurality of memory devices has respective chain inputs, and whether to configure in parallel or sequentially may include features based on programmable options. .

In another embodiment, the present invention applies a fixed priority method between master groups grouped into at least one master performing the same function, and bus usage rights can be evenly distributed among masters in each group. It may include features that apply bus arbitration methods.

In another embodiment, the present invention is to temporarily select a priority for bus use of the specific master as a priority when the waiting time of a bus use request of one of the masters exceeds a preset time. Features may further include.

In another embodiment, the present invention further includes the step of temporarily selecting a priority for the bus use of the specific master as a priority when the waiting time of a specific master bus use request exceeds a preset time. Features may be included.

In another embodiment, the present invention may include a feature that the bus arbitration method in which the bus usage authority is evenly distributed is one of round robin, TDMA, and rotary bus methods.

In another embodiment, the present invention may include a feature that the master groups consist of masters having the same or similar number of bus requests.

In another embodiment, the present invention may include a feature of initializing priorities of the masters constituting the master group according to the number of bus use requests, when the number of bus use requests of masters is changed.

The bus system of the present application includes one bus, a plurality of masters, a plurality of slaves, an arbiter, and a master bus memory controller that controls the priority of the bus.

When a plurality of masters want to connect to a plurality of slaves, that is, when the masters want to transmit data from slaves or to load data from slaves, the arbitrator requests the use of the bus. At this time, the arbiter determines the priority of each of the masters to use the bus according to a predetermined priority determination method, and the master who has obtained the use permission of the bus from the arbiter connects to the slaves through the bus 10.

In the present application, in order to manage a memory connected to an efficient bus master, at least one of bus presence / absence of the data to be transmitted / received through the bus from another master, the size of the data, the number of requests for bus use, and the waiting time for bus use Data information including information of is received.

The bus master controller groups masters according to the received data information, and the grouped masters are given priority according to predetermined rules.

The criteria for giving priority include the presence or absence of the burst of the data and the size of the data. In addition, a master group having a large number of requests for bus use may select a high priority for the bus use of the master.

The priority may be allocated in proportion to the number of use requests for efficient use of the bus. However, if the priority is different from the existing assigned priority, the priority may be applied by averaging the priority to be allocated and the existing priority, or maintaining a predetermined priority.

Since the memory of the bus master controller always performs a lot of operations, the number of prioritization counts a certain number, or when the use of the bus by the master is completed with the assigned priority, it is stored in a plurality of memory devices that specify the priority. The priority is initialized, and the initialization area may be an area for priority allocation, or may be initialized including the entire memory.

When the memory is initialized, for priority allocation, 1) contains information of at least one of the presence or absence of bursts of data to be transmitted and received from the master through the bus, the size of the data, the number of requests to use the bus, and the waiting time for bus use Receiving data information; Restart to reassign the priority.

In addition, the memory of the bus master controller is configured in parallel or sequentially, and each of the plurality of memory devices has respective chain inputs, and whether to configure in parallel or sequentially includes features based on programmable options. You can also use a backup system using a heartbit for operational stability.

In assigning the priority, a group of at least one master performing the same function is grouped, or a fixed priority method is applied between master groups grouped by a group arbitrarily set by an operator, and between masters in each group. Bus usage rights can be evenly distributed.

When the waiting time for a bus use request of one of the masters connected to the bus exceeds a preset time or there is a lot of data to be transmitted, the priority for the bus use of the specific master may be temporarily increased and selected.

The grouped masters can effectively distribute the bus usage rights so that the masters connected to the bus can be efficiently operated.

In addition, in grouping masters, it is possible to group masters having the same or similar number of bus requests. However, when the number of bus use requests of the masters changes, the priority of the masters constituting the master group may be initialized according to the number of bus use requests to allocate resources of the limited bus system fairly.

Hereinafter, a memory control system and a memory interface method using the same according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a memory control system according to an embodiment of the present invention.

Referring to FIG. 1, a memory control system according to an embodiment of the present invention includes a processor 10, a memory control unit 20, a main memory 30, and a storage device 40.

The processor 10 is a part that performs computing operations on at least one or more processes (eg, system processes, application processes, etc.). In addition, the processor 10 is a part that controls the entire memory control system and executes various program instructions.

In addition, the processor 10 may issue an allocation request command to the memory control unit 20 to allocate the main memory 30, or a release request command to the memory control unit 20 to release the memory object from the main memory 30. You can. For example, when the processor 10 instructs the memory control unit 20 to secure a space, the memory control unit 20 processes a series of processes for securing the space. 2 will be described below in detail.

The memory control unit 20 is a part that controls the main memory 30. The memory control unit 20 may include an integrated memory control unit 21, a first memory control unit 23, and a second memory control unit 25. The integrated memory control unit 21 may be configured to control the first memory control unit 23. 2 controls the memory control unit 25, the first memory control unit 23 controls the first memory 33, and the second memory control unit 25 controls the second memory 35.

For example, the integrated memory control unit 21 receives a space securing command from the processor 10, so that the first memory control unit 23 and the second memory control unit 25 have a first memory 33 and a second memory ( It controls to allocate, deallocate, and move and retrieve memory objects in 35).

The first memory control unit 23 and the second memory control unit 25 control to allocate and release memory objects in the first memory 33 and the second memory 35, and to move and retrieve them to secure space. To the integrated memory control unit 21.

In addition, when the memory object allocation request is received from the processor 10, the integrated memory control unit 21 selects a target sub-memory to allocate a memory object from among the first memory 33 and the second memory 35, and the first The allocation request is transmitted to the corresponding portion among the memory control unit 23 and the second memory control unit 25.

In addition, when receiving a request for releasing a specific memory object from the processor 10, the integrated memory control unit 21 determines the location of the specific memory object in the first memory 33 and the second memory 35, and the first memory control unit (23) and the second memory control unit (25) transmits a release request to the corresponding part.

In addition, the memory control unit 20 determines the first sacrificial object when the first usable area is insufficient in the first memory 33, and if the second usable area is present in the second memory 35, the first sacrificial object. Controls moving to the second usable area.

Also, the memory control unit 20 determines whether to move the first victim object, and controls the recovery of the first victim object if the first victim object is not moved.

It is noted that the memory control unit 20 of the present invention may exist in hardware or in software.

The main memory 30 is a portion for storing data and result data during a computing operation for at least one process processed by the processor 10. In addition, the main memory 30 is a storage device due to causes such as termination of the computing operation for the process, the processor 10 reads and temporarily stores the necessary files from the storage device 40 for computing operations for the process. Until data is transferred to (40), data during the computing operation and result data may be stored.

The main memory 30 may include a first memory 33 and a second memory 35. The first memory 33 and the second memory 35 constituting the main memory 30 may be either non-volatile memory or volatile memory. For example, the main memory 30 may be expressed as a hybrid memory, and the configuration of the main memory 30 may be varied such as non-volatile memory and volatile memory, volatile memory and volatile memory, non-volatile memory and non-volatile memory. And the present invention is applicable to various embodiments.

The non-volatile memory may be, for example, non-volatile random access memory (NVRAM), and the non-volatile RAM may be storage class memory (SCM), which is a storage class memory (PCRAM). Examples include Change RAM (MRAM), Magneto-resistive RAM (MRAM), and Ferroelectric RAM (FeRAM). DRAM is possible as a volatile memory.

In addition, in this embodiment, the case where the main memory 30 is composed of two memories is exemplified, but the present invention is applicable even when the main memory 30 is two or more.

The storage device 40 is a part for storing data. For example, the storage device 40 may be a hard disk or the like.

2 is a block diagram of a memory control system according to an embodiment of the present invention.

Referring to FIG. 2, a memory control system according to an embodiment of the present invention includes a central processing unit 100, a memory control unit 200, and a memory 300. It shows only a schematic configuration necessary for description according to an embodiment of the present invention, but is not limited to such configuration.

The central processing unit (CPU) 100 generates a memory control signal and transmits the generated memory control signal to the memory control unit 200.

In addition, the memory control unit 200 is formed outside the central processing unit 100. The memory control unit 200 controls the operation of the memory 200 using a memory control signal transmitted from the central processing unit 100.

And, between the central processing unit 100 and the memory control unit 200, a single link made of a serial link is formed according to an embodiment of the present invention. Then, the central processing unit 100 transmits a memory control signal to the memory control unit 200 through the single link.

Here, the memory control signal includes any one or more of a command signal for controlling the memory 300 or data stored in the memory 300. Accordingly, when the memory control signal according to an embodiment of the present invention includes both a command signal and data, a single link can simultaneously transmit the command signal and the data in one serial packet.

In addition, the memory 300 stores data and performs an operation by an external control signal such as a memory control signal. Here, the memory 300 according to an embodiment of the present invention includes a DDR double data rate synchronous DRAM (SDRAM).

Also, the memory 300 may be a non-volatile memory or a volatile memory.

Nonvolatile memory, such as flash memory or EIPROM, is read and write as the main command, and the operation is performed through several other commands.

In the case of SDRAM, which is a volatile memory, in addition to reading and writing, operations are performed through commands of refresh, precharge and active, and to maintain internal data in the power-up state. There are basic operation commands.

Although the preferred embodiment of the present invention has been described through the above, the present invention is not limited to this, and it is possible to carry out various modifications or changes within the scope of the claims and detailed description of the invention and the accompanying drawings. Moreover, it is natural that they fall within the scope of the present invention.

10 processors
20 Memory control unit
21 Integrated Memory Control
23 1st memory control unit
25 Second memory control unit
30 main memory
33 1st memory
35 Second memory
40 storage
100 central processing unit
110 Transaction Layer
120 data layer
130 Physical Layer
200 memory control unit
210 Physical Layer
220 data layer
230 Transaction Layer
300 memory

Claims (3)

In the memory control method considering the priority of the master bus,
1) The controller including the bus priority controller includes information on at least one of the presence or absence of bursts of data to be transmitted and received through the bus from other bus masters, the size of the data, the number of requests to use the bus, and the waiting time for bus use. Receiving data information;
2) grouping masters according to the data information;
3) Priority for the use of the bus of the master is selected according to the presence / absence of the burst of the data and the size of the data, and when the waiting time for a bus use request of a specific master exceeds a preset time, the specific master Temporarily selecting a priority for bus use as a priority;
4) selecting a high priority for the use of the bus of the master for the master group having a large number of requests for bus use;
5) assigning the priority in proportion to the number of use requests;
6) if the priority is different from the previously assigned priority, applying the priority by averaging the priority to be allocated and the existing priority;
7) When the use of the bus by the master is completed with the assigned priority, re-assigning the priority by initializing the priority stored in a plurality of memory devices that specify the priority and restarting from step 1) above for priority assignment. ;
The memory devices are configured in parallel or sequentially, each of the plurality of memory devices has a respective chain input, and whether to configure in parallel or sequentially is based on a programmable option. Memory control method considering rank. According to claim 1,
The bus arbitration method in which the bus usage authority can be evenly distributed is one of round robin, TDMA, and rotary bus methods, and the memory control method considering the priority of the master bus. According to claim 1,
The master group is a memory control method considering the priority of the master bus, characterized in that the number of bus use requests are made of the same or similar masters.

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