KR20200026569A - Display apparatus - Google Patents

Abstract

According to the present invention, a display device comprises: a substrate including a display area having a plurality of pixels and a pad area having at least one pad electrode; a protective layer covering the edge of the pad electrode while covering the display area; a first encapsulation layer covering the protective layer on the display area; a second encapsulation layer additionally covering the protective layer on the pad area while covering the first encapsulation layer; and a third encapsulation layer covering the second encapsulation layer on the display area. Thus, the protective layer can be selectively patterned without adding a separate mask process.

Description

Display device {DISPLAY APPARATUS}

The present application relates to a display device.

The display device is widely used as a display screen of a notebook computer, a tablet computer, a smartphone, a portable display device, a portable information device, etc. in addition to the display screen of a television or a monitor.

Recently, research and development of a light emitting display device using a micro light emitting device have been conducted. Since such a light emitting display device has high image quality and high reliability, it has been spotlighted as a next generation display. Such a light emitting display device is a self-luminous element, and has low power consumption, high response speed, high light emission efficiency, high luminance, and a wide viewing angle. Such a light emitting display device is mounted on an electronic product or a home appliance such as a television, a monitor, a notebook computer, a smartphone, a tablet computer, an electronic pad, a wearable device, a watch phone, a portable information device, a navigation device, or a vehicle control display device It is attracting attention as a next generation display that can be used as a display for displaying a.

The light emitting display device displays an image in a top emission method or a bottom emission method.

A conventional top emission type light emitting display device includes a pixel circuit including a driving thin film transistor disposed in a sub pixel region, an anode connected to the driving thin film transistor, a light emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light emitting layer. It may include. In this case, the anode electrode is made of a reflective metal material, and the cathode electrode is made of a transparent conductive metal material to improve transmittance.

However, the conventional top emission type light emitting display device requires a separate patterning process and a plasma damage may occur when the protective layer patterning process covering the pad electrode is performed through a dry etching process. Accordingly, the conventional light emitting display device requires a separate etching protection layer for preventing plasma damage, and deteriorates the reliability of the panel.

The present application provides a display device capable of selectively patterning a protective layer without adding a separate mask process by using an encapsulation layer as a mask in a process of patterning a protective layer covering an edge of a pad electrode. Shall be.

In addition, the present application is to provide a display device that can prevent the moisture permeation through the pad contact hole provided with an anisotropic conductive film by surrounding the side of the pad electrode and the anisotropic conductive film through a protective layer and an encapsulation layer. do.

A display device according to the present application includes a substrate including a display area having a plurality of pixels and a pad area having at least one pad electrode, a protective layer covering the edge of the pad electrode while covering the display area, and a protective layer on the display area. An encapsulation layer includes a covering first encapsulation layer, a second encapsulation layer further covering the protective layer on the pad region while covering the first encapsulation layer, and a third encapsulation layer covering the second encapsulation layer on the display region.

Specific details of other examples are included in the detailed description and the drawings.

The display device according to the present application may selectively pattern the protective layer without adding a separate mask process by using the encapsulation layer as a mask in the process of patterning the protective layer covering the edge of the pad electrode.

In the display device according to the present application, the side surfaces of the pad electrode and the anisotropic conductive film are surrounded by the protective layer and the encapsulation layer, thereby preventing moisture permeation through the pad contact hole provided with the anisotropic conductive film.

In addition to the effects of the present application mentioned above, other features and advantages of the present application will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a plan view illustrating a display device according to an example of the present application.
2 is a cross-sectional view taken along the line II ′ of FIG. 1.
3 is an enlarged view of region A of FIG. 2.
4 is a cross-sectional view illustrating a method of manufacturing a display device according to an example of the present application, which is a cross-sectional view taken along line II ′ of FIG. 2.

Advantages and features of the present application, and a method of achieving them will be apparent with reference to the examples described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the examples disclosed below, but will be implemented in various forms, and only the examples are intended to complete the disclosure of the present invention and to those skilled in the art to which the present invention pertains. It is provided to inform the full scope of the invention, which is to be defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the example of the present application are exemplary and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present application, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present application, the detailed description thereof will be omitted. When 'include', 'have', 'consist of', etc. mentioned in the present application are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as 'on', 'upper', 'lower', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present invention.

In describing the components of the present application, terms such as first and second may be used. These terms are only to distinguish the components from other components, and the terms are not limited in nature, order, order or number of the components. When a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but between components It will be understood that the elements may be "interposed" or each component may be "connected", "coupled" or "connected" through other components.

Accordingly, the display device in the present application may include a narrow display device itself, such as an LCM, an OLED module, and the like, or a set device that is an application product or an end consumer device including the LCM, an OLED module, and the like.

For example, when the display panel is an organic electroluminescent (OLED) display panel, the display panel may include a plurality of gate lines and data lines, and a plurality of pixels formed at an intersection of the gate lines and the data lines. . And an array substrate including a thin film transistor, which is an element for selectively applying a voltage to each pixel, an organic light emitting element (OLED) layer on the array substrate, and an encapsulation substrate disposed on the array substrate to cover the organic light emitting element layer. Or an encapsulation substrate. The encapsulation substrate protects the thin film transistor, the organic light emitting element layer, and the like from an external impact, and can prevent moisture and oxygen from penetrating into the organic light emitting element layer. The layer formed on the array substrate may include an inorganic light emitting layer, for example, a nano-sized material layer or a quantum dot.

The display panel may further include a backing such as a metal plate attached to the display panel. Not only the metal plate but also other structures may be included.

Each of the features of the various examples of the present application may be combined or combined with each other, partly or wholly, and technically various interlocking and driving are possible, and each of the examples may be independently implemented with respect to each other or may be implemented in association with each other. .

Hereinafter, an example of the present application will be described with reference to the accompanying drawings and examples.

1 is a plan view illustrating a display device according to an example of the present application.

Referring to FIG. 1, the display device 100 includes a substrate 110, a pixel array layer 190, a display driving circuit unit 210, and a scan driving circuit unit 220.

The substrate 110 may be a flexible substrate as a base substrate. For example, the substrate 110 may include a transparent polyimide material. Since the substrate 110 made of polyimide is made of a high temperature deposition process, a polyimide having excellent heat resistance that can withstand high temperatures may be used. The polyimide substrate 110 may be formed by curing a polyimide resin coated with a predetermined thickness on a front surface of a sacrificial layer provided on a carrier glass substrate. Here, the carrier glass substrate may be separated from the substrate 110 by release of the sacrificial layer by a laser release process. The sacrificial layer may be formed through amorphous silicon (a-Si) or silicon nitride (SiNx).

According to an example, the substrate 110 may be a glass substrate. For example, the substrate 110 may include silicon oxide (SiO 2) or aluminum oxide (Al 2 O 3) as a main component.

The substrate 110 may include a display area AA, a non-display area NA, and a pad area PA. The display area AA is an area in which an image is displayed and may be defined in the central portion of the substrate 110. The display area AA may correspond to the active area of the pixel array layer 190. For example, the display area AA may include a plurality of pixels (not shown) formed for each pixel area intersected by a plurality of gate lines (not shown) and a plurality of data lines (not shown). Here, each of the plurality of pixels may be defined as an area of a minimum unit that emits light.

The non-display area NA is an area where no image is displayed and may surround the display area AA together with the pad area PA. That is, the non-display area AA may be defined at an edge portion of the substrate 110 surrounding the display area AA.

The pad area PA may be disposed at one edge of the substrate 110, and the pad electrode of the pad area PA may be electrically connected to the flexible circuit film 211 of the display driving circuit 210. Accordingly, the display device 100 may receive a signal and a power from the display driving circuit 210 through the pad electrode.

The pixel array layer 190 includes a thin film transistor layer and a light emitting device layer. The thin film transistor layer may include a thin film transistor, a gate insulating film, an interlayer insulating film, a protective film, and a planarization layer. The light emitting device layer may include a plurality of organic light emitting devices and a plurality of banks. A detailed configuration of the pixel array layer 190 will be described in detail with reference to FIG. 2 below.

The display driving circuit unit 210 may be connected to a pad unit (or pad electrode) provided in the pad area PA of the substrate 110 to display an image corresponding to image data supplied from the display driving system on each pixel. According to an example, the display driving circuit unit 210 may include a plurality of flexible circuit films 211, a plurality of data driving integrated circuits 213, a printed circuit board 215, and a timing controller 217.

Input terminals provided on one side of each of the plurality of flexible circuit films 211 are attached to the printed circuit board 215 by a film attaching process, and output terminals provided on the other side of each of the plurality of flexible circuit films 211 are formed of a film attaching process. It can be attached to the pad portion (or pad electrode) by. According to an example, each of the plurality of flexible circuit films 211 may be implemented by bending the flexible circuit film to reduce the bezel area of the display device 100. For example, the plurality of flexible circuit films 211 may be formed of a tape carrier package (TCP) or a chip on flexible board or chip on film (COF).

Each of the plurality of data driver integrated circuits 213 may be separately mounted on each of the plurality of flexible circuit films 211. Each of the plurality of data driving integrated circuits 213 receives pixel data and a data control signal provided from the timing controller 217, and converts the pixel data into an analog type pixel-specific data signal according to the data control signal. Can be supplied to data lines.

The printed circuit board 215 may support the timing controller 217 and transfer signals and power between the components of the display driving circuit unit 210. The printed circuit board 215 may provide the plurality of data driver integrated circuits 213 and the scan driver circuit 220 with signals and driving power supplied from the timing controller 217 to display an image on each pixel. To this end, signal transmission lines and various power lines may be provided on the printed circuit board 215. For example, the printed circuit board 215 may be formed of one or more according to the number of the flexible circuit film 211.

The timing controller 217 may be mounted on the printed circuit board 215 and receive image data and a timing synchronization signal provided from the display driving system through a user connector provided on the printed circuit board 215. The timing controller 217 may generate pixel data by aligning the image data according to the pixel arrangement structure based on the timing synchronization signal, and provide the generated pixel data to the corresponding data driving integrated circuit 213. The timing controller 217 generates a data control signal and a scan control signal based on the timing synchronization signal, controls the driving timing of each of the plurality of data driver integrated circuits 213 through the data control signal, and controls the scan. The driving timing of the scan driving circuit unit 220 may be controlled through the signal. The scan control signal may be supplied to the corresponding scan driving circuit 220 through the first or / and the last flexible circuit film 211 of the plurality of flexible circuit films 211 and the non-display area NA of the substrate 110. have.

The scan driving circuit unit 220 may be provided in the non-display area NA of the substrate 110. The scan driving circuit unit 220 may generate a scan signal according to a scan control signal provided from the display driving circuit unit 210 and supply the scan signal to a scan line corresponding to a set order. In example embodiments, the scan driving circuit 220 may be formed in the non-display area NA of the substrate 110 together with the thin film transistor.

2 is a cross-sectional view taken along the line II ′ of FIG. 1, and FIG. 3 is an enlarged view of region A of FIG. 2.

2 and 3, the display device 100 includes a substrate 110, a light blocking layer LS, a buffer layer 120, a thin film transistor T, a gate insulating layer 130, an interlayer insulating layer 140, and a second insulating layer 140. The first passivation layer 150, the planarization layer 160, the organic light emitting device E, the bank B, the second passivation layer 170, the encapsulation layer 180, the first and second auxiliary power lines EVSS1, EVSS2, a line contact pattern LCP, a contact pad CP, a storage capacitor Cst, a signal pad SP, a pad auxiliary electrode PAE, and a pad electrode PE.

The substrate 110 may be a transparent flexible substrate that can be bent or bent as a base substrate. According to an example, the substrate 110 may include a transparent polyimide material, but is not limited thereto and may be made of a transparent plastic material such as polyethylene terephthalate. In addition, the polyimide substrate 110 may be a polyimide having excellent heat resistance that can withstand high temperatures in consideration of a high temperature deposition process.

According to an example, the substrate 110 may be a glass substrate. For example, the substrate 110 may include silicon dioxide (SiO 2) or aluminum oxide (Al 2 O 3) as a main component.

The light blocking layer LS may be disposed on the substrate 110 to overlap the thin film transistor T. For example, the light blocking layer LS may be formed by depositing a metal on the substrate 110 and then performing exposure patterning. According to an example, the light blocking layer LS may be made of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), and silver (Ag) or an alloy thereof, but is not limited thereto. It can be implemented in various materials. The light blocking layer LS may include a lower light blocking layer LS1 and an upper light blocking layer LS2.

The lower light blocking layer LS1 may be formed between the substrate 110 and the upper light blocking layer LS2 to promote adhesion between the substrate 110 and the upper light blocking layer LS2. The lower light blocking layer LS1 may prevent the lower surface of the upper light blocking layer LS2 from corroding.

The upper light blocking layer LS2 may be formed on an upper surface of the lower light blocking layer LS1. In detail, the upper light blocking layer LS2 may be formed of a metal having a lower resistance than the lower light blocking layer LS1. The upper light blocking layer LS2 may be formed thicker than the lower light blocking layer LS1 in order to reduce the overall resistance of the light blocking layer LS.

The buffer layer 120 may be disposed on the substrate 110 and the light blocking layer LS. According to an example, the buffer layer 120 may be formed by stacking a plurality of inorganic layers. For example, the buffer layer 120 may be formed of a multilayer film in which at least one inorganic film of a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiON) is stacked. The buffer layer may be formed on the entire upper surface of the substrate 110 to block moisture penetrating into the organic light emitting device E through the substrate 110. Therefore, the buffer layer 120 may include a plurality of inorganic films, thereby improving the water vapor transmission rate (WVTR) of the panel.

The thin film transistor T may be disposed in each of the plurality of pixel regions on the buffer layer 120. In example embodiments, the thin film transistor T may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

The active layer ACT may be provided in the pixel area of the substrate 110. The active layer ACT may be disposed to overlap the gate electrode GE, the source electrode SE, and the drain electrode DE. The active layer ACT may directly contact the source electrode SE and the drain electrode DE, and may face each other with the gate electrode GE and the gate insulating layer 130 interposed therebetween.

According to an example, the active layer ACT may include a channel region ACT1 and a source / drain region ACT2. The channel region ACT1 may be formed in the center region of the active layer ACT, and the source / drain region ACT2 may be formed in parallel with each other with the channel region ACT1 interposed therebetween. The channel region ACT1 may overlap the gate electrode GE, and the source / drain region ACT2 may overlap the source electrode SE and the drain electrode DE.

The gate insulating layer 130 may be provided on the active layer ACT. In detail, the gate insulating layer 130 may be disposed on the channel region ACT1 of the active layer ACT and may insulate the active layer ACT from the gate electrode GE.

The gate electrode GE may be provided on the gate insulating layer 130. The gate electrode GE may overlap the channel region ACT1 of the active layer ACT with the gate insulating layer 130 interposed therebetween.

In example embodiments, the gate electrode GE may include a lower gate electrode GE1 and an upper gate electrode GE2.

The lower gate electrode GE1 may be formed between the gate insulating layer 130 and the upper gate electrode GE2 to enhance the adhesive force between the gate insulating layer 130 and the upper gate electrode GE2, and the upper gate electrode GE2 Can prevent corrosion of the lower surface.

The upper gate electrode GE2 may be formed on an upper surface of the lower gate electrode GE1. According to an example, the thickness of the upper gate electrode GE2 is formed to be thicker than the thickness of the lower gate electrode GE1, so that the overall resistance of the gate electrode GE may be reduced.

The interlayer insulating layer 140 may be provided on the gate electrode GE. The interlayer insulating layer 140 may function to protect the thin film transistor T. The interlayer insulating layer 140 may have a corresponding region removed to contact the active layer ACT and the source electrode SE or the drain electrode DE. For example, the interlayer insulating layer 140 may include a first contact hole through which the source electrode SE penetrates and a second contact hole through which the drain electrode DE penetrates.

The source electrode SE and the drain electrode DE may be spaced apart from each other on the interlayer insulating layer 140. The source electrode SE contacts one end of the source / drain region ACT2 of the active layer ACT through the first contact hole provided in the interlayer insulating layer 140, and the drain electrode DE is connected to the interlayer insulating layer 140. The second contact hole may contact the other end of the source / drain region ACT2 of the active layer ACT. In addition, the source electrode SE may directly contact the anode AE through the third contact hole of the first passivation layer 150 and the fourth contact hole of the planarization layer 160.

According to an example, the source electrode SE may include a lower source electrode SE1 and an upper source electrode SE2.

The lower source electrode SE1 may be formed between the interlayer insulating layer 140 and the upper source electrode SE2 to promote adhesion between the interlayer insulating layer 140 and the upper source electrode SE2. In addition, the lower source electrode SE1 may protect the lower surface of the upper source electrode SE2 from preventing corrosion of the lower surface of the upper source electrode SE2.

The upper source electrode SE2 may be formed on an upper surface of the lower source electrode SE1. The upper source electrode SE2 may be made of a metal having a lower resistance than the lower source electrode SE1. The thickness of the upper source electrode SE2 may be formed thicker than the thickness of the lower source electrode SE1 in order to reduce the overall resistance of the source electrode SE.

In example embodiments, the drain electrode DE may include a lower drain electrode DE1 and an upper drain electrode DE2.

The lower drain electrode DE1 may be formed between the interlayer insulating layer 140 and the upper drain electrode DE2 to increase the adhesion between the interlayer insulating layer 140 and the upper drain electrode DE2, and the upper drain electrode DE2. Can prevent corrosion of the lower surface.

The upper drain electrode DE2 may be formed on an upper surface of the lower drain electrode DE1. The upper drain electrode DE2 may be formed thicker than the lower drain electrode DE1 to reduce the overall resistance of the drain electrode DE.

The first passivation layer 150 may be provided on the interlayer insulating layer 140, the source electrode SE, and the drain electrode DE. The first passivation layer 150 may function to protect the source electrode SE and the drain electrode DE. The first passivation layer 150 may include a third contact hole through which the anode AE passes. The third contact hole of the first passivation layer 150 may be connected to the fourth contact hole of the planarization layer 160 to pass through the anode AE.

The planarization layer 160 may be disposed on the substrate 110 and may cover the thin film transistor T disposed in each of the plurality of pixel regions. In detail, the planarization layer 160 may be provided on the thin film transistor T to planarize an upper end of the thin film transistor T. According to an example, the anode AE and the contact pad CP may be provided to be spaced apart from each other at the top of the planarization layer 160. For example, the planarization layer 160 may include a fourth contact hole through which the anode AE passes. Here, the fourth contact hole of the planarization layer 160 may be connected to the third contact hole of the first passivation layer 150 to pass through the anode electrode AE.

The organic light emitting device E may be disposed on the planarization layer 160 of the plurality of pixel regions, and may be electrically connected to the thin film transistor T. The organic light emitting device E may include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE.

The anode AE may be provided on the planarization layer 160 of the plurality of pixel regions, and may be electrically connected to the source electrode SE of the thin film transistor T. The anode AE may contact the source electrode SE of the thin film transistor T through a fourth contact hole provided in the planarization layer 160. The anode electrode AE may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3.

The first anode AE1 may be formed between the third anode AE3 and the second anode AE2. According to an example, the first anode AE1 may be formed of a metal having a lower resistance than the third anode AE3 and the second anode AE2. The first anode AE1 may be formed thicker than each of the third anode AE3 and the second anode AE2 in order to reduce the overall resistance of the anode AE.

The second anode electrode AE2 may be formed on the first anode electrode AE1. In detail, the second anode AE2 may prevent the first anode AE1 from being exposed to the outside. Therefore, the second anode AE2 is formed to cover the top surface of the first anode AE1, thereby preventing the first anode AE1 from corroding. For example, the oxidation degree of the second anode electrode AE2 may be lower than that of the first anode electrode AE1. The second anode AE2 may be made of a material having higher corrosion resistance than the first anode AE1.

The third anode electrode AE3 may be provided on the flat surface of the planarization layer 160. In detail, the oxidation degree of the third anode electrode AE3 may be lower than that of the first anode electrode AE1.

The emission layer EL may be provided on the anode AE and the contact pad CP. The emission layer EL may be formed to be common to all pixels without being classified for each pixel region. For example, the emission layer EL may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. According to an example, the light emitting layer EL may further include at least one or more functional layers for improving the light emitting efficiency and lifespan of the light emitting layer. In addition, the emission layer EL disposed on the contact pad CP may be removed for the cathode contact between the contact pad CP and the cathode electrode CE.

The cathode electrode CE may be provided on the emission layer EL. The cathode electrode CE may be implemented in the form of an electrode that is common to all pixels without being divided into pixel regions. In example embodiments, the cathode electrode CE may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The bank B may be disposed on the planarization layer 160 to partition the plurality of anode electrodes AE and the plurality of contact pads CP. In detail, the bank B may electrically insulate the anode AE from the contact pad CP. The bank B may cover a portion of the top surface of the contact pad CP, and other portions and side surfaces of the top surface of the contact pad CP not covered by the bank B may be exposed to the cathode contact region CCA.

The bank B may cover a portion of the anode AE. Therefore, the bank B may be disposed between the plurality of anode electrodes AE and the contact pads CP to electrically insulate the anode electrodes AE and the contact pads CP adjacent to each other.

The second passivation layer 170 may cover the edge of the pad electrode PE while covering the display area AA. In detail, the second passivation layer 170 may be disposed on the organic light emitting device E of the display area AA and may be disposed in an area of the pad area PA except for the center portion of the pad electrode PE. Here, the center portion of the pad electrode PE may correspond to an area in contact with the flexible circuit film 211 through the anisotropic conductive film ACF.

According to an example, the second passivation layer 170 may be formed on the entire surface of the organic light emitting device E, the pad electrode PE, and the first passivation layer 150 by atomic layer deposition (ALD). Can be coated. Here, the second protective layer 170 may be formed by coating various materials by atomic layer deposition (ALD), and the organic light emitting device E, the pad electrode PE, and the first protective layer 150 may be formed. It can be deposited stably regardless of the material constituting the. For example, after the second protective layer 170 is coated on the entire substrate 110, the region overlapping with the center portion of the pad electrode PE is removed, so that the second protective layer 170 is formed of the pad region PA. The display panel may be disposed on the entire region of the organic light emitting element E of the display area AA and the region except for the center portion of the pad electrode PE.

According to an example, before the encapsulation layer 180 is formed, the second protective layer 170 may surround all of the top, side, and bottom surfaces of the substrate 110. In addition, the second passivation layer 170 overlapping the pad electrode PE may be removed, and the second passivation layer 170 covering the side surface of the substrate 110 may be formed on the pad electrode PE. 211) may be removed before deployment. Here, the second protective layer 170 covering the lower surface of the substrate 110 may remain even after the flexible circuit film 211 is attached, but is not necessarily limited thereto.

The second passivation layer 170 may include a first pad contact hole PCH1 overlapping the remaining portion except the edge of the pad electrode PE. In detail, the first pad contact hole PCH1 may accommodate an anisotropic conductive film ACF that electrically connects the pad electrode PE and the flexible circuit film 211. Therefore, the anisotropic conductive film ACF may be surrounded by the second protective layer 170 covering the edge of the pad electrode PE. In other words, the anisotropic conductive film ACF may be surrounded by the first pad contact hole PCH1 of the second protective layer 170.

The second passivation layer 170 may cover the top edge and the side surface of the pad electrode PE exposed on the first passivation layer 150. In detail, the pad electrode PE may be formed of the same material as the anode electrode AE of the display area AA on the first passivation layer 150. In addition, the pad electrode PE is patterned together in the patterning process of the anode AE, so that the upper edge and the side surface of the pad electrode PE may be exposed. In this case, the second passivation layer 170 may face the anode electrode AE with the emission layer EL and the cathode electrode CE therebetween in the display area AA, and the pad electrode in the pad area PA. It may be in direct contact with the upper edge and side of the PE. In addition, the second encapsulation layer 182 may cover the second protective layer 170 covering the upper edge and the side surface of the pad electrode PE.

The encapsulation layer 180 may cover the second passivation layer 170 on the display area AA. In detail, the encapsulation layer 180 may be provided on the entire upper end of the cathode electrode CE. The encapsulation layer 180 may prevent deterioration of the light emitting layer EL by preventing penetration of moisture, which may be introduced from the outside. According to an example, the encapsulation layer 180 may be formed of a combination of at least one inorganic layer and at least one organic layer.

The encapsulation layer 180 may include first to third encapsulation layers 181, 182, and 183.

The first encapsulation layer 181 may cover the entire surface of the second passivation layer 170 on the display area AA. For example, the first encapsulation layer 181 may be an inorganic film made of silicon dioxide (SiO 2), silicon nitride film (SiNx), silicon oxynitride film (SiON), or multiple layers thereof.

The second encapsulation layer 182 can cover the first encapsulation layer 181 and further cover the second protective layer 170 on the pad area PA. For example, the second encapsulation layer 182 may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamides resin, or a polyimides resin. It may be an organic film consisting of.

The second encapsulation layer 182 may include a second pad contact hole PCH2 overlapping the remaining portion except for the edge of the pad electrode PE. In detail, the second pad contact hole PCH2 may accommodate an anisotropic conductive film ACF that electrically connects the pad electrode PE to the flexible circuit film 211. Here, the second pad contact hole PCH2 may be connected to the first pad contact hole PCH1 of the second protective layer 170 so as to pass through the anisotropic conductive film ACF. Therefore, the anisotropic conductive film ACF may be surrounded by the first and second pad contact holes PCH1 and PCH2.

The third encapsulation layer 183 can cover the second encapsulation layer 182 on the display area AA. For example, the third encapsulation layer 183 may be an inorganic film made of silicon dioxide (SiO 2), silicon nitride film (SiNx), silicon oxynitride film (SiON), or multiple layers thereof.

In example embodiments, the second encapsulation layer 182 on the display area AA and the second encapsulation layer 182 on the pad area PA may be spaced apart from each other. In detail, the second encapsulation layer 182 on the display area AA is disposed on the second passivation layer 170 and the first encapsulation layer 181 and the second encapsulation layer 182 on the pad area PA. May be disposed on the second protective layer 170. Here, the second passivation layer 170 may be exposed in a region where the second encapsulation layer 182 on the display area AA and the second encapsulation layer 182 on the pad area PA are spaced apart from each other. The encapsulation layer 183 may contact the exposed second protective layer 170 to cover the second encapsulation layer 182 on the display area AA. In addition, an end of the third encapsulation layer 183 is in contact with the second passivation layer 170 between the display area AA and the pad area PA, thereby forming the second encapsulation layer 182 on the display area AA. And the second encapsulation layer 182 on the pad area PA may be separated. As described above, the third encapsulation layer 183 covers the second encapsulation layer 182 on the display area AA, thereby preventing moisture or oxygen from penetrating into the organic light emitting element E. FIG.

The flexible circuit film 211 may be attached to the pad electrode PE through an anisotropic conductive film (ACF) including conductive particles. According to an example, the flexible circuit film 211 may be connected to the pad electrode PE through the anisotropic conductive film ACF while covering a part of the second encapsulation layer 182 on the pad area PA. At this time, the upper surface of the anisotropic conductive film (ACF) is covered by the flexible circuit film 211, the side surface of the anisotropic conductive film (ACF) is surrounded by the second protective layer 170 and the second encapsulation layer 182 The bottom surface of the anisotropic conductive film ACF may be in direct contact with the pad electrode PE. Therefore, since the anisotropic conductive film (ACF) is surrounded by the flexible circuit film 211, the second protective layer 170, the second encapsulation layer 182, and the pad electrode PE is not exposed to the outside, the present application The display device may prevent external moisture permeation through the first and second pad contact holes PCH1 and PCH2 provided with the anisotropic conductive film ACF.

The first auxiliary power line EVSS1 may be electrically connected to the line contact pattern LCP, and may be formed of the same material on the same layer as the gate electrode GE. In detail, the first auxiliary power line EVSS1 may be disposed on the gate insulating layer 130. For example, the first auxiliary power line EVSS1 may overlap the second auxiliary power line EVSS2 with the buffer layer 120 and the gate insulating layer 130 interposed therebetween. The first auxiliary power line EVSS1 may include a lower first auxiliary power line EVSSa and an upper first auxiliary power line EVSSb. The first auxiliary power line EVSS1 may provide the contact pad CP with a low potential voltage supplied from the display driving circuit unit 210 through the pad electrode PE disposed at one edge of the substrate 110. .

The lower first auxiliary power line EVSSa is formed between the gate insulating layer 130 and the upper first auxiliary power line EVSSb to promote adhesion between the gate insulating layer 130 and the upper first auxiliary power line EVSSb. Can be. The lower first auxiliary power line EVSSa may prevent the lower surface of the upper first auxiliary power line EVSSb from corroding.

The upper first auxiliary power line EVSSb may be formed on an upper surface of the lower first auxiliary power line EVSSa. In detail, the upper first auxiliary power line EVSSb may be formed of a metal having a lower resistance than the lower first auxiliary power line EVSSa. The upper first auxiliary power line EVSSb may be formed thicker than the lower first auxiliary power line EVSSa to reduce the overall resistance of the first auxiliary power line EVSS1.

The second auxiliary power line EVSS2 is electrically connected to the line contact pattern LCP and may be made of the same material as the light blocking layer LS. In detail, the second auxiliary power line EVSS2 may be disposed on the substrate 110. For example, the second auxiliary power line EVSS2 may overlap the first auxiliary power line EVSS1 with the buffer layer 120 and the gate insulating layer 130 interposed therebetween. The second auxiliary power line EVSS2 may include a lower second auxiliary power line EVSSc and an upper second auxiliary power line EVSSd. The second auxiliary power line EVSS2 may provide the contact pad CP with a low potential voltage supplied from the display driving circuit unit 210 through the pad electrode PE disposed at one edge of the substrate 110. .

As such, the first and second auxiliary power lines EVSS1 and EVSS2 may be electrically connected to the line contact pattern LCP to increase the sum of the thicknesses of the electrodes connected to the contact pad CP. Therefore, the first and second auxiliary power lines EVSS1 and EVSS2 are electrically connected to the line contact pattern LCP, thereby reducing the overall resistance of the electrodes connected to the contact pad CP.

The lower second auxiliary power line EVSSc may be formed between the substrate 110 and the upper second auxiliary power line EVSSd to promote adhesion between the substrate 110 and the upper second auxiliary power line EVSSd. . The lower second auxiliary power line EVSSc may prevent the lower surface of the upper second auxiliary power line EVSSd from corroding.

The upper second auxiliary power line EVSSd may be formed on an upper surface of the lower second auxiliary power line EVSSc. In detail, the upper second auxiliary power line EVSSd may be formed of a metal having a lower resistance than the lower second auxiliary power line EVSSc. The upper second auxiliary power line EVSSd may be formed thicker than the lower second auxiliary power line EVSSc to reduce the overall resistance of the second auxiliary power line EVSS2.

The line contact pattern LCP may be disposed on the planarization layer 160 to be spaced apart from the source electrode SE and the drain electrode DE. The line contact pattern LCP may be electrically connected to the contact pad CP through a contact hole provided in the planarization layer 160. In detail, the line contact pattern LCP contacts the contact pad CP through the contact hole formed in the planarization layer 160, and the first auxiliary power line EVSS1 through the contact hole provided in the interlayer insulating layer 140. The second auxiliary power line EVSS2 may be in contact with each other through a contact hole provided in the interlayer insulating layer 140 and the buffer layer 120. Accordingly, the line contact pattern LCP connected to the contact pad CP may be electrically connected to each of the first and second auxiliary power lines EVSS1 and EVSS2, thereby increasing the sum of thicknesses of the electrodes connected to the contact pad CP. Can be increased. Therefore, the line contact pattern LCP may be electrically connected to each of the first and second auxiliary power lines EVSS1 and EVSS2, thereby reducing the overall resistance of the electrodes connected to the contact pad CP.

The line contact pattern LCP may include a lower line contact pattern LCP1 and an upper line contact pattern LCP2.

The lower line contact pattern LCP1 may be formed between the interlayer insulating layer 140 and the upper line contact pattern LCP2 to promote adhesion between the interlayer insulating layer 140 and the upper line contact pattern LCP2. The lower line contact pattern LCP1 may protect the lower surface of the upper line contact pattern LCP2 to prevent the lower surface of the upper line contact pattern LCP2 from corroding.

The upper line contact pattern LCP2 may be formed on an upper surface of the lower line contact pattern LCP1. The upper line contact pattern LCP2 may be formed of a metal having a lower resistance than the lower line contact pattern LCP1. The thickness of the upper line contact pattern LCP2 may be formed thicker than the thickness of the lower line contact pattern LCP1 in order to reduce the overall resistance of the line contact pattern LCP.

The contact pad CP may be disposed on the planarization layer 160 of the plurality of pixel areas, and may be electrically connected to the line contact pattern LCP. The contact pad CP may be electrically connected to the line contact pattern LCP through the contact hole provided in the planarization layer 160. The contact pad CP may include a first metal film CP1, a second metal film CP2, and a third metal film CP3.

The first metal film CP1 may be disposed between the third metal film CP3 and the second metal film CP2. In example embodiments, the first metal film CP1 may be formed of a metal having a lower resistance than the third metal film CP3 and the second metal film CP2. The first metal film CP1 may be formed thicker than each of the third metal film CP3 and the second metal film CP2 in order to reduce the overall resistance of the contact pad CP.

The second metal film CP2 may be formed on the first metal film CP1. In detail, the second metal film CP2 may prevent the first metal film CP1 from being exposed to the outside. Therefore, the second metal film CP2 may be formed to cover the top surface of the first metal film CP1, thereby preventing the first metal film CP1 from corroding.

The third metal film CP3 may be provided on the flat surface of the planarization layer 160. In detail, the oxidation degree of the third metal film CP3 may be lower than that of the first metal film CP1.

According to an example, the upper surface or the side surface of the contact pad CP is in direct contact with the cathode electrode CE, thereby preventing luminance unevenness due to a voltage drop IR drop of the cathode voltage CE supplied to the cathode electrode CE. It can prevent.

The signal pad SP may be formed on the buffer layer 120. For example, the signal pad SP may be made of the same material in the same layer as the gate electrode GE. The signal pad SP may include a lower signal pad SP1 and an upper signal pad SP2.

The lower signal pad SP1 may be formed between the buffer layer 120 and the upper signal pad SP2 to promote adhesion between the buffer layer 120 and the upper signal pad SP2. In addition, the lower signal pad SP1 may prevent the lower surface of the upper signal pad SP2 from being corroded.

The upper signal pad SP2 may be formed on an upper surface of the lower signal pad SP1. In detail, the upper signal pad SP2 may be formed of a metal having a lower resistance than the lower signal pad SP1. The upper signal pad SP2 may be formed thicker than the lower signal pad SP1 in order to reduce the overall resistance of the signal pad SP.

The pad auxiliary electrode PAE may be provided on the interlayer insulating layer 140. For example, the pad auxiliary electrode PAE may contact the signal pad SP through the contact hole provided in the interlayer insulating layer 140, and the pad electrode PE through the contact hole provided in the first passivation layer 150. ) Can be contacted. The pad auxiliary electrode PAE may include a lower pad auxiliary electrode PAE1 and an upper pad auxiliary electrode PAE2.

The lower pad auxiliary electrode PAE1 may be formed between the interlayer insulating layer 140 and the upper pad auxiliary electrode PAE2 to promote adhesion between the interlayer insulating layer 140 and the upper pad auxiliary electrode PAE2. In addition, the lower pad auxiliary electrode PAE1 may prevent the lower surface of the upper pad auxiliary electrode PAE2 from being corroded by protecting the lower surface of the upper pad auxiliary electrode PAE2.

The upper pad auxiliary electrode PAE2 may be formed on an upper surface of the lower pad auxiliary electrode PAE1. The upper pad auxiliary electrode PAE2 may be formed of a metal having a lower resistance than the lower pad auxiliary electrode PAE1. The thickness of the upper pad auxiliary electrode PAE2 may be thicker than the thickness of the lower pad auxiliary electrode PAE1 in order to reduce the overall resistance of the pad auxiliary electrode PAE.

The pad electrode PE may be formed on the first protective layer 150. For example, the pad electrode PE may contact the pad auxiliary electrode PAE through a contact hole provided in the first passivation layer 150. The pad electrode PE may include a first pad electrode PE1, a second pad electrode PE2, and a third pad electrode PE3.

The first pad electrode PE1 may be disposed between the second pad electrode PE2 and the third pad electrode PE3. In example embodiments, the first pad electrode PE1 may be formed of a metal having a lower resistance than the second pad electrode PE2 and the third pad electrode PE3. The first pad electrode PE1 may be formed thicker than each of the second pad electrode PE2 and the third pad electrode PE3 in order to reduce the overall resistance of the pad electrode PE.

The second pad electrode PE2 may be formed on the first pad electrode PE1. In detail, the second pad electrode PE2 may prevent the first pad electrode PE1 from being exposed to the outside. Accordingly, the second pad electrode PE2 may be formed to cover the top and side surfaces of the first pad electrode PE1, thereby preventing the first pad electrode PE1 from corroding.

The third pad electrode PE3 may be formed to cover the top surface of the upper pad auxiliary electrode PAE2 exposed through the contact hole of the first passivation layer 150, thereby preventing corrosion of the upper pad auxiliary electrode PAE2. . Therefore, since the third pad electrode PE3 can prevent corrosion of the upper pad auxiliary electrode PAE2, the pad auxiliary electrode PAE can be formed in the two-layer structure described above.

The storage capacitor Cst may include a lower capacitor electrode BC, a center capacitor electrode MC, and an upper capacitor electrode TC. In detail, the lower capacitor electrode BC and the center capacitor electrode MC may face each other with the buffer layer 120 interposed therebetween, and the center capacitor electrode MC and the upper capacitor electrode TC may be interlayer insulating layer 140. You can face each other with. Therefore, the storage capacitor Cst forms a capacitance between the lower capacitor electrode BC and the center capacitor electrode MC, and also forms a capacitance between the center capacitor electrode MC and the upper capacitor electrode TC, thereby increasing the overall capacitance. You can.

The lower capacitor electrode BC may include a first lower capacitor electrode BC1 and a second lower capacitor electrode BC2. The lower capacitor electrode BC may be made of the same material as the light blocking layer LS and the second auxiliary power line EVSS2 in the same layer.

The first lower capacitor electrode BC1 may be formed between the substrate 110 and the second lower capacitor electrode BC2 to promote adhesion between the substrate 110 and the second lower capacitor electrode BC2. In addition, the first lower capacitor electrode BC1 may prevent the lower surface of the second lower capacitor electrode BC2 from corroding.

The second lower capacitor electrode BC2 may be formed on an upper surface of the first lower capacitor electrode BC1. In detail, the second lower capacitor electrode BC2 may be formed of a metal having a lower resistance than the first lower capacitor electrode BC1. The second lower capacitor electrode BC2 may be formed thicker than the first lower capacitor electrode BC1 in order to reduce the overall resistance of the lower capacitor electrode BC.

The center capacitor electrode MC may include a first center capacitor electrode MC1 and a second center capacitor electrode MC2. Here, the central capacitor electrode MC may be made of the same material in the same layer as each of the gate electrode GE and the first auxiliary power line EVSS1.

The first center capacitor electrode MC1 may be formed between the buffer layer 120 and the second center capacitor electrode MC2 to promote adhesion between the buffer layer 120 and the second center capacitor electrode MC2. In addition, the first center capacitor electrode MC1 may prevent the lower surface of the second center capacitor electrode MC2 from corroding.

The second center capacitor electrode MC2 may be formed on an upper surface of the first center capacitor electrode MC1. In detail, the second center capacitor electrode MC2 may be formed of a metal having a lower resistance than the first center capacitor electrode MC1. The second center capacitor electrode MC2 may be formed thicker than the first center capacitor electrode MC1 in order to reduce the overall resistance of the second capacitor electrode.

The upper capacitor electrode TC may include a first upper capacitor electrode TC1 and a second upper capacitor electrode TC2. The upper capacitor electrode TC may be made of the same material as the source electrode SE, the drain electrode DE, and the line contact pattern LCP in the same layer.

The first upper capacitor electrode TC1 may be formed between the interlayer insulating layer 140 and the second upper capacitor electrode TC2 to promote adhesion between the interlayer insulating layer 140 and the second upper capacitor electrode TC2. The first upper capacitor electrode TC1 may prevent the lower surface of the second upper capacitor electrode TC2 from being corroded by protecting the lower surface of the second upper capacitor electrode TC2.

The second upper capacitor electrode TC2 may be formed on an upper surface of the first upper capacitor electrode TC1. The second upper capacitor electrode TC2 may be made of a metal having a lower resistance than the first upper capacitor electrode TC1. The thickness of the second upper capacitor electrode TC2 may be formed thicker than the thickness of the first upper capacitor electrode TC1 in order to reduce the overall resistance of the upper capacitor electrode TC.

4 is a cross-sectional view illustrating a method of manufacturing a display device according to an example of the present application, which is a cross-sectional view taken along line II ′ of FIG. 2.

In FIG. 4A, the second protective layer 170 is coated on the entire surface of the organic light emitting device E, the pad electrode PE, and the first protective layer 150 by atomic layer deposition (ALD). Can be. Here, the second protective layer 170 may be formed by coating various materials by atomic layer deposition (ALD), and the organic light emitting device E, the pad electrode PE, and the first protective layer 150 may be formed. It can be deposited stably regardless of the material constituting the. For example, after the second protective layer 170 is coated on the entire substrate 110, the region overlapping with the center portion of the pad electrode PE is removed, whereby the second protective layer 170 is formed of the pad region PA. The display panel may be disposed on the entire region of the organic light emitting element E of the display area AA and the region except for the center portion of the pad electrode PE.

According to an example, the second protective layer 170 may be formed by coating a metal oxide film, a metal nitride film, or a silicon oxide film on the entire substrate 110 through atomic layer deposition (ALD). In this case, the second protective layer 170 may be formed not only on the upper surface of the substrate 110 but also on the side surface and the lower surface of the substrate 110 by atomic layer deposition (ALD). The second passivation layer 170 may be formed through atomic layer deposition (ALD), thereby improving thickness uniformity and physical properties of the thin film and lowering the process temperature. Therefore, before the encapsulation layer 180 is formed, the second passivation layer 170 may surround all of the top, side, and bottom surfaces of the substrate 110.

In FIG. 4B, the encapsulation layer 180 may include first to third encapsulation layers 181, 182, and 183.

The first encapsulation layer 181 may cover the entire surface of the second passivation layer 170 on the display area AA.

The second encapsulation layer 182 can cover the first encapsulation layer 181 and further cover the second protective layer 170 on the pad area PA. The second encapsulation layer 182 may include a second pad contact hole PCH2 overlapping the remaining portion except for the edge of the pad electrode PE. In detail, the second pad contact hole PCH2 may accommodate an anisotropic conductive film ACF that electrically connects the pad electrode PE to the flexible circuit film 211. The second protective layer 170 overlapping the center portion of the pad electrode PE may be patterned by a wet etching process using the second encapsulation layer 182 as a mask.

The third encapsulation layer 183 can cover the second encapsulation layer 182 on the display area AA.

In example embodiments, the second encapsulation layer 182 on the display area AA and the second encapsulation layer 182 on the pad area PA may be spaced apart from each other. In detail, the second encapsulation layer 182 on the display area AA is disposed on the second passivation layer 170 and the first encapsulation layer 181 and the second encapsulation layer 182 on the pad area PA. May be disposed on the second protective layer 170. Here, the second passivation layer 170 may be exposed in a region where the second encapsulation layer 182 on the display area AA and the second encapsulation layer 182 on the pad area PA are spaced apart from each other. The encapsulation layer 183 may contact the exposed second protective layer 170 to cover the second encapsulation layer 182 on the display area AA. In addition, an end of the third encapsulation layer 183 is in contact with the second passivation layer 170 between the display area AA and the pad area PA, thereby forming the second encapsulation layer 182 on the display area AA. And the second encapsulation layer 182 on the pad area PA may be separated. As described above, the third encapsulation layer 183 covers the second encapsulation layer 182 on the display area AA, thereby preventing moisture or oxygen from penetrating into the organic light emitting element E. FIG.

In FIG. 4C, the second protective layer 170 may be patterned by a wet etching process using the second encapsulation layer 182 as a mask. Specifically, after the second protective layer 170 is coated on the entire substrate 110, by a wet etching process using the second encapsulation layer 182 patterned on the second protective layer 170 as a mask, The first pad contact hole PCH1 of the second protection layer 170 may be formed. For example, the wet etching process may be performed using an alkali compound using sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH 4 OH), or a combination thereof as an etching solution. In addition, since the wet etching process is performed after the encapsulation layer 180 is provided, the reliability of the display device can be improved. Therefore, the region of the second passivation layer 170 that overlaps with the center portion of the pad electrode PE is removed to remove the region of the pad region PA except for the center portion of the pad electrode PE and the organic layer of the display region AA. It may be disposed on the entire surface of the light emitting device (E).

If the second protective layer 170 is patterned through a dry etching process, a separate patterning process for dry etching may be required and plasma damage may occur. In addition, when the second passivation layer 170 is patterned through a dry etching process, a separate etching passivation layer is required to prevent plasma damage, and the panel has a problem of deteriorating reliability.

Accordingly, the display device according to the present application performs the patterning process of the second protective layer 170 using the second encapsulation layer 182 as a mask, thereby eliminating the need for an additional mask process for patterning, and thus the second protection. Layer 170 may be selectively patterned. In addition, since the display device according to the present application uses a wet etching process, since plasma damage is not generated in advance, a separate etching protection layer is not required, and thus the process cost can be reduced.

In addition, the second protective layer 170 covering the side surface of the substrate 110 may be cut before the flexible circuit film 211 is disposed on the pad electrode PE. According to an example, the thickness uniformity of the second protective layer 170 covering the upper surface of the substrate 110 may be different from the thickness uniformity of the second protective layer 170 covering the side surface of the substrate 110. Accordingly, the display device may remove the second passivation layer 170 covering the side surface of the substrate 110, thereby reducing the thickness uniformity of the second passivation layer 170 covering the display area AA and the pad area PA. Physical properties can be improved. Here, the second protective layer 170 covering the lower surface of the substrate 110 may remain even after the flexible circuit film 211 is attached, but is not necessarily limited thereto. As a result, the display device 100 according to the present application includes a process of forming the second passivation layer 170 through atomic layer deposition (ALD), and is made of the same material as that of the second passivation layer 170. It may further include a coating film 170 disposed on the lower surface of the (110).

In FIG. 4D, the flexible circuit film 211 may be attached to the pad electrode PE via an anisotropic conductive film ACF including conductive particles. According to an example, the flexible circuit film 211 may be connected to the pad electrode PE through the anisotropic conductive film ACF while covering a part of the second encapsulation layer 182 on the pad area PA. At this time, the upper surface of the anisotropic conductive film (ACF) is covered by the flexible circuit film 211, the side surface of the anisotropic conductive film (ACF) is surrounded by the second protective layer 170 and the second encapsulation layer 182 The bottom surface of the anisotropic conductive film ACF may be in direct contact with the pad electrode PE. Therefore, since the anisotropic conductive film (ACF) is surrounded by the flexible circuit film 211, the second protective layer 170, the second encapsulation layer 182, and the pad electrode PE is not exposed to the outside, the present application The display device may prevent external moisture permeation through the first and second pad contact holes PCH1 and PCH2 provided with the anisotropic conductive film ACF.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical details of the present application. It will be apparent to those who have the knowledge of. Therefore, the scope of the present application is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts thereof are included in the scope of the present application.

100: display device
110: substrate 120: buffer layer
T: transistor LS: light shielding layer
130: gate insulating film 140: interlayer insulating film
150: first protective layer 160: planarization layer
170: second protective layer 180: encapsulation layer
181, 182, and 183: first to third encapsulation layers E: organic light emitting element
AE: anode electrode EL: light emitting layer
CE: cathode electrode CP: contact pad
EVSS1, EVSS2: first and second auxiliary power lines
LCP: Line Contact Pattern Cst: Storage Capacitor
SP: Signal Pad PAE: Pad Auxiliary Electrode
PE: pad electrode B: bank
210: display driver circuit portion 211: flexible circuit film
220: scan driving circuit portion

Claims (11)

A substrate including a display area having a plurality of pixels and a pad area having at least one pad electrode;
A protective layer covering an edge of the pad electrode while covering the display area; And
A first encapsulation layer covering the protective layer on the display area, a second encapsulation layer further covering the protective layer on the pad area while covering the first encapsulation layer, and a third encapsulation layer on the second encapsulation layer on the display area A display device comprising an encapsulation layer having an encapsulation layer. The method of claim 1,
The pad electrode is made of the same material as the anode electrode of each of the plurality of pixels,
And the passivation layer facing the anode electrode with the light emitting layer and the cathode electrode of each of the plurality of pixels in the display area interposed therebetween, and directly contacting an upper edge and a side surface of the pad electrode in the pad area. The method of claim 1,
And a flexible circuit film attached to the pad electrode via an anisotropic conductive film containing conductive particles. The method of claim 3, wherein
The side surface of the anisotropic conductive film is surrounded by the protective layer covering the edge of the pad electrode and the second encapsulation layer covering the protective layer. The method of claim 3, wherein
The protective layer includes a first pad contact hole overlapping the remaining portion except the edge of the pad electrode, and the anisotropic conductive film is surrounded by the first pad contact hole. The method of claim 3, wherein
The second encapsulation layer includes a second pad contact hole overlapping the remaining portion except for the edge of the pad electrode, and the anisotropic conductive film is surrounded by the second pad contact hole. The method of claim 3, wherein
And the flexible circuit film covers a portion of the second encapsulation layer on the pad region. The method of claim 1,
The second encapsulation layer on the display area and the second encapsulation layer on the pad area are spaced apart from each other, and the third encapsulation layer covers a side surface of the second encapsulation layer on the display area. The method of claim 1,
An end of the third encapsulation layer is in contact with the protective layer between the display area and the pad area to separate the second encapsulation layer on the display area from the second encapsulation layer on the pad area. The method of claim 1,
And a coating film made of the same material as the passivation layer and disposed on a bottom surface of the substrate. The method of claim 1,
The first and third encapsulation layers are inorganic films made of silicon dioxide (SiO 2), silicon nitride film (SiNx), silicon oxynitride film (SiON), or multiple layers thereof, and the second encapsulation layer is an acrylic resin. The display device which is an organic film which consists of an epoxy resin, a phenolic resin, a polyamides resin, or a polyimides resin.

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