KR20190132901A - Logic memory circuit using magnetic resistance and method of performing logic operation using the same - Google Patents

Abstract

Disclosed is a logic memory circuit using a magnetic tunnel junction (MTJ). The logic memory circuit comprises a sense circuit, at least one input memory coupled to the sense circuit, a reference circuit unit coupled to the sense circuit, and at least one logic circuit unit. At least one of the input memory, the reference circuit unit, and the logic circuit unit may include the MTJ. Here, the logic memory circuit may perform both a read operation and a logic calculation operation. The input memory and the reference circuit unit are activated during the read operation, and the input memory and the logic circuit unit are activated during the logic operation.

Description

Logic memory circuit using magnetoresistance and method of performing logical operation using same {LOGIC MEMORY CIRCUIT USING MAGNETIC RESISTANCE AND METHOD OF PERFORMING LOGIC OPERATION USING THE SAME}

The present invention relates to a logic memory circuit using magnetoresistance and a method of performing logic operation using the same.

Conventionally, a system is designed using a logic circuit and a memory module to make a CMOS-based VLSI processor. Generally, DRAM and SRAM are used as memories. In this case, all the operations require a back-up and boost-up process in the memory, which limits the large power consumption and operation speed.

VLSI circuits based on existing CMOS processes have been scaled down as the process evolved to realize high speed and high density circuits. However, the recent scale-down has resulted in a severe power consumption due to leakage current, and requires a new type of circuit.

In addition, although a technology that requires low-power and high-speed calculation such as IoT has recently emerged, in a conventional CMOS-based VLSI system, memory and logic circuits are separated so that the communication speed between the memory and the logic circuit is a bottleneck. Caused the phenomenon.

KR 10-2018-0053314 A

The present invention provides a logic memory circuit using MTJ and a method of performing logic operation using the same.

In order to achieve the above object, a logic memory circuit according to an embodiment of the present invention comprises a sensing circuit; At least one input memory coupled to the sense circuit; A reference circuit portion connected to the sensing circuit; And at least one logic circuit portion, wherein at least one of the input memory, the reference circuit portion, and the logic circuit portion includes a magnetic tunnel junction (MTJ). Here, the logic memory circuit may perform both a read operation and a logic operation operation, the input memory and the reference circuit portion are activated during the read operation, and the input memory and the logic circuit portion are activated during the logic operation. .

According to another embodiment of the present invention, a logic memory circuit may include a sensing circuit; At least one input memory coupled to the sensing circuit and storing input data; And a first logic circuit portion. Here, the input memory and the first logic circuit portion has a magnetic tunnel junction (MTJ), the resistance of the input memory and the resistance of the first logic circuit portion in the logic operation is compared and output through the sensing circuit do.

A sensing circuit according to an embodiment of the present invention, at least one input memory coupled to the sensing circuit and comprising a first MTJ, a reference circuit comprising a second MTJ, a first logic circuit comprising a third MTJ and a first A method of performing a logic operation in a logic memory circuit having a second logic circuit portion comprising 4 MTJs comprises: flowing a current through the input memory; Flowing a current through the reference circuit portion and the first logic circuit portion; And the sensing circuit comparing the sum of the resistance of the input memory and the resistance of the reference circuit and the first logic circuit portion as the currents flow, and outputting a comparison result as a result of the first logic operation.

Logic in a logic memory circuit having a sensing circuit according to another embodiment of the present invention, a plurality of input memories connected to the sensing circuit and comprising a first MTJ, a reference circuit portion comprising a second MTJ, a cache circuit and an output circuit The method of performing an operation includes flowing a current through a first input memory; Flowing a current through the reference circuit portion; Comparing the resistance of the first input memory with the resistance of the reference circuit unit and outputting the resistance through the sensing circuit; Storing the output of the output sense circuit in the cache circuit; Flowing a current through the second input memory; Flowing a current through the reference circuit portion; Comparing the resistance of the second input memory with the resistance of the reference circuit unit and outputting the resistance through the sensing circuit; And performing a logic operation using data output by comparing the data stored in the cache circuit with the resistance of the second input memory and the resistance of the reference circuit unit.

The logic memory circuit and the logic operation performing method using the same according to the present invention implement a memory and a logic circuit as one circuit and use the MTJ for logic operation, and as a result, low power and high speed operation can be realized. In particular, the logic memory circuit can perform all logic operations.

1 is a diagram illustrating a logic memory circuit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an AND operation and an OR operation using the logic circuit of FIG. 1.
3 is a diagram illustrating a word line read process using the logic memory circuit of FIG. 1.
4 is a diagram illustrating a process of recording an output using the logic memory circuit of FIG. 1.
FIG. 5 is a diagram illustrating an XOR operation using the logic memory circuit of FIG. 1.
FIG. 6 is a diagram illustrating a full adder operation using the logic memory circuit of FIG. 1.
7 is a diagram showing a layout of a logic memory circuit according to an embodiment of the present invention.
8 is a diagram illustrating an operation sequence for each operation.
9 is a diagram showing a simulation result of a logic memory circuit.

As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly indicates otherwise. In this specification, terms such as “consisting of” or “comprising” should not be construed as necessarily including all of the various components or steps described in the specification, and some of the components or some steps It should be construed that it may not be included or may further include additional components or steps. In addition, the terms "... unit", "module", etc. described in the specification mean a unit for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software. .

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic memory circuit and a method of performing logic operations using the same, and uses a magnetic tunnel junction (MTJ). In particular, the logic memory circuit implements a logic circuit and a memory as one circuit, but the memory may also be implemented as an MTJ.

In the related art, since the logic circuit and the memory are separately implemented, bottlenecks occur due to the communication speed between the logic circuit and the memory. On the other hand, since the logic memory circuit of the present invention implements the logic circuit and the memory as one circuit, this bottleneck may not occur.

In addition, unlike the prior art in which the circuit structure is different for each logic circuit to be implemented, the logic memory circuit of the present invention can implement all logic, for example, an AND operation, an OR operation, an XOR operation, and a full adder operation, in one circuit. have.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a logic memory circuit according to an embodiment of the present invention, FIG. 2 is a diagram illustrating an AND operation and an OR operation using the logic circuit of FIG. 1, and FIG. 3 is a logic memory circuit of FIG. 1. A diagram illustrating a word line read process using FIG. 4 is a diagram illustrating a process of writing an output using the logic memory circuit of FIG. 1, FIG. 5 is a diagram illustrating an XOR operation using the logic memory circuit of FIG. 1, and FIG. 6 is a logic memory circuit of FIG. 1. A diagram illustrating a full adder operation using. 7 is a diagram showing a layout of a logic memory circuit according to an embodiment of the present invention, FIG. 8 is a diagram showing an operation sequence for each operation, and FIG. 9 is a diagram showing a simulation result of the logic memory circuit. to be.

Referring to Fig. 1, the logic memory circuit of this embodiment includes a sensing circuit 100, input memories 102 and 104, an output memory 106, a reference circuit section 108, a first logic circuit section 109, and a second. The logic circuit unit 110 and the driver 120 may be included.

The sensing circuit 100 senses and outputs the read data or logical operation data. Here, the outputs DOUT and DOUTB (DOUT bars) are the sensing results, that is, the read data or logical operation data.

The sensing circuit 100 is not limited to the structure of FIG. 1, and may be variously modified as long as data is sensed.

The input memories 102 and 104 can store input data. For example, when performing a particular logical operation, the input memories 102 and 104 store data input for the logical operation. Although two input memories are illustrated in FIG. 1, the number of input memories may vary as necessary.

According to an embodiment, each of the input memories 102 and 104 may store one bit of input data, and may be implemented as one cell as shown in FIG. 1. Here, one cell may include one MTJ 130 and two MOS transistors M1 and M2. Since the structure of this cell is applied to all the input memories 102 and 104 and the output memory 106, the structure of the cell of the input memory 102 will be described as a representative.

The first MOS transistor M1 may be an N-MOS transistor, a drain may be connected to the data line DL, and a gate may be connected to the word line. Here, the data line DL may be connected to the source of the first sense transistor of the sense circuit 100.

The second MOS transistor M2 may be an N-MOS transistor, a drain is connected to the source of the first MOS transistor M1, a gate is connected to the scan line SL, and the source is connected to the column line CL. Can be connected. Here, the column line CL may not be used for a read operation but may be used only for a logical operation.

One end of the MTJ 130 may be connected to the bit line BL, and the other end may be connected between the transistors M1 and M2.

The output memory 106 can store the data DOUT output from the sensing circuit 100. Of course, since the output memory 106 has the same structure as the input memory 102 or 104, it can also be used as the input memory. In addition, although only one output memory is illustrated in FIG. 1, a plurality of output memories may be implemented.

The read transistor M _RD1 is a transistor used for a read operation and may be an N-MOS transistor.

The read transistor (M _RD1) the read signal (RD) to be input, the operation of the read transistor (M _RD1) is determined in accordance with the read signal (RD). Specifically, during the read operation, the read signal RD for activating the read transistor M _RD1 is input.

The logic transistor M _L1 is a transistor used for a logic operation, and may be an N-MOS transistor.

Logic transistor and the logic signals (LOGIC) input to the (M _L1), the operation of the logic transistor (M _L1) is determined in accordance with the logic signals (LOGIC). Specifically, during a logic operation, a logic signal LOGIC for activating the logic transistor M _L1 is input. Here, when the logic transistor M _L1 is activated, the read transistor M _RD1 may be deactivated.

The driver 120 includes a first inverter IN1 to which data DOUTB output from the sensing circuit 100 is input, a second inverter IN2 to which data DOUT output from the sensing circuit 100 is input, and a first inverter. One CMOS transistor pair C1 and C2 and a second CMOS transistor pair C3 and C4 may be included.

The NOTB signal is input to some of the gates of the first CMOS transistor pairs C1 and C2 and the NOT signal is input to the remaining gates, and the output by the first CMOS transistor pairs C1 and C2 is connected to the bit line BL. Activation can be determined.

NOT and NOTB signals are generated by the inverter 152 to which the output of the XOR gate 150 and the XOR gate 150 are input.

The NOT_OP signal and the PRE_DOUT signal, which is previously read data, are input to the inputs of the NOR gate 150. The NOR gate 150 may output a NOTB signal.

The output of the NOR gate 150 is input to the inverter 152, and the inverter 152 outputs a NOT signal.

The NOTB signal is input to some of the gates of the second CMOS transistor pairs C3 and C4 and the NOT signal is input to the remaining gates, and the output of the second CMOS transistor pairs C3 and C4 is connected to the column line CL. Activation can be determined.

However, since the data DOUTB AND DOUT input to the first inverter IN1 and the second inverter IN2 have a 180 degree phase difference, the bit line BL and the column line CL operate complementarily. Done.

That is, when the bit line BL is activated, the column line CL is deactivated, and as a result, a read operation is performed. When the column line CL is activated, the bit line BL is deactivated, and as a result, a logic operation is performed.

The circuit structure of the driver 120 may be variously modified as long as the bit line BL and the column line CL are complementarily operated.

Of course, this operation may be equally applied to the reference column line RCL and the reference bit line RBL.

The reference circuitry 108 provides a reference resistor used for data read, for example, one reference transistor MR, a first MTJ 140 in a P state, a second MTJ 142 in a P state and an AP state. The third MTJ 144 may be included.

The reference transistor MR may be an N-MOS transistor, the drain may be connected to the lead line RL connected to the second sense transistor of the sense circuit 100, and the source may be connected to one end of the first MTJ 140. Can be connected. In addition, a logic signal LOGIC or a read signal RD may be input to the gate of the reference transistor MR.

The other end of the first MTJ 140 may be connected to one end of the second MTJ 142 and one end of the third MTJ 144.

The other end of the second MTJ 142 may be connected to the other end of the third MTJ 144 and may be connected to the reference bit line RBL.

The other end of the third MTJ 144 may also be connected to the reference bit line RBL.

The first logic circuit unit 109 is a circuit used for a logic operation, and may be used for an AND operation or the like.

According to an embodiment, the first logic circuit 109 may include the MTJ 146 and two transistors M3 and M4.

One end of the MTJ 146 may be connected to the reference bit line RBL, and the other end may be connected between the source of the transistor M3 and the drain of the transistor M4, and may have a P state.

The source of the transistor M4 is connected to the reference column line RCL, and a first logic signal can be input to the gate. For example, the first logic signal may be an AND signal SL _AND .

The second logic circuit unit 110 may include an MTJ 148 and two transistors M5 and M6.

One end of the MTJ 148 is connected to the reference bit line RBL, and the other end is connected between the source of the transistor M5 and the drain of the transistor M6 and may have an AP state.

The source of the transistor M6 is connected to the reference column line RCL, and a second logic signal can be input to the gate. For example, the second logic signal may be an OR signal SL _OR .

The read transistor M _RD2 is a transistor used for a read operation and may be an N-MOS transistor.

The read transistor (M _RD2) the read signal (RD) to be input, the operation of the read transistor (M _RD2) is determined in accordance with the read signal (RD). Specifically, in the read operation, the read signal RD for activating the read transistor M _RD2 is input.

The logic transistor M _L2 is a transistor used for a logic operation, and may be an N-MOS transistor.

Logic transistor and the logic signals (LOGIC) input to the (M _L2), the operation of the logic transistor _(L2 M) is determined in accordance with the logic signals (LOGIC). Specifically, during a logic operation, a logic signal LOGIC for activating the logic transistor M _L2 is input. Here, when the logic transistor M _L2 is activated, the read transistor M _RD2 may be deactivated.

Hereinafter, a read operation and a logic operation using the logic memory circuit will be described with reference to the accompanying drawings. The red line shows the current flow.

AND operation

Referring to the AND operation with reference to FIG. 2, the logic signal LOGIC is input to activate the logic transistor M _L1 and the logic transistor M _L2 . At this time, the read transistors M _RD1 and M _RD2 are inactivated. In addition, the transistor M4 of the first logic circuit unit 109 is activated by the first logic signal, and the transistor M6 of the second logic circuit unit 110 is inactivated by the second logic signal.

As a result, a first current flows through the first input memory 102, the second input memory 104, and the column line CL, and the second current flows through the reference circuit portion 108, the first logic circuit portion 109, and the like. It flows through the reference column line RCL. Thus, the resistance of the data stored in the input memories 102 and 104 and the sum of the resistances of the reference circuit section 108 and the first logic circuit section 109 are compared, and the comparison result (output of the sensing circuit, DOUT and DOUTB) is compared. It is output through the sensing circuit 100.

The output of this sensing circuit 100 is shown in Table 1 below. For example, if the data stored in the input memories 102 and 104 are '0' and '0', respectively, DOUT may be '0'.

OR operation

Referring to the OR operation with reference to FIG. 2, the logic signal LOGIC is input to activate the logic transistor M _L1 and the logic transistor M _L2 . At this time, the read transistors M _RD1 and M _RD2 are inactivated. In addition, the transistor M4 of the first logic circuit portion 109 is deactivated by the first logic signal, and the transistor M6 of the second logic circuit portion 110 is activated by the second logic signal.

As a result, a first current flows through the first input memory 102, the second input memory 104, and the column line CL, and the second current flows through the reference circuit portion 108, the second logic circuit portion 110, and the like. It flows through the reference column line RCL. Thus, the resistance of the data stored in the input memories 102 and 104 and the sum of the resistances of the reference circuit portion 108 and the second logic circuit portion 110 are compared, and the comparison result (output of the sensing circuit, DOUT and DOUTB) is compared. It is output through the sensing circuit 100.

The output of this sensing circuit 100 is shown in Table 1 above. For example, if the data stored in the input memories 102 and 104 are '1' and '0', respectively, DOUT may be '1'.

Lead behavior

Referring to FIG. 3, a read operation of data of the first input memory 102 is performed. For example, when the read signal RD is input to the read transistor M _RD1 and the read transistor M _RD2 , the read operation is performed. When activated, the first word line signal WL ₁ is input to activate the transistor M1. At this time, the transistors M _ML1 and M _ML2 are deactivated. In addition, the transistors M4 and M5 of the logic circuit portions 109 and 110 are inactivated by the logic signals.

As a result, the first current flows through the first input memory 102 and the bit line BL, and the second current flows through the reference circuit portion 108 and the reference bit line RBL. Therefore, the resistance of the data stored in the input memory 102 and the resistance of the reference circuit section 108 are compared, and the comparison result (output of the sensing circuit, DOUT and DOUTB) is output through the sensing circuit 100.

Of course, when reading data from another input memory, a word line signal is input to the input memory to be activated, and the other input memories are deactivated.

Output write operation

Referring to the output write operation with reference to FIG. 4, the transistor M _O2 of the output memory 106 is activated to allow current to flow through the MTJ 132. As a result, the output DOUT or DOUTB of the sense circuit 100 can be written to the MTJ 132.

XOR operation

Referring to FIG. 5, an XOR operation may be implemented by a single IN1 read operation, a single IN2 read operation, and an output operation.

First, a single IN1 read operation is performed. Specifically, the read signal RD is input to activate the read transistor M _RD1 and the read transistor M _RD2 , and the first word line signal WL ₁ is input to activate the transistor M1. At this time, the transistors M _ML1 and M _ML2 are deactivated. In addition, the transistors M4 and M5 of the logic circuit portions 109 and 110 are inactivated by the logic signals.

As a result, the first current flows through the first input memory 102 and the bit line BL, and the second current flows through the reference circuit portion 108 and the reference bit line RBL.

In this case, the output of the sensing circuit 100 may be stored in the latch 518 of the cache circuit 500. In FIG. 5, the inverters for the cache circuit 500 to cut the outputs of the NAND gates 510 and 514 and the NAND gates 510 and 514 to which the outputs DOUT and DOUTB of the sense circuit 100 are respectively input. 512 and 516, the outputs of the inverters 512 and 516 may be implemented with two transistors M10 and M11 and a latch 518. Here, CACHE_WR input to the type force stage of the NAND gates 510 and 514 serves to activate a cache operation.

Meanwhile, as long as the cache circuit 500 may temporarily store the output of the sensing circuit 100, the sensing circuit 100 may be variously modified.

Subsequently, a single IN2 read operation is performed. Specifically, the read signal RD is input to activate the read transistor M _RD1 and the read transistor M _RD2 , and the k-th word line signal WL _k is input to activate the transistor. At this time, the logic transistors M _ML1 and M _ML2 are deactivated. In addition, the transistors M4 and M5 of the logic circuit portions 109 and 110 are inactivated by the logic signals.

As a result, the first current flows through the second input memory 104 and the bit line BL, and the second current flows through the reference circuit portion 108 and the reference bit line RBL.

Subsequently, an output operation is performed. Specifically, an XOR operation is performed using data PRE_DOUT stored in the latch 518 of the cache circuit 500 and the outputs DOUT [2] and DOUTB [2] of the sensing circuit 100 in the Single IN2 read operation. This can be done.

According to one embodiment, the output circuit 502 has two inverters for inverting the output of the two NAND gates 520 and 524, the NAND gates 520 and 524, into which the NOT_OP signal or PRE_DOUT is input. Inverters 522 and 526, outputs of the inverters 522 and 526 are input to the input terminals, an NOR gate 528, an inverter 530 that inverts the output of the NOR gate 528, and outputs a NOT signal. And an inverter 534 that outputs NOW_DOUT and NOW_DOUTB by inverting the output of the XOR gate 532 and the XOR gate 532 that perform an XOR operation on the NOT signal output from 530 and DOUT [2]. Here, NOW_DOUT is the final output of the output circuit 502, that is, the result of performing the XOR operation on the input data.

On the other hand, as long as the XOR operation is performed using the data PRE_DOUT stored in the latch 518 and the outputs DOUT [2] and DOUTB [2] of the sensing circuit 100 in the Single IN2 read operation, the output circuit ( 502 may be variously modified.

Full adder operation

Looking at the full adder operation with reference to FIG. 6, the full adder process is additionally performed after the XOR operation. Since the XOR operation and the circuit are the same as those in FIG.

For the output operation, the full adder circuit 604 is an inverter 642 for inverting the output of the XOR gate 640, the XOR gate 640, the output of the XOR 632 is input to the input terminal, and outputs a SUM signal, It may include two CMOS transistors 644 and 646 that output the output C _OUT according to NOW_DOUT and NOW_DOUTB input to the gates. Here, output C _OUT is the final output of the full adder operation.

However, the full adder operation is performed using the data PRE_DOUT stored in the latch 618 of the cache circuit 600 and the outputs DOUT [2] and DOUTB [2] of the sensing circuit 100 in the single IN2 read operation. As long as it is performed, the full adder circuit 604 may be modified in various ways.

Finally, the XOR operation and the full adder operation are shown in Table 2 below.

The operation sequence of the above logical operations is shown in FIG. 8, the simulation result is shown in FIG. 9, and the layout is shown in FIG. 7.

In summary, the logic memory circuit of the present invention can perform all logic operations including a sensing circuit, an input memory, an output memory, a reference circuit section, at least one logic circuit section and a driver. In particular, the input memory, the output memory, the reference circuit portion and the logic circuit portion may all use MTJ.

On the other hand, the components of the above-described embodiment can be easily identified from a process point of view. That is, each component can be identified as a respective process. In addition, the process of the above-described embodiment can be easily understood in terms of the components of the apparatus.

In addition, the technical contents described above may be embodied in the form of program instructions that may be executed by various computer means and may be recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

The embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art having ordinary knowledge of the present invention may make various modifications, changes, and additions within the spirit and scope of the present invention. Should be considered to be within the scope of the following claims.

100: detection circuit 102: first input memory
104: second input memory 106: output memory
108: reference circuit portion 109: first logic circuit portion
110: second logic circuit portion 120: driver

Claims (16)

In a logic memory circuit,
Sensing circuit;
At least one input memory coupled to the sense circuit;
A reference circuit portion connected to the sensing circuit; And
At least one logic circuit portion,
At least one of the input memory, the reference circuit portion and the logic circuit portion includes a magnetic tunnel junction (MTJ),
The logic memory circuit may perform both a read operation and a logic operation, wherein the input memory and the reference circuit portion are activated during the read operation, and the input memory and the logic circuit portion are activated during the logic operation. Logic memory circuit. The method of claim 1, wherein the input memory, the reference circuit portion and the logic circuit portion each comprises an MTJ,
The sensing circuit outputs a comparison result by comparing the resistance of the input memory with the resistance of the reference circuit unit during the read operation, and compares the resistance of the input memory with the resistance of the logic circuit unit during the logic operation. Outputting a logic memory circuit. The method of claim 1,
Further comprising an output memory for storing the output of the sensing circuit,
And the output memory comprises an MTJ. The method of claim 3, wherein the input memory and the output memory has the same structure,
The input memory,
A first transistor;
A second transistor; And
Includes the MTJ,
A drain of the first transistor is connected to the sensing circuit through a data line DL, a source of the first transistor and a drain of the second transistor are connected, and a source of the second transistor is a column for a logic operation. A line connected to a line (CL), one end of the MTJ is connected between the transistors, and the other end of the MTJ is connected to a bit line (BL) for a read operation. 5. The logic circuit of claim 4, wherein a read transistor for activating the bit line BL is connected to the bit line BL, and a logic transistor for activating the column line CL is connected to the column line CL. But
And the read transistor and the logic transistor are complementary to each other. The method of claim 1, wherein the reference circuit unit,
Reference transistor;
Two first reference MTJs and a second reference MTJ having a P state; And
A third reference MTJ having an AP status,
A drain of the reference transistor is connected to the sensing circuit, a source of the reference transistor is connected to one end of a first reference MTJ, and the other end of the first MTJ is connected to one ends of the second MTJ and the third MTJ. The other ends of the second MTJ and the third MTJ are connected to a reference bit line RBL for a read operation, and a read transistor for activating the reference bit line RBL is provided in the reference bit line RBL. A logic memory circuit characterized in that it is connected. The method of claim 1, wherein the logic circuit portion comprises a first logic circuit portion and a second logic circuit portion,
The first logic circuit portion is used for an AND operation, the second logic circuit portion is used for an OR operation, the second logic circuit portion is deactivated when the first logic circuit portion is operated, and the first logic circuit portion is operated when the second logic circuit portion is operated. 1 The logic circuit is characterized in that the logic circuit is inactivated. The method of claim 7, wherein
The first logic circuit portion,
A first logic MTJ having two P states and two first transistors, one end of the first logic MTJ being connected to a reference bit line RBL and the other end being connected between the first transistors; The source of one of the transistors is connected to a reference column line RCL,
The second logic circuit portion,
A second logic MTJ having two AP states and two second transistors, one end of the second logic MTJ being connected to the reference bit line RBL and the other end being connected between the second transistors; And a source of one of the two transistors is connected to a reference column line (RCL). Sensing circuit;
At least one input memory coupled to the sensing circuit and storing input data; And
A first logic circuit portion,
The input memory and the first logic circuit portion has a magnetic tunnel junction (MTJ), and when a logic operation, the resistance of the input memory and the resistance of the first logic circuit portion are compared and output through the sensing circuit. Logic memory circuit characterized in that. The method of claim 9,
Further comprising a second logic circuit portion having an MTJ,
Only a first logic circuit portion of the logic circuit portions is activated during a first logic operation, only a second logic circuit portion of the logic circuit portions is activated during a second logic operation, and a logic operation result of the input data is output through the sensing circuit. Logic memory circuit, characterized in that. The method of claim 10, wherein the first logical operation is an AND operation, and the second logical operation is an OR operation.
And a resistance state of the MTJ of the first logic circuit portion and a resistance state of the MTJ of the second logic circuit portion. A sense circuit, at least one input memory coupled to the sense circuit and comprising a first MTJ, a reference circuit portion comprising a second MTJ, a first logic circuit portion comprising a third MTJ and a second logic comprising a fourth MTJ A method of performing a logic operation in a logic memory circuit having a circuit portion,
Flowing a current through the input memory;
Flowing a current through the reference circuit portion and the first logic circuit portion; And
And the sensing circuit comparing the sum of the resistance of the input memory and the resistance of the reference circuit and the first logic circuit part as the currents flow and outputting a comparison result as a result of the first logic operation. Logical operation performing method. The method of claim 12,
Flowing a current through the input memory;
Flowing a current through the reference circuit and the second logic circuit portion; And
The sensing circuit comparing the sum of the resistance of the input memory and the resistance of the reference circuit and the second logic circuit portion as the currents flow and outputting a comparison result as a result of the second logic operation; Characteristic method of performing a logical operation. The method of claim 13, wherein the first logical operation is an AND operation, and the second logical operation is an OR operation.
And a resistance state of the third MTJ of the first logic circuit portion and a resistance state of the fourth MTJ of the second logic circuit portion are different. A method for performing logic operations in a logic memory circuit having a sense circuit, a plurality of input memories coupled to the sense circuit and comprising a first MTJ, a reference circuit portion comprising a second MTJ, a cache circuit and an output circuit,
Flowing a current through the first input memory;
Flowing a current through the reference circuit portion;
Comparing the resistance of the first input memory with the resistance of the reference circuit unit and outputting the resistance through the sensing circuit;
Storing the output of the output sense circuit in the cache circuit;
Flowing a current through the second input memory;
Flowing a current through the reference circuit portion;
Comparing the resistance of the second input memory with the resistance of the reference circuit unit and outputting the resistance through the sensing circuit; And
And performing a logic operation using data stored in the cache circuit and data output by comparing a resistance of the second input memory with a resistance of the reference circuit unit. 16. The method of claim 15, wherein the logical operation is an XOR operation or a full adder operation.

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