KR20190123083A - Auxiliary memory unit corresponding program temperature variation or process loading effect and method of operating the same - Google Patents

Abstract

The present invention relates to a secondary memory device actively responding to a program temperature change or a process loading effect, and an operating method for the device. The secondary memory device comprises: a storage medium; a temperature detecting sensor for detecting the temperature of the storage medium; and a controller electrically connected to the storage medium and the temperature detecting sensor. In addition, the controller detects the temperature of the storage medium through the temperature detecting sensor and then, applies the method of incremental step pulse programming (ISPP) by temperatures to the storage medium or measures electrical data related to the processing loading effect of a word line in the storage medium and then, applies the method of ISPP by loadings to the storage medium. The present invention can improve reading performance for memory cells and reduce bit error rate.

Description

AUXILIARY MEMORY UNIT CORRESPONDING PROGRAM TEMPERATURE VARIATION OR PROCESS LOADING EFFECT AND METHOD OF OPERATING THE SAME}

The present invention relates to an auxiliary memory device corresponding to a program temperature change or a process loading effect to implement a desired threshold voltage distribution in a memory cell while eliminating temperature effects and process effects during programming in at least one 2D or 3D NAND flash memory. It relates to a driving method of.

In general, the auxiliary memory device is a memory device for assisting the main memory device when the storage capacity of the main memory device (for example, a core memory device or a personal computer ROM, RAM, etc.) is insufficient. Here, the auxiliary storage device refers to a hard disk drive (HDD) or a solid state drive (SSD), but will be described as being limited to a solid state drive for the development of the present invention.

The solid state drive is electrically connected to a user host and mediates data exchange between an external user host and an internal semiconductor memory chip using a controller provided therein. The semiconductor memory chip has a 2D or 3D NAND Flash memory to function as a storage medium.

The 2D or 3D NAND flash memory has a nonvolatile characteristic that preserves data already written therein even when the power is turned off. The 2D or 3D NAND flash memory intersects bit lines and word lines to position memory cells at intersections to form a cell array.

Meanwhile, the user host stores data in a semiconductor memory chip through a controller. To this end, the controller programs a plurality of memory cells of a cell array in a 2D or 3D NAND flash memory of a semiconductor memory chip using an incremental step pulse programming (ISPP) scheme.

1 and 2, in order to program multiple threshold voltage (Vt) levels to individual memory cells in the cell array, the incremental step pulse programming scheme includes a program start potential (Vps1 in FIG. 1) and a program verify potential. (Vpv1 in FIG. 1) and the program step potential (ΔVs1 in FIG. 1) are used. The 2D or 3D NAND flash memory uses a plurality of threshold voltages to identify data information.

Specifically, when the plurality of memory cells are programmed to one threshold voltage level (2 in FIG. 2) at room temperature, the incremental step pulse programming scheme may be used to generate a program start potential (i.e., a threshold voltage lower than a desired threshold voltage). Start the program at Vps1 in FIG. 1, confirm the completion of the program using the program verify potential (Vpv1 in FIG. 1), and start the program start potential Vps1 until the completion of program verification in all cells of the selected page. To the program step potential (ΔVs1 in FIG. 1) repeatedly.

Here, the individual memory cells are implemented as multi-level cells (MLCs) as memory cell types of flash memory using a plurality of bit information, and the multi-level cells are multiplied by (2 ^N −1). N is the number of bits of the program verify potential (e.g., three Vpv1 having different sizes when the MLC of two bits).

Here, the one threshold voltage level 2 is programmed in a plurality of memory cells to have a predetermined threshold voltage distribution as shown in FIG. 2 in the plurality of memory cells. In addition, when the plurality of memory cells are multi-level cells, when programmed to the remaining threshold voltage levels (6 in Fig. 2) at room temperature, the threshold voltage levels (2, 6) are predetermined to enable error correction upon reading. A plurality of memory cells are programmed to be spaced apart from each other by a potential of, and have a predetermined threshold voltage distribution as shown in FIG. 2.

However, when the auxiliary memory device is exposed to the high temperature of the external environment, when the cell array is programmed to the same threshold voltage level through the incremental step programming scheme disclosed above, the high temperature threshold voltage levels 4 and 8 become the cell array. As seen from the threshold voltage distribution of, the threshold voltage levels 2 and 6 at room temperature are shifted to a high potential as shown in FIG. 2.

This is because the individual memory cells in the cell array store many electrons in the word line at a high temperature compared with the room temperature. Therefore, the read reference voltage for the threshold voltage levels 2 and 6 at room temperature should be kept different from the read reference voltage for the threshold voltage levels 4 and 8 at high temperature.

The auxiliary memory device has a high possibility of generating a read error when applying the same read reference voltage to the same threshold voltage levels (2 & 4 or 6 & 8) according to room temperature and high temperature, and has a high threshold voltage level. In order to find the read reference voltage shifted so as to properly correspond to the multiple read operations, the performance is degraded.

In addition, before configuring the auxiliary memory device, the 2D or 3D NAND flash memory may have a word line size in a plurality of memory cells affected by a process in a cell array. The process effect results from the plasma density magnitude in the dry etching process or the pattern density magnitude in the plurality of word lines or the pattern density magnitude around the plurality of word lines.

While the 2D or 3D NAND flash memory is process influenced to form an auxiliary memory device, since the cell array has different word line sizes for each page position in a block, the plurality of memory cells may be written with the same data. Each line has a different threshold voltage.

The different threshold voltages may produce a bell-shaped threshold voltage distribution of a Korean bell at one of the room temperature and high temperature threshold voltages (2, 4) or the remaining room temperature and high temperature threshold voltages (6, 8) shown in FIG. Eskimo Igloo shaped threshold spread. The different threshold voltages also generate read errors regardless of the temperature.

As a related art in this regard, an invention of programming a plurality of memory cells by adjusting a program start potential according to temperature is disclosed in US Pat. No. 8,289,787.

United States Patent Application Publication US 8,289,787

SUMMARY OF THE INVENTION The present invention has been made to solve a conventional problem, and when a plurality of memory cells in a 2D or 3D NAND flash memory are programmed at room temperature and high temperature, the reading reference voltage (hereinafter referred to as "program verify potential") Of a secondary memory device corresponding to a program temperature change or a process loading effect, so as to be suitable for maintaining a threshold voltage in a plurality of memory cells after programming of a plurality of memory cells when they are differently or under process influence. The purpose is to provide a driving method.

According to the present invention, an auxiliary memory device corresponding to a program temperature change or a process loading effect includes a storage medium having at least one 2D or 3D NAND flash memory; A temperature sensor for sensing a temperature of the storage medium; And a controller electrically connected to the storage medium and the temperature sensing sensor, wherein the controller senses a temperature of the storage medium through the temperature sensing sensor, and then increases step pulse programming for each temperature of the storage medium. In an incremental step pulse programming (ISPP) by temperatures scheme, a program start potential, a program verify potential, and a program step potential are applied to individual memory cells of a cell array of the storage medium in order to match threshold voltage distributions of the same data state for each temperature. Is applied differently, or after measuring electrical data related to a process loading effect of a word line in the storage medium, the incremental step pulse programming (ISPP by loadings) method for each loading of the storage medium Grouping a plurality of pages located in one block of the storage medium Tied to the corresponding one of the threshold voltage according to the group, is characterized in that, while applying the same potential to the start of the program and the program step potential to the memory cells of the individual pages is different from the program-verify voltage.

The controller may be configured to program the individual memory cell of the cell array into a multi-level cell (LCC) according to the threshold voltage distribution in the temperature-increased step pulse programming scheme. When applying the first stepwise incremental step pulse programming scheme to a memory cell, the storage medium is programmed based on a first program start potential, a first program verify potential, and a first program step potential, and the individual at high temperature. When the second temperature-specific incremental step pulse programming method is applied to a memory cell, the storage medium may be programmed based on a second program start potential, a second program verify potential, and a second program step potential.

The high temperature is higher than the room temperature and may have a size larger than a reference temperature preset in an algorithm of a processor located inside the controller.

The first program start potential may have a smaller size than the second program start potential.

The first program verify potential may have a constant magnitude in the first incremental step pulse programming scheme.

The second program verify potential has a smaller magnitude than the first program verify potential, and is further from the first program verify potential at a threshold voltage distribution higher than a threshold voltage distribution when viewed at a threshold voltage distribution of the multi-level cell. It can be spaced apart by a large dislocation gap.

The first program step potential may have a larger magnitude than the second program step potential.

In the loading-specific incremental step pulse programming scheme, the controller may be configured to generate at least one characteristic of the electrical data related to the size of the word line in the one block when programming the memory cells of the individual page. After grouping a plurality of pages, when the incremental step pulse programming scheme for each loading is applied to the one block, the program start potential, the program verify potential, and the program step potential are kept constant in a separate group. As the size of the word line increases in the group, the size of the program start potential may increase.

A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect according to the present invention includes connecting an auxiliary memory device to a user host, checking the temperature of a storage medium using a temperature sensor in the auxiliary memory device, Compare the reference temperature of the processor in the controller of the auxiliary storage device to the temperature of the storage medium, and when the temperature of the storage medium is less than the reference temperature of the processor, loading the storage medium using the controller Perform incremental step pulse programming (ISSP by loadings) or when the temperature of the storage medium is greater than the reference temperature of the processor, use the controller to program the temperature incremental step pulse to the storage medium. Performing storage (ISSP by temperatures), the storage medium May include at least one 2D or 3D NAND flash memory.

The incremental step pulse programming method for each loading grouping a plurality of pages according to the size of a word line for each location in one block in the at least one 2D or 3D NAND flash memory to provide the same threshold voltage to the memory cells in the plurality of groups. Can be performed with.

Implementing the incremental step pulse programming scheme for each load reflects the effect of process loading of word lines per position in the one block to group a plurality of pages in one block in the at least one 2D or 3D NAND flash memory. In order to provide power to the storage medium at the time when the storage medium is provided to the auxiliary storage device, the program verification potential for each load is selected from the storage medium during the initialization process of the storage medium, and the program is stored during the program of the storage medium. And by performing the loading-specific program on the storage medium using the loading-specific program verify potential.

Selecting the program verify potential for each loading includes (A) setting a search pulse potential, (B) programming the one block using the search pulse potential, and (C) the plurality of the plurality of blocks in the one block. Measure a program threshold search potential of memory cells in a page, (D) group the plurality of pages according to the order of the program threshold search potential of individual pages in the plurality of pages, and (E) program verify potentials of individual groups It may include setting a.

The program threshold search potential is progressively shifted from the individual page having the lowest sized wordline to the individual page having the highest sized wordline, as seen in the size order of the wordline by the position in the one block. Can be small.

In the step (E), the potential difference between the target threshold potential and the program threshold search potential of the individual group is checked, and the potential difference is equal to the program threshold search potential of the individual group corresponding to the potential difference for each individual group. Adds the program verify potential, maps the group sequence to the program verify potential for each individual group, and stores the program verify potential and the group sequence in a storage area of the control unit in the 2D or 3D flash memory. Alternatively, the method may include reflecting the verification potential offset of the corresponding group in the verification potential charge register when the page is programmed in the 3D flash memory.

The target threshold potential has the same magnitude for each individual group, the program threshold search potential has a gradually smaller magnitude as the magnitude order of the wordline increases, and the program verify potential increases with the magnitude order of the wordline. Therefore, it may gradually have a large size.

Performing the loading-specific program includes: (a) setting a program start potential applied to the at least one 2D or 3D flash memory, and (b) individually in the one block in the at least one 2D or 3D flash memory. Apply the program start potential to individual memory cells of a page, and (c) perform program verification of an individual group formed by grouping the plurality of pages in the one block using the program verify potential, and (d) the The method may include setting and applying an incremental program potential for each load based on the program start potential according to a potential difference between a target threshold voltage and a program threshold voltage in an individual group.

The step (a) may include selecting a potential having a magnitude smaller than a target threshold voltage of the individual memory cell in the individual page, and initializing a counter in the processor to select a count k as k = 1. Can be.

In step (c), the sequence number of the individual group is verified in the verification potential responsible register of the 2D or 3D flash memory, and the controller of the verification potential responsible register is controlled by the controller of the 2D or 3D flash memory. Reading the program verifying potential corresponding to the sequence number and calling the program verifying potential from the controller, and comparing the program threshold potential of the individual group with respect to the program verifying potential to determine whether the target threshold potential of the individual group has been reached. have.

In step (d), in order to set and apply the incremental program potential for each loading, after step (c), the processor shifts the count k by one by one (k = k + 1) and starts the program. The program step potential is added to the potential to be assigned to the loading type incremental program potential, and the loading type incremental program potential is applied to the individual memory cells to reach the target threshold voltage of the program threshold voltage of the individual group. Wherein the program start potential and the program step potential have a constant magnitude in an individual group, and the program verify potential may have a different magnitude in the individual group.

The temperature-specific incremental step pulse programming scheme is an individual of the cell array of the at least one 2D or 3D NAND flash memory at room temperature and high temperature located below and above the reference temperature, respectively, based on the reference temperature of the processor. It may be performed to match the threshold voltage distribution of the memory cell.

Performing the temperature-dependent incremental step pulse programming scheme includes: (a) setting a program start potential at room temperature or at a high temperature, and (b) the individual page in a respective page of a cell array of the at least one 2D or 3D NAND flash memory. The program start potential is applied to a memory cell, (c) program verification is performed in the individual memory cell, and (d) the program start potential is changed according to a potential difference between a target threshold voltage and a program threshold voltage in the individual memory cell. It may be implemented by the processor of the controller to include setting and applying the incremental program potential for each temperature based.

In the step (a), selecting a potential having a magnitude smaller than a target threshold voltage of the individual memory cell at the room temperature or the high temperature, and initializing a counter in the processor to select the count k as k = 1. Implemented by the processor of the controller to include, the room temperature program start potential may have a smaller size than the high temperature program start potential.

In the step (d), after the step (c) at the room temperature or the high temperature in order to set and apply the increased program potential for each temperature, the processor shifts the count k one by one (k = k + 1). The program step potential is added to the program start potential of the room temperature or the high temperature, and assigned as the incremental program potential for each temperature, and the program threshold voltage of the individual memory cell is reached to reach the target threshold voltage. Implemented by the processor of the controller to include applying the temperature-dependent incremental program potential to a memory cell, the program step potential at the high temperature is set smaller than the program step potential at the high temperature, and the program verification at the high temperature. The potential is increased at room temperature in the ascending order of threshold voltage distribution in the cell array. It may be gradually larger away from the gram verify potential.

According to the present invention, a cell array configured by crossing word lines and bit lines in a 2D or 3D NAND flash memory, a 2D or 3D NAND flash memory having a nonvolatile characteristic with respect to data stored in a storage medium, and a wordline in a cell array A plurality of blocks each consisting of pages located along the lines and strings located along the bit lines, and a plurality of memory cells located along individual pages or individual strings in one block. So that

The present invention, by using an incremental step pulse programming (ISPP) by temperatures method for each temperature, to increase the program start potential at a high temperature compared to room temperature, to lower the program step potential at a high temperature compared to room temperature, By lowering the program verify potential for the same data, the program time is reduced for a plurality of memory cells, and over-programming is prevented for a plurality of memory cells, and a plurality of memory cells are stored with the same data at room temperature and high temperature. When programming, it is possible to have different program verification potentials at room temperature and high temperature.

According to the present invention, an incremental step pulse programming (ISPP) by loadings scheme for each load is used, even if the memory lines have different word lines due to process effects in a plurality of memory cells. When exposing 2D array or 3D array memory cells at room temperature according to their position, the same threshold voltage is applied to memory cells of 2D array or 3D array when programming the same data per word line by different program step potential and program verify potential per word line. By having a dispersion, it is possible to improve read performance for memory cells and to reduce bit error rate.

1 is a program time Tpgm vs. program potential Vpgm schematically showing an incremental step pulse programming (ISPP) scheme applied to a 2D or 3D NAND flash memory in an auxiliary memory device according to the related art. Is a graph of.
FIG. 2 is a graph of the threshold voltage distribution of the cell array versus the number of memory cells shown in the 2D or 3D NAND flash memory after programming the 2D or 3D NAND flash memory using the incremental step pulse program method of FIG. 1.
3 is a schematic diagram showing an auxiliary memory device according to the present invention.
FIG. 4 is a circuit diagram schematically illustrating a 2D NAND flash memory in the auxiliary memory device of FIG. 3.
FIG. 5 is a cross-sectional view illustrating a plurality of memory cells in one string in one block in FIG. 4.
FIG. 6 is a circuit diagram schematically illustrating a 3D NAND flash memory in the auxiliary memory device of FIG. 3.
FIG. 7 is a cross-sectional view illustrating a plurality of memory cells in one string in one block in FIG. 6.
FIG. 8 is a cross-sectional view illustrating a shape of an active region made of conductive polysilicon positioned around the word lines of FIG. 7.
FIG. 9 is a circuit diagram illustrating pages of individual groups by grouping word lines in one block according to size in a 2D or 3D NAND flash memory in the auxiliary memory of FIG. 3.
FIG. 10 is a program time Tpgm vs. program potential schematically showing a loading-by-load incremental step pulse programming (ISPP) by loadings method applied to a 2D or 3D NAND flash memory in the auxiliary memory of FIG. 3. (Vpgm) is a graph.
FIG. 11 is a program time (Tpgm) vs. program potential schematically showing a temperature-specific incremental step pulse programming (ISPP) by temperatures method applied to a 2D or 3D NAND flash memory in the auxiliary memory of FIG. 3. (Vpgm) is a graph.
FIG. 12 is a graph of the threshold voltage distribution of the cell array versus the number of memory cells shown in the auxiliary memory device after the 2D or 3D NAND flash memory is programmed by the temperature-increasing step pulse program method of FIG. 11.
13 to 17 are flowcharts illustrating a driving method of the auxiliary memory device of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention are different, but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. .

FIG. 3 is a schematic diagram illustrating an auxiliary memory device according to the present invention, FIG. 4 is a circuit diagram schematically illustrating a 2D NAND flash memory in the auxiliary memory device of FIG. 3, and FIG. 5 is a string in one block in FIG. 4. A cross-sectional view showing a plurality of memory cells.

FIG. 6 is a circuit diagram schematically illustrating a 3D NAND flash memory in the auxiliary memory device of FIG. 3. FIG. 7 is a cross-sectional view illustrating a plurality of memory cells in one string in one block in FIG. 6, and FIG. 8 is a diagram of FIG. 7. A cross-sectional view showing the shape of an active region made of conductive polysilicon positioned around wordlines.

FIG. 9 is a circuit diagram illustrating pages of individual groups by grouping word lines in one block according to size in a 2D or 3D NAND flash memory of the auxiliary memory device of FIG. 3, and FIG. It is a graph of program time (Tpgm) vs. program potential (Vpgm) that schematically shows how incremental step pulse programming (ISPP) by loadings is applied to 2D or 3D NAND flash memory.

FIG. 11 is a program time (Tpgm) vs. program potential schematically showing a temperature-specific incremental step pulse programming (ISPP) by temperatures method applied to a 2D or 3D NAND flash memory in the auxiliary memory of FIG. 3. (Vpgm), and FIG. 12 is a graph of the threshold voltage distribution of the cell array versus the number of memory cells shown in the auxiliary memory device after programming the 2D or 3D NAND flash memory using the incremental step pulse program method according to the temperature of FIG. to be.

First, referring to FIGS. 3 to 7, the auxiliary memory device 120 according to the present invention includes the controller 10, the storage medium 100, and the temperature sensor 110 as shown in FIG. 3. The controller 10 is electrically connected to the storage medium 100 and the temperature sensor 110. The storage medium 100 includes at least one 2D or 3D NAND flash memory 94 or 98 as shown in FIG. 4 or 6.

The 2D NAND flash memory 94 of FIG. 4 is arranged to two-dimensionally arrange word lines (WL1, ..., WLn in FIG. 4) and bit lines (BL1, ..., BLn in FIG. 4). They cross and have memory cells 34 in FIG. The 3D NAND flash memory 98 of FIG. 6 includes three-dimensionally arranged word lines (WL1, ..., WLn in FIG. 6) and bit lines (BL1, ..., BLn in FIG. 6). They cross and have memory cells (38 in FIG. 7) at the intersection.

More specifically, the at least one 2D or 3D NAND flash memory 94 or 98 may include word lines (WL1, ..., WLn in FIG. 4 or 6) and a bit line in the 2D or 3D NAND flash memory. Cells (BL1, ..., BLn in FIG. 4 or 6) are intersected.

In addition, the at least one 2D or 3D NAND flash memory 94 or 98 may include pages positioned along word lines (WL1, ..., WLn in FIG. 4 or 6) in a cell array, respectively. A plurality of blocks of strings each positioned along the bit lines (BL1,..., BLn in FIG. 4 or 6), and along individual pages or individual strings in one block A plurality of memory cells (34 of FIG. 5 or 38 of FIG. 7).

Here, the individual memory cells 34 of the 2D NAND flash memory 94 are on the silicon substrate 24 when viewed in one string (84 in FIG. 5) (or one bit line (BL in FIG. 5)). A word line arranged in two dimensions (WL in FIG. 5) may be included, and external power may be applied to the bit line (BL in FIG. 5) and the word line (WL in FIG. 5).

The word lines WL of FIG. 5 are sequentially stacked on the silicon substrate 24 to form a pair and a pair of two-dimensionally arranged floating gates and control gates. It includes. Individual memory cells 34 of the 2D NAND flash memory 94 have active regions on the silicon substrate 24.

Accordingly, the control gate and the bit line (BL of FIG. 5) set an electric field to the active region and the floating gate through the active region of the silicon substrate 24 to program or erase the floating gate.

In addition, the individual memory cells 38 of the 3D NAND flash memory 98 are on the silicon substrate 28 when viewed in one string (88 in FIG. 7) (or one bitline (BL in FIG. 7)). A word line arranged in three dimensions (WL in FIG. 7) may be included, and external power may be applied to the bit line (BL in FIG. 7) and the word line (WL in FIG. 7).

The word line (WL in FIG. 7) includes a gate pattern (parts hatched only in one direction of FIG. 7) and a silicon substrate 28 in which three or more layers are sequentially stacked and three-dimensionally stacked on the silicon substrate 28. The data storage region 50 is positioned along the stacking direction of the gate pattern.

The individual memory cells 38 of the 3D NAND flash memory 98 have an active region 60 on the silicon substrate 28 in contact with the silicon substrate 28 and the data storage region 50. The bit line (BL in FIG. 7) is in contact with the active region 60 through a conductive plug. Here, the remaining patterns 40 and 70 include an insulating material.

Accordingly, the gate pattern and the bit line (BL of FIG. 7) are configured to set an electric field in the active region 60 and the data storage region 50 on the silicon substrate 28 through the active region 60. 50) Program or erase. The temperature sensor 110 detects the temperature of the storage medium 100.

More specifically, the temperature sensor 110 detects the temperature of the storage medium 100 and transfers the sensed temperature to the controller 10. Similarly, the temperature sensor 110 may detect the internal temperature of the storage medium 100 or the ambient temperature of the storage medium 100 and transmit the detected temperature to the controller 10.

Overall, referring to FIGS. 3 to 12, in accordance with the present invention, the controller 10 includes incremental step pulse programming for each program in the storage medium 100 for loading of the storage medium 100. (ISPP) by loadings) or incremental step pulse programming by temperature (ISPP by temperatures). First, the loading-by-loading incremental step pulse programming (ISPP by loadings) scheme is described below.

The storage medium 100 may have a structure as shown in FIG. 5 by being influenced by one block in the 2D NAND flash memory 94 of FIG. 4. The process influence has been described in detail in the prior art. More specifically, in one block of the 2D NAND flash memory 94, a word line located directly near a source select line (SSL) and a drain select line (DSL) (Fig. 5 WLs and word lines (WL in FIG. 5) located in the center region between the source select line SSL and the drain select line DSL have different sizes in terms of the length of the gate of the transistor. .

In addition, the storage medium 100 may have a structure as shown in FIG. 7 by being influenced by one block in the 3D NAND flash memory 98 of FIG. 6. In one block of the 3D NAND flash memory 98, the gate pattern (WL in FIG. 7) is sequentially stacked on the silicon substrate 28, and the active region 60 is formed by the gate pattern (WL in FIG. 7). Are located along the More specifically, in FIG. 8, the active region 60 forms the silicon substrate (28 of FIG. 7) and the bit line (FIG. 7) at a predetermined angle θ with a dotted line perpendicular to the silicon substrate 28. BL).

That is, the active region 60 has a shape of a fallopian tube that gradually opens while extending along the hole H from the silicon substrate 28 toward the bit line (BL in FIG. 7). Thus, in view of the width of the gate of the transistor, the gate pattern (WL in FIG. 7) has a larger gate width around the bit line (BL in FIG. 7) than around the silicon substrate 28. The change in the length of the gate in the 2D NAND flash memory 94 and the change in the width of the gate in the 3D NAND flash memory 98 described above greatly affect the threshold voltage Vt of the transistor. Thereafter, the length or width of the gate is replaced by the size of the word line.

In order to overcome this, the controller 10 measures electrical data related to a process loading effect of a word line in the storage medium 100, and then increases by loading of the storage medium 100. In the ISPP by loadings method, a plurality of pages located in one block of 2D or 3D flash memory in the storage medium 100 are grouped as shown in FIG. To correspond to the voltage Vt, the program start potential Vps and the program step potential DELTA Vs are equally applied to the individual memory cells 34 or 38 of the individual pages, and the individual memory cells 34 or of the individual pages are equally applied. The program verify potential Vpv is applied differently to 38).

More specifically, the controller 10, in an incremental step-by-load incremental programming scheme, when programming the memory cells 34 or 38 of individual pages, the size of the word line (WL) in one block After grouping a plurality of pages by sizes of at least one characteristic (e.g., program threshold potential) of related electrical data, and then applying the incremental step pulse programming method by loading to one block, the program start potential in an individual group (Vps), the program verify potential (Vpv), and the program step potential (ΔVs) are kept constant, and the size of the program verify potential (Vpv) increases as the size of the word line (WL) increases in the plurality of groups.

That is, the individual group applies the program start potential Vps2, the program verify potential Vpv2 or Vpv3 or Vpv4, and the program step potential DELTA Vs2 corresponding to the size of a specific word line as shown in FIG. I can receive it. The program verify potential initiates, but is not limited to, Vpv2 or Vpv3 or Vpv4. Thus, the program verify potential Vpv2 or Vpv3 or Vpv4 is individual when programming the individual memory cells 34 or 38 into multilevel cells (hereinafter referred to as 'multi-level cells' (MLCs)). The threshold voltage level of the memory cell 34 or 38 is used to verify the threshold voltage level of one of the number of allowed threshold voltage levels 2 ⁿ -1 (except for the erase threshold voltage level). The program verifying potentials Vpv2, Vpv3, and Vpv4 are sequentially large in magnitude. Here, the program step potential DELTA Vs2 may be gradually increased as the size of the word line increases.

On the other hand, the temperature-specific incremental step pulse programming (ISPP by temperatures) method is described. Here, the storage medium 100 receives a threshold voltage Vt while receiving a process effect of FIG. 5 or 7 in a block in a 2D or 3D NAND flash memory 94 or 98 by the position of a word line. The temperature may be severely affected.

In order to overcome this, the controller 10 senses the temperature of the storage medium 100 through the temperature sensor 110 and then increases the step pulse programming for each temperature of the storage medium 100 (ISPP by temperatures). In the scheme (see FIGS. 1 and 11), in order to match the threshold voltage distribution of the same data state for each temperature, the program start potential Vps and the individual memory cells 34 or 38 of the cell array of the storage medium 100 are matched. The program verify potential Vpv and the program step potential DELTA Vs are applied differently.

More specifically, the controller 100 is a multi-level cell (MLC) in the incremental step pulse programming method for each temperature, the individual memory cells 34 or 38 of the cell array according to the threshold voltage distribution ), The first program start potential Vps1 and the first program verify when the first temperature-dependent incremental step pulse programming scheme (see FIG. 1) is applied to the individual memory cells 34 or 38 at room temperature. The storage medium 100 is programmed based on the potential Vpv1 and the first program step potential ΔVs1.

Subsequently, when the second temperature-increasing step pulse programming scheme (see FIG. 11) is applied to the individual memory cells 34 or 38 at a high temperature, the controller 10 receives the second program start potential Vps5 and the second. The storage medium 100 is programmed based on the program verify potential Vpv5 and the second program step potential DELTA Vs5. The high temperature is higher than room temperature and has a size larger than a reference temperature preset in an algorithm of a processor located inside the controller 10.

The first program start potential Vps1 has a smaller size than the second program start potential Vps5. The first program verify potential Vpv1 has a constant magnitude in the first incremental step pulse programming scheme. The second program verify potential Vpv5 has a smaller size than the first program verify potential Vpv1. The first program step potential DELTA Vs1 has a larger magnitude than the second program step potential DELTA Vs5.

More specifically, the one memory cell 34 or 38 corresponds to a distribution of threshold voltages (= increasing or decreasing magnitude of the threshold voltage in FIG. 12) as shown in FIG. 11, and thus the second program start potential. Vps5, the second program verifying potential Vpv5 or Vpv6 or Vpv7, and the second program step potential DELTA Vs5 may be applied. The second program verifying potentials Vpv5, Vpv6, and Vpv7 have large sizes in order.

The second program verify potentials Vpv5, Vpv6, and Vpv7 are larger potential gaps from the first program verify potential Vpv1 at a higher threshold voltage than at a lower threshold voltage when viewed in the threshold voltage distribution of the cell array in FIG. 12. spaced apart by a gap. Therefore, when the temperature-dependent step pulse programming scheme is used, the high temperature threshold voltage levels 134 and 138 move along the dashed arrow to overlap with the threshold voltage levels 132 and 136 of room temperature. Matches threshold voltage levels 132 and 136.

Next, a method of driving the auxiliary memory device according to the present invention will be described with reference to FIGS. 13 to 17.

13 to 17 are flowcharts illustrating a driving method of the auxiliary memory device of FIG. 3. 13 to 17 will be described with reference to FIGS. 3 to 12. In addition, the method of driving the auxiliary memory device may receive a data input command from a user host through the auxiliary memory device to initiate a series of processes for programming data to a storage medium of the auxiliary memory device and verifying the data programmed in the auxiliary memory device. Is performed.

13 to 17, in the method of driving an auxiliary memory device according to the present invention, an auxiliary memory device (120 of FIG. 1) is connected to a user host (not shown) (S230). In operation 120, the temperature sensor 110 checks the temperature of the storage medium 100 in FIG. 1 using the temperature sensor 110 (S260), and the controller of the auxiliary storage device 120 compares with the temperature of the storage medium 110. In reference numeral 10 of FIG. 1, the reference temperature of the processor is compared (S290), and when the temperature of the storage medium 100 is smaller than the reference temperature of the processor of the controller 10, the controller 10 is loaded into the storage medium. 13 may include performing an incremental step pulse programming method (ISSP by loadings) for each star (S700).

The incremental step pulse programming method for each load grouping a plurality of pages according to the size of a word line for each position in one block in at least one 2D or 3D NAND flash memory in the storage medium 100 to group memory pages in a plurality of groups. (34 in FIG. 5 or 38 in FIG. 7) may be performed to have the same threshold voltage Vt. Performing the incremental step pulse programming scheme for each loading (S700) is performed in one block to group a plurality of pages in one block in at least one 2D or 3D NAND flash memory as illustrated in FIG. 14. In order to reflect the process loading effect of the word lines for each location, the storage medium 100 is supplied to the auxiliary storage device 120 at the time when the storage medium 100 is provided, and then the storage medium 100 is initialized during the initialization process of the storage medium 100. Selecting the program verification potential for each loading from the operation 100 (S400), and performing the loading-specific program to the storage medium 100 using the program verification potential for each loading during the program of the storage medium 100 (S600). To be implemented by the processor of the controller.

Selecting the program verification potential for each loading (S400), as shown in Figure 15, (A) setting the search pulse potential (S310), (B) using a search pulse potential to program one block (S330), (C) measure the program threshold search potential of the memory cells 34 or 38 in the plurality of pages in one block (S350), and (D) determine the program threshold search potential of the individual pages in the plurality of pages. The plurality of pages may be grouped according to the size order (S370), and (E) the program verifying potential of the individual groups may be set (S390).

The program threshold search potential may be gradually decreased from the individual page having the lowest size order word lines to the individual page having the highest order word lines when viewed in the size order of the word lines per position in one block. have. In the step (E), the potential difference between the target threshold potential and the program threshold search potential of the individual group is identified, and the program verifying potential is derived by adding the potential difference to the program threshold search potential of the individual group corresponding to the potential difference for each individual group. For each group, the group sequence number corresponds to the program verify potential, and the program verify potential and the group sequence are stored in the storage area of the control unit in the 2D or 3D flash memory and correspond to the verify potential register during page programming in the 2D or 3D flash memory. Reflecting the group's verify potential offset.

The target threshold potential has the same magnitude for each individual group, the program threshold search potential has a gradually smaller size as the size order of word lines increases, and the program verify potential gradually increases as the size order of word lines increases. It can have a large size.

To perform the loading-specific program, as shown in FIG. 16, (a) sets a program start potential (Vps2 of FIG. 10) applied to the at least one 2D or 3D flash memory (S520), (b In the at least one 2D or 3D flash memory, a program start potential is applied to individual memory cells 34 or 38 of individual pages in one block (S540), and (c) a plurality of blocks in one block using the program verify potential. Program verification of the individual groups formed by grouping the pages of (S560), and (d) loading by loading based on the program start potential (Vps2 of FIG. 10) in accordance with the potential difference between the target threshold voltage and the program threshold voltage in the individual group It may include setting an incremental program potential (see description below) (S580). The incremental program potential for each loading is stored in the storage area of the control unit in the 2D or 3D flash memory, and corresponding information is read from the storage area of the control unit whenever power is applied to the 2D or 3D flash memory through the controller 10. Since it is set by placing the information, it is set without requiring an external control operation in a subsequent page program.

In the step (a), the potential of the magnitude smaller than the target threshold voltage Vt of the individual memory cells 34 or 38 in the individual page is selected, and the processor initializes the counter to set the count k to k = 1. May include selecting. In the step (c), the sequence numbers of the individual groups of the verification potential charge registers of the 2D or 3D flash memory are identified, and the control unit of the 2D or 3D flash memory corresponds to the sequence numbers of the verification potential charge registers. Read the program verify potential (Vpv2, Vpv3 or Vpv4) to read the program verify potential (Vpv2, Vpv3 or Vpv4) from the control, and compare the program threshold potentials of the individual groups against the program verify potential (Vpv2, Vpv3 or Vpv4) It may include checking whether the target threshold potential of the group is reached. Here, step (c) may be connected to step (E) in selecting the program verification potential for each loading of FIG. 14 (S400).

In step (d), in order to set and apply an incremental program potential for each load, the processor shifts the count k one by one after step (c) (k = k + 1), and at program start potential Vps2. In order to assign the program step potential ΔVs2 to the loading type incremental program potential, and to increase the program threshold voltage of the individual group to the target threshold voltage, the loading type incremental program potential of each memory cell 34 or 38 is assigned to the individual memory cell 34 or 38. May include applying. Here, the program start potential Vps2 and the program step potential ΔVs2 may have a constant size in separate groups. The program verify potential Vpv2 may have a different size in a separate group.

On the other hand, in the method of driving the auxiliary storage device according to the present invention, the auxiliary storage device 120 is connected to the user host (S230), and the storage medium 100 using the temperature sensor 110 in the auxiliary storage device 120. The temperature of the storage medium 100 is determined (S260), and the controller 10 of the auxiliary storage device 120 is compared with the temperature of the storage medium 110 (S290). When the temperature is greater than the reference temperature of the processor, using the controller 10 to perform the incremental step pulse programming (ISSP by temperatures) for each temperature on the storage medium 100 as shown in FIG. 13 (S900). have.

The temperature-specific incremental step pulse programming scheme is characterized by the individual memory cells of a cell array of at least one 2D or 3D NAND flash memory at room temperature and high temperature positioned below and above the reference temperature, respectively, relative to the reference temperature of the processor (FIG. 34 of 5 or 38 of FIG. 7 may be performed to match the threshold voltage distribution Vt.

Performing the incremental step pulse programming method for each temperature (S900), (a) setting the program start potential (Vps1 of Figure 1 or Vps5 of Figure 1) at room temperature or high temperature (S820), (b) at least In a separate page of a cell array of one 2D or 3D NAND flash memory, a program start potential Vps1 or Vps5 is applied to an individual memory cell 34 or 38 (S840), (c) an individual memory cell 34 or 38 Program verification in step S860, and (d) an incremental program for each temperature based on the program start potential Vps1 or Vps5 according to the potential difference between the target threshold voltage and the program threshold voltage in the individual memory cells 34 or 38. It may be implemented by the processor of the controller 10 to include setting and applying the potential (S880) as shown in FIG. 17.

Step (a) selects a potential (= program start potential) of a magnitude smaller than the target threshold voltage of the individual memory cells 34 or 38 at room temperature or high temperature, and initializes the counter in the processor to count (k). May include selecting k = 1. The program start potential Vps1 at room temperature may have a smaller size than the program start potential Vps5 at high temperature.

In step (d), after setting step (c) at room temperature or high temperature to set and apply an increased program potential for each temperature, the processor shifts the count (k) one by one (k = k + 1), and at room temperature or The program step potential ΔVs1 or ΔVs5 is added to the high temperature program start potential Vps1 or Vps5 to be assigned as an incremental program potential for each temperature, and the program threshold voltage of the individual memory cells 34 or 38 is adjusted to the target threshold voltage. In order to reach, it may include applying a temperature-dependent incremental program potential to individual memory cells 34 or 38. The program step potential DELTA Vs5 at the high temperature may be set smaller than the program step potential DELTA Vs1 at room temperature.

In addition, in FIGS. 11 and 13, the program verifying potentials Vps5, Vps6, and Vps7 at the high temperature may be gradually separated from the program verifying potential (Vps1) at room temperature according to the ascending order of threshold voltage distribution in the cell array. have.

10; Controller, 100; Storage media
110; Temperature sensing sensor, 120; Auxiliary memory

Claims (23)

A storage medium having at least one 2D or 3D NAND flash memory;
A temperature sensor for sensing a temperature of the storage medium; And
A controller electrically connected to the storage medium and the temperature sensing sensor,
The controller,
After sensing the temperature of the storage medium through the temperature sensor, in the incremental step pulse programming (ISPP) by temperatures of the storage medium, the threshold voltage distribution of the same data state for each temperature In order to match, different program start potentials and program verify potentials and program step potentials are applied to individual memory cells of the cell array of the storage medium,
After measuring electrical data related to a process loading effect of a word line in the storage medium, in an incremental step pulse programming (ISPP by loadings) method for each storage medium, among the storage media In order to group a plurality of pages located in one block into groups and to correspond to one threshold voltage according to a group, the program verify potential is applied to the memory cells of the individual pages while applying the same program start potential and program step potential. Auxiliary storage device that actively responds to program temperature changes or process loading effects that are applied differently.
According to claim 1,
In the controller, the temperature-specific incremental step pulse programming method,
When programming the individual memory cells of the cell array into multi-level cells (MLCs) in accordance with the threshold voltage distribution,
Program the storage medium based on a first program start potential, a first program verify potential, and a first program step potential when the first temperature-dependent incremental step pulse programming scheme is applied to the individual memory cells at room temperature,
Programming the storage medium based on a second program start potential, a second program verify potential, and a second program step potential upon application of the second temperature-dependent incremental step pulse programming scheme to the individual memory cells at a high temperature, Auxiliary memory corresponding to program temperature changes or process loading effects.
The method of claim 2,
Wherein the high temperature is higher than the room temperature and has a size larger than a reference temperature preset in an algorithm of a processor located inside the controller, corresponding to a program temperature change or a process loading effect.
The method of claim 2,
Wherein the first program start potential has a smaller magnitude than the second program start potential, corresponding to a program temperature change or a process loading effect.
The method of claim 2,
And the first program verifying potential corresponds to a program temperature change or a process loading effect having a constant magnitude in the first incremental step pulse programming scheme.
The method of claim 2,
The second program verify potential is
Has a size smaller than the first program verify potential,
An auxiliary corresponding to a program temperature change or process loading effect, spaced from the first program verify potential to a larger potential gap at a higher threshold voltage than at a lower threshold voltage distribution in the multi-level cell distribution store.
The method of claim 2,
And the first program step potential corresponds to a program temperature change or a process loading effect, the magnitude of which is greater than the second program step potential.
According to claim 1,
The controller, in the incremental step pulse programming method for each loading,
When programming the memory cells of the individual page,
After the plurality of pages are grouped by sizes of at least one characteristic of the electrical data related to the size of the word line in the one block, when the incremental step pulse programming method for each loading is applied to the one block, Program temperature change or process loading effect to maintain the program start potential, the program verify potential and the program step potential constant in a group and increase the magnitude of the program start potential as the size of the word line increases in a plurality of groups Auxiliary storage device corresponding to.
Connect auxiliary storage to the user host,
Check the temperature of the storage medium using a temperature sensor in the auxiliary storage device,
Compare a reference temperature of a processor in the controller of the auxiliary storage device to a temperature of the storage medium,
When the temperature of the storage medium is less than the reference temperature of the processor, the controller performs load-by-load incremental step pulse programming (ISSP by loadings) on the storage medium, or the temperature of the storage medium. When the controller is greater than the reference temperature of the processor, using the controller to perform temperature-specific incremental step pulse programming (ISSP by temperatures) on the storage medium,
And the storage medium includes at least one 2D or 3D NAND flash memory, and corresponds to a program temperature change or a process loading effect.
The method of claim 9,
The incremental step pulse programming method for each loading grouping a plurality of pages according to the size of a word line for each location in one block in the at least one 2D or 3D NAND flash memory to provide the same threshold voltage to the memory cells in the plurality of groups. A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect, to be carried out with.
The method of claim 9,
Performing the incremental step pulse programming method for each loading,
In order to reflect the effect of the process loading of word lines per position in the one block to group a plurality of pages in one block in the at least one 2D or 3D NAND flash memory,
After the storage medium is supplied to the auxiliary storage device, power is supplied to the storage medium, and the program verification potential for each load is selected from the storage medium during the initialization process of the storage medium.
Implemented by the processor of the controller to include executing the loading-specific program on the storage medium using the loading-specific program verify potential during the program of the storage medium,
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 11, wherein
Selecting the program verification potential for each loading,
(A) Set the search pulse potential,
(B) program the one block using the search pulse potential,
(C) measuring a program threshold search potential of memory cells in the plurality of pages in the one block,
(D) grouping the plurality of pages according to the order of magnitude of program threshold search potential of individual pages in the plurality of pages,
(E) to set the program verify potential of the individual groups,
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 12,
The program threshold search potential is progressively shifted from the individual page having the lowest sized wordline to the individual page having the highest sized wordline, as seen in the size order of the wordline by the position in the one block. A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect so as to be small.
The method of claim 12,
Step (E),
Identify a potential difference between a target threshold potential of the individual group and the program threshold search potential,
The program verifying potential is derived by adding the potential difference to the program threshold search potential of the individual group corresponding to the potential difference for each individual group,
For each individual group the group sequence number corresponds to the program verify potential,
While storing the program verification potential and the group sequence number in a storage area of the control unit in the 2D or 3D flash memory, the verification potential offset of the corresponding group is reflected in the verification potential responsible register during the page programming in the 2D or 3D flash memory. To include things that
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 14,
The target threshold potential has the same magnitude for each individual group,
The program threshold search potential has a gradually smaller size as the size order of the word lines increases.
The program verify potential is gradually increased in magnitude as the magnitude order of the word line increases.
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 11, wherein
To execute the loading-specific program,
(a) setting a program start potential applied to the at least one 2D or 3D flash memory,
(b) applying the program start potential to individual memory cells of individual pages in the one block in the at least one 2D or 3D flash memory,
(c) perform program verification of an individual group formed by grouping the plurality of pages in the one block using the program verify potential,
(d) setting and applying an incremental program potential for each loading based on the program start potential according to a potential difference between a target threshold voltage and a program threshold voltage in the respective group;
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 16,
In step (a),
Selecting a potential having a magnitude smaller than a target threshold voltage of the individual memory cells in the individual page,
And a method of responsive to program temperature changes or process loading effects, including initializing a counter in said processor to select a count (k) as k = 1.
The method of claim 16,
In step (c),
Confirms a sequence number associated with a group sequence number of the individual group in a register for verifying potential of the 2D or 3D flash memory;
Read the program verify potential corresponding to the sequence number of the verify potential responsible register from the control unit of the 2D or 3D flash memory and load it from the control unit;
And matching the program threshold potentials of the individual groups with respect to the program verify potentials to determine whether the target threshold potentials of the individual groups have been reached.
The method of claim 16,
In step (d),
In order to set and apply the incremental program potential for each loading,
After the step (c), the processor shifts the count k by one (k = k + 1),
The program step potential is added to the program start potential and assigned as the incremental program potential for each loading,
Applying the loading-specific program potential to the individual memory cells to reach the program threshold voltage of the individual group to the target threshold voltage.
The program start potential and the program step potential have a constant magnitude in a separate group,
The program verify potentials have different magnitudes in the individual groups,
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 9,
The temperature-specific incremental step pulse programming scheme is characterized by the separation of the cell array of the at least one 2D or 3D NAND flash memory at room temperature and high temperature respectively located below and above the reference temperature relative to the reference temperature of the processor. A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect, which is performed to match a threshold voltage distribution of a memory cell.
The method of claim 9,
To perform the incremental step pulse programming method for each temperature,
(a) Set the program start potential at room temperature or high temperature,
(b) applying the program start potential to the individual memory cells in individual pages of a cell array of the at least one 2D or 3D NAND flash memory,
(c) performing program verification on the individual memory cells,
(d) being implemented by a processor of the controller to include setting and applying an incremental program potential for each temperature based on the program start potential in accordance with the potential difference between a target threshold voltage and a program threshold voltage in the respective memory cell. And a method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 21,
In step (a),
Select a potential having a magnitude smaller than a target threshold voltage of the individual memory cell at the room temperature or the high temperature,
Implemented by the processor of the controller to include initializing a counter in the processor to select a count k by k = 1;
The program start potential of the room temperature is smaller than the program start potential of the high temperature,
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.
The method of claim 21,
In step (d),
In order to set and apply the increased program potential for each temperature,
After the step (c) at the room temperature or the high temperature, the processor shifts the count k by one (k = k + 1),
The program step potential is added to the room temperature or the high temperature program start potential and assigned as the incremental program potential for each temperature.
Implemented by the processor of the controller to include applying the temperature-dependent incremental program potential to the individual memory cell to reach the program threshold voltage of the individual memory cell to the target threshold voltage.
The program step potential at the high temperature is set smaller than the program step potential at the normal temperature,
The program verify potential at the high temperature is gradually spaced apart from the program verify potential at the room temperature according to the ascending order of threshold voltage distribution in the cell array.
A method of driving an auxiliary memory device corresponding to a program temperature change or a process loading effect.

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