KR20190121690A - Display panel and electronic apparatus including the same - Google Patents

Abstract

A display panel includes at least one hole, a hole region in which the hole is defined, an insulating substrate including a display region surrounding the hole region and a peripheral region adjacent to the display region, a plurality of pixels disposed in the display region, main signal wires disposed in the display region and electrically connected to the pixels, and sub signal wires disposed in the hole region and electrically connected to the main signal wires. The hole region includes a wiring region surrounding the hole and the sub signal wires are arranged, and a compensation region disposed between the wiring region and the display region on a plane and displaying black color. Various defects in the region adjacent to the hole can be prevented from being displayed.

Description

DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAME}

The present invention relates to a display panel and an electronic device including the same, and more particularly, to a display panel in which at least one hole is defined and an electronic device including the same.

The electronic device is activated according to the electrical signal. The electronic device may include a display device for displaying an image or a touch sensing device for sensing an external input. In the display device, the organic light emitting display device has low power consumption, high luminance, and high response speed.

The organic light emitting diode display includes an organic light emitting diode. The organic light emitting diode is vulnerable to moisture or oxygen and can be easily damaged. Accordingly, in the organic light emitting diode display, as the moisture or oxygen flowing in from the outside is stably blocked, the reliability of the organic light emitting diode display may be improved and the lifespan may be improved.

An object of the present invention is to provide a display panel and an electronic device including the same that can prevent various defects in the area adjacent to the hole from being visually recognized.

The display panel according to an exemplary embodiment of the present invention may include an insulating substrate including at least one hole defined therein, the hole area in which the hole is defined, a display area surrounding the hole area, and a peripheral area adjacent to the display area. A plurality of pixels disposed in an area, main signal wires disposed in the display area and electrically connected to the pixels, and sub signal wires disposed in the hole area and electrically connected to the pixels; The area includes a wiring area surrounding the hole and in which the sub-signal wires are arranged, and a compensation area disposed between the wiring area and the display area on a plane and displaying a black color.

The display device may further include a metal pattern disposed in the compensation area and spaced apart from each other in the plane from the pixels.

The metal pattern may be a floating electrode.

The metal pattern may have a ground voltage.

The metal pattern may have the same voltage as the sub signal lines.

The metal pattern may be disposed on the same layer as the sub signal lines.

The sub signal lines and the main signal lines may be disposed on different layers.

The metal pattern may be disposed on a layer different from the sub signal lines.

At least one of the sub signal wires may be disposed on the same layer as at least one of the main signal wires.

The metal pattern may extend to the wiring area, and the metal pattern may overlap the sub signal lines on a plane.

The display panel according to an exemplary embodiment may further include an encapsulation layer covering the pixels, and the metal pattern may be disposed on the encapsulation layer.

The display device may further include a plurality of light emitting devices disposed in the compensation area and spaced apart from each other in a plane from the pixels.

Each of the light emitting devices may be electrically connected to at least one of the main signal wires and the sub signal wires, and each of the light emitting devices may display light having a black color.

Each of the light emitting devices may be electrically insulated from the main signal wires and the sub signal wires.

The insulating substrate includes a plurality of holes spaced apart from each other, the hole area overlapping each of the holes and provided as a plurality of areas spaced apart from each other, and each of the compensation areas of the hole areas defines an edge of each of the holes. Can be arranged accordingly.

The insulating substrate may include a plurality of holes spaced apart from each other, the hole region may be provided as one region overlapping all of the holes, and the holes may be surrounded by one compensation region.

An electronic device according to an embodiment of the present invention includes a hole area displaying black and a display area surrounding the hole area and displaying an image according to an electrical signal, and including a through hole defined in the hole area. A display panel, and an electronic module disposed below the display panel and overlapping the hole region, wherein the hole region includes a wiring region surrounding the through hole, the wiring region, and the wiring region and the wiring region. A compensation area disposed between the display areas, wherein the display panel includes: a plurality of pixels disposed in the display area, a plurality of main signal wires disposed in the display area and connected to the pixels; A plurality of sub-signal wires arranged and connected to the main signal wires, and a compensation element disposed in the compensation area and displaying a black color. The.

The compensation element may include a metal pattern covering the compensation area and spaced apart from the pixels in a plane, and the metal pattern may be optically opaque.

The metal pattern may overlap at least one of the main signal wires and the sub signal wires in plan view.

Each of the pixels may include a thin film transistor and a light emitting device connected to the thin film transistor, and the compensation device may have a structure in which at least one of the thin film transistor and the light emitting device is omitted.

The compensation element includes a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode, wherein the first electrode is electrically connected to the main signal wires and the sub signal wires. It can be insulated.

The first electrode may be a floating pattern.

The compensation element may have the same structure as at least one of the pixels, and the compensation element may generate light having a black color.

The sub signal wires may include a curve extending along at least a portion of an edge of the through hole, and the main signal wires may include a straight line.

According to the present invention, it is possible to prevent a problem that stains or the like on the display panel caused by external contamination penetrating through the hole are visually recognized from the outside. In addition, according to the present invention, by electrically shielding the pixels disposed in the area adjacent to the hole from the various signal wires disposed adjacent to the hole, the influence of the pixels by signals other than the electrical signal provided to the pixels Can be reduced. Accordingly, a problem of distorting an image in an area adjacent to a hole may be prevented, and thus a display panel and an electronic device having a uniform image may be provided.

1 is a perspective view illustrating an electronic device according to an embodiment of the present invention.
FIG. 2A is an exploded perspective view of the electronic device shown in FIG. 1.
FIG. 2B is a block diagram of the electronic device shown in FIG. 1.
FIG. 3A is an equivalent circuit diagram schematically illustrating some components of FIG. 2A.
FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 2A.
4 is a plan view illustrating the region XX ′ illustrated in FIG. 2A.
5A is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention.
FIG. 5B is a schematic cross-sectional view of a portion of FIG. 5A.
6A is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention.
FIG. 6B is a schematic cross-sectional view of a portion of FIG. 6A.
7A is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention.
7B to 7D are cross-sectional views briefly illustrating some regions of FIG. 7A.
8 is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention.
9A to 9G are cross-sectional views illustrating some regions of the display panel according to the exemplary embodiment.
10A is an exploded perspective view illustrating an electronic device according to an embodiment of the present invention.
FIG. 10B is a plan view briefly illustrating a region YY ′ illustrated in FIG. 10A.
11A is an exploded perspective view illustrating an electronic device according to an embodiment of the present invention.
FIG. 11B is a plan view briefly illustrating some regions illustrated in FIG. 11A.

Embodiments of the present invention for achieving the above object will be described in detail below with reference to the accompanying drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Also, like reference numerals refer to like elements throughout. In the accompanying drawings, the scales of some components are exaggerated or reduced in order to clearly express various layers and regions. Hereinafter, the present invention will be described with reference to the drawings.

1 is a perspective view illustrating an electronic device according to an embodiment of the present invention. FIG. 2A is an exploded perspective view of the electronic device shown in FIG. 1. FIG. 2B is a block diagram of the electronic device shown in FIG. 1. Hereinafter, an electronic device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 2B.

The electronic device EA may be a device activated according to an electrical signal. The electronic device EA may include various embodiments. For example, the electronic device EA may include a tablet, a notebook, a computer, a smart television, and the like. In this embodiment, the electronic device EA is exemplarily shown as a smart phone.

As shown in FIG. 1, the electronic device EA may provide a display surface displaying an image IM on the front surface. The display surface may be defined parallel to the surface defined by the first direction DR1 and the second direction DR2. The display surface includes a transmissive area TA and a bezel area BZA adjacent to the transmissive area TA.

The electronic device EA displays the image IM in the transmission area TA. In FIG. 1, an internet search box is shown as an example of an image IM. The transmission area TA may have a quadrangular shape parallel to each of the first direction DR1 and the second direction DR2. However, this is only illustrative, and the transmission area TA may have various shapes and is not limited to any one embodiment.

The bezel area BZA is adjacent to the transmission area TA. The bezel area BZA may surround the transmission area TA. However, this is only an example, and the bezel area BZA may be disposed adjacent to only one side of the transmission area TA, or may be omitted. An electronic device according to an embodiment of the present disclosure may include various embodiments and is not limited to any one embodiment.

The normal direction of the display surface may correspond to the thickness direction DR3 (hereinafter, referred to as a third direction) of the electronic device EA. In this embodiment, the front (or front) and back (or bottom) of each member is defined based on the direction in which the image IM is displayed. The front and rear surfaces face each other in the third direction DR3.

Meanwhile, the direction indicated by the first to third directions DR1 and DR2 DR3 may be converted to another direction as a relative concept.

As shown in FIG. 2A, the electronic device EA includes a display panel 100, a window member 200, an electronic module 300, and a storage member 400. As illustrated in FIG. 2B, the electronic device EA may further include a display module DD, a first electronic module EM1, a second electronic module EM2, and a power supply module PM. In FIG. 2A, some of the elements illustrated in FIG. 2B are omitted. Hereinafter, the electronic device EA will be described in detail with reference to FIGS. 2A and 2B.

The display module DD may include a display panel 100 and a touch sensing unit TSU. The display panel 100 generates an image IM. The display panel 100 may detect a user's input applied from the outside. In this case, the display panel 100 may further include a touch sensor, and the touch sensing unit TSU described later may be omitted.

The touch sensing unit TSU senses a user's input applied from the outside. The user's input includes various forms of external inputs such as part of the user's body, light, heat, or pressure. In FIG. 2A, the touch sensing unit TSU is omitted.

In the present exemplary embodiment, the display panel 100 may include a display area DA, a peripheral area NDA, and a hole area PA, which are divided on a plane. The display area DA may be an area where the image IM is generated. The display panel 100 includes a pixel PX disposed in the display area DA. A plurality of pixels PX may be provided and arranged in the display area DA. The light generated by the pixel PX implements the image IM.

The peripheral area NDA is adjacent to the display area DA. The peripheral area NDA may surround the display area DA. In the peripheral area NDA, a driving circuit or driving wiring for driving the display area DA may be disposed.

Although not shown, a portion of the peripheral area NDA of the display panel 100 may be bent. Accordingly, some of the peripheral area NDA may face the front surface of the electronic device EA and other portions of the peripheral area NDA may face the rear surface of the electronic device EA. In the display panel 100 according to an exemplary embodiment, the peripheral area NDA may be omitted.

The hole area PA may be an area surrounded by the display area DA. In the cross section, the hole area PA is spaced apart from the peripheral area NDA with the display area DA interposed therebetween. The display panel 100 according to the exemplary embodiment of the present invention may include at least one module hole MH. The module hole MH may be disposed in the hole area PA. Accordingly, the module hole HM may be surrounded on the plane by the display area DA in which the image is displayed.

The module hole MH passes through the display panel 100. The module hole MH may have a cylindrical shape having a height in the third direction DR3. The module hole HM overlaps the electronic module 300 in a plane. The electronic module 300 may be accommodated in the module hole MH or may have a size similar to that of the module hole MH. The electronic module 300 may receive an external input through the module hole MH. Detailed description of the electronic module 300 will be described later.

In the present invention, since the display panel 100 includes the module hole HM, a separate space for the electronic module 300 may not be provided through the peripheral area NDA. As a result, the area of the peripheral area NDA may be reduced to implement the electronic device EA having a narrow bezel. In addition, when the electronic module 300 is accommodated in the module hole HM, the thin electronic device EA may be implemented.

The window member 200 provides a front surface of the electronic device EA. The window member 200 may be disposed on the front surface of the display panel 100 to protect the display panel 100. For example, the window member 200 may include a glass substrate, a sapphire substrate, or a plastic film. The window member 200 may have a multilayer or single layer structure. For example, the window member 200 may have a laminated structure of a plurality of plastic films bonded with an adhesive, or may have a laminated structure of a glass film and a plastic film bonded with an adhesive.

The window member 200 may be divided into a transmission area TA and a bezel area BZA. The transmission area TA may be an area corresponding to the display area DA. For example, the transmission area TA overlaps the entire surface or at least a portion of the display area DA. The image IM displayed in the display area DA of the display panel 100 may be visually recognized through the transmission area TA.

The bezel area BZA defines the shape of the transmission area TA. The bezel area BZA is adjacent to the transmission area TA and may surround the transmission area TA. The bezel area BZA may have a predetermined color. The bezel area BZA may cover the peripheral area NDA of the display panel 100 to prevent the peripheral area NDA from being viewed from the outside. On the other hand, this is shown by way of example, in the window member 200 according to an embodiment of the present invention, the bezel area BZA may be omitted.

The power supply module PM supplies power required for the overall operation of the electronic device EA. The power supply module PM may include a conventional battery module.

The accommodation member 400 may be coupled to the window member 200. The accommodation member 400 provides a rear surface of the electronic device EA. The accommodation member 400 may be combined with the window member 200 to define an interior space, and the display panel 100, the electronic module 300, and various components illustrated in FIG. 2B may be accommodated in the interior space. The accommodation member 400 may include a material having a relatively high rigidity. For example, the accommodation member 400 may include a plurality of frames and / or plates made of glass, plastic, and metal. The accommodation member 400 may stably protect components of the electronic device EA accommodated in the internal space from external shock.

The electronic module 300 includes various functional modules for operating the electronic device EA. As described above, the electronic module 300 may receive an external input transmitted through the module hole MH or provide an output through the module hole MH. The electronic module 300 may include a first electronic module EM1 and a second electronic module EM2.

The first electronic module EM1 may be directly mounted on the motherboard electrically connected to the display module DD or may be mounted on a separate board and electrically connected to the motherboard through a connector (not shown).

The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an acoustic input module AIM, a memory MM, and an external interface EF. have. Some of the modules may not be mounted on the motherboard but may be electrically connected to the motherboard through a flexible circuit board.

The control module CM controls the overall operation of the electronic device EA. The control module CM may be a microprocessor. For example, the control module CM activates or deactivates the display module DD. The control module CM may control other modules such as an image input module IIM or an acoustic input module AIM based on the touch signal received from the display module DD.

The wireless communication module TM may transmit / receive a radio signal with another terminal using a Bluetooth or Wi-Fi line. The wireless communication module TM may transmit / receive a voice signal using a general communication line. The wireless communication module TM includes a transmitter TM1 for modulating and transmitting a signal to be transmitted, and a receiver TM2 for demodulating a received signal.

The image input module IIM processes the image signal and converts the image signal into image data displayable on the display module DD. The sound input module AIM receives an external sound signal by a microphone in a recording mode and a voice recognition mode, and converts the external sound signal into electrical voice data.

The external interface EF serves as an interface connected to an external charger, a wired / wireless data port, a card socket (eg, a memory card, a SIM / UIM card), or the like.

The second electronic module EM2 may include an acoustic output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, and the like. The components may be directly mounted on the motherboard, or mounted on a separate board to be electrically connected to the display module DD through a connector (not shown) or the like, or may be electrically connected to the first electronic module EM1.

The sound output module AOM converts the sound data received from the wireless communication module TM or the sound data stored in the memory MM and outputs the sound data to the outside.

The light emitting module LM generates and outputs light. The light emitting module LM may output infrared light. The light emitting module LM may include an LED element. The light receiving module LRM may detect infrared rays. The light receiving module LRM may be activated when an infrared ray of a predetermined level or more is detected. The light receiving module LRM may include a CMOS sensor. After the infrared light generated by the light emitting module LM is output, it may be reflected by an external object (for example, a user's finger or face), and the reflected infrared light may be incident on the light receiving module LRM. The camera module CMM captures an external image.

The electronic module 300 illustrated in FIG. 2A may be any one of the modules configuring the first electronic module EM1 and the second electronic module EM2. For example, the electronic module 300 may be a camera, a speaker, or a sensing sensor such as light or heat. The electronic module 300 may detect an external subject received through the module hole HM or provide a sound signal such as a voice to the outside through the module hole HM. In this case, the remaining components of the first electronic module EM1 and the second electronic module EM2 may be arranged in different positions and not shown. However, this is only an example, and the electronic module 300 may include a plurality of modules constituting the first electronic module EM1 and the second electronic module EM2. It is not limited.

FIG. 3A is an equivalent circuit diagram schematically illustrating some components of FIG. 2A. FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 2A. FIG. 3A briefly illustrates an equivalent circuit diagram of one pixel PX for easy description, and FIG. 3B omits some of the configurations of the pixel PX shown in FIG. 3A. Hereinafter, the present invention will be described with reference to FIGS. 3A and 3B.

The display panel 100 may include an insulating substrate BS, a base layer BL, a circuit layer DP-CL, a display element layer DP-OLED, and an encapsulation layer TFE.

The insulating substrate BS includes an insulating material. The insulating substrate BS may include a flexible material. For example, the insulating substrate BS may include polyimide (PI). However, this is described as an example, and the insulating substrate BS may be rigid, or the insulating substrate BS may be made of various materials such as glass and plastic, and is not limited to any one embodiment.

The pixel PX may be disposed on the insulating substrate BS. As described above, the pixel PX may be disposed in the display area DA of the insulating substrate BS.

Referring to FIG. 3A, the pixel PX may be connected to a plurality of signal lines. In the present exemplary embodiment, the pixel PX connected to the i-th gate line GLi and the i-th emission control line ECLi among the signal lines is illustrated. However, this is exemplarily illustrated, and the pixel PX according to an embodiment of the present invention may be additionally connected to various signal lines, and is not limited to any one embodiment. The light emitting device ELD emits light. Contains substances. The light emitting device ELD may generate light of a color corresponding to the light emitting material. The color of the light generated by the light emitting device ELD may be any one of red, green, blue, and white.

The pixel PX may include a light emitting element ELD and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 -T7 and a capacitor CP. The pixel circuit CC controls the amount of current flowing in the light emitting element ELD in response to the data signal.

The light emitting element ELD may emit light at a predetermined luminance corresponding to the amount of current supplied from the pixel circuit CC. The level of the first power supply ELVDD may be set higher than the level of the second power supply ELVSS.

The capacitor CP is disposed between the power supply line PL and the node ND. The capacitor CP stores a voltage corresponding to the data signal. The amount of current flowing in the first transistor T1 when the fifth transistor T5 and the sixth transistor T6 is turned on may be determined according to the voltage stored in the capacitor CP.

Each of the transistors T1 -T7 may include an input electrode (or a source electrode), an output electrode (or a drain electrode), and a control electrode (or a gate electrode).

The input electrode of the first transistor T1 is connected to the power supply pattern VDD via the fifth transistor T5, and the output electrode of the first transistor T1 is connected to the light emitting device via the sixth transistor T6. ELD). The first transistor T1 may be referred to as a driving transistor within the present specification. The first transistor T1 controls the amount of current flowing through the light emitting element ELD in response to the voltage applied to the control electrode of the first transistor T1.

The second transistor T2 is connected between the first signal line SNL1 and the input electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the i-th gate line GLi. The second transistor T2 is turned on when the i-th scan signal is provided to the i-th gate line GLi to electrically connect the first signal line SNL1 and the input electrode of the first transistor T1.

The third transistor T3 is connected between the output electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th gate line GLi. The third transistor T3 is turned on when the i-th scan signal is provided to the i-th gate line GLi to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. Connect. When the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

The fourth transistor T4 is connected between the node ND and the initialization power generator (not shown). The control electrode of the fourth transistor T4 is connected to the i-1 th gate line GLi-1. The fourth transistor T4 is turned on when the i-1 th scan signal is provided to the i-1 th gate line GLi-1 to provide an initialization voltage Vint to a predetermined node ND.

The fifth transistor T5 is connected between the power supply wiring PL and the input electrode of the first transistor T1. The control electrode of the fifth transistor T5 is connected to the i-th light emission control line ECLi.

The sixth transistor T6 is connected between the output electrode of the first transistor T1 and the light emitting element ELD. The control electrode of the sixth transistor T6 is connected to the i-th light emission control line ECLi.

The seventh transistor T7 is connected between the initialization power generator (not shown) and the light emitting element ELD. The control electrode of the seventh transistor T7 is connected to the i + 1th gate line GLi + 1. The seventh transistor T7 is turned on when the i + 1 th scan signal is provided to the i + 1 th gate line GLi + 1 to provide the initialization voltage Vint to the light emitting device ELD.

The seventh transistor T7 can improve the black expression capability of the pixel PX. Specifically, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light emitting device ELD is discharged. When the black luminance is implemented, a defect in which the light emitting device ELD emits light due to a leakage current from the first transistor T1 may be improved, and thus the black color may be improved.

In addition, in FIG. 3A, the control electrode of the seventh transistor T7 is illustrated as being connected to the i + 1 th gate line GLi + 1, but the present invention is not limited thereto. In another embodiment of the present invention, the control electrode of the seventh transistor T7 may be connected to the i-th gate line GLi or the i-th gate line GLi-1.

 In FIG. 3A, the PMOS is illustrated as a reference, but is not limited thereto. For example, in another embodiment of the present invention, the pixel circuit CC may be configured as an NMOS. Alternatively, for example, in one embodiment of the present invention, the pixel circuit CC may be configured by a combination of an NMOS and a PMOS. In FIG. 3B, the pixel transistor TR-P, which is part of the configurations of the pixel PX, may be configured. ) And the light emitting device ELD are illustrated. The pixel transistor TR-P may correspond to the sixth thin film transistor TR6 of FIG. 3A. The pixel transistor TR-P is disposed on the insulating substrate BS.

The pixel transistor TR-P constitutes a circuit layer DP-CL. Meanwhile, in the present exemplary embodiment, the display panel 100 may further include a base layer BL disposed between the circuit layer DP-CL and the insulating substrate BS. The base layer BL may include a single layer or a plurality of insulating layers. For example, the base layer BL may include at least one of a buffer layer and a barrier layer. Accordingly, the circuit layer DP-CL may be stably formed on the base layer BL, and the base layer BL may have oxygen or moisture flowing through the insulating substrate BS in the circuit layer DP-CL. ) Can be prevented.

The pixel transistor TR-P includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The control electrode CE of the pixel transistor TR-P is spaced apart from the semiconductor pattern SP with the first insulating layer 10 therebetween.

The input electrode IE and the output electrode OE of the pixel transistor TR-P are spaced apart from the control electrode CE of the pixel transistor TR-P with the second insulating layer 20 therebetween. The input electrode IE and the output electrode OE of the pixel transistor TR-P may pass through the first insulating layer 10 and the second insulating layer 20 to one side and the other side of the semiconductor pattern SP. Each is connected.

In the pixel transistor TR-P, the control electrode CE may be disposed under the semiconductor pattern SP, and the input electrode IE and the output electrode OE may be disposed under the semiconductor pattern SP. Alternatively, the semiconductor layer may be disposed on the same layer as the semiconductor pattern SP and directly connected to the semiconductor pattern SP. The pixel transistor TR-P according to an embodiment of the present invention may be formed in various structures and is not limited to any one embodiment.

The light emitting element ELD is disposed on the third insulating layer 30. The light emitting element ELD and the fourth insulating layer 40 constitute a display element layer DP-OLED. The light emitting device ELD includes a first electrode E1, a light emitting layer EL, and a second electrode E2 sequentially stacked along the third direction DR3.

The first electrode E1 may pass through the third insulating layer 30 and be connected to the pixel transistor TR-P. Although not shown, a separate connection electrode disposed between the first electrode E1 and the pixel transistor TR-P may be further added. In this case, the first electrode E1 may be a pixel transistor through the connection electrode. It can be electrically connected to (TR-P).

The fourth insulating layer 40 is disposed on the third insulating layer 30. An opening OP may be defined in the fourth insulating layer 40. The opening OP exposes at least a portion of the first electrode E1. The fourth insulating layer 40 may be a pixel defining layer.

The light emitting layer EL is disposed in the opening OP and is disposed on the first electrode E1. The emission layer EL may include a light emitting material. For example, the light emitting layer EL may be formed of at least one of materials emitting red, green, and blue, and may include a fluorescent material or a phosphorescent material. The emission layer EL may include an organic material and / or an inorganic material. The emission layer EL may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

The second electrode E2 is disposed on the light emitting layer EL. The second electrode E2 may face the first electrode E1. The second electrode E2 may be connected to the power supply terminal VSS of FIG. 3A. The light emitting element ELD receives the second power supply voltage through the second electrode E2.

The second electrode E2 may include a transmissive conductive material or a semi-transmissive conductive material. Accordingly, light generated in the emission layer EL may be easily emitted toward the third direction DR3 through the second electrode E2. However, this is only illustrative, and the light emitting device ELD according to the exemplary embodiment of the present invention may be driven by a bottom emission method in which the first electrode E1 includes a transmissive or semi-transmissive material, according to a design. It may be driven by a double-sided light emission method that emits light toward both the front and back, it is not limited to any one embodiment.

Although not shown, the light emitting device ELD may include at least one organic layer or at least one of the light emitting layer EL disposed between at least one of the light emitting layer EL and the first electrode E1, and between the light emitting layer EL and the second electrode E2. It may further include one inorganic layer. The organic layer or the inorganic layer may improve the light efficiency and lifespan of the light emitting device ELD by controlling the movement of electric charges flowing into the light emitting layer EL from the first electrode E1 and the second electrode E2.

The encapsulation layer TFE is disposed on the light emitting device ELD to encapsulate the light emitting device ELD. Although not shown, a capping layer covering the second electrode E2 may be further disposed between the second electrode E2 and the encapsulation layer TFE.

The encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 sequentially stacked along the third direction DR3. However, the present invention is not limited thereto, and the encapsulation layer TFE may further include a plurality of inorganic layers and organic layers.

The first inorganic layer IOL1 may cover the second electrode E2. The first inorganic layer IOL1 may prevent external moisture or oxygen from penetrating the light emitting device ELD. For example, the first inorganic layer IOL1 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer IOL1 may be formed through a deposition process.

The organic layer OL may be disposed on the first inorganic layer IOL1 to contact the first inorganic layer IOL1. The organic layer OL may planarize the upper portion of the first inorganic layer IOL1. Effects of bending on the top surface of the first inorganic layer IOL1 or particles present on the first inorganic layer IOL1 may be covered by the organic layer OL and formed on the organic layer OL. Can be blocked. In addition, the organic layer OL may relieve stress between the layers in contact. The organic layer OL may include an organic material and may be formed through a solution process such as spin coating, slit coating, or inkjet process.

The second inorganic layer IOL2 is disposed on the organic layer OL to cover the organic layer OL. The second inorganic layer IOL2 may be stably formed on a relatively flat surface than the second inorganic layer IOL1. The second inorganic layer IOL2 encapsulates moisture and the like emitted from the organic layer OL to prevent the second inorganic layer IOL2 from flowing into the outside. The second inorganic layer IOL2 may include silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer IOL2 may be formed through a deposition process.

Although not shown, an input sensing unit including a plurality of sensor patterns may be further disposed on the encapsulation layer TFE. The input sensing unit may be directly formed on the encapsulation layer TFE to sense an external input such as a touch or a pressure. The input sensing unit may be, for example, a touch sensing unit (TSU, see FIG. 2B). On the other hand, this is described by way of example, the display panel according to an embodiment of the present invention may include a variety of embodiments, it is not limited to any one embodiment.

The display panel 100 may further include a thin film transistor TR-D (hereinafter, referred to as a driving transistor), conductive patterns E-VSS, E-CNT, VIN, and CL, and dam units DM1 and DM2. have. The driving transistor TR-D and the conductive patterns E-VSS, E-CNT, VIN, and CL may form a circuit layer DP-CL.

The driving transistor TR-D is disposed in the peripheral region NDA. In the present embodiment, the driving transistor TR-D may have a structure corresponding to the pixel transistor TR-P. For example, the driving transistor TR-D may include the semiconductor pattern SP disposed on the base layer BL, the control electrode CE disposed on the first insulating layer 10, and the second insulating layer 20. ) May include an input electrode IE and an output electrode OE. Accordingly, the pixel transistor TR-P and the driving transistor TR-D may be simultaneously formed in the same process, thereby simplifying the process and reducing the process cost. However, this is exemplarily illustrated, and the driving transistor TR-D according to the exemplary embodiment of the present invention may have a structure different from that of the pixel transistor TR-P, and is not limited to any one embodiment. .

The conductive patterns E-VSS, E-CNT, VIN, and CL include a power supply line E-VSS, a connection electrode E-CNT, an initialization voltage line VIN, and a driving signal line CL. can do. The power supply line E-VSS may correspond to the power terminal VSS of the pixel PX. Accordingly, the power supply line E-VSS supplies the second power supply voltage to the light emitting element ELD. In the present embodiment, the second power supply voltages supplied to the pixels PX may be a voltage common to all the pixels PX.

The power supply line E-VSS is disposed on the second insulating layer 20 to constitute the circuit layer DP-CL. The power supply line E-VSS may be simultaneously formed in the same process as the input electrode IE or the output electrode OE of the driving transistor TR-D. However, this is only shown as an example, and the power supply line E-VSS is disposed on a different layer from the input electrode IE or the output electrode OE of the driving transistor TR-D and may be formed through a separate process. It may be formed, but is not limited to any one embodiment.

The connection electrode E-CNT is disposed on the third insulating layer 30 to form the display element layer DP-OLED. The connection electrode E-CNT is electrically connected to the power supply line E-VSS. The connection electrode E-CNT extends from the third insulating layer 30 to cover the top surface of the power supply line E-VSS exposed from the third insulating layer 30.

The second electrode E2 of the light emitting element ELD extends from the display area DA and is connected to the connection electrode E-CNT. The connection electrode E-CNT may receive a second power supply voltage from the power supply line E-VSS. Accordingly, the second power supply voltage may be transferred to the second electrode E2 through the connection electrode E-CNT and provided to each pixel.

The connection electrode E-CNT may be disposed on the same layer as the first electrode E1 of the light emitting device ELD and formed simultaneously with the first electrode E1. However, this is only illustrative, and the connection electrode E-CNT may be disposed on a layer different from the first electrode E1.

The driving signal line CL may be provided in plural and disposed on the second insulating layer 20. The driving signal line CL may be disposed in the peripheral area NDA. The driving signal line CL may be a routing line connected to a pad (not shown) or a line constituting an integrated circuit IC. The driving signal lines CL are spaced apart from each other in the second direction DR2 and independently transmit electrical signals.

The initialization voltage line VIN is disposed in the display area DA to provide an initialization voltage to the pixel PX. Although not shown, a plurality of initialization voltage lines VIN may be provided to provide an initialization voltage to each of the plurality of pixels.

The driving signal line CL and the initialization voltage line VIN may be disposed on the same layer and simultaneously formed through the same process. However, this is only an example, and the driving signal line CL and the initialization voltage line VIN may be formed independently through a separate process, and are not limited to any one embodiment.

The dam parts DM1 and DM2 are arranged in the peripheral area NDA. In the dams DM1 and DM2, when the organic layer OL of the encapsulation layer TFE is formed, the organic layer OL is directed from the display area DA toward the outside of the dams DM1 and DM2, for example, FIG. 3B. Flows in the direction opposite to the second direction DR2. The dam units DM1 and DM2 may be disposed adjacent to at least one side of the display area DA. The dams DM1 and DM2 may surround the display area DA on a plane. The dam units DM1 and DM2 may be provided in plural and include the first dam unit DM1 and the second dam unit DM2.

The first dam portion DM1 may be disposed closer to the display area DA than the second dam portion DM2. The first dam unit DM1 may be disposed to overlap the power supply line E-VSS in plan view. In the present embodiment, the connection electrode E-CNT may pass between the first dam portion DM1 and the power supply line E-VSS in cross section.

In the present embodiment, the first dam portion DM1 includes the same material as the fourth insulating layer 40 and may be formed simultaneously with the fourth insulating layer 40 through one mask. Accordingly, a separate process for forming the first dam portion DM1 may not be added, thereby reducing process cost and simplifying the process.

The second dam portion DM2 may be disposed on the outer side relative to the first dam portion DM1. The second dam unit DM2 may be disposed at a position covering a portion of the power supply line E-VSS. In the present embodiment, the second dam portion DM2 may have a multilayer structure including a first layer DM2-L1 and a second layer DM2-L2. For example, the first layer DM2-L1 may be formed simultaneously with the third insulating layer 30, and the second layer DM2-L2 may be formed simultaneously with the fourth insulating layer 40. Accordingly, the second dam portion DM2 may be easily formed without adding a separate process.

In the present exemplary embodiment, the connection electrode E-CNT may be partially overlapped on the first layer DM2-L1 of the second dam portion DM2. An end of the connection electrode E-CNT may be inserted between the first layer DM2-L1 and the second layer DM2-L2. However, this is only an example, and the connection electrode E-CNT may not extend to the second dam portion DM2 and is not limited to any one embodiment.

The first inorganic layer IOL1 and the second inorganic layer IOL2 may extend from the display area DA to the outer side of the second dam portion DM2. The first inorganic layer IOL1 and the second inorganic layer IOL2 cover the first dam portion DM1 and the second dam portion DM2. The organic layer OL may be disposed inside the second dam portion DM2. However, this is illustrated by way of example, and a portion of the organic layer OL may be formed to extend to a region overlapping with the first dam portion DM1, but is not limited to any one embodiment.

4 is a plan view illustrating the region XX ′ illustrated in FIG. 2A. In FIG. 4, an area including the hole area PA is enlarged. Hereinafter, with reference to FIG. 4, this invention is demonstrated.

As shown in FIG. 4, the module hole MH is formed in the hole area PA. The hole area PA may be surrounded on the plane by the display area DA. Accordingly, the pixels PX may be arranged along the periphery of the hole area PA. The hole area PA may include a margin area MA, a wiring area LA, and a compensation area BA. In FIG. 4, the boundaries of each region are illustrated by dotted lines for easy description.

The margin area MA may be an area left without being removed while the module hole MH is formed. The margin area MA may be an area where signal lines or electronic devices are not disposed. Although not shown, grooves formed by recessing at least a portion of the insulating substrate BS (see FIG. 2B) may be disposed in the margin area MA. The display panel 100 may further include a groove to block a penetration path through which moisture or air penetrated through the module hole MH toward the display area DA.

The margin area MA may be adjacent to the module hole MH. The margin area MA may surround the module hole MH on a plane. The size or shape of the margin area MA may vary depending on the size of the module hole MH or the position of the module hole MH. On the other hand, this is shown by way of example, in the display panel according to an embodiment of the present invention, the margin area (MA) may be omitted.

The wiring area LA is adjacent to the margin area MA. The wiring area LA may surround the module hole MH. In the present embodiment, the wiring area LA may have a concentric circle shape. However, this is only an example, and the wiring area LA may have various shapes as long as it surrounds the module hole MH, and is not limited to any one embodiment.

The wiring area LA may be an area in which a plurality of signal wires SSL (hereinafter referred to as sub signal wires) are disposed. The sub signal lines SSL may extend along the edge of the module hole MH. Each of the sub signal lines SSL may have a closed line shape surrounding the module hole MH. In the present embodiment, each of the sub signal lines SSL has a circular shape.

The sub signal lines SSL may be arranged to be spaced apart from each other in the wiring area LA. The sub signal lines SSL may transmit signals independent of each other. The sub-signal wires SSL may include, for example, at least one of a wire for transmitting a gate signal, a wire for transmitting a data signal, a wire for transmitting an initialization voltage, a wire for transmitting a light emission control signal, and a wire for transmitting a power supply voltage. It may include any one.

The sub signal wires SSL may include n wires sequentially spaced apart from the module hole MH. The n wires may be wires that transmit electrical signals provided to pixels arranged in rows and columns occupied by the module hole MH. The sub signal lines SSL may be electrically connected to main signal lines connected to the pixels disposed adjacent to the module hole HM.

The sub-signal wires SSL are shown in FIG. 4 for ease of description, and the sub-signal wires SSL are disposed in the first sub-signal wire SSL1 disposed closest to the module hole MH, and the first sub-signal wires. The second sub-signal wire SSL2 surrounding SSL1 and the n-th sub-signal wire SSLn disposed farthest from the module hole MH are illustrated.

Each of the sub signal wires SSL may be electrically connected to a corresponding main signal wire among the main signal wires connected to the pixels. In detail, the sub signal lines SSL may be connected to main signal lines connected to the pixels PX to transmit electrical signals to the corresponding pixels.

The main signal wires are disposed in the display area DA and are connected to corresponding ones of the pixels PX. 4 shows a first main signal line SL11, a second main signal line SL12, a third main signal line SL21, and a fourth main signal line SL22 among the main signal wires. Illustrated illustratively.

The first main signal line SL11 may be a data line for providing a data signal to the first pixel PX-A1, and the second main signal line SL12 may provide a data signal to the second pixel PX-A2. It may be a providing data line. The third main signal line SL21 may be a gate line for providing a gate signal to the third pixel PX-B1, and the fourth main signal line SL22 may provide a gate signal to the fourth pixel PX-B2. It may be a gate line to provide. In the present exemplary embodiment, the first pixel PX-A1 and the second pixel PX-A2 may be pixels spaced apart from each other with the hole area PA therebetween and disposed in the same column. The third pixel PX-B1 and the fourth pixel PX-B2 may be pixels spaced apart from each other with the hole area PA therebetween and disposed in the same row.

Although not shown, the main signal wires may further include an emission control line for transmitting the emission control signal to the pixel and an initialization voltage line for providing the initialization voltage to the pixel. The main signal wires may include various embodiments as long as they are connected to each of the pixels PX disposed in the display area DA to provide an electrical signal for controlling the pixels PX. It is not limited to.

In this embodiment, the connection between the main signal wires SL11, SL12, SL21, SL22 and the sub signal wires SSL is shown by a dotted line. The first main signal wire SL11 and the second main signal wire SL12 are connected to the first sub signal wire SSL1, and the third main signal wire SL21 and the fourth main signal wire SL22 are the nth sub wire. It may be connected to the signal line SSLn. Accordingly, the first main signal wire SL11 and the second main signal wire SL12 transmit substantially the same electrical signals, and the third main signal wire SL21 and the fourth main signal wire SL22 are substantially the same. Carries the same electrical signal.

In this embodiment, the main signal wires and the sub signal wires connected to each other may be disposed on the same layer. In addition, the main signal wiring and the sub signal wiring connected to each other may be formed in an integral shape.

According to the present invention, the first main signal wire SL11 and the second main signal wire SL12 are connected to each other through one first sub-signal wire SSL1, and thus spaced apart from each other with the module hole MH interposed therebetween. Thus, the common electrical signals may be provided to the first and second pixels PX-A1 and PX-A2 constituting the same column. Similarly, the third main signal wire SL21 and the fourth main signal wire SL22 are connected through one n-th sub-signal wire SSLn to be spaced apart from each other with the module hole MH interposed therebetween. Electrical signals common to the third and fourth pixels PX-B1 and PX-B2 may be provided. Accordingly, the plurality of pixels PX spaced apart from each other via the module hole MH may be stably provided with an electrical signal without disconnection of the signal line.

The compensation area BA is adjacent to the wiring area LA. The compensation area BA may be defined between the wiring area LA and the display area DA on a plane. The compensation area BA may be an area displaying black according to an electrical signal.

For example, the compensation area BA may be an area that implements the color of black by blocking incident light. Alternatively, for example, the compensation area BA may be an area for generating and displaying light having a low gray level that can be substantially seen as a black color.

As described above, since the wiring area LA is a region where the plurality of sub-signal wires SSL are concentrated, the wiring area LA is visually recognized as a black color from the outside. The compensation area BA may be viewed as an area having continuity from the wiring area LA by implementing a color of black.

According to the present invention, by further comprising a compensation area BA displaying black in the area adjacent to the module hole MH, spots or the like that may be generated in the area adjacent to the module hole MH are not recognized from the outside. You can do that.

In addition, according to the present invention, by further comprising a compensation area BA disposed between the wiring area LA and the display area DA, the sub-signal wires SSL which are densely arranged in the wiring area LA may be pixels. It is possible to prevent the electrical influence on the PX). Accordingly, the image distortion phenomenon around the module hole MH can be prevented and the display quality in the entire area of the display area DA can be maintained uniformly.

5A is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention. FIG. 5B is a schematic cross-sectional view of a portion of FIG. 5A. For ease of explanation, FIG. 5A illustrates regions corresponding to some regions of the region illustrated in FIG. 4. Hereinafter, the present invention will be described with reference to FIGS. 5A and 5B. In the meantime, the same reference numerals are given to the same components as those described with reference to FIGS. 1 to 4, and redundant descriptions thereof will be omitted.

The display panel 100 -A illustrated in FIGS. 5A and 5B includes a hole area PA10. The hole area PA10 may correspond to that in which the margin area MA is omitted from the hole area PA shown in FIG. 4. Accordingly, the hole area PA10 includes the wiring area LA and the compensation area BA, and in the hole area PA10, the wiring area LA may be directly defined adjacent to the module hole MH. have.

FIG. 5B exemplarily illustrates a cross-sectional view of a region in which the module hole MH is defined. As illustrated in FIG. 5B, the module hole MH may be formed through the display panel 100 -A. Accordingly, the insulating substrate BS, the base layer BL, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 are formed in the module hole. The edge MH-E defining the inner surface of the MH can be configured.

The display panel 100 -A according to the exemplary embodiment of the present invention may include the metal pattern MP disposed in the compensation area BA. The metal pattern MP may be disposed spaced apart from the sub signal lines SSL and the pixels PX in a plane.

The metal pattern MP covers at least a portion of the compensation area BA. The metal pattern MP may cover most of the compensation area BA. For example, the metal pattern MP may have a concentric shape that is substantially the same shape as the compensation area BA.

The metal pattern MP may include an optically opaque material. The metal pattern MP shields incident light. Accordingly, the compensation area BA may be visually recognized as a black color from the outside.

5B illustrates a first sub-signal wire SSL1A (hereinafter referred to as a first sub-signal wire) connected to a data line among the sub-signal wires SSL and an n-th sub-signal wire SSLnA connected to a gate line. 2 sub-signal wirings) are exemplarily illustrated. In the present exemplary embodiment, the first sub signal line SSL1A and the second sub signal line SSLnA may be disposed on different layers. For example, the first sub-signal wire SSL1A is disposed between the second insulating layer 20 and the third insulating layer 30, so that the input electrode IE and the output electrode OE of the pixel transistor TR-P are disposed. ) May be disposed on the same layer. The second sub signal line SSLnA may be disposed between the first insulating layer 10 and the second insulating layer 20 and disposed on the same layer as the control electrode CE of the pixel transistor TR-P. .

Meanwhile, in the present exemplary embodiment, the display panel 100 -A may further include a fifth insulating layer 50 disposed between the second insulating layer 20 and the third insulating layer 30. Accordingly, the light emitting device ELD may pass through the third insulating layer 30 and the fifth insulating layer 50 to be connected to the pixel transistor TR-P. In addition, the first sub-signal wire SSL1A may be disposed between the second insulating layer 20 and the fifth insulating layer 50.

The metal pattern MP may be disposed on a different layer from the first sub signal line SSL1A and the second sub signal line SSLnA. For example, the metal pattern MP may be disposed between the fifth insulating layer 50 and the third insulating layer 30.

In the present exemplary embodiment, the main signal lines DRL and SCL may extend from the display area DA to be connected to the sub signal lines SSL. The first sub signal line SSL1A and the second sub signal line SSLnA may be integrally formed with the main signal lines DRL and SCL. The main signal lines DRL and SCL electrically connect the wiring area LA and the display area DA through the compensation area BA. Accordingly, the metal pattern MP may overlap the main signal lines DRL and SCL in plan view.

According to the present invention, the metal pattern MP is disposed on a different layer from the first sub signal wire SSL1A and the second sub signal wire SSLnA, and thus, the first sub signal wire SSL1A and the second sub signal wire. It may be electrically insulated from the main signal lines DRL and SCL connected to the SSL2A. Accordingly, even when the metal pattern MP is disposed in the compensation area BA, the metal pattern MP is not electrically connected to the main signal lines DRL and SCL, thereby providing a stable electrical connection between the wiring area LA and the display area DA. I can keep it.

The metal pattern MP may be in an electrically floating state. That is, the metal pattern MP may be a pattern of concentric circles surrounding the module hole MH.

Alternatively, the metal pattern MP may receive a predetermined electrical signal. For example, the metal pattern MP may be connected to a DC line providing a power supply voltage or an initialization voltage, or may be connected to an AC line providing a data voltage or a gate voltage. For example, the metal pattern MP may be connected to a power line not shown to receive a ground voltage.

Alternatively, the metal pattern MP may be connected to a gate line or a data line provided to a pixel closest to the metal pattern MP among the pixels PX. In this case, the metal pattern MP may include a plurality of metal patterns arranged to be spaced apart from each other by the number of adjacent pixels. Accordingly, the pixels disposed closest to the metal pattern MP may not be affected by signals other than the signal lines connected to the pixels.

According to the present invention, the metal pattern MP is maintained at a predetermined voltage, thereby electrically shielding between the wiring area LA and the display area DA. Accordingly, the problem in which the sub-signal wires SSL disposed in the wiring area LA are electrically coupled to adjacent pixels can be solved, so that stable driving of the pixels arranged around the module hole MH can be easily performed. Can be done.

6A is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention. FIG. 6B is a schematic cross-sectional view of a portion of FIG. 6A. For ease of explanation, FIG. 6A shows a region corresponding to FIG. 5A and FIG. 6B shows a region corresponding to FIG. 5B. Hereinafter, the present invention will be described with reference to FIGS. 6A and 6B. In the meantime, the same reference numerals are given to the same components as those described with reference to FIGS. 1 to 5B, and redundant descriptions thereof will be omitted.

The display panel 100 -B according to the present invention includes a hole area PA10 in which the module hole MH is disposed and a display area DA surrounding the hole area PA10. The main signal wires DRL11, DRL12, and SCL10 may extend from the display area DA and be connected to the sub signal wires SSL10 across the compensation area BA.

6A illustrates a first main signal line DRL11 (hereinafter referred to as a first data line) and a second main signal line connected to a first sub signal line SSL1B (hereinafter referred to as a first sub signal line) among the main signal wires for easy description. A third main signal line SCL10 (hereinafter referred to as a gate line) connected to the DRL12 (hereinafter referred to as a second data line) and the second sub signal line SSLnB (hereinafter referred to as a second sub signal line) is illustrated.

In the present invention, the sub signal lines SSL10 may be disposed on a different layer from the main signal lines DRL11, DRL12, and SCL10. Accordingly, the first sub signal line SSL1B may be disposed on a different layer from the input electrode IE and the output electrode OE of the pixel transistor TR-P disposed in the display area DA. The second sub signal line SSLnB may be disposed on a layer different from the control electrode CE of the pixel transistor TR-P disposed in the display area DA.

Accordingly, the display panel 100 -B may further include contact parts CTP1 and CTP2 disposed in the hole area PA10. The first contact portion CTP1 of the contact portions CTP1 and CTP2 connects the first sub signal wire SSL1B and the data lines DRL11 and DRL12, and the second contact portion CTP2 connects the second sub signal wire. The SSLnB is connected to the gate line SCL10. Although not shown, the first contact portion CTP1 connects the data lines DRL11 and DRL12 and the first sub signal line SSL1B through the fifth insulating layer 50, and the second contact portion CTP2. The gate line SCL10 and the second sub signal line SSLnB may be connected to each other through the second insulating layer 20 and the fifth insulating layer 50. According to the present invention, by further including the contact portions CTP1 and CTP2, the sub signal lines SSL10 may be simultaneously formed on the same layer, thereby simplifying the process.

Meanwhile, in the present embodiment, the metal pattern MP may be disposed on the same layer as the sub signal lines SSL10. The metal pattern MP may be spaced apart from the sub signal lines SSL10 in a plane and electrically insulated from the sub signal lines SSL10. Since the main signal wires DRL11, DRL12, and SCL10 are connected to the sub signal wires SSL10 through the contact parts CP1 and CTP2, the main signal wires DRL11, DRL12, and SCL10 may overlap the metal pattern MP on the plane even after passing through the compensation area BA. It does not come in contact with the metal pattern MP. Accordingly, regardless of the area occupied by the metal pattern MP in the compensation area BA, the wiring area LA and the display area DA may be stably connected through the contact parts CTP10.

7A is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention. 7B to 7D are cross-sectional views briefly illustrating some regions of FIG. 7A. For ease of explanation, FIG. 7A shows a region corresponding to FIG. 5A, and FIGS. 7B to 7D show a region corresponding to FIG. 5B. Hereinafter, the present invention will be described with reference to FIGS. 7A to 7D. In the meantime, the same reference numerals are given to the same components as those described with reference to FIGS. 1 to 6B, and redundant descriptions thereof will be omitted.

As shown in FIG. 7A, in the display panel 100 -C according to an exemplary embodiment, the metal pattern MP-1 may extend to the wiring area LA30. The metal pattern MP-1 may be provided in an area and a shape overlapping the compensation area BA30 and the wiring area LA30 at the same time. The metal pattern MP-1 may be disposed to overlap the sub signal lines SSL on a plane.

As shown in FIG. 7B, in the display panel 100-C1, the metal pattern MP-11 is disposed on a layer different from the sub signal lines SSL. The sub signal lines SSL may be disposed below the fifth insulating layer 50 and the metal pattern MP-1 may be disposed above the fifth insulating layer 50. The sub-signal wires SSL and the metal pattern MP-11 spaced apart from each other with the insulating layer 50 interposed therebetween may be electrically insulated even when overlapped on a plane.

Alternatively, as shown in FIG. 7C, in the display panel 100-C2, the metal pattern MP-12 may be disposed on the encapsulation layer TFE. The metal pattern MP-2 is disposed on the second inorganic layer IOL2 and overlaps the compensation area BA30 and the wiring area LA30. The sub-signal wires SSL and the metal pattern MP-12 spaced apart from each other with the plurality of insulating layers 30, 40, 50 and the encapsulation layer TFE therebetween may be electrically insulated even when overlapped on a plane. .

Alternatively, as shown in FIG. 7D, in the display panel 100-C3, the metal pattern MP-13 may further include the metal pattern MP3 disposed in the wiring area LA30. That is, the metal pattern MP-3 may include a metal pattern MP31 (hereinafter referred to as a first pattern) disposed in the compensation area BA30 and a metal pattern MP32 (hereinafter referred to as a second pattern) arranged in the wiring area LA30. Can be. The first pattern MP31 is illustrated as being disposed at a position corresponding to the metal pattern MP illustrated in FIG. 6B.

The second pattern MP32 is disposed in the wiring area LA30. The second pattern MP32 may be spaced apart from the sub wires SSL on a plane. In detail, the sub-wires SSL may be non-overlapping on the plane. In the present exemplary embodiment, the second pattern MP32 is illustrated as being disposed on the fifth insulating layer 50, which is the same layer as the first pattern MP31, but the second pattern MP32 is formed of the sub-wires SSL. It may be disposed on the same layer as either one, but is not limited to any one embodiment.

The second pattern MP32 may be provided in plural so as to be disposed in each of the spaces between the sub-wires SSL. The second pattern MP32 and the sub wirings SSL may reduce the empty space in the wiring area LA, so that the entire wiring area LA may have even light shielding properties.

7A to 7D, the arrangement regions of the metal patterns MP-1, MP-11, MP-12, and MP-13 extend from the compensation region BA30 to the wiring region LA30, thereby providing a wiring region ( Substantially the same light blocking area may be formed in LA30 and the compensation area BA30. The metal patterns MP-1, MP-11, MP-12, and MP-13 are disposed in both the wiring area LA30 and the compensation area BA30, so that the compensation area BA30 and the wiring area LA30 are equal to each other. It can be recognized in black. Accordingly, the poor visibility in the wiring area LA30 due to the external light reflection of the sub-signal wires SSL may cause the metal patterns MP-1, MP-11, MP-12, and MP-13 to have the sub-signal wires ( Can be resolved by covering SSL). Further, by providing one metal pattern MP-1, MP-11, MP-12, and MP-13 in the compensation area BA30 and the wiring area LA30, the compensation area BA30 and the wiring area LA30 are provided. It is possible to design such that the black color represented by is substantially the same. Accordingly, uniform light blocking may be achieved in the hole area PA30.

8 is a plan view illustrating a portion of a display panel according to an exemplary embodiment of the present invention. 9A through 9G are cross-sectional views illustrating some regions of the display panel according to the exemplary embodiment. 9A to 9G illustrate regions corresponding to the compensation region BA40. Hereinafter, the present invention will be described with reference to FIGS. 8 to 9G. In the meantime, the same reference numerals are given to the same components as those described with reference to FIGS. 1 to 7D, and redundant descriptions thereof will be omitted.

As illustrated in FIG. 8, the display panel 100 -D includes a hole area PA40 including a compensation area BA40, a wiring area LA40, and a margin area MA. In this case, the display panel 100 -D may further include a plurality of compensation pixels PX-S disposed in the hole area PA40. The compensation pixels PX-S may be arranged in the compensation area BA40. The arrangement of the compensation pixels PX-S may be continuous with the arrangement of the pixels PX disposed in the display area DA. Each of the compensation pixels PX-S may display a black color. Each of the compensation pixels PX-S is exemplarily illustrated in each of FIGS. 9A to 9D.

As illustrated in FIG. 9A, the display panel 100-D1 may include a compensation pixel PX-S1 disposed in the compensation area BA40. The compensation pixel PX-S1 includes a first electrode E1 -S, a second electrode E2-S1, and a light emitting layer EL-S. The compensation pixels PX-S1 may have the same structure as the light emitting device ELD (see FIG. 3B) disposed in the display area DA. The first electrode E1-S, the light emitting layer EL-S, and the second electrode E2-S are the first electrode E1 and the light emitting layer EL of the light emitting element ELD disposed in the display area DA. ) And the second electrode E2 may be simultaneously formed in the same process. Accordingly, the compensation pixel PX-S1 may be formed without additional process, and thus the process may be simplified and the process cost may be reduced.

According to the present invention, the compensation pixel PX-S1 may have a structure including only a part of the configuration of the pixel PX (see FIG. 3B) disposed in the display area DA (see FIG. 3B). For example, the compensation pixels PX-S1 may correspond to the floating light emitting devices. In detail, the compensation pixel PX-S1 includes a first electrode E1-S, a second electrode E2-S, and a light emitting layer EL-S, wherein the first electrodes E1-S are thin films. It may be provided in a floating state without being connected to the transistor TR (see FIG. 3B).

That is, unlike the pixel PX of the display area DA, the compensation pixels PX-S1 may not be connected to the main signal line or the sub signal line. The first electrodes E1 -S of the compensation pixels PX-S1 are not connected to the thin film transistor or separate signal wires, and thus do not receive a separate electrical signal. Accordingly, the compensation pixels PX-S1 may be areas that do not generate light, and thus may be substantially visible in black color. However, this is exemplarily illustrated, and the compensation pixels PX-S1 according to the exemplary embodiment of the present invention may have a structure in which a light emitting element is omitted from the pixel PX and includes only a pixel transistor or a capacitor. It is not limited to one embodiment.

Alternatively, as illustrated in FIG. 9B, in the display panel 100-D2, the compensation pixels PX-S2 are formed of the emission layer EL among the pixels PX disposed in the display area DA. ) May be omitted. Accordingly, the compensation pixel PX-S2 may include the thin film transistor TR-S, the first electrodes E1 -S, and the second electrodes E2 -S. The thin film transistor TR-S includes a semiconductor pattern SL-S, a control electrode CE-S, an input electrode IE-S, and an output electrode OE-S. The thin film transistor TR-S may have a structure corresponding to the pixel transistor TR-P disposed in the display area DA.

The second electrodes E2-S may be directly disposed on the first electrodes E1-S. Due to the omission of the light emitting layer EL, which may be activated and emitted by the voltage difference, the compensation pixels PX-S2 may not generate light. Accordingly, the compensation pixels PX-S2 may be visually recognized as black color.

Alternatively, as illustrated in FIG. 9C, in the display panel 100-D3, the compensation pixel PX-S3 may include the first electrode E1 among the configurations of the pixel PX disposed in the display area DA. It may have a structure omitted. Accordingly, the compensation pixel PX-S3 may include the thin film transistor TR-S, the emission layer EL-S, and the second electrode E2-S. Since one of the two electrodes disposed between the light emitting layers EL-S, which may generate a voltage difference, is omitted, a voltage for emitting the light emitting layers EL-S is applied to the light emitting layers EL-S. It doesn't work. Accordingly, the compensation pixels PX-S3 may be visually recognized as black color. Although not illustrated, the compensation pixels PX-S3 may have a structure in which the second electrode E2 is omitted in the configuration of the pixel PX, and the compensation pixels PX-S3 are not limited to any one embodiment.

Alternatively, as shown in FIG. 9D, the display panel 100-D4 may include the compensation pixels PX-S4 disposed in the compensation area BA40. The compensation pixel PX-S4 may include a thin film transistor TR-S and a light emitting device ELD-S. The light emitting device ELD-S includes a first electrode E1-S, a second electrode E2-S, and a light emitting layer EL-S.

The compensation pixels PX-S4 may have a structure corresponding to the pixels PX disposed in the display area DA. Accordingly, the thin film transistor TR-S has a structure corresponding to the pixel transistor TR-P disposed in the display area DA, and the light emitting device ELD-S emits light that is disposed in the display area DA. It may have a structure corresponding to the device ELD. Therefore, the compensation pixels PX-S4 may be formed in the same process as the pixels PX disposed in the display area DA. Accordingly, the process can be simplified and the process cost can be reduced.

The compensation pixels PX-S4 may display light having a low gradation color. The light of red gradation color can be visually recognized as black color by the user. Accordingly, when the image IM (see FIG. 1) is displayed in the display area DA, a black image may be displayed in the hole area PA30.

Alternatively, as shown in FIG. 9E, the display panel 100-D5 may include a compensation pixel PX-S5 including the compensation light emitting device ELD-S1. The compensation pixel PX-S5 includes the thin film transistor TR-S and the compensation light emitting device ELD-S1. The thin film transistor TR-S corresponds to the thin film transistor TR-S shown in FIG. 9D.

The compensation light emitting device ELD-S1 may have a different shape than the light emitting device ELD-S shown in FIG. 9D in the first electrodes E1-S1. In detail, the first electrodes E1-S1 have a smaller area than the first electrodes E1-S shown in FIG. 9D, and may be provided to overlap the emission layer EL-S on a plane.

Accordingly, the compensation light emitting device ELD-S1 includes the first electrode E1-S1 connected to the thin film transistor TR-S and the light emitting layer EL-S provided in the opening OP, while the light emitting layer EL- The light does not emit due to the non-overlapping structure between S) and the first electrodes E1-S1. Therefore, the compensation area BA-40 may be displayed in substantially black color due to the compensation pixel PX-S5 including the compensation light emitting device ELD-S1.

According to the present invention, by using an existing process, for example, the process of forming the light emitting device ELD of the display area DA, the area of the first electrodes E1-S1 disposed in the compensation area BA40 is changed. The compensation pixels PX-S5 may be formed. Thus, process design can be simplified and process costs can be reduced.

Alternatively, as shown in FIG. 9F, in the display panel 100-D6, an opening OP (see FIG. 3B) corresponding to the compensation pixel PX-S6 may be omitted in the fourth insulating layer 40. have. The display panel 100-C5 may include a compensation pixel PX-S6 including the thin film transistor TR-S and the first electrodes E1 -S. In this case, since the fourth insulating layer 40 does not provide the opening OP in the compensation area BA40, the first electrode E1 -S and the second electrode E2 -S are the compensation pixel illustrated in FIG. 9B. Unlike in PX-S2, the fourth insulating layer 40 may be spaced apart from each other.

Alternatively, as illustrated in FIG. 9G, the display panel 100-D7 has a structure in which the light emitting device ELD (see FIG. 3B) is omitted among the pixels PX disposed in the display area DA (see FIG. 3B). It may include a compensation pixel (PX-S7) having a. The compensation pixels PX-S7 may have a structure including only the thin film transistor TR.

According to the present invention, the hole area PA40, specifically, the compensation area BA40 may display a black color regardless of the image displayed on the display area DA. The compensation area BA40 is viewed or compensated as a black color area through the compensation pixels PX-S1, PX-S2, PX-S3, PX-S5, PX-S6, and PX-S7 that do not generate light. Through the pixels PX-S4, light having a low gray level that can be intentionally recognized as a black color can be generated and displayed. As a result, it is possible to prevent a problem that stains or the like appearing in the hole area PA40 are visually recognized. In addition, the process may be simplified by forming the compensation area BA40 having a configuration corresponding to at least one of the configurations of the display area DA.

10A is an exploded perspective view illustrating an electronic device according to an embodiment of the present invention. FIG. 10B is a plan view briefly illustrating a region YY ′ illustrated in FIG. 10A. Hereinafter, the present invention will be described with reference to FIGS. 10A and 10B. In the meantime, the same reference numerals are given to the same components as those described with reference to FIGS. 1 to 9F, and redundant descriptions thereof will be omitted.

As shown in FIG. 10A, the electronic device EA-1 includes a display panel 100-1, a window member 200, a plurality of electronic modules 310 and 320, and a storage member 400. . Since the window member 200 and the accommodating member 400 correspond to the window member 200 and the accommodating member 400 illustrated in FIG. 1, overlapping description thereof will be omitted.

The electronic modules 310 and 320 may be any one of the modules configuring the first electronic module EM1 (see FIG. 2B) and the second electronic module EM2 (see FIG. 2B) illustrated in FIG. 2B. For example, each of the electronic modules 310 and 320 may be a camera, a speaker, or a sensing sensor such as light or heat. The electronic modules 310 and 320 may include a first electronic module 310 and a second electronic module 320. The first electronic module 310 and the second electronic module 320 may be the same or different from each other.

The display panel 100-1 may include a plurality of module holes MH1 and MH2. The module holes MH1 and MH2 may correspond to the electronic modules 310 and 320, respectively. The module holes MH1 and MH2 may include a first module hole MH1 overlapping the first electronic module 310 and a second module hole MH2 overlapping the second electronic module 320.

The display panel 100-1 may provide hole regions PA1 and PA2 corresponding to each of the module holes MH1 and MH2. The hole areas PA1 and PA2 include a first hole area PA1 in which the first module hole MH1 is formed and a second hole area PA2 in which the second module hole MH2 is formed.

Referring to FIG. 9B, the display area DA may surround the first hole area PA1 and the second hole area PA2. The first hole area PA1 and the second hole area PA2 are spaced apart from each other on a plane. The first hole area PA1 and the second hole area PA2 include the wiring areas LA1 and LA2 and the compensation areas BA1 and BA2. In the present exemplary embodiment, the wirings disposed in the wiring areas LA1 and LA2 and the pixels disposed in the display area DA are omitted.

The compensation area BA1 of the first hole area PA1 and the compensation area BA2 of the second hole area PA2 may each display black. The compensation area BA1 of the first hole area PA1 and the compensation area BA2 of the second hole area PA2 may be viewed as black color areas or may display black color light.

The compensation area BA1 of the first hole area PA1 and the compensation area BA2 of the second hole area PA2 are formed to be spaced apart from each other. A portion of the display area DA may be positioned between the first hole area PA1 and the second hole area PA2. Accordingly, at least one pixel displaying the image IM may be disposed between the first hole area PA1 and the second hole area PA2.

According to the present invention, by providing the compensation areas BA1 and BA2 adjacent to each of the module holes MH1 and MH2, it is possible to prevent defects such as spots generated near the module holes MH1 and MH2 from being recognized. Can be. In addition, defects such as distortion of an image in an area adjacent to the module holes MH1 and MH2 may be prevented by electrical interaction between the wiring areas LA1 and LA2 and the display area DA. .

11A is an exploded perspective view illustrating an electronic device according to an embodiment of the present invention. FIG. 11B is a plan view briefly illustrating some regions illustrated in FIG. 11A. Hereinafter, the present invention will be described with reference to FIGS. 11A and 11B. In the meantime, the same reference numerals are assigned to the same components as those described with reference to FIGS. 1 to 10B, and redundant descriptions thereof will be omitted.

As illustrated in FIG. 11A, the electronic device EA-2 includes a display panel 100-2, a window member 200, a plurality of electronic modules 310 and 320, and a storage member 400. . The window member 200, the plurality of electronic modules 310 and 320, and the accommodating member 400 may include the window member 200, the plurality of electronic modules 310 and 320, and the accommodating member illustrated in FIG. 10A. 400). Duplicate descriptions will be omitted below.

The display panel 100-2 includes a first module hole MH1 and a second module hole MH2 corresponding to the electronic modules 310 and 320, respectively, and the first module hole MH1 and the second module. The hole MH2 may include the hole area PA-2 in which the hole MH2 is formed. That is, in the present invention, the plurality of module holes MH1 and MH2 may be formed in one hole area PA-2.

11B briefly illustrates the hole area PA-2. Referring to FIG. 10B, the hole area PA-2 may include a first wiring area LA1, a second wiring area LA2, and a compensation area BA-2. The first wiring region LA1 may surround the first module hole MH1 adjacent to the first module hole MH1. In the first wiring area LA1, a plurality of sub-signal wires, which are not shown, may surround the first module hole MH1.

The second wiring area LA2 may surround the second module hole MH2 adjacent to the second module hole MH2. The second wiring area LA2 may be defined to be spaced apart from the first wiring area LA1 in a plane. In the second wiring area LA2, a plurality of sub-signal wires, which are not shown, may surround the second module hole MH2. Duplicate description thereof will be omitted.

The compensation area BA-2 may be adjacent to the first wiring area LA1 and the second wiring area LA2. The compensation area BA-2 may surround each of the first wiring area LA1 and the second wiring area LA2. Accordingly, the first module hole MH1 and the second module hole MH2 may be adjacent to the single compensation area BA-2 simultaneously. The compensation area BA-2 may be viewed as areas having black color, or may display black color light.

According to the present invention, by providing a single compensation area BA-2 with respect to the plurality of module holes MH1 and MH2, the compensation area BA-2 having a shape different from that of the module holes MH1 and MH2 can be easily provided. Can be formed. In addition, the compensation area BA-2 having a constant size can be formed regardless of the number of the module holes MH1 and MH2, so that even if the number of the module holes MH1 and MH2 changes, the design of the display area DA can be improved. It can be made easily and stably.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art without departing from the spirit and scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope thereof.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

EA: Electronic Device MH: Module Hole
PA: Hall area LA: Wiring area
BA: Compensation Area

Claims (24)

An insulating substrate including at least one hole defined therein and including a hole area in which the hole is defined, a display area surrounding the hole area, and a peripheral area adjacent to the display area;
A plurality of pixels disposed in the display area;
Main signal wires disposed in the display area and electrically connected to the pixels; And
Sub-signal wires disposed in the hole area and electrically connected to the pixels;
The hole area is,
A wiring area surrounding the hole and in which the sub signal wires are arranged; And
And a compensation area disposed between the wiring area and the display area on a plane and displaying a black color. According to claim 1,
And a metal pattern disposed in the compensation area and spaced apart from the pixels in a plane and optically intransparent. The method of claim 2,
The metal pattern is a floating electrode. The method of claim 2,
The metal pattern has a ground voltage. The method of claim 2,
The metal pattern has the same voltage as the sub signal lines. The method of claim 2,
And the metal pattern is disposed on the same layer as the sub signal lines. The method of claim 6,
And the sub signal lines and the main signal lines are on different layers. The method of claim 2,
And the metal pattern is disposed on a layer different from the sub signal lines. The method of claim 8,
At least one of the sub signal wires is disposed on the same layer as at least one of the main signal wires. The method of claim 8,
The metal pattern extends to the wiring region;
The metal pattern overlaps the sub signal lines on a plane. The method of claim 2,
A sealing layer covering the pixels;
The metal pattern is disposed on the encapsulation layer. According to claim 1,
And a plurality of light emitting elements disposed in the compensation area and spaced apart from each other in a plane from the pixels. The method of claim 12,
Each of the light emitting elements is electrically connected to at least one of the main signal wires and the sub signal wires.
Each of the light emitting elements displays light of black color. The method of claim 12,
And each of the light emitting elements is electrically insulated from the main signal lines and the sub signal lines. According to claim 1,
The insulating substrate includes a plurality of holes spaced apart from each other,
The hole area is provided as a plurality of areas overlapping each of the holes and spaced apart from each other,
Each of the compensation regions of the hole regions is disposed along an edge of each of the holes. According to claim 1,
The insulating substrate includes a plurality of holes spaced apart from each other,
The hole area is provided as one area overlapping all of the holes,
The holes are surrounded by one compensation area. A display panel including a hole area displaying black and a display area surrounding the hole area and displaying an image according to an electrical signal, the display panel including a through hole defined in the hole area; And
An electronic module disposed under the display panel and overlapping the hole area;
The hole region includes a wiring region surrounding the through hole, a compensation region surrounding the wiring region and disposed between the wiring region and the display region,
The display panel,
A plurality of pixels disposed in the display area;
A plurality of main signal wires disposed in the display area and connected to the pixels;
A plurality of sub signal wires disposed in the wiring area and connected to the main signal wires; And
And a compensation element disposed in the compensation area and displaying a black color. The method of claim 17,
The compensation element covers the compensation area and includes a metal pattern spaced apart from the pixels in a plane.
The metal pattern is an optically opaque electronic device. The method of claim 18,
And the metal pattern overlaps at least one of the main signal wires and the sub signal wires in plan view. The method of claim 17,
Each of the pixels includes a thin film transistor and a light emitting device connected to the thin film transistor,
And the compensation element has a structure in which at least one of the components of the thin film transistor and the light emitting element is omitted. The method of claim 17,
The compensation element includes a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode,
And the first electrode is electrically insulated from the main signal wires and the sub signal wires. The method of claim 21,
The first electrode is a floating pattern. The method of claim 17,
The compensation element has the same structure as at least one of the pixels,
The compensation device is an electronic device for generating light of black color. The method of claim 17,
The sub-signal wires include a curve extending along at least a portion of an edge of the through hole,
And the main signal wires comprise straight lines.

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