KR20190120690A - Reed solomon decoder and semiconductor deivce including the same - Google Patents

Abstract

According to the present invention, a reed Solomon decoder comprises: a syndrome calculation (SC) circuit for calculating a syndrome from a codeword; a key equation solver (KES) circuit for calculating an error position polynomial function and an error evaluation polynomial function from the syndrome; and a Chien search and error evaluation (CSEE) circuit for computing an error position and error value from the error position polynomial function and the error evaluation polynomial function. Each of a plurality of sub KES circuits, the SC circuit, and the CSEE circuit constitutes a pipeline stage.

Description

Reed Solomon Decoder and Semiconductor Device Comprising the Same {{{LOD}} SOLOMON DECODER AND SEMICONDUCTOR DEIVCE INCLUDING THE SAME

The present invention relates to a Reed Solomon decoder and a semiconductor device including the same.

1 is a block diagram illustrating a conventional Reed Solomon decoder.

Conventional Reed-Solomon decoders have outputs from a Syndrome Calculation (SC) circuit 10 for calculating syndromes from codewords, a Key Equation Solver circuit 20 for solving key equations using syndromes, and a KES circuit 20. Compute the Chien Search and Error Evaluation (CSEE) circuit 30, which performs the Chien search and error evaluation, and the output of the CSEE circuit 30 and the received codeword to provide error-corrected output data. And an error correction operation circuit 40.

FIG. 2 is a block diagram showing the operation of the KES circuit 20 of FIG.

The conventional KES circuit 20 outputs an error position polynomial and an error evaluating polynomial from the syndrome. To this end, the KES circuit 20 performs an operation while looping 2t times.

In this case, 2t is associated with the number of parity symbols included in the codeword. For example, if a block encoded with a Reed Solomon code includes 255 symbols, and among these, 32 data symbols are 223 parity symbols, 2t is equal to 32.

For example, if one clock is required for the operation of the SC circuit 10, two clocks for the operation of the CSEE circuit 30, and one clock is required for the KES circuit 20 to loop once, the latency becomes 2t + 3.

In addition, the conventional Reed Solomon decoder cannot start the decoding operation for the new codeword while the decoding operation for the previously input codeword is in progress.

Accordingly, the conventional Reed Solomon decoder has a long latency and low throughput, and thus high speed decoding is not possible.

KR 10-2004-0045922 A US 8365354 B2

 D. V. Sarwate and N. R. Shanbhag, "High-speed Architectures for Reed-Solomon decoders," IEEE Trans. on VLSI Syst., vol. 9, pp. 641-655, Oct. 2001. (Pubitemid 32992893)

The present invention provides a Reed Solomon decoder capable of a high speed decoding operation and a semiconductor device including the same.

Reed Solomon decoder according to an embodiment of the present invention includes an SC circuit for calculating a syndrome from a codeword; A KES circuit for calculating an error position polynomial and an error evaluation polynomial from the syndrome; And a CSEE circuit for calculating an error position and an error value from the error position polynomial and the error evaluation polynomial, wherein the KES circuit includes a plurality of sub-KES circuits connected in series, each of the plurality of sub-KES circuits, the SC circuit and the CSEE. The circuit constitutes a pipeline stage.

In an embodiment, a semiconductor device may include an error correction encoder that encodes data and outputs a codeword; A memory cell storing a codeword output from an error correction encoder; And an error correction decoder that decodes the codeword output from the memory cell and outputs data in which the error is corrected.

The Reed Solomon decoder according to the present invention performs parallel processing in the SC circuit and the CSEE circuit to enable high-speed computation.

The Reed Solomon decoder according to the present invention divides the KES circuit into a plurality of sub-circuits so that the operation of the entire decoding circuit can be pipelined to improve throughput.

The semiconductor device according to the present invention may internally perform an error correction operation by embedding an error correction encoder and a decoder therein.

Since the semiconductor device according to the present invention does not require a separate device for error correction, the area and manufacturing cost of the system can be reduced.

1 is a block diagram of a conventional Reed Solomon decoder.
2 is a block diagram showing operation of the KES circuit of FIG.
3 is a block diagram of a Reed Solomon decoder according to an embodiment of the present invention.
4 is a detailed block diagram of the SC circuit of FIG.
5 is a detailed block diagram of the sub KES circuit of FIG.
6 is an algorithm illustrating operation of the sub KES circuit of FIG.
FIG. 7 is a block diagram illustrating the PE circuit of FIG. 3. FIG.
8 is a detailed block diagram of the PE circuit of FIG.
9 is a detailed block diagram of the control circuit of FIG.
10 is a detailed block diagram of the CSEE circuit of FIG.
11 is a block diagram of a semiconductor device according to one embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings discloses an embodiment of the present invention.

3 is a block diagram of a Reed Solomon decoder 1 according to an embodiment of the present invention.

The Reed Solomon decoder 1 according to an embodiment of the present invention includes an SC circuit 100, a KES circuit 200, and a CSEE circuit 300.

Reed Solomon decoder 1 according to an embodiment of the present invention is a register 500 for sequentially queuing the input codeword and the codeword provided from the register 500 and the error position output from the CSEE circuit 300 and It may further include an error correction operation circuit 400 for calculating the error value to generate output data in which the error is corrected.

The SC circuit 100 outputs syndromes S ₀ to S _2t-1 generated using the codeword r (x).

Hereinafter, a codeword may be expressed as a codeword polynomial and a syndrome may be expressed as a syndrome polynomial.

The KES circuit 200 outputs an error position polynomial [lambda] (x) and an error evaluation polynomial [Omega (x)) generated from syndromes, respectively.

The CSEE circuit 300 receives an error position polynomial λ (x) and an error evaluation polynomial Ω (x) and outputs an error position and an error value.

In this embodiment, the basic operation principle of the SC circuit 100, the KES circuit 200, and the CSEE circuit 300 is similar to the conventional Reed Solomon decoder shown in FIG.

For example, the CSEE circuit 300 may implement a Chien Search algorithm and a Forney algorithm.

Since these algorithms are well known, detailed descriptions thereof are omitted.

SC circuit 100 and CSEE circuit 300 may have a parallel structure to increase the processing speed.

In this embodiment, the KES circuit 200 includes a plurality of sub KES circuits 210 connected in series.

In the present embodiment, the sub KES circuit 210 includes t (natural numbers).

The t sub KES circuits 210 replace the conventional KES circuits 20 that perform operations in loop 2t.

In this case, each sub KES circuit 210, the SC circuit 100, and the CSEE circuit 300 may configure a pipeline stage, respectively.

For example, if each pipeline stage operates for two clocks, the overall latency can be reduced to t + 4.

In addition, since the Reed Solomon decoder 1 according to an embodiment of the present invention operates in a pipelined manner, a decoding operation for a new codeword may be performed while a decoding operation for a previously inputted codeword is performed to increase throughput. Can be. For example, in this embodiment, two clocks are required to perform each pipeline step, so that one codeword can be decoded every two clocks.

The register 500 sequentially queues the codewords and provides the error correction arithmetic circuit 400 with codewords corresponding to the error position and the error value output from the CSEE circuit 300. In one embodiment, register 500 may be configured to queue codewords for the entire pipeline stages contained in SC circuit 100, KES circuit 200, and CSEE circuit 300 and operate in a first-in, first-out manner. Can be.

The error correction operation circuit 400 outputs data in which an error is corrected by referring to the error position and the error value.

4 is a detailed block diagram of the sub SC circuit 110 constituting the SC circuit 100 of FIG. 3.

The sub-SC circuit 110 outputs one syndrome (Si) and the SC circuit 100 is arranged in parallel to output a plurality of syndromes (Si, i = 0, ..., 2t-1) simultaneously. The sub SC circuit 110 is included. In this case, 2t is equal to the number of parity symbols included in the codeword r (x).

Hereinafter, the codeword polynomial is represented by r (x), the error-corrected data polynomial is represented by c (x), and the error polynomial is represented by e (x).

In this case, the received codeword polynomial may be expressed as follows.

r (x) = c (x) + e (x)

If the message polynomial is m (x) and the codeword generation polynomial is g (x), the codeword polynomial can be expressed as follows.

g (x) = (x-α ¹ )... (x-α ^2t )

c (x) = m (x) g (x)

Α ⁱ (i = 0, ..., 2t-1) is the root of the primitive polynomial constituting the Galois field.

In the syndrome polynomial, each syndrome (Si) is expressed as

Si = r (α ⁱ ) = c (α ⁱ ) + e (α ⁱ ) = e (α ⁱ ), i = 0, ..., 2t-1

FIG. 5 is a detailed block diagram of the sub KES circuit 210 of FIG.

The sub KES circuit 210 includes 3t + 1 PE (Processing Element) circuits 211 and a control circuit 212 for controlling them.

The sub KES circuit 210 of FIG. 5 corresponds to the r th sub KES circuit (r = 0, 1, ..., t-1) among the sub KES circuits of FIG. Instructions can be made using 210-r.

The r th sub KES circuit 210 receives signals such as θ _i (r), δ _i (r), γ (r) and k (r) from the sub KES circuit of the previous step (i = 0, 1, 2, ..., 3t).

For example, θ _i (r) is input to the i-th PE circuit 211-i, i = 0, 1, ..., 3t and δ _{i + 1} (r) is the i-th PE circuit 211-i, i = 0, 1, ..., 3t-1) and a fixed value 0 is input to the 3t-th PE circuit 211-3t instead of δ _{3t + 1} (r). δ ₀ (r), γ (r) and k (r) are input to the control circuit 212.

For the 0th sub KES circuit 211-0, the input signals θ _i (0) and δ _i (0) are initialized to Si for i = 0, 1, ..., 2t-1, and i = 2t Is initialized to 0 for 2t + 1, ..., 3t-2, 3t-1, and 1 for i = 3t. K (0) is also initialized to 0 and γ (0) is initialized to 1.

The r-th sub KES circuit 210 outputs signals such as θ _i (r + 1), δ _i (r + 1), γ (r + 1), and k (r + 1) to the next sub KES circuit ( i = 0, 1, ..., 3t). Θ _i (r + 1) and δ _i (r + 1) are output from the ith PE circuit 211-i and γ (r + 1) and k (r + 1) are output from the control circuit 212. do.

The (t-1) th sub KES circuit provides the coefficient λ _i (t) of the error position equation λ (x) and the coefficient Ω _i (t) of the error evaluation equation Ω (x). Λ _i (t) = δ _{i + 1} (t), Ω _i (t) = δ _i (t) (i = 0, 1, ..., t-1).

The operation of the PE circuit is described below.

FIG. 6 is an algorithm illustrating the operation of the KES circuit 200 of FIG. 3.

In this embodiment, the KES circuit 200 uses a two-stage unfolded RiBM algorithm.

This embodiment includes t sub KES circuits 210 unlike the prior art.

Each sub KES circuit 210 performs an operation between lines 6 to 35 of the algorithm of FIG.

t sub KES circuits 210 are connected in series, and the r (r = 0, 1, ..., t-1) th sub KES circuits correspond to the r values described in line 5 of the algorithm of FIG. Perform the action.

The control circuit 212 controls to perform the first operation and the second operation in each of the 3t + 1 PE circuits 211.

The first operation corresponds to the operation performed on lines 7 to 20 of the algorithm of FIG. 6, and the second operation corresponds to the operation performed on lines 21 to 35.

The control circuit 212 controls the 3t + 1 PE circuits 211 to perform the second operation after performing the first operation. For this purpose, the control circuit 212 uses the signal MC (r) representing the determination result calculated in line 8 of the algorithm of FIG. 211 to each.

The first operation and the second operation may be sequentially performed in the 3t + 1 PE circuits 211.

FIG. 7 is a block diagram illustrating the i-th PE circuit 211 in FIG. 5.

The PE circuit 211 includes terminals for inputting and outputting signals necessary for the first operation performed on lines 7, 10, and 16 of the algorithm of FIG. 6 and the second operation performed on the lines 22, 25, and 31.

For example, the PE circuit 211 includes θ _i (r), δ _{i + 1} (r), δ ₀ (r), γ (r), δ ' ₀ (r), γ' (r), and MC (r ) And MC '(r) and the like, θ _i (r + 1), δ _i (r + 1), δ ₀ (r), γ (r), δ' ₀ (r) and γ ' (r) outputs a signal.

FIG. 8 is a detailed circuit diagram of the PE circuit 211 of FIG. 7.

The PE circuit 211 includes a first arithmetic circuit 2111 for a first operation and a second arithmetic circuit 2112 for a second operation.

The first calculation circuit 2111 includes a first calculation block 21111 and a second calculation block 21112.

The second arithmetic circuit 2112 includes a third arithmetic block 21121 and a fourth arithmetic block 21122.

For example, the first operation block 21111 performs line 7 of the algorithm of FIG. 6, and the second operation block 21112 performs line 10 or 16 of the algorithm of FIG. 6.

Similarly, third operation block 21121 performs line 22 of the algorithm of FIG. 6, and fourth operation block 21122 performs line 25 or 31 of the algorithm of FIG. 6.

The third operation block 21121 and the fourth operation block 21122 include a D flip-flop to hold data at the corresponding pipeline stage.

In the circuit of FIG. 8, each operation block is a symbol of the algorithm of FIG. 6 as it is, and thus a detailed description thereof will be omitted.

9 is a detailed block diagram of the control circuit 212 of FIG. 7.

The control circuit 212 performs a first control operation performed on lines 8, 11, 12, 17, and 18 and a second control operation performed on lines 23, 26, 27, 32, and 33 in the algorithm of FIG. 6.

The control circuit 212 includes a first control circuit 2121 for a first control operation and a second control circuit 2122 for a second control operation.

The first control circuit 2121 includes a first control block 221211, a second control block 221212, and a third control block 221213.

The second control circuit 2122 includes a fourth control block 221221, a fifth control block 21222, and a sixth control block 221223.

The fifth control block 21222 and the sixth control block 221223 include a D flip-flop to hold data at the corresponding pipeline stage.

The signal representing the determination result of line 8 of the algorithm of FIG. 6 is represented by MC (r), and the signal representing the determination result of line 23 is represented by MC '(r).

For example, the first control block 221211 generates a signal MC (r) corresponding to the determination result of line 8 of the algorithm of FIG. 6, and the second control block 221212 is line 11 or 17 of the algorithm of FIG. 6. And the third control block 221213 performs an operation corresponding to line 12 or 18 of the algorithm of FIG. 6.

Similarly, fourth control block 221221 generates signal MC '(r) corresponding to the determination result of line 23 of the algorithm of FIG. 6, and fifth control block 21222 generates line 26 or 32 of the algorithm of FIG. 6. And a sixth control block 221223 performs an operation corresponding to line 27 or 33 of the algorithm of FIG.

The operation of lines 12 and 27 represents a two's complement operation for representing negative numbers. For example, a negative value of k (r) is equivalent to adding 1 after inverting k (r) bit by bit. Accordingly, the value of inverting k (r) bit by bit is equal to minus one from the negative value of k (r) as shown in line 12 of the algorithm of FIG. 6.

Each control block of FIG. 9 is a direct symbolization of the corresponding algorithm of FIG. 6, and thus a detailed description thereof will be omitted.

10 is a detailed block diagram of the CSEE circuit 300 of FIG.

The CSEE circuit 300 includes a chien search (CS) circuit 310 and an error evaluation (EE) circuit 320.

The CS circuit 310 implements a Chien search algorithm and receives an error position polynomial λ (x) output from the KES circuit 200 to calculate an error position.

The EE circuit 310 implements a pony algorithm and calculates an error value by receiving an error evaluation polynomial (Ω (x)) output from the KES circuit 200 and an error position output from the CS circuit 310.

The circuitry for implementing the Chien search algorithm and the Pony algorithm is variously known in the art.

In order to improve the computational speed, it is desirable to implement the circuit in parallel.

11 is a block diagram of a semiconductor device 2 according to an embodiment of the present invention.

The semiconductor device 2 may include an input buffer 610 that receives data, an error correction encoder 620 that encodes data output from the input buffer 610 according to an error correction algorithm, and outputs a codeword, and an encoded codeword. An error correction decoder 640 and an error correction decoder 640 which decode the codewords output from the memory cell 630 and the memory cell 630 according to an error correction algorithm and output the data whose error is corrected. And an output buffer 650 for buffering data and providing the data to the outside.

The memory cell 630 may separately store data and parity, and in this case, the memory cell 630 may include a main cell 631 storing data and a parity cell 632 storing parity.

In this embodiment, the error correction algorithm includes a Reed Solomon algorithm, wherein the error correction decoder 640 includes the Reed Solomon decoder 1 disclosed in FIG. 3.

The semiconductor device 2 according to the present invention may be implemented in various embodiments, such as a semiconductor memory device and a network device.

FIG. 11 illustrates a representative configuration included in the semiconductor device 2 according to the present invention, and blocks through which data passes may be added to paths between the blocks of FIG. 11.

In the semiconductor device 2 according to the present invention, since the error correction decoder 640 performs decoding at high speed, the bottleneck in the decoding process can be prevented.

Since the semiconductor device 2 according to the present invention performs an error correction encoding and decoding function by itself, it is not necessary to add a separate encoding and decoding device outside the semiconductor device.

As a result, the area and manufacturing cost of the system including the semiconductor device 2 can be reduced.

Since the above disclosure describes the embodiments of the present invention, the scope of the present invention is not limited to the above disclosure. The scope of the present invention is defined by the scope literally described in the following claims and their equivalents.

1: Reed Solomon Decoder
2: semiconductor device
10, 100: SC circuit
20, 200: KES circuit
210: sub KES circuit
211: PE circuit
212: control circuit
30, 300: CSEE circuit
310: CS circuit
320: EE circuit
40, 400: error correction operation circuit
500: register
610: input buffer
620: error correction encoder
630: memory cell
640: error correction decoder
650 output buffer

Claims (18)

An SC circuit for calculating a syndrome from a codeword;
A KES circuit for calculating an error position polynomial and an error evaluation polynomial from the syndrome; And
CSEE circuit for calculating an error position and an error value from the error position polynomial and the error evaluation polynomial
Including,
The KES circuit includes a plurality of sub KES circuits connected in series,
And each of said plurality of sub KES circuits, said SC circuit and said CSEE circuit constitute a pipeline stage. The method according to claim 1,
A register for queuing the codeword; And
An error correction arithmetic circuit for calculating the codeword output from the register, the error position, and the error value and outputting data in which the error is corrected
Reed Solomon decoder including more. The Reed Solomon decoder of claim 1, wherein the sub KES circuit comprises a plurality of PE circuits connected in series and a control circuit for controlling the operation of the PE circuit. The Reed Solomon decoder of claim 3, wherein the number of sub-KES circuits is t (t is a natural number), and the number of PE circuits is 3t + 1. The apparatus of claim 3, wherein the PE circuit comprises a second operation circuit performing a first operation operation and a second operation circuit performing a second operation operation, wherein the control circuit is configured to control the first operation circuit. A reed solomon decoder comprising a control circuit and a second control circuit for controlling the second arithmetic circuit. The Reed Solomon decoder of claim 1, wherein the SC circuit comprises a plurality of sub SC circuits, each calculating one syndrome from a codeword. The Reed Solomon decoder of claim 6, wherein the plurality of sub-SC circuits operate in parallel to output a plurality of syndromes. The circuit of claim 1 wherein the CSEE circuitry is
A CS circuit for calculating an error position from the error position polynomial; And
An EE circuit for calculating an error value from the error evaluation polynomial and the error location
Reed Solomon decoder including. An error correction encoder for encoding data and outputting a codeword;
A memory cell storing a codeword output from the error correction encoder; And
An error correction decoder that decodes a codeword output from the memory cell and outputs data with error correction
Including,
The error correction decoder
An SC circuit for calculating a syndrome from a codeword output from the memory cell;
A KES circuit for calculating an error position polynomial and an error evaluation polynomial from the syndrome; And
CSEE circuit for calculating an error position and an error value from the error position polynomial and the error evaluation polynomial
Including,
The KES circuit includes a plurality of sub KES circuits connected in series,
Each of the plurality of sub KES circuits, the SC circuit and the CSEE circuit constitute a pipeline stage.
A semiconductor device comprising a Reed Solomon decoder. The method according to claim 9,
An input buffer for buffering externally input data and providing the same to the error correction encoder;
An output buffer that buffers the data output from the error correction decoder and provides it to the outside
The semiconductor device further comprising. The semiconductor device of claim 9, wherein the codeword includes a data portion and a parity portion, and the memory cell includes a main cell storing the data portion and a parity cell storing the parity portion. The method of claim 9, wherein the error correction decoder is
A register for queuing a codeword output from the memory cell; And
An error correction arithmetic circuit for calculating the codeword output from the register, the error position, and the error value and outputting data in which the error is corrected
The semiconductor device further comprising. The semiconductor device of claim 9, wherein the sub-KES circuit comprises a plurality of PE circuits connected in series and a control circuit for controlling the operation of the PE circuit. The semiconductor device according to claim 13, wherein the number of sub-KES circuits is t (t is a natural number), and the number of PE circuits is 3t + 1. The apparatus of claim 13, wherein the PE circuit comprises a second operation circuit performing a first operation operation and a second operation circuit performing a second operation operation, wherein the control circuit is configured to control the first operation circuit. And a second control circuit for controlling the control circuit and the second arithmetic circuit. 10. The semiconductor device of claim 9, wherein the SC circuit comprises a plurality of sub SC circuits each calculating one syndrome from a codeword. The semiconductor device of claim 16, wherein the plurality of sub-SC circuits operate in parallel to output a plurality of syndromes. The system of claim 9, wherein the CSEE circuitry is
A CS circuit for calculating an error position from the error position polynomial; And
An EE circuit for calculating an error value from the error evaluation polynomial and the error location
A semiconductor device comprising a.

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