KR20190120536A - Semiconductor memory module and memory system including semiconductor memory module - Google Patents

Abstract

The present invention relates to a semiconductor memory module. According to an embodiment of the present invention, the semiconductor memory module comprises: a random access memory; a nonvolatile memory; a buffer memory; and a controller configured to perform a read operation on the buffer memory in response to the activation of a control signal. According to a result of the read operation, the controller is further configured to perform a flush operation of storing first data stored in the random access memory in the nonvolatile memory.

Description

A memory system including a semiconductor memory module and a semiconductor memory module {SEMICONDUCTOR MEMORY MODULE AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY MODULE}

The present invention relates to a semiconductor device, and more particularly, to a memory system including a semiconductor memory module and a semiconductor memory module.

Semiconductor memories are used to store data using semiconductor elements. Semiconductor memory includes volatile memory such as dynamic random access memory or static random access memory, and nonvolatile memory such as flash memory, phase change memory, ferroelectric memory, magnetic memory, resistive memory, and the like.

Typically, volatile memory supports high speed random access and is used as the main memory of computing systems such as personal computers, servers or workstations. Nonvolatile memory supports large storage capacities and is used as secondary storage for computing systems.

In recent years, research and development on storage class memory (SCM) has been progressing. Storage class memory is being developed with the goal of supporting both large nonvolatile storage capacity and high speed random access. The storage class memory may be implemented using nonvolatile memory.

For compatibility with the existing main memory, the storage class memory is researched and developed based on the memory module of the main memory. However, due to the difference between the operation characteristics of the conventional main memory, the dynamic random access memory (DRAM), and the operation characteristics of the nonvolatile memory of the storage class memory, the speed of the storage class memory may be lower than that of the existing main memory.

An object of the present invention is to provide a memory system including a semiconductor memory module and a semiconductor memory module having an improved speed.

A semiconductor memory module according to an embodiment of the present invention includes a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to perform a read operation on a buffer memory in response to activation of a control signal. According to the result of the read operation, the controller is further configured to perform a flush operation of storing the first data stored in the random access memory in the nonvolatile memory.

A semiconductor memory module according to an embodiment of the present invention performs a read operation on a buffer memory and a random access memory in response to activation of a random access memory, a nonvolatile memory, a buffer memory, and a control signal, and reads from the buffer memory And a controller configured to store data in a nonvolatile memory and to perform a flush operation of storing second data read from the random access memory into a buffer memory.

A memory system according to an embodiment of the present invention includes a semiconductor memory module and a central control block. The semiconductor memory module includes a random access memory, a nonvolatile memory, and a controller. The central control block is configured to activate a control signal transmitted to the controller if an access error is detected when accessing the semiconductor memory module. In response to the control signal being activated, the controller is configured to read the first of the data stored in the random access memory and to store the first data as the second data in the nonvolatile memory.

According to the present invention, the semiconductor memory module uses a write table to flush some of the data of the random access memory to the nonvolatile memory. In addition, the semiconductor memory module may store data in which a cache miss occurs in the buffer memory. Thus, a semiconductor memory module with improved speed is provided. Further, according to the present invention, the memory system may instruct the semiconductor memory module to flush when an access error occurs. Thus, a memory system with improved speed is provided.

1 is a block diagram illustrating a memory system according to an example embodiment of the disclosure.
2 is a flowchart illustrating a method of operating a memory system according to an exemplary embodiment of the inventive concept.
3 shows a first example instructing a flush operation when an access error occurs.
4 shows another example in which the hub activates the first control signal.
5 shows a second example of instructing a flush operation when an access error occurs.
6 is a block diagram illustrating a memory system according to another example embodiment of the disclosure.
7 is a flowchart illustrating a method of operating a first memory module or a third memory module according to an embodiment of the present invention.
8 illustrates a first example of storing data in a first memory module.
9 illustrates a first example in which a flush operation is performed using a buffer memory in a first memory module.
10 illustrates a second example in which a flush operation is performed by using a buffer memory in a first memory module.
FIG. 11 shows an example in which a flush operation is performed following FIG. 10.
12 shows an application example in which the first memory module uses a buffer memory.
13 is a block diagram illustrating a memory system according to an example embodiment of the disclosure.
14 shows an example in which a processor accesses first and third memory modules.
15 is a flowchart illustrating a method of operating a memory system according to a first example of the present invention.
16 shows an example of reading data from a first memory module.
17 shows an example in which exception processing is performed on the first memory module.
18 is a flowchart illustrating an operating method according to a second example of the present invention.
19 shows an example where a monarch core is assigned.
20 shows a first example in which the remaining cores are managed.
21 shows an example of managing cores for exception handling according to an embodiment of the present invention.
22 shows a second example in which the remaining cores are managed.
23 shows an example in which other exception processing occurs while the first core performs exception processing.
24 shows an example in which the first core completes the exception processing following the state of FIG. 11.
25 shows a first example of an error signal generated by the cores or the processor.
26 is a block diagram illustrating a first type memory module according to an embodiment of the present invention.
27 is a block diagram illustrating a memory system according to an example embodiment of the disclosure.
28 shows an example of a processor accessing first and third memory modules.
29 shows an example in which a page member occurs.
30 shows an example in which the member processing is performed.
FIG. 31 shows an example in which a virtual storage space identified by virtual addresses of '01' to '16' is allocated to a first application.
32 shows an example in which virtual addresses are allocated according to the first embodiment subsequent to FIG. 5.
33 illustrates an example in which the page absence processor performs page absence processing on virtual addresses of '01' to '16' according to the first embodiment.
34 is a view illustrating a member processing method according to a second embodiment of the present invention.
FIG. 35 shows an example in which virtual addresses are allocated according to the second embodiment following FIG. 32.
FIG. 36 shows an example in which virtual addresses are allocated according to the second embodiment subsequent to FIG. 35.
FIG. 37 shows an example in which the page absence processor performs page absence processing on virtual addresses of '01' to '16' according to the second embodiment.
38 shows an example of adjusting the number of pages according to an embodiment of the present invention.
39 shows an example in which the result of the member processing is transferred to the first memory module.
40 is a block diagram illustrating a first type memory module according to an embodiment of the present invention.
41 is a block diagram illustrating a memory system according to an example embodiment of the disclosure.
42 is a flowchart illustrating a method of operating a first type memory module according to an embodiment of the present invention.
43 shows an example in which the memory controller performs initialization with the first and third memory modules.
44 shows an example in which a media controller configures a channel with a memory controller during training after initialization is performed.
45 shows an example in which the media controller controls training commands during training.
46 shows an example in which the media controller establishes a channel with the second type memory.
47 shows an example where the media controller detects completion of training.
48 is a block diagram illustrating a first type memory module according to an embodiment of the present invention.
49 is a block diagram illustrating a computing device according to an example embodiment.
50 shows an example in which the first controller performs a read operation on the main memory.
51 illustrates a first example in which a read operation is performed according to the operating method of FIG. 50.
52 is a view illustrating a modification of the read operation of FIG. 51.
53 illustrates a second example in which a read operation is performed according to the operating method of FIG. 50.
54 is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present invention.
55 is a view illustrating a first example in which a read operation is performed according to the operating method of FIG. 54.
FIG. 56 shows a second example in which a read operation is performed according to the operating method of FIG. 54.
FIG. 57 shows a modification of the read operation of FIG. 56.
58 shows an application example of the operation method of FIG. 54.
59 shows an example of performing a read operation while measuring the third time.
60 is a block diagram illustrating a computing device according to another example of the inventive concept.
61 shows an example of a main memory including an SPD device and a register updater.
62 is a flowchart showing how the main memory updates registers.
63 is a block diagram illustrating a computing device according to another example of the present disclosure.
64 is a flowchart illustrating an example in which a first controller performs a write operation.
65 is a flowchart illustrating an example in which the main memory performs a write operation.
66 illustrates a first example in which a write operation is performed according to the operation method of FIG. 65.
67 is a view illustrating a second example in which a write operation is performed according to the operating method of FIG. 65.
FIG. 68 shows a second example in which a write operation is performed according to the operation method of FIG. 66.
69 is a view illustrating a modification of the read operation of FIG. 68.
70 shows another modified example of the read operation of FIG. 68.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that those skilled in the art can easily carry out the present invention.

1 is a block diagram illustrating a memory system 100a according to an exemplary embodiment of the inventive concept. For example, the memory system 100a may include a server such as an application server, a client server, and a data server. As another example, memory system 100a may comprise a personal computer or workstation.

Referring to FIG. 1, the memory system 100a may include a central control block 110, a first memory module 120a, a second memory module 130a, a third memory module 140, and a fourth memory module 150. , Root complex 160, storage device 170, power management block 180, and peripherals 190.

The central control block 110 includes a processor 111 and a hub 114. The processor 111 may control the components of the memory system 100a and the operations of the components. The processor 111 may execute an operating system and applications and process data using the operating system or applications.

The processor 111 may include a memory controller 112 and a cache memory 113. The memory controller 112 may include the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module through the main channels MCH and the auxiliary channels SCH. 150 may be accessed. Cache memory 113 may include high speed memory, such as static random access memory (SRAM).

Hub 114 may be connected to power management block 180. The hub 114 may connect the processor 111 with various peripheral devices 190. Hub 114 may include various controllers for controlling peripherals 190. For example, the hub 114 may include a platform controller hub (PCH).

The hub 114 may transmit the first control signal CS1 and the second control signal CS2 to the first type memory modules 120a and 130a, respectively. For example, the first control signal CS1 and the second control signal CS2 each request an ADR DRAM refresh requesting that the first memory module 120a and the second memory module 130a perform a flush operation. ) Signal may be included.

The first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 are connected to the memory controller through the main channels MCH and the auxiliary channels SCH. 112). The main channels MCH are data stored in the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 (eg, semiconductor memory modules). It may be channels used for storing or reading data. The main channels MCH may include channels provided for the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150, respectively.

The auxiliary channels SCH may include a first memory in addition to storing or reading data in the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150. Additional functions associated with the module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may be provided.

For example, the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may store their own information through the auxiliary channels SCH. Memory controller 112. The auxiliary channels SCH may include channels provided for the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150, respectively.

The first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may be used as main memory of the memory system 100a. The first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may include a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and an LRDIMM ( Communication with the memory controller 112 in accordance with one of the standards of a memory module, such as Load Reduced DIMM).

The root complex 160 may communicate directly with the processor 111 or with the processor 111 via the hub 114. The root complex 160 can provide channels through which the central control block 110 accesses various peripheral devices. For example, the storage device 170 may be connected to the root complex 160. The storage device 170 may include a hard disk drive, an optical disk drive, a solid state drive, and the like.

In exemplary embodiments, peripheral devices connected to the root complex 160 are not limited to the storage device 170. For example, the root complex 160 can be connected to various devices such as a modem, graphics processing unit (GPU), neuromorphic processor, and the like.

The power management block 180 may observe power supplied to the memory system 100a and control power supplied to components of the memory system 100a. The power management block 180 may provide a signal to the hub 114 to notify the SPO when a sudden power off (SPO) occurs in the memory system 100a.

The processor 111 may include a cache memory 113, a main memory first memory module 120a, a second memory module 130a, a third memory module 140 and a fourth memory module 150, and a storage device ( 170) can be managed hierarchically. For example, the processor 111 may store necessary data among the data stored in the storage device 170 in the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module ( 150) to the main memory including the. The processor 111 may flush data to be backed up from the data stored in the main memory to the storage device 170.

Some of the storage areas of the main memory including the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may be mapped to the cache memory 113. Can be. When the processor 111 needs to access a specific storage space of the main memory, the processor 111 may determine whether the specific storage space is mapped to the cache memory 113.

If a particular storage space is mapped to the cache memory 113, the processor 111 can access the particular storage space of the cache memory 113. If a specific storage space is not mapped in the cache memory 113, the processor 111 may include the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150. ) Can store (or fetch) certain storage spaces in cache memory 113.

If the storage space of the cache memory 113 is insufficient, the processor 111 may release the storage space previously mapped to the cache memory 113. When the data of the storage space to be released is updated, the processor 111 transmits the updated data to the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150. Can be flushed to

The first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may include heterogeneous memory modules. For example, the first and second memory modules 120a and 130a may be first type memory modules. The third and fourth memory modules 140 and 150 may be second type memory modules.

The first memory module 120a may include a first type memory 121, a second type memory 122, a media controller 123, and a serial presence detection device (SPD) device 125. have. The second memory module 130a may include a first type memory 131, a second type memory 132, a media controller 133, and a serial presence detection (SPD) device 135. . Hereinafter, the first type memory modules 120a and 130a will be described with reference to the first memory module 120a.

The first type memory 121 may include a high speed volatile memory, for example, a dynamic random access memory (DRAM). The second type memory 122 may include a nonvolatile memory having a slower speed than the first type memory 121 and having a larger storage capacity than the first type memory 121. For example, the second type memory 122 may include a flash memory, a phase change memory, a ferroelectric memory, a magnetic memory, a resistive memory, and the like. .

The media controller 123 may receive an access command from an external host device, for example, the memory controller 112 or the processor 111, transmitted through a corresponding channel among the main channels MCH. Alternatively, the data may be transferred to the second type memory 122. According to the access command, the media controller 123 may exchange data with an external host device, for example, the memory controller 112 or the processor 111, through a corresponding channel among the main channels MCH.

 The media controller 123 may provide a storage capacity or a storage space of the second type memory 122 to an external host device, for example, the memory controller 112 or the processor 111. The media controller 123 may use the first type memory 121 as a cache memory of the second type memory 122.

For example, the media controller 123 may map some of the storage spaces of the second type memory 122 to the first type memory 121. If the storage space associated with an access command from an external host device, for example, the memory controller 112 or the processor 111, is mapped to the first type memory 121, the media controller 123 issues the first access command. It may be transferred to the type memory 121.

If the storage space associated with an access command from an external host device, for example, the memory controller 112 or the processor 111, is not mapped in the first type memory 121, the media controller 123 may store the storage space. Mapping (or backing up) from the second type memory 122 to the first type memory 121 may be performed.

If the storage space of the first type memory 121 is insufficient, the media controller 123 may release the storage space previously mapped to the first type memory 121. If data of the storage space to be released is updated, the media controller 123 may flush the updated data to the second type memory 122.

The SPD device 125 may communicate with an external host device, for example, the memory controller 112 or the processor 111 through a corresponding channel among the auxiliary channels SCH. For example, when the first memory module 120a is initialized, the SPD device 125 transmits the stored information to an external host device, for example, the memory controller 112, through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 111 may provide the processor 111.

For example, the SPD device 125 may store information about a storage capacity provided to an external host device, for example, the memory controller 112 or the processor 111 as a storage space of the first memory module 120a. have. For example, the SPD device 125 may store information about a storage capacity of the second type memory 122. Upon initialization, the SPD device 125 may provide information about the storage capacity of the second type memory 122 to an external host device, for example, the memory controller 112 or the processor 111.

For example, the capacity information stored in the SPD device 125 may include information about a user capacity of the second type memory 122. The storage capacity of the second type memory 122 may include a user capacity, a meta capacity, and a spare capacity. The user capacity may be a storage capacity provided by the second type memory 122 to an external host device, for example, the memory controller 112.

The meta capacity stores various meta information for managing the second type memory 122 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 112. The spare capacity is reserved for managing the second type memory 122 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 112.

The capacity information stored in the SPD device 125 may include information about a user capacity of the second type memory 122. Hereinafter, unless otherwise specified, it may be understood that the capacity of the second type memory 122 refers to the user capacity of the second type memory 122.

The third memory module 140 may include a first type memory 141 and a serial presence detection (SPD) device 145. The fourth memory module 150 may include a first type memory 151 and a serial presence detection (SPD) device 155. Hereinafter, the second type memory modules 140 and 150 will be described with reference to the third memory module 140.

The first type memory 141 may include a dynamic random access memory like the first type memory 121 of the first memory module 120a. The SPD device 145 may communicate with an external host device, for example, the memory controller 112 or the processor 111 through a corresponding channel among the auxiliary channels SCH. For example, when the third memory module 140 is initialized, the SPD device 145 transmits the stored information to an external host device, for example, the memory controller 112 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 111 may provide the processor 111.

For example, the SPD device 145 may store information about a storage capacity provided to an external host device, for example, the memory controller 112 or the processor 111 as a storage space of the third memory module 140. have. For example, the SPD device 145 may store information about a storage capacity of the first type memory 141. At initialization, the SPD device 145 may provide information about a storage capacity of the first type memory 141 to an external host device, for example, the memory controller 112 or the processor 111.

When power is supplied to the memory system 100a, the memory controller 112 initializes with the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150. Can be performed. For example, the SPD devices 125 to 155 of the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150 may include auxiliary channels (SCH). The capacity information may be provided to the memory controller 112 through, respectively.

The SPD devices 125 and 135 of the first type memory modules 120a and 130a may provide the storage controllers of the second type memories 122 and 132 to the memory controller 112, respectively. The SPD devices 145 and 155 of the second type memory modules 140 and 150 may provide the storage controllers of the first type memories 141 and 151 to the memory controller 112, respectively. For example, the memory controller 112 may read the storage capacities from the SPD devices 125 to 155, respectively.

2 is a flowchart illustrating a method of operating a memory system 100a according to an exemplary embodiment of the inventive concept. 1 and 2, in step S11, the processor 111 accesses one of the first type memory modules 120a and 130a when accessing the memory module, for example, the first memory module 120a. It can detect that an error occurs.

In operation S12, as the access error is detected, the central control block 110 may activate the control signal CS so that the first memory module 120a flushes the data. That is, if an access error occurs when the first memory module 120a or 130a accesses the memory system 100a, the memory system 100a may instruct a flush operation to the memory module in which the error occurs.

3 shows a first example instructing a flush operation when an access error occurs. In order to avoid unnecessary complexity of the drawings, only the central control block 110, the first memory module 120a and the third memory module 140 are shown in FIG. 3. The first memory module 120a communicates with the memory controller 112 through the first main channel MCH1, and the third memory module 140 communicates with the memory controller 112 through the second main channel MCH2. can do.

For example, an example in which an access error occurs when accessing the first memory module 120a is illustrated in FIG. 3. 1 and 3, in step S21, the processor 111 may detect an access error when accessing the first memory module 120a. For example, an access error may include a page fault or an uncorrectable error.

An operating system or an application running on the processor 111 may generate an access request for the first memory module 120a using the virtual address. The memory controller 112 may refer to a page table stored in one memory module of the first memory module 120a, the second memory module 130a, the third memory module 140, and the fourth memory module 150. You can convert virtual addresses to physical addresses. The memory controller 112 may access the first memory module 120a using a physical address.

When the operating system or application requests to store new data, or when the operating system or application requests access to storage space that has already been released, there is no page table corresponding to the access request. At this time, a page member may occur. When a page member occurs, the processor 111 may perform exception processing.

When the memory controller 112 sends a read request to the first memory module 120a, the media controller 123 determines whether the requested data is stored in the first type memory 121 (ie, whether it is a cache hit) or not. It may be determined whether it is stored in the two-type memory 122 (that is, whether it is a cache miss).

In the case of a cache miss, the media controller 123 must fetch the read requested data from the second type memory 122 to the first type memory 121. Due to the time required for retrieving data, the first memory module 120a cannot provide the memory controller 112 with the read requested data within the time limit set in the memory controller 112. In this case, the memory controller 112 may determine that an uncorrectable error has occurred and perform exception processing.

In the case of a cache hit, the first type memory 121 may transmit data to the memory controller 112 according to a read request from the memory controller 112. If the transmitted data has an uncorrectable error, the memory controller 112 may determine that an uncorrectable error has occurred and perform exception processing.

As described above, if an access error occurs when the processor 111 or the memory controller 112 accesses the first memory module 120a, the processor 111 may perform an exception process. While the exception processing is performed, the processor 111 or the memory controller 112 is prohibited from accessing the first memory module 120a.

That is, while the exception processing is performed, the idle time when the access request is not transmitted from the processor 111 or the memory controller 112 to the first memory module 120a may be guaranteed to the first memory module 120a.

The memory system 100a according to an exemplary embodiment of the present disclosure may notify the first memory module 120a that exception processing is performed. For example, in step S22, the processor 111 may request the hub 114 to activate the first control signal CS1. In step S23, the hub 114 may activate the first control signal CS1.

As the first control signal CS1 is activated, the media controller 123 may identify that the processor 111 is performing exception processing, and thus the idle time is guaranteed. As the idle time is guaranteed, the media controller 123 may perform background operations required for the first memory module 120a to operate.

For example, the background operations may be operations that are not requested by the central control block 110 and are not recognized by the central control block 110. The first memory module 120a may perform a background operation during an idle time in which there is no access request from the central control block 110. The first memory module 120a may perform a background operation between processing access requests from the central control block 110.

For example, in operation S24, the media controller 123 may perform a flush operation for transferring data stored in the first type memory 121 to the second type memory 122. For example, all or part of data stored in the first type memory 121 may be written to the second type memory 122 through a flush operation.

The first type memory 121 is used as a cache memory of the second type memory 122. Therefore, data stored in the first type memory 121 must be transferred to the second type memory 122 through a flush operation.

For example, when data is to be written to the first type memory 121 according to an access request of the processor 111 or the memory controller 112, the free storage space of the first type memory 121 may be insufficient. Alternatively, when the data stored in the second type memory 122 should be fetched to the first type memory 121 according to an access request of the processor 111 or the memory controller 112, the first type memory 121 may be used. May run out of free storage space.

When the free storage space of the first type memory 121 is insufficient, a flush operation may be performed to secure the free storage space of the first type memory 121. In addition, when the power of the memory system 100a is turned off, a flush operation of transferring data stored in the first type memory 121 to the second type memory 122 to preserve the data stored in the first type memory 121 may be performed. Can be performed.

If a flush operation is performed when the media controller 123 processes the access request received from the processor 111 or the memory controller 112, the latency of the access of the first memory module 120a increases due to the flush operation. The first memory module 120a according to an embodiment of the present invention performs a flush operation when an access error occurs. Therefore, the frequency of performing the flush operation when processing the access request is reduced, and the latency of access of the first memory module 120a and the memory system 100a is reduced.

In exemplary embodiments, as described with reference to the first memory module 120a, an access error may occur in the second memory module 130a. The hub 114 may activate the second control signal CS2, and the second memory module 130a may perform a background operation. For example, the background operation performed by the first memory module 120a and the second memory module 130a is not limited to the flush operation.

Background operations include read reclaim, bad block management, wear leveling, garbage collection, and erase operations performed by the media controller 123 to manage the second type memory 122. And the like.

4 shows another example in which the hub 114 activates the first control signal CS1. In order to avoid unnecessary complexity of the drawings, only the central control block 110, the first memory module 120a, the third memory module 140, and the power management block 180 are shown in FIG. 4.

1 and 4, in operation S31, the power management block 180 may detect a sudden power off (SPO). When the SPO occurs, the memory system 100a may perform subsequent processing corresponding to the SPO by using power charged in a charging element such as a battery, a super capacitor, or the like.

As the SPO is detected, in step S32, the power management block 180 may request the hub 114 to activate the first control signal CS1. For example, the power management block 180 may instruct the hub 114 to activate both the first control signal CS1 and the second control signal CS2 transmitted to the first type memory modules 120a and 130a. You can request

As the SPO is detected in the power management block 180, in step S33, the hub 114 may activate the first control signal CS1. In response to the activation of the first control signal CS1, in operation S34, the first memory module 120a may perform a flush operation of transferring data stored in the first type memory 121 to the second type memory 122. Can be. For example, all or part of data stored in the first type memory 121 may be written to the second type memory 122 through a flush operation.

Similarly, as the second control signal CS2 is activated, the second memory module 130a may perform a flush operation for transferring data stored in the first type memory 131 to the second type memory 132. For example, all or part of data stored in the first type memory 131 may be written to the second type memory 132 through a flush operation.

5 shows a second example of instructing a flush operation when an access error occurs. In order to avoid unnecessary complexity of the drawings, only the central control block 110, the first memory module 120a and the third memory module 140 are shown in FIG. 5. For example, an example in which an access error occurs when accessing the first memory module 120a is illustrated in FIG. 5.

1 and 5, in operation S41, the processor 111 may detect an access error when accessing the first memory module 120a. As the access error is detected, in operation S42, the processor 111 may activate the third control signal CS3 transmitted to the first memory module 120a through the first main channel MCH1.

As the third control signal CS3 is activated, the media controller 123 may perform a background operation such as a flush operation. That is, the memory controller 112 may directly transmit that the access error has occurred to the first memory module 120a without passing through the hub 114.

For example, as described with reference to FIGS. 3 and 4, when an access error is detected or when an SPO is detected, the hub 114 may activate the first control signal CS1. As another example, as described with reference to FIGS. 4 and 5, the memory controller 112 activates the third control signal CS3 when an access error is detected, and the hub 114 when the SPO is detected. May activate the first control signal CS1.

6 is a block diagram illustrating a memory system 100b according to another exemplary embodiment. Referring to FIG. 6, the memory system 100b includes a central control block 110, a first memory module 120b, a second memory module 130b, a third memory module 140, and a fourth memory module 150. , Root complex 160, storage device 170, power management block 180, and peripherals 190.

The central control block 110, the third memory module 140, the fourth memory module 150, the root complex 160, the storage device 170, the power management block 180, and the peripheral devices 190 may be It may operate in the same manner as the memory system 100a of FIG. 1 and may be configured in the same manner.

For example, the central control block 110 may activate the first control signal CS1 (see FIG. 3) or the third control signal CS3 (see FIG. 5) when an access error is detected. The central control block may activate the first control signal CS1 (see FIG. 4) when the SPO is detected.

The first memory module 120b may perform a background operation, for example, a flush operation, in response to the first control signal CS1 or the third control signal CS3. The second memory module 130b may perform a background operation, for example, a flush operation, in response to the second control signal CS2 or the third control signal CS3.

The first memory module 120b further includes a buffer memory 126. The second memory module 130b further includes a buffer memory 136. The first memory module 120b may perform a flush operation by using the buffer memory 126. The second memory module 130b may perform a flush operation by using the buffer memory 136.

7 is a flowchart illustrating a method of operating the first memory module 120b or the third memory module 140b according to an embodiment of the present invention. For example, an operating method according to an exemplary embodiment of the present invention will be described with reference to the first memory module 120b. 6 and 7, in step S51, the media controller 123 of the first memory module 120b may include a control signal CS, for example, a first control signal CS1 or a third control signal CS3. ) Activation can be detected.

In operation S52, the media controller 123 may perform a read operation on the buffer memory 126. In operation S53, the media controller 123 may perform a flush operation based on the result of the read operation. That is, the media controller 123 may perform a flush operation to write data stored in the first type memory 121 to the second type memory 122 by using the information read from the buffer memory 126.

8 illustrates a first example of storing data in the first memory module 120b. In order to avoid unnecessary complexity of the drawings, only the first type memory 121, the second type memory 122, the media controller 123, and the buffer memory 126 are shown in FIG. 8.

In FIG. 8, the first storage space SC1 of the first type memory 121 is illustrated as including first to eighth pages PAGE1 to PAGE8. The page may be a unit in which the central control block 110 accesses the first memory module 120b. For example, the central control block 110 may store data in or read data from the first memory module 120b in units of pages.

In FIG. 8, the write table WT may be stored in the second storage space SC2 of the buffer memory 126. The write table WT may include information of first to eighth pages PAGE1 to PAGE8 of the first type memory 121. For example, the write table WT may store information on whether data stored in the first to eighth pages PAGE1 to PAGE8 of the first type memory 121 is newly written data.

6 and 8, in step S61, the central control block 110 may transmit a write request to the first memory module 120b. The media controller 123 may receive a write request from the central control block 110. For example, the write request may include write data and an address. The address may indicate a specific storage space of the storage space of the second type memory 122.

In operation S62, the media controller 123 may determine whether the free storage capacity of the first type memory 121 is sufficient. For example, when the free storage capacity of the first type memory 121 is equal to or larger than that of the write data, the media controller 123 may determine that there is sufficient free storage capacity.

As the free storage capacity of the first type memory 121 is sufficient, in step S63, the media controller 123 may transfer a write request from the central control block 110 to the first type memory 121.

According to the write request, in operation S64, write data may be written in the first page PAGE1 of the first type memory 121. As write data is written in the first page PAGE1, in operation S65, the media controller 123 may update the write table WT. In operation S66, a dirty indication (or a flag) indicating that new data is written in the first page PAGE1 of the first type memory 121 may be recorded in the write table WT.

9 illustrates a first example in which a flush operation is performed by using the buffer memory 126 in the first memory module 120b. In FIG. 8, the third storage capacity SC3 of the second type memory 122 may be divided into first to fourth memory blocks BLK1 to BLK4. Each of the first to fourth memory blocks BLK1 to BLK4 may be divided into first to eighth nonvolatile pages NPAGE1 to NPAGE8.

The nonvolatile page may be a unit in which the media controller 123 accesses the second type memory 122. In exemplary embodiments, the capacity of the nonvolatile page may be the same as or different from the capacity of the page. 6, 8, and 9, in step S71, the media controller 123 may detect that the first control signal CS1 or the third control signal CS3 is activated.

In response to activation of the first control signal CS1 or the third control signal CS3, the media controller 123 may perform a flush operation. For example, in operation S72, the media controller 123 may read the write table WT stored in the buffer memory 126. According to the write table WT, in step S73, the media controller 123 may check the dirty flag of the first page PAGE1 of the first type memory 121.

For example, the media controller 123 writes that new data is written to the first page PAGE1 of the first type memory 121 after the previous flush operation or after power is supplied to the memory system 100b. It can detect from the dirty table of the table WT.

Data newly written in the first page PAGE1 of the first type memory 121 should be stored in the second type memory 122, and thus may be data requiring a flush operation. The data stored in the second to eighth pages PAGE2 to PAGE8 of the first type memory 121 may be data stored in the second type memory 122 or invalid data, and thus data that does not require a flush operation. .

In operation S74, the media controller 123 may transmit a read request to the first type memory 121. For example, the media controller 123 may transmit a read request of the first page PAGE1 that requires a flush operation to the first type memory 121. According to the read request, in step S75, data of the first page PAGE1 of the first type memory 121 may be read.

In operation S76, the media controller 123 may transmit a write request to the second type memory 122. For example, the media controller 123 may transmit a write request of data of the first page PAGE1 read from the first type memory 121 to the second type memory 122.

In operation S77, data newly written in the first type memory 121 may be written in the third nonvolatile page NPAGE3 of the first memory block BLK1 of the second type memory 122. By writing data newly written in the first type memory 121 to the second type memory 122, the movement of the data may be terminated.

In operation S78, the media controller 123 may clear dirty indications of the write table WT. In addition, the media controller 123 may clear the mapping relationship between the first type memory 121 and the second type memory 122. When the flush operation is performed, data newly written in the first type memory 121 may be flushed to the second type memory 122, and the first type memory 121 may be empty.

According to an embodiment of the present disclosure, only data that requires a flush operation, that is, data newly written in the first type memory 121, from among data stored in the first type memory 121, is flushed through the second type memory 122. ). Since the movement of data is reduced, the time required for the flush operation is reduced, and the latency of the first memory module 120b is reduced.

For example, the flush operation described with reference to FIG. 9 may be performed even when the first type memory 121 is full. In exemplary embodiments, the third storage capacity SC3 of the second type memory 122 is not limited to four memory blocks. Each memory block is not limited to having eight nonvolatile pages.

10 illustrates a second example in which the flush operation is performed by using the buffer memory in the first memory module 120b. In FIG. 10, the second storage space SC2 of the buffer memory 126 may be divided into first to eighth pages PAGE1 to PAGE8. The capacity of the page of the second storage space SC2 may be equal to or different from the capacity of the page of the first storage space SC1.

The capacity of the buffer memory 126 may be the same as or different from that of the first type memory 121. 6 and 8, in step S81, the media controller 123 may detect activation of the first control signal CS1 or the third control signal CS3.

According to the activation of the first control signal CS1 or the third control signal CS3, in operation S82, the media controller 123 may transmit a read request to the buffer memory 126. In exemplary embodiments, the media controller 123 may transmit a read request of valid data to be written to the second type memory 122 among data stored in the buffer memory 126.

For example, the data of the first page PAGE1 of the buffer memory 126 may be valid data. According to the read request, in step S83, data of the first page PAGE1 of the buffer memory 126 may be read. In operation S84, the media controller 123 may transmit a write request to the second type memory 122.

For example, the media controller 123 may transmit a write request of data of the first page PAGE1 read from the buffer memory 126 to the second type memory 122. According to the write request, in operation S85, data may be written to the third nonvolatile page NPAGE3 of the second type memory 122.

FIG. 11 shows an example in which a flush operation is performed following FIG. 10. 6, 10, and 11, in step S91, the media controller 123 may transmit a read request to the first type memory 121. According to the read request, in operation S92, data stored in the first type memory 121 may be read.

In operation S93, the media controller 123 may transmit a write request to the buffer memory 126. For example, the media controller 123 may transmit a write request of data read from the first type memory 121 to the buffer memory 126. According to the write request, in operation S94, data may be stored in the buffer memory 126.

The first memory module 120b writes the data stored in the buffer memory 126 to the second type memory 122 and writes the data stored in the first type memory 121 to the buffer memory 126 to perform a flush operation. You can complete Thereafter, the media controller 123 may perform a background operation of writing data stored in the buffer memory 126 into the second type memory 122.

For example, when the free storage capacity of the buffer memory 126 is greater than the data read from the first type memory 121, the first memory module 120b may store the data of the first type memory 121 in the buffer memory 126. ), The flush operation can be completed. That is, the flushing operation may be completed through the steps described with reference to FIG. 11 without the steps described with reference to FIG. 10.

When data of the first type memory 121 is stored in the buffer memory 126, the media controller 123 removes the mapping information of the first type memory 121 and the second type memory 122 as reference information and then removes the mapping information. Can be cleared. The media controller 123 may perform a background operation of writing data stored in the buffer memory 126 into the second type memory 122 using the reference information.

According to an embodiment of the present disclosure, during the flush operation, data of the first type memory 121 is written to the buffer memory 126. Data written to the buffer memory 126 may be transferred to the second type memory 122 through a background operation. Thus, the latency of the flush operation is reduced.

In exemplary embodiments, the media controller 123 may observe the free storage capacity of the first type memory 121. When the free storage capacity of the first type memory 121 becomes less than the threshold value or decreases below the threshold ratio, the media controller 123 may perform a flush operation.

12 shows an application example in which the first memory module 120b uses the buffer memory 126. Referring to FIG. 12, the second storage space SC2 of the buffer memory 126 may include a write table WT and a buffer area BA. The write table WT may store dirty indications as described with reference to FIGS. 8 and 9.

When the first control signal CS1 or the third control signal CS3 is activated, the media controller 123 may refer to the write table WT. The media controller 123 may read data associated with a dirty display of the write table WT among data stored in the first type memory 121 and store the read data in the buffer area BA of the buffer memory 126.

If the free storage capacity of the buffer memory 126 is insufficient, the media controller 123 reads data from the buffer area BA of the buffer memory 126 and writes the read data to the second type memory 122. You can do it first. After the flush operation is completed, the media controller 123 may move data existing in the buffer memory 126 to the second type memory 122 through a background operation.

In exemplary embodiments, the central control block 110 may observe the free storage capacity of the first type memory 120a or 120b. When the free storage capacity of the first type memory 121 becomes less than the threshold value or decreases below the threshold ratio, the central control block 110 activates and flushes the first control signal CS1 or the third control signal CS3. May cause motion.

13 is a block diagram illustrating a memory system 200 according to an exemplary embodiment of the inventive concept. For example, the memory system 200 may include a server such as an application server, a client server, and a data server. As another example, memory system 200 may include a personal computer or workstation.

Referring to FIG. 13, the memory system 200 includes a processor 210, first to fourth memory modules 220 to 250, a root complex 260, and a storage device 270. The processor 210 may control the components of the memory system 200 and the operations of the components. The processor 210 may execute an operating system and applications and process data using the operating system or applications.

The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first through fourth memory modules 220 ˜ 250 through the main channels MCH and the auxiliary channels SCH. Cache memory 212 may include high speed memory, such as static random access memory (SRAM).

The first to fourth memory modules 220 to 250 may be connected to the memory controller 211 through the main channels MCH and the auxiliary channels SCH. The main channels MCH may be channels used to store data or read data in the memory modules 220 to 250 (eg, semiconductor memory modules). The main channels MCH may include channels provided for the first to fourth memory modules 220 to 250, respectively.

The auxiliary channels SCH may provide additional functions associated with the first to fourth memory modules 220 to 250 in addition to storing or reading data in the first to fourth memory modules 220 to 250. have. For example, the first to fourth memory modules 220 to 250 may provide their own unique information to the memory controller 211 through the auxiliary channels SCH. The auxiliary channels SCH may include channels provided for the first to fourth memory modules 220 to 250, respectively.

The first to fourth memory modules 220 to 250 may be used as main memory of the memory system 200. The first to fourth memory modules 220 to 250 may include a memory controller according to one of the standards of a memory module such as a dual in-line memory module (DIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), or the like. 211).

Root complex 260 can provide channels through which processor 210 accesses various peripheral devices. For example, the storage device 270 may be connected to the root complex 260. The storage device 270 may include a hard disk drive, an optical disk drive, a solid state drive, and the like.

In exemplary embodiments, peripheral devices connected to the root complex 260 are not limited to the storage device 270. For example, the root complex 260 can be connected to various devices, such as a modem, graphics processing unit (GPU), neuromorphic processor, and the like.

The processor 210 may hierarchically manage the cache memory 212, the first to fourth memory modules 220 to 250, which are main memories, and the storage device 270. For example, the processor 210 may load necessary data among data stored in the storage device 270 into the main memory including the first to fourth memory modules 220 to 250. The processor 210 may flush data to be backed up from the data stored in the main memory to the storage device 270.

Some of the storage areas of the main memory including the first to fourth memory modules 220 to 250 may be mapped to the cache memory 212. When the processor 210 needs to access a specific storage space of the main memory, the processor 210 may determine whether the specific storage space is mapped to the cache memory 212.

If a particular storage space is mapped to the cache memory 212, the processor 210 can access the particular storage space of the cache memory 212. If a particular storage space is not mapped to the cache memory, the processor 210 maps (or fetches) the specific storage space of the first to fourth memory modules 220 to 250 to the cache memory 212. Can be.

If the storage space of the cache memory 212 is insufficient, the processor 210 may release the storage space previously mapped to the cache memory 212. If data of the storage space to be released is updated, the processor 210 may flush the updated data to the first to fourth memory modules 220 to 250.

The first to fourth memory modules 220 to 250 may include heterogeneous memory modules. For example, the first and second memory modules 220 and 230 may be first type memory modules. The third and fourth memory modules 240 and 250 may be second type memory modules.

The first memory module 220 may include a first type memory 221, a second type memory 222, a media controller 223, and a serial presence detection (SPD) device 225. have. The second memory module 230 may include a first type memory 231, a second type memory 232, a media controller 233, and a serial presence detection (SPD) device 235. . Hereinafter, the first type memory modules 220 and 230 will be described with reference to the first memory module 220.

The first type memory 221 may include a high speed volatile memory, for example, a dynamic random access memory (DRAM). The second type memory 222 may include a nonvolatile memory having a slower speed than the first type memory 221 and having a larger storage capacity than the first type memory 221. For example, the second type memory 222 may include a flash memory, a phase change memory, a ferroelectric memory, a magnetic memory, a resistive memory, and the like. .

The media controller 223 receives the access command from an external host device, for example, the memory controller 211 or the processor 210, which is transmitted through a corresponding channel among the main channels MCH. Alternatively, the data may be transferred to the second type memory 222. According to the access command, the media controller 223 may exchange data with an external host device, for example, the memory controller 211 or the processor 210 through a corresponding channel among the main channels MCH.

 The media controller 223 may provide a storage capacity or a storage space of the second type memory 222 to an external host device, for example, the memory controller 211 or the processor 210. The media controller 223 may use the first type memory 221 as a cache memory of the second type memory 222.

For example, the media controller 223 may map some of the storage spaces of the second type memory 222 to the first type memory 221. If the storage space associated with an access command from an external host device, for example, the memory controller 211 or the processor 210, is mapped to the first type memory 221, the media controller 223 issues the first access command. It may be transferred to the type memory 221.

If the storage space associated with an access command from an external host device, for example, the memory controller 211 or the processor 210, is not mapped in the first type memory 221, the media controller 223 may be configured to store the storage space. Mapping (or backup) from the second type memory 222 to the first type memory 221 may be performed.

If the storage space of the first type memory 221 is insufficient, the media controller 223 may release the storage space previously mapped to the first type memory 221. If data of the storage space to be released is updated, the media controller 223 may flush the updated data to the second type memory 222.

The SPD device 225 may communicate with an external host device, for example, the memory controller 211 or the processor 210 through a corresponding channel among the auxiliary channels SCH. For example, when the first memory module 220 is initialized, the SPD device 225 transmits the stored information to an external host device, for example, the memory controller 211 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 210 may provide the processor 210.

For example, the SPD device 225 may store information about a storage capacity provided to an external host device, for example, the memory controller 211 or the processor 210 as a storage space of the first memory module 220. have. For example, the SPD device 225 may store information about a storage capacity of the second type memory 222. Upon initialization, the SPD device 225 may provide information about the storage capacity of the second type memory 222 to an external host device, for example, the memory controller 211 or the processor 210.

For example, the capacity information stored in the SPD device 225 may include information about a user capacity of the second type memory 222. The storage capacity of the second type memory 222 may include a user capacity, a meta capacity, and a spare capacity. The user capacity may be a storage capacity provided by the second type memory 222 to an external host device, for example, the memory controller 211.

The meta capacity stores various meta information for managing the second type memory 222 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 211. The spare capacity is reserved for managing the second type memory 222 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 211.

The capacity information stored in the SPD device 225 may include information about a user capacity of the second type memory 222. Hereinafter, unless otherwise specified, the capacity of the second type memory 222 may be understood to indicate the user capacity of the second type memory 222.

The third memory module 240 may include a first type memory 241 and a serial presence detection (SPD) device 245. The fourth memory module 250 may include a first type memory 251 and a serial presence detection (SPD) device 255. Hereinafter, the second type memory modules 240 and 250 will be described with reference to the third memory module 240.

The first type memory 241 may include a dynamic random access memory like the first type memory 221 of the first memory module 220. The SPD device 245 may communicate with an external host device, for example, the memory controller 211 or the processor 210 through a corresponding channel among the auxiliary channels SCH. For example, when the third memory module 240 is initialized, the SPD device 245 transmits the stored information to an external host device, for example, the memory controller 211 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 210 may provide the processor 210.

For example, the SPD device 225 may store information about a storage capacity provided to an external host device, for example, the memory controller 211 or the processor 210 as a storage space of the third memory module 240. have. For example, the SPD device 245 may store information about a storage capacity of the first type memory 241. At initialization, the SPD device 245 may provide information on the storage capacity of the first type memory 241 to an external host device, for example, the memory controller 211 or the processor 210.

When power is supplied to the memory system 200, the memory controller 211 may perform initialization with the first to fourth memory modules 220 to 250. For example, the SPD devices 225 to 255 of the first to fourth memory modules 220 to 250 may provide capacity information to the memory controller 211 through auxiliary channels SCH, respectively.

The SPD devices 225 and 235 of the first type memory modules 220 and 230 may provide the storage controllers of the second type memories 222 and 232 to the memory controller 211, respectively. The SPD devices 245 and 255 of the second type memory modules 240 and 250 may provide the storage controllers of the first type memories 241 and 251 to the memory controller 211, respectively. For example, the memory controller 211 may read storage capacities from the SPD devices 225 to 255, respectively.

14 shows an example in which the processor 210 accesses the first and third memory modules 220 and 240. In order to avoid unnecessary complexity of the drawings, components other than the processor 210, the first memory module 220, and the third memory module 240 are omitted.

13 and 14, the processor 210 may include first to nth cores CORE1 to COREn. In other words, the processor 210 may be a multi-core processor. The entities executed by the first to nth cores CORE1 to COREn are shown in the execution area EA.

 Referring to the execution region EA, an operating system (OS) may be executed in the processor 210. In addition, based on the support of the operating system (OS), the first to third applications APP1 to APP3 may be executed in the processor 210.

The operating system (OS) may include a machine check exception handler (MCEH). The machine check exception processor MCEH may handle an error that occurs when the memory controller 211 accesses the first to fourth memory modules 220 to 250. The operation of the machine check exception handler MCEH is described in more detail with reference to FIG. 15.

The memory controller 211 may access the first to fourth memory modules 220 to 250 according to a request of the first to nth cores CORE1 to COREn. For example, the memory controller 211 may access the first memory module 220 through the first main channel MCH1, and may access the third memory module 240 through the second main channel MCH2. have.

15 is a flowchart illustrating a method of operating a memory system 200 according to a first example of the present invention. 13 to 15, in step S110, the memory controller 211 may read data from one of the first to fourth memory modules 220 to 250. For example, the memory controller 211 may read data at the request of the first to third applications APP1 to APP3 or the operating system OS.

In operation S120, the memory controller 211 may detect an uncorrectable error. For example, the memory controller 211 may perform error correction decoding on the read data. The memory controller 211 may correct the error or detect an uncorrectable error according to the result of the error correction decoding.

For example, when the read data includes error bits that exceed the number of error bits that are corrected by error correction decoding, an uncorrectable error may be detected. For example, the memory controller 211 may perform read retries a specific number of times. If an uncorrectable error is detected even when the read retry is repeatedly performed, exception handling may be performed.

For example, exception processing may be performed by having one of the first to n th cores CORE1 to COREn of the processor 210 reach and execute the machine check exception handler MCEH. The exception processing may include steps S230 to S180.

In operation S230, the machine check exception processor MCEH may perform a machine check. For example, the machine test may include determining whether the memory controller 211 or the first memory module 220 operates normally or malfunctions. Machine inspection may include determining whether the detected error is a fatal error or a catastrophic error.

For example, if an uncorrectable error occurs in critical data, a disaster error can be determined. Data necessary for controlling or operating the memory system 200 may be important data. Data requested by the first to third applications APP1 to APP3 or the operating system OS and used by the first to third applications APP1 to APP3 or the operating system OS may be important data.

For example, if an uncorrectable error occurs in noncritical data, a fatal error can be determined. Data unrelated to the control or operation of the memory system 200 may be insignificant data. Data requested by the first to third applications APP1 to APP3 or the operating system OS and not used by the first to third applications APP1 to APP3 or the operating system OS may be insignificant data. .

In operation S240, if uncorrectable data is a significant error, the machine check exception processor MCEH performs operation S250. In operation S240, the machine check exception processor MCEH may record that a catastrophic error has occurred in the error log. Subsequently, in step S160, a system reboot or kernel panic of the memory system 200 may occur.

In operation S240, if the uncorrectable data is a non-critical error, the machine check exception processor MCEH performs operation S170. In operation S170, the machine check exception processor MCEH may record that a fatal error has occurred in the error log.

16 illustrates an example of reading data from the first memory module 220. 13 and 16, in operation S111, for example, the first application APP1 may transmit a read request for the first memory module 220 to the memory controller 211. The read request may be transmitted to the memory controller 211 through the operating system OS and the first to n th cores CORE1 to COREn.

In operation S112, in response to the read request, the memory controller 211 may transmit a read command to the first memory module 220. In operation S113, the read command may cause access to the second type memory 222. For example, when the data corresponding to the read command is not mapped in the first type memory 221, the media controller 223 reads the corresponding data from the second type memory 222 and the first type memory 221. Can be mapped to

The procedure of accessing the first memory module 220 by the memory controller 211 is the same as the procedure of accessing the third memory module 240. For example, the time condition until the memory controller 211 receives the data after transmitting the read command to the first memory module 220 is adapted to the access speed of the first type memory 221 or 241. .

The access speed of the second type memory 222 is slower than that of the first type memory 221. Therefore, in operation S114, a timeout may occur in which data is not read from the second type memory 222 until the time according to the time condition of the memory controller 211 elapses.

For example, although the first memory module 220 does not transmit data to the first main channel MCH1, the memory controller 211 may detect data from voltages of the first main channel MCH1. . In this case, the memory controller 211 may determine that data having an uncorrectable error has been received.

As another example, as time passes according to a time condition, the first memory module 220 may transmit dummy data to the first main channel MCH1. The memory controller 211 may receive dummy data through the first main channel MCH1. The memory controller may determine that the dummy data has an uncorrectable error. For example, the dummy data may be data having a specific pattern or data having an arbitrary pattern.

17 shows an example in which exception processing is performed on the first memory module 220. By way of example, FIG. 17 shows operations subsequent to step S114 of FIG. 16. 13 and 17, in step S115, the memory controller 211 receives data having an uncorrectable error UE from the first memory module 220.

For example, as mentioned above, the media controller 223 may not transmit data to the memory controller 211 or may transmit dummy data to the memory controller 211. The memory controller 211 may perform error correction decoding on the read data, and determine that the read data has an uncorrectable error.

If an uncorrectable error is detected, in operation S116, the memory controller 211 may output an interrupt signal IRQ. The interrupt signal IRQ may be transmitted to at least one core of the first to nth cores CORE1 to COREn. The interrupt signal IRQ may be transmitted to the first application APP1 or the operating system OS of the execution area EA through at least one core.

In response to the interrupt signal IRQ, in operation S117, context switching may occur from the first application APP1 to the operating system OS or the machine check exception processor MCEH. The operating system (OS) or the machine check exception handler (MCEH) generates an exception broadcast indicating that exception handling is required by generating an exception in the first to nth cores CORE1 to COREn. Can be done.

For example, the exception broadcast may be a call in which the first to nth cores CORE1 to COREn call to execute the machine check exception handler MCEH. According to the exception broadcast, the first to n th cores CORE1 to COREn may stop operations currently performed and access the machine check exception processor MCEH.

For example, currently performing operations may include processes, threads, tasks, operations, series of codes or instructions. Each action may have one or more breakpoints. At each breakpoint, the core performing the action may be allowed to stop and resume performing the action.

One core of the first to n th cores CORE1 to COREn may execute the machine check exception processor MCEH to perform exception processing. The core performing the exception processing may be a monarchy core. The cores other than the monarch core among the first to nth cores CORE1 to COREn may not execute the machine check exception processor MCEH.

The memory controller 211 accesses the first type memory 221 of the first memory module 220. The first type memory 221 is a cache memory of the second type memory 222. Uncorrectable data read from the first memory module 220 means that the data stored in the first type memory 221 has an uncorrectable error or that the data is not mapped in the first type memory 221. do.

If the corresponding data stored in the first type memory 221 has an uncorrectable error, the error may be healed by rewriting the corresponding data stored in the second type memory 222 into the first type memory 221. If the data is not mapped in the first type memory 221, the error may be healed by mapping the data stored in the second type memory 222 to the first type memory 221.

That is, when access to the second type memory 222 is completed, accurate data may be read from the first memory module 220. However, according to the method described with reference to FIG. 15, when an access to the second type memory 222 occurs in the first memory module 220, the memory system 200 (see FIG. 1) may enter a kernel panic or system reboot. You can enter.

In order to prevent a kernel panic or a system reboot from occurring when an access to the second type memory 222 occurs in the first memory module 220, the memory system 200 according to an embodiment of the present invention may include a first memory module. Exception processing of the memory module 220 may be performed according to a second example different from the first example.

18 is a flowchart illustrating an operating method according to a second example of the present invention. 1, 17, and 18, steps S121 to S123 may be performed in the same manner as step S230 in step S110 of FIG. 15. Therefore, duplicate descriptions of the steps S121 to S123 are omitted.

In operation S124, the machine check exception processor MCEH may record that an error associated with the first memory module 220 has occurred in the error log. For example, the machine check exception handler (MCEH) can log fatal or disaster errors in the error log. For example, step S124 may be selectively performed. Step S124 may be performed or not performed and may be omitted. For example, in the machine inspection of step S123, the function of determining whether the detected error is a fatal error or a disaster error may be omitted.

When the exception processing is completed, context switching is performed from the machine check exception processor MCEH to the first application APP1. As described in operation S111 of FIG. 16, the first application APP1 may transmit a read request to the first memory module 220 again.

A first time may be spent in context switching (step S117 of FIG. 17) from the first application APP1 to the machine check exception processor MCEH. The second time may be spent on the mechanical inspection (step S123). A third time may be spent switching the context from the machine check exception processor MCEH to the first application APP1.

While the first time, the second time, and the third time pass, the media controller 223 reads data corresponding to the read command (see step S112 of FIG. 16) from the second type memory 222 to the first type memory ( 221). Therefore, when the memory controller 211 retransmits the read command to the first memory module 220 as the first application APP1 retransmits the read request, the memory controller 211 may correct the read command from the first memory module 220. The data can be read.

As described with reference to FIG. 18, the machine check exception handler MCEH does not determine a fatal error or a catastrophic error at the time of exception processing for the first memory module 220, and as a kernel panic or system reboot. Do not enter. Thus, even if access to the second type memory 222 occurs in the first memory module 220, the memory system 200 does not experience a kernel panic or system reboot, and therefore the memory system 200 may correct the first memory module 220. Data can be obtained.

For example, exception processing according to the second example described with reference to FIG. 18 may be applied to the first type memory modules 220 and 230. Also, exception processing according to the first example described with reference to FIG. 15 may be applied to the second type memory modules 240 and 250.

19 shows an example where a monarch core is assigned. For example, an example in which the monarch core is allocated among the first to fourth cores CORE1 to CORE4 is illustrated in FIG. 19. 17 and 19, the first to fourth cores CORE1 to CORE4 may stop operations currently being performed according to the exception broadcast (step S118).

However, timings at which the first to fourth cores CORE1 to CORE4 may stop the operations may vary according to the types of operations that the first to fourth cores CORE1 to CORE4 are performing. For example, the stopping points of the threads in which the first to fourth cores CORE1 to CORE4 are running may be different.

In exemplary embodiments, the first core CORE1 of the first to fourth cores CORE1 to CORE4 may stop an operation that is being performed first and respond to the call. The first core CORE1, which first responds to the call, may be considered to have reached the machine check exception handler MCEH first.

The first core CORE1 that first reaches the machine check exception handler MCEH may be designated (or assigned) as a monarchy core. The first core CORE1 may execute the machine check exception processor MCEH to perform the exception processing described with reference to FIG. 15 or 18.

20 shows a first example in which the remaining cores are managed. Referring to FIG. 20, the second to fourth cores CORE2 to CORE4 may reach the machine check exception processor MCEH later than the first core CORE1. In exemplary embodiments, the second to fourth cores CORE2 to CORE4 may wait until the first core CORE1 completes the exception processing.

The second to fourth cores CORE2 to CORE4 may be waiting cores. When the first core CORE1 completes the exception processing, the first to fourth cores CORE1 to CORE4 may return to previously performed operations. For example, when the exception processing is completed without kernel panic or system reboot, the first to fourth cores CORE1 to CORE4 may return to operations previously performed.

As with the exception handling described with reference to FIG. 18, if the exception handling is completed without a kernel panic or system reboot, waiting for the second to fourth cores CORE2 to CORE4 causes a waste of resources. To prevent this, the memory system 200 according to an embodiment of the present invention provides a new algorithm for removing waiting cores.

21 shows an example of managing cores for exception handling according to an embodiment of the present invention. 17 and 21, in step S131, the operating system OS or the machine check exception processor MCEH may call cores CORE1 to COREn through an exception broadcast (step S118).

In step S232, the operating system (OS) or machine check exception handler (MCEH) may detect the arrival of the core. For example, when a particular core stops executing an action and responds to a call, it may be considered that the particular core has arrived. In operation S430, the operating system (OS) or the machine check exception processor (MCEH) may determine whether the arrived core is the first core.

In step S430, if the arrived core is the first core, step S440 is performed. In operation S440, the operating system (OS) or the machine check exception handler (MCEH) may allocate (or designate) the arrived core to the machine check exception processing. For example, the arriving core may perform exception handling by executing the code of the machine check exception handler (MCEH). For example, the arriving core may perform exception processing in accordance with the method described with reference to FIG. 15 or 18.

In step S430, if the arrived core is not the first core, step S450 is performed. In operation S450, the operating system OS or the machine check exception processor MCEH may return the arrived core to the stopped operation. The arriving core may return to the suspended operation and resume the suspended operation.

22 shows a second example in which the remaining cores are managed. For example, in FIG. 19, an example in which the remaining cores are managed after the first core CORE1 is designated as the monarch core is illustrated in FIG. 22. 13 and 22, the second to fourth cores CORE2 to CORE4 may reach the machine check exception processor MCEH later than the first core CORE1.

In exemplary embodiments, the second core CORE2 may reach the second machine inspection exception handler MCEH after the first core CORE1. Recognizing that the first core CORE1 is already designated as the monarch core, the second core CORE2 may return to the stopped operation and resume the stopped operation (see step S450 of FIG. 21). For example, the second core CORE2 may execute codes of the stopped operation from the stop point of the stopped operation.

Similarly, the third and fourth cores CORE3 and CORE4 may reach the machine check exception handler MCEH later than the first core CORE1. Recognizing that the first core CORE1 is already designated as the monarch core, the third and fourth cores CORE3 and CORE4 may return to the suspended operations, respectively, and resume the suspended operations, respectively ( See step S450 of FIG. 21).

As described with reference to FIG. 18, during exception processing for the first memory module 220, no kernel panic or system reboot occurs. When the exception processing for the first memory module 220 is completed, the monarch core returns to the stopped operation. Since the kernel panic or the system reboot does not occur during the exception processing for the first memory module 220, the second to fourth cores CORE2 to CORE4 need not wait for the completion of the exception processing.

Therefore, the second to fourth cores CORE2 to CORE4 may return to suspended operations while the first core CORE1 performs the exception processing. By returning earlier to the stopped operations of the second to fourth cores CORE2 to CORE4, waste of resources of the second to fourth cores CORE2 to CORE4 is prevented, and the performance of the memory system 200 is reduced. This is improved.

In exemplary embodiments, the first type memory modules 220 and 230 store (or back up) data in the second type memories 222 and 232, and the media controllers 223 and 233 may store the second type memories. Separate error correction means for 222, 232. Accordingly, the first type memory modules 220 and 230 may guarantee error free data.

That is, as described with reference to FIG. 18, a method in which kernel panic or system reboot does not occur during exception handling may be applied to the first type memory modules 220 and 230. In addition, as described with reference to FIG. 22, the method of returning to the operations in which the second to fourth cores CORE2 to CORE4 are suspended while the first core CORE1 performs exception processing is the first type. It may be applied to the memory modules 220 and 230.

On the other hand, the second type memory modules 240 and 250 may include only the first type memories 241 and 251 and may not include its own error correction means for the first type memories 241 and 251. have. Therefore, an uncorrectable error may occur in data stored in the second type memories 241 and 251.

That is, as described with reference to FIG. 15, a method of generating a kernel panic or a system reboot during exception handling may be applied to the second type memory modules 240 and 250. In addition, as described with reference to FIG. 20, the second to fourth cores CORE2 to CORE4 wait for a kernel panic or system reboot while the first core CORE1 performs an exception processing. The first type memory modules 220 and 230 may be applied.

FIG. 23 shows an example in which other exception processing occurs while the first core CORE1 performs exception processing. 13 and 23, while the first core CORE1 performs an exception process on the uncorrectable first error UE1 occurring in the first memory module 220, the second to fourth memory modules are processed. An uncorrectable second error UE2 may occur in one of the memory modules 230 to 250.

As described with reference to FIG. 17, the exception broadcast S118 may be performed on the second non-correctable error UE2, and cores CORE1 to CORE4 may be called. The first core CORE1 that performs exception processing may not respond to the call. The second to fourth cores CORE2 to CORE4 that do not perform exception processing may respond to the call.

For example, the fourth core CORE4 may respond first to the call, thereby reaching the machine check exception handler MCEH first. Therefore, the fourth core CORE4 may be designated (or assigned) as the monarch core for the second error UE2 that cannot be corrected. The fourth core CORE4 may perform exception processing on the second error UE2 that cannot be corrected.

FIG. 24 shows an example in which the first core CORE1 completes the exception processing following the state of FIG. 23. Referring to FIGS. 13 and 24, the first core CORE1 may complete the exception processing while the fourth core CORE4 performs exception processing on the second error UE2 that cannot be corrected. When the exception processing is completed, the first core CORE1 may return to the stopped operation (or an operation previously performed) regardless of whether the fourth core CORE4 performs the exception processing.

If the first core CORE1 returns to the stopped operation without waiting until the exception processing of the fourth core CORE4 is completed, resource waste of the memory system 200 is further prevented, and Performance can be further improved.

FIG. 25 illustrates a first example of an error signal CAT_ERR_N generated by the cores CORE1 to COREn or the processor 210. 13 and 25, the error signal CAT_ERR_N may be controlled in the form of the first line C1 or the second line C2.

For example, when the memory controller 211 detects an uncorrectable error, the error signal CAT_ERR_N may transition from the high level to the low level. If the uncorrectable error is a fatal error that is not a catastrophic error, the error signal CAT_ERR_N may transition from the low level to the high level like the first line C1.

If the uncorrectable error is a disaster, the error signal CAT_ERR_N, like the second line C2, may be maintained at a low level until a system reboot is performed. If an uncorrectable error occurs in the first type memory modules 220 and 230, no kernel panic or system reboot occurs as described with reference to FIG. 18.

For example, an uncorrectable error for the first type memory modules 220 and 230 may be treated as a fatal error or no error. Therefore, as described with reference to the first line C1, the error signal CAT_ERR_N may transition from a low level to a high level.

FIG. 26 illustrates a second example of the error signals CAT_ERR_N generated by the cores CORE1 to COREn or the processor 210. 13 and 26, the error signal CAT_ERR_N may be controlled in the form of the third line C3 or the fourth line C4.

For example, when the memory controller 211 detects an uncorrectable error and the uncorrectable error is a fatal error rather than a catastrophic error, the error signal CAT_ERR_N, like the third line C3, may maintain a high level. have.

When the memory controller 211 detects an uncorrectable error and the uncorrectable error is a disaster, the error signal CAT_ERR_N may transition from the high level to the low level as in the fourth line C4. When the system reboot is performed, the error signal CAT_ERR_N may be restored to a high level.

For example, an uncorrectable error for the first type memory modules 220 and 230 may be treated as a fatal error or no error. Therefore, as described with reference to the third line C3, the error signal CAT_ERR_N may maintain a high level.

27 is a block diagram illustrating a memory system 300 according to an exemplary embodiment of the inventive concept. For example, the memory system 300 may include a server such as an application server, a client server, and a data server. As another example, memory system 300 may include a personal computer or workstation.

Referring to FIG. 27, the memory system 300 includes a processor 310, first to fourth memory modules 320 to 350, a root complex 360, and a storage device 370. The processor 310 may control the components of the memory system 300 and operations of the components. The processor 310 may execute an operating system and applications, and process data using the operating system or applications.

The processor 310 may include a memory controller 311 and a cache memory 312. The memory controller 311 may access the first through fourth memory modules 320 ˜ 350 through the main channels MCH and the auxiliary channels SCH. Cache memory 312 may include high speed memory, such as static random access memory (SRAM).

The memory controller 311 may include a register R. The register R may store various information necessary for the memory controller 311 to access the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 by referring to the information stored in the register R. Referring to FIG.

The first to fourth memory modules 320 to 350 may be connected to the memory controller 311 through the main channels MCH and the auxiliary channels SCH. The main channels MCH may be channels used to store data or read data in the memory modules 320 to 350 (eg, semiconductor memory modules). The main channels MCH may include channels provided for the first to fourth memory modules 320 to 350, respectively.

The auxiliary channels SCH may provide additional functions associated with the first to fourth memory modules 320 to 350 in addition to storing or reading data in the first to fourth memory modules 320 to 350. have. For example, the first to fourth memory modules 320 to 350 may provide their own information to the memory controller 311 through the auxiliary channels SCH. The auxiliary channels SCH may include channels provided for the first to fourth memory modules 320 to 350, respectively.

The first to fourth memory modules 320 to 350 may be used as a main memory of the memory system 300. The first to fourth memory modules 320 to 350 may include a memory controller according to one of standards of a memory module such as a dual in-line memory module (DIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), or the like. 311).

The root complex 360 can provide channels through which the processor 310 accesses various peripheral devices. For example, the storage device 370 may be connected to the root complex 360. The storage device 370 may include a hard disk drive, an optical disk drive, a solid state drive, and the like.

In exemplary embodiments, peripheral devices connected to the root complex 360 are not limited to the storage device 370. For example, the root complex 360 can be connected to various devices, such as a modem, graphics processing unit (GPU), neuromorphic processor, and the like.

The processor 310 may hierarchically manage the cache memory 312, the first to fourth memory modules 320 to 350, which are main memories, and the storage device 370. For example, the processor 310 may load necessary data among data stored in the storage device 370 into a main memory including the first to fourth memory modules 320 to 350. The processor 310 may flush data to be backed up to the storage device 370 among data stored in the main memory.

Some of the storage areas of the main memory including the first to fourth memory modules 320 to 350 may be mapped to the cache memory 312. When the processor 310 needs to access a specific storage space of the main memory, the processor 310 may determine whether the specific storage space is mapped to the cache memory 312.

If a particular storage space is mapped to the cache memory 312, the processor 310 can access the particular storage space of the cache memory 312. If a particular storage space is not mapped to the cache memory, the processor 310 maps (or fetches) the specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312. Can be.

If the storage space of the cache memory 312 is insufficient, the processor 310 may release the storage space previously mapped to the cache memory 312. When data of the storage space to be released is updated, the processor 310 may flush the updated data to the first to fourth memory modules 320 to 350.

The first to fourth memory modules 320 to 350 may include heterogeneous memory modules. For example, the first and second memory modules 320 and 330 may be first type memory modules. The third and fourth memory modules 340 and 350 may be second type memory modules.

The first memory module 320 may include a first type memory 321, a second type memory 322, a media controller 323, and a serial presence detection (SPD) device 325. have. The second memory module 330 may include a first type memory 331, a second type memory 332, a media controller 333, and a serial presence detection (SPD) device 335. . Hereinafter, the first type memory modules 320 and 330 will be described with reference to the first memory module 320.

The first type memory 321 may include high speed volatile memory, for example dynamic random access memory (DRAM). The second type memory 322 may include a nonvolatile memory having a slower speed than the first type memory 321 and having a larger storage capacity than the first type memory 321. For example, the second type memory 322 may include a flash memory, a phase change memory, a ferroelectric memory, a magnetic memory, a resistive memory, and the like. .

The media controller 323 receives the access command from an external host device, for example, the memory controller 311 or the processor 310, transmitted through a corresponding one of the main channels MCH, and the first type memory 321. Alternatively, the data may be transferred to the second type memory 322. According to the access command, the media controller 323 may exchange data with an external host device, for example, the memory controller 311 or the processor 310 through a corresponding channel among the main channels MCH.

 The media controller 323 may provide a storage capacity or a storage space of the second type memory 322 to an external host device, for example, the memory controller 311 or the processor 310. The media controller 323 may use the first type memory 321 as a cache memory of the second type memory 322.

For example, the media controller 323 may map some of the storage spaces of the second type memory 322 to the first type memory 321. If the storage space associated with an access command from an external host device, such as the memory controller 311 or the processor 310, is mapped to the first type memory 321, the media controller 323 issues the first access command. It may be transferred to the type memory 321.

If the storage space associated with an access command from an external host device, for example, the memory controller 311 or the processor 310, is not mapped in the first type memory 321, the media controller 323 may not be able to store the storage space. Mapping (or backup) from the second type memory 322 to the first type memory 321 may be performed.

If the storage space of the first type memory 321 is insufficient, the media controller 323 may release the storage space previously mapped to the first type memory 321. If data of the storage space to be released is updated, the media controller 323 may flush the updated data to the second type memory 322.

The SPD device 325 may communicate with an external host device, for example, the memory controller 311 or the processor 310 through a corresponding channel among the auxiliary channels SCH. For example, when the first memory module 320 is initialized, the SPD device 325 transmits the stored information to an external host device, for example, the memory controller 311 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 310 may provide the processor 310 with the processor 310.

For example, the SPD device 325 may store information about a storage capacity provided to an external host device, for example, the memory controller 311 or the processor 310 as a storage space of the first memory module 320. have. For example, the SPD device 325 may store information about a storage capacity of the second type memory 322. Upon initialization, the SPD device 325 may provide information about the storage capacity of the second type memory 322 to an external host device, for example, the memory controller 311 or the processor 310.

For example, the capacity information stored in the SPD device 325 may include information about a user capacity of the second type memory 322. The storage capacity of the second type memory 322 may include a user capacity, a meta capacity, and a spare capacity. The user capacity may be a storage capacity provided by the second type memory 322 to an external host device, for example, the memory controller 311.

The meta capacity stores various meta information for managing the second type memory 322 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 311. The spare capacity is reserved for managing the second type memory 322 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 311.

The capacity information stored in the SPD device 325 may include information about a user capacity of the second type memory 322. Hereinafter, unless otherwise specified, it may be understood that the capacity of the second type memory 322 refers to the user capacity of the second type memory 322.

The third memory module 340 may include a first type memory 341 and a serial presence detection (SPD) device 345. The fourth memory module 350 may include a first type memory 351 and a serial presence detection (SPD) device 355. Hereinafter, the second type memory modules 340 and 350 will be described with reference to the third memory module 340.

The first type memory 341 may include a dynamic random access memory like the first type memory 321 of the first memory module 320. The SPD device 345 may communicate with an external host device, for example, the memory controller 311 or the processor 310 through a corresponding channel among the auxiliary channels SCH. For example, when the third memory module 340 is initialized, the SPD device 345 transmits the stored information to an external host device, for example, the memory controller 311 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 310 may provide the processor 310 with the processor 310.

For example, the SPD device 325 may store information on a storage capacity provided to an external host device, for example, the memory controller 311 or the processor 310 as a storage space of the third memory module 340. have. For example, the SPD device 345 may store information about a storage capacity of the first type memory 341. Upon initialization, the SPD device 345 may provide information about the storage capacity of the first type memory 341 to an external host device, for example, the memory controller 311 or the processor 310.

When power is supplied to the memory system 300, the memory controller 311 may perform initialization with the first to fourth memory modules 320 to 350. For example, the SPD devices 325 to 355 of the first to fourth memory modules 320 to 350 may provide capacity information to the memory controller 311 through auxiliary channels SCH, respectively.

The SPD devices 325 and 335 of the first type memory modules 320 and 330 may provide the storage controllers of the second type memories 322 and 332 to the memory controller 311, respectively. The SPD devices 345 and 355 of the second type memory modules 340 and 350 may provide the storage controllers of the first type memories 341 and 351 to the memory controller 311, respectively. For example, the memory controller 311 may read storage capacities from the SPD devices 325 to 355, respectively.

In the above-described embodiment, the storage device 370 is shown connected to the root complex 360. However, the device connected to the root complex 360 is not limited to the storage device 370.

28 illustrates an example in which the processor 310 accesses the first and third memory modules 320 and 340. In order to prevent unnecessary drawings, components other than the processor 310, the first memory module 320, and the third memory module 340 are omitted.

Referring to FIGS. 27 and 27, an execution area EA is shown that shows objects executed in the processor 310. Referring to the execution area EA, an operating system (OS) may be executed in the processor 310. In addition, based on the support of the operating system (OS), the first to third applications APP1 to APP3 may be executed in the processor 310.

The operating system OS may include a page fault processor PFH. The page absence processor PFH may handle a page fault that occurs when the first to third applications APP1 to APP3 access the first and third memory modules 320 and 340. . The operation of the page member processor PFH is described in more detail with reference to FIGS. 29 and 30.

The first memory module 320 provides a storage space of the second type memory 322 to the processor 310. The storage space corresponding to the user capacity of the first memory module 320 is shown as the first storage area SA1. The first storage area SA1 may include first to third sub storage areas SA1_1 to SA1_3.

The first to third sub storage areas SA1_1 to SA1_3 belong to a storage space of the second type memory 322, and may be logical or physically distinct storage areas. The first to third sub storage areas SA1_1 to SA1_3 may be accessed by different addresses.

In addition to the first storage area SA1, the storage space corresponding to the meta capacity of the first memory module 320 is illustrated as the first meta storage area SA1_M. The media controller 323 may store various information necessary for accessing the first storage area SA1 in the first meta storage area SA1_M.

The third memory module 340 provides the processor 310 with a storage space of the first type memory 341. The storage space of the third memory module 340 is illustrated as a second storage area SA2. The second storage area SA2 may be smaller than the first storage area SA1.

When the memory system 300 is initialized, the memory controller 311 of the processor 310 may identify storage spaces of the first through fourth memory modules 320 ˜ 350 through the auxiliary channels SCH. The processor 310, for example the operating system OS, may assign addresses, eg, virtual addresses VA, to the identified storage spaces.

The processor 310, for example, the operating system OS, may access the first storage area SA1 and the second storage area SA2 using the virtual addresses VA. The processor 310, for example, the operating system OS, may store the storage space of the first to fourth memory modules 320 to 350 by using the virtual addresses VA. ) Can be assigned.

The memory controller 311 may receive an access command based on the virtual addresses VA from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first through fourth memory modules 320 ˜ 350 through the main channels MCH based on actual addresses. For example, the memory controller 311 may access the first and third memory modules 320 and 3400 through the first and second main channels MCH1 and MCH2, respectively.

The memory controller 311 uses the mapping information of the virtual addresses VA allocated by the processor 310 and the actual addresses of the first to fourth memory modules 320 to 350 as a page table PT. May be stored in module 340. The page table PT may include first to fourth tables T1 to T4 corresponding to the first to fourth memory modules 320 to 350, respectively.

In exemplary embodiments, the memory controller 311 may store the page table PT in one of the second type memory modules 340 and 350. As another example, the memory controller 311 may store the page table PT in one of the first to fourth memory modules 320 to 350. For example, the memory controller 311 may store the first to fourth tables T1 to T4 of the first to fourth memory modules 320 to 350 in one memory module.

The second type memory modules 340 and 350 are directly accessed by the memory controller 311. The addresses used by the memory controller 311 when accessing the second type memory modules 340 and 350 may be physical addresses PA of the first type memories 341 and 351. Thus, the third and fourth tables T3 and T4 for the second type memory modules 340 and 350 are the virtual addresses VA and the physical addresses of the second type memory modules 340 and 350. (PA) may include mapping information.

The first type memory modules 320 and 330 are not directly accessed by the memory controller 311. The memory controller 311 accesses the first type memory modules 320 and 330 through the media controllers 323 and 333. The addresses used by the memory controller 311 when accessing the first type memory modules 320 and 330 are not the physical addresses PA of the second type memories 322 and 332, and the logical addresses LA. It can be called).

The media controller 323 or 333 stores mapping information between the logical addresses LA used by the memory controller 311 and the physical addresses PA of the second type memory 322 or 332. SA1_M). Using the mapping information stored in the first meta storage area SA1_M, the media controller 323 or 333 may convert an access command from the memory controller 311 into an access command for the second type memory 322 or 332. Can be.

Since the memory controller 311 uses the logical addresses LA of the first type memory modules 320 and 330, the first and second tables T1 for the first type memory modules 320 and 330 are used. , T2 may include mapping information between the virtual addresses VA and the logical addresses LA.

The memory controller 311 may store information about the start address of the storage space of the third memory module 340 in which the page table PT is stored and the size of the page table PT in the register R. When the operating system OS or the first to third applications APP1 to APP3 instruct access to the first to fourth memory modules 320 to 350 based on the virtual addresses VA, a memory controller. 311 may search the page table PT with reference to the register R, and transmit an access command to the first to fourth memory modules 320 to 350 according to the search result.

29 shows an example in which a page fault occurs. Referring to FIGS. 27 and 29, in operation S211, the first application APP1 may instruct a memory access to the first memory module 320. Instructions of the first application APP1 may be transmitted to the memory controller 311 through the operating system OS. In operation S212, the memory controller 311 may search the page table PT with reference to the register R. FIG.

If the mapping information of the virtual addresses VA of the first memory module 320 requested for memory access does not exist in the first table T1, a page fault may occur in step S213. For example, when the first application APP1 requests allocation of a new memory, the operating system OS may instruct the memory controller 311 to access a memory for allocation of the memory.

Since the allocation of a new memory that has not been used previously is requested, the mapping information may not exist in the first table T1. That is, when a new memory allocation is performed, a page fault may occur. For example, when execution of the first application APP1 starts, allocation of a new memory is requested and a page member may occur. When a page absence occurs, in operation S214, context switching may be performed from the first application APP1 to the operating system OS.

30 shows an example in which fault handling is performed. Referring to FIG. 30, in operation S215, the page member processor PFH of the operating system OS may perform a member process. For example, the page absence processor PFH may map the logical address LA of the free page of the first memory module 320 to the virtual address VA requested by the first application APP1.

For example, when the free capacity of the first to fourth memory modules 320 to 350 is insufficient, the processor 310 may delete a portion of data stored in the first storage area SA1 of the first memory module 320. By swapping the storage device 370 and releasing the storage space of the swapped data, free capacity can be secured in the first storage area SA1.

The mapped logical address LA may be allocated to the first storage area SA1 as the first application storage area SA_APP1 for the first application APP1. In operation S216, the memory controller 311 may update the page table by writing mapping information of the first application storage area SA_APP1 to the first table T1 of the page table PT. In operation S217, context switching may be performed from the page absence processor PFH to the first application APP1 after the absence processing is completed.

As described with reference to Figs. 29 and 30, when a page member occurs and the member processing is performed, two context exchanges are performed. Contextual exchanges consume resources of the memory system 300 and can hinder the speed of operation of the memory system 300.

FIG. 31 shows an example in which a virtual storage area VSA identified by virtual addresses of '01' to '16' is allocated to the first application APP1. Referring to FIGS. 27 and 31, in operation S221, the first application APP1 may instruct access to the virtual address VA of '01' of the virtual storage area VSA. For example, the virtual address VA of '01' may correspond to the first memory module 320.

Since the mapping information of the virtual address VA of '01' does not exist in the first table T1 (see FIG. 29), a page member may occur in step S222. The context exchange can then be performed and the page fault handler PFH can be activated. In step S223, the page member processor PFH may perform the member processing.

For example, the page member processor PFH may map a logical address LA of '21' of the first application storage area SA_APP1 to a virtual address VA of '01'. The logical address LA of '21' may correspond to the first memory module 320. In step S224, the page absence processor PFH may perform a page table update on the first table T1 to include mapping information of the virtual address VA of '01' and the logical address LA of '21'. Can be.

32 shows an example in which virtual addresses VA are allocated according to the first embodiment subsequent to FIG. 31. Referring to FIG. 32, in operation S231, the first application APP1 may access a next page having a virtual address VA of '02' of the virtual storage area VSA. The page member may occur in step S232, and the member processing may be performed in step S233.

The page absence processor PFH may allocate a logical address LA of '22' of the first application storage area SA_APP1 to a virtual address VA of '02'. In step S234, the page absence processor PFH may perform a page table update on the first table T1 to include mapping information of the virtual address VA of '02' and the logical address LA of '22'. Can be. As described with reference to FIGS. 31 and 32, the first application APP1 may sequentially request access to virtual addresses VA of '01' to '16'.

33 illustrates an example in which the page absence processor PFH performs page absence processing on virtual addresses VA of '01' to '16' according to the first embodiment. Referring to FIG. 33, through step S241, step S242, and step S243, the page member processor PFH stores the first application in virtual addresses VA of '01' to '16' of the virtual storage area VSA. The logical addresses LA of '21' to '36' of the area SA_APP1 may be mapped. The page absence processor PFH may perform page absence processing for each of the virtual addresses VA of '01' to '16'.

Typically, the size of the page may be 4 KB. The memory capacity used by the first application APP1 may be several MB to several GB. As large storage class memories such as the first type memory modules 320 and 330 are introduced, the memory capacity used by the first application APP1 may be further increased.

When the first application APP1 allocates a large memory, performing the absence processing in units of 4 KB pages consumes excessive resources of the processor 310 and speeds up the operation of the processor 310 and the memory system 300. Can be significantly inhibited. In order to solve such a problem, the processor 310 (or the operating system OS) according to an embodiment of the present invention may perform the absence processing of less than the number of pages for which the first application APP1 requests access. Can be.

34 is a view illustrating a member treating method according to a second embodiment of the present invention. 28 and 34, in step S251, the page member processor PFH may adjust the number of pages. In step S252, the page absence processor PFH may allocate pages according to the adjusted number of pages. In operation S253, the page absence processor PFH may update the page table PT according to the allocation.

 For example, the page member processor PFH may adjust the number of pages according to the characteristics of the access where the page member has occurred. The page absence processor PFH may map two or more virtual addresses VA and two or more logical addresses LA in the absence processing associated with a particular access.

When a page fault occurs due to accesses to consecutive virtual addresses, such as memory allocation, the page fault handler PFH determines the number of virtual addresses VA and logical addresses LA that are mapped in the absence process. The number can be increased sequentially.

FIG. 35 illustrates an example in which virtual addresses VA are allocated according to the second embodiment subsequent to FIG. 31. Referring to FIG. 35, in operation S261, the first application APP1 may access a next page having a virtual address VA of '02' of the virtual storage area VSA. The page member may be generated in step S262, and the member processing may be performed in step S263.

The page fault handler PFH may map two or more logical addresses to two or more virtual addresses. For example, the page absence processor PFH assigns a logical address LA of '22' of the first application storage area SA_APP1 to a virtual address VA of '02', and a logical address of '23' ( LA) may be mapped to a virtual address VA of '03'.

In step S264, the page absence processor PFH includes mapping information of the virtual address VA of '02' and the logical address LA of '22', and the virtual address VA of '03' and '23'. A page table update may be performed on the first table T1 to include mapping information of the logical address LA of '.

FIG. 36 shows an example in which virtual addresses are allocated according to the second embodiment subsequent to FIG. 35. Referring to FIG. 36, in step S271, the first application APP1 may include a page having a virtual address VA of '02' of a virtual storage area VSA and a page having a virtual address VA of '03'. Can be accessed sequentially.

Since the virtual address VA of '03' is mapped to the logical address LA of '23', a page member does not occur when the first application APP1 accesses the virtual address VA of '03'. . Since the virtual address VA of '04' is not mapped with the logical address LA, in step S272, a page member may occur when the first application APP1 accesses the virtual address VA of '04'. have. In step S273, the member processing may be performed.

The page fault handler PFH may map two or more logical addresses to two or more virtual addresses. For example, the page absence processor PFH allocates a logical address LA of '24' of the first application storage area SA_APP1 to a virtual address VA of '04', and a logical address of '25' ( LA) maps to a virtual address (VA) of '05', assigns a logical address (LA) of '26' to a virtual address (VA) of '06', and assigns a logical address (LA) of '27' to ' It may map to 07 'virtual address (VA).

In step S274, the page absence processor PFH includes the virtual address VA of '05' and the '25' to include mapping information of the virtual address VA of '04' and the logical address LA of '24'. To include mapping information of logical address LA, to include mapping information of virtual address VA of '06' and logical address LA of '26', and to the virtual address VA of '07' and ' A page table update may be performed on the first table T1 to include mapping information of the logical address LA of 27 '.

 As described with reference to FIGS. 35 and 36, the first application APP1 may sequentially increase the number of logical addresses LA and the virtual addresses VA mapped in the absence process. .

FIG. 37 illustrates an example in which the page absence processor PFH performs page absence processing on virtual addresses VA of '01' to '16' according to a second embodiment. Referring to FIG. 37, through step S281, S282, and S283, the page member processor PFH stores the first application in virtual addresses VA of '16' in '01' of the virtual storage area VSA. The logical addresses LA of '21' to '36' of the area SA_APP1 may be mapped. The page absence processor PFH may perform page absence processing for each of the virtual addresses VA of '01', '02', '04', '08', and '16'.

As compared with FIG. 33 according to the first embodiment, the number of times member processing is performed in FIG. 31 according to the second embodiment decreases. Thus, the number of times the context exchange is performed is reduced, and the speed of the processor 310 and the memory system 300 with improved speed is improved by performing the member processes faster.

38 shows an example of adjusting the number of pages according to an embodiment of the present invention. Referring to FIGS. 28 and 38, in step S291, the page absence processor PFH may determine successive accesses (eg, consecutive virtual addresses VA) from an application (eg, APP1) in which the page absence is the same. ) Can be determined.

For example, it may be determined whether the virtual address of the access that caused the page fault is contiguous with the previous virtual address of the previous access. If the page member does not correspond to successive accesses, that is, the virtual address is not contiguous with the virtual address of the previous access, step S292 is performed. In operation S292, the page absence processor PFH may adjust the number of pages to a default value, for example, '1'. The adjustment then ends.

If the page member corresponds to consecutive accesses, that is, the virtual address is contiguous with the virtual address of the previous access, step S293 is performed. In operation S293, the page member processor PFH may determine whether the number of pages reaches a threshold. If the number of pages does not reach the threshold, step S294 is performed. In step S294, the page absence processor PFH may adjust the number of pages to twice the number of previous allocated pages. The adjustment then ends.

If the number of pages has reached the threshold, step S295 is performed. In step S295, the page absence processor PFH may adjust the number of pages to the number of previous allocated pages. For example, the page member processor PFH can keep the number of pages the same as in previous member processing. The adjustment then ends.

By way of example, the page member processor PFH is not limited to doubling the number of pages. The page member processor PFH may increase the number of pages by a predetermined number. For example, the page member processor PFH may increase the number of pages by '2' or '4' when member processing is performed in association with successive accesses.

As an example, the page fault processor PFH may perform debt processing associated with successive accesses by splitting it into two or more phases. In the first phase, the page absence processor PFH may adjust the number of pages by K times the number of previous allocated pages (K is a positive integer). In the second phase, the page absence processor PFH may adjust the number of pages to the number of previous allocated pages plus I (I is a positive integer).

In the above-described embodiments, the page member processor PFH performs the member processing on the first memory module 320 according to the second embodiment described with reference to FIGS. 31, 35, 36, and 37. Was explained. However, the member processing according to the second embodiment described with reference to FIGS. 31, 35, 36, and 37 may be applied to all of the first to fourth memory modules 320 to 350.

For example, when the member processing according to the second embodiment described with reference to FIGS. 31, 35, 36, and 37 is applied to the second type memory modules 340 and 350, FIGS. The logical addresses LA mentioned in FIGS. 36 and 37 may be changed to physical addresses PA of the third memory module 340 or the fourth memory module 350.

In exemplary embodiments, the page member processor PFH may set a method of member processing differently according to types of memory modules. For example, when a page member occurs in the first type memory modules 320 and 330, the page member processor PFH may be configured in the second embodiment described with reference to FIGS. 31, 35, 36, and 37. According to the member processing can be performed.

When a page member occurs in the second type memory modules 340 and 350, the page member processor PFH may perform the member processing according to the first embodiment described with reference to FIGS. 31, 32, and 33. have. For example, types of the first to fourth memory modules 320 to 350 may be provided from the SPD devices 325, 335, 345, and 355 to the processor 310 at initialization.

39 shows an example in which the result of the member processing is transferred to the first memory module 320. By way of example, after the member processing described with reference to FIGS. 29 and 30 is completed, the procedures shown in FIG. 39 may be performed. Referring to FIGS. 27 and 39, in step S218, the page absence processor PFH may perform the absence notification.

For example, the page absence processor PFH may instruct the memory controller 311 to transmit the mapped logical address LA to the first memory module 320 associated with the logical address LA during the absence processing. have. The memory controller 311 may transmit the mapped logical address LA to the media controller 323 of the first memory module 320.

For example, the memory controller 311 may instruct a read operation by transmitting a read command and a read address to the first memory module 320. The memory controller 311 may instruct a write operation by transmitting a write command and a write address to the first memory module 320. The memory controller 311 may transmit the logical address LA to the first memory module 320 in a form different from the read command and the read address and in a form different from the write command and the write address.

In exemplary embodiments, the page absence processor PFH may perform the absence notification whenever the absence processing is performed. As another example, the page absence processor PFH may perform an absence notification when the absence processing associated with consecutive addresses is performed a certain number of times. As another example, the page member processor PFH may perform an absence notification if no other member processing is performed for a specific time after the member processing is performed. The condition under which the page absence processor PFH performs the absence notification may be variously applied and modified.

As mentioned above, the absence process may occur when the first application APP1 requests the allocation of a new memory. When the allocation of the requested memory is completed, the first application APP1 may use the allocated memory. That is, if absence processing is performed for a particular logical address LA, the specific logical address LA can be expected to be accessed.

In operation S219, the media controller 323 may perform cache allocation to map the storage space of the second type memory 322 corresponding to the specific logical address LA to the first type memory 321. For example, as absence processing is performed on the logical addresses LA of the first application storage area SA_APP1 of the second type memory 322, the media controller 323 may perform the first application storage area SA_APP1. May be mapped to the first type memory 321.

When the media controller 323 maps the first application storage area SA_APP1 to the first type memory 321, the cache misses in the first type memory 321 when the first application APP1 accesses the allocated memory. A cache hit does not occur and a cache hit occurs. Thus, the speed of the memory system 300 is improved.

40 is a block diagram illustrating a first type memory module 1100 according to an embodiment of the present invention. In exemplary embodiments, the first type memory module 1100 may be a memory module based on the LRDIMM standard. Referring to FIGS. 1 and 40 or 27 and 40, the first type memory module 1100 may include a volatile memory device 1110, a nonvolatile memory device 1120, a media controller 1130, and a first through a first through first memory modules. 8 data buffers 1141-1148.

The volatile memory device 1110 includes first to fourth volatile memories 1111 to 1114. The first to fourth volatile memories 1111 to 1114 may be formed as packages separated from each other. The first to fourth volatile memories 1111 to 1114 may include dynamic random access memories. The volatile memory device 1110 may be a first type memory 321 or 331.

The nonvolatile memory device 1120 may include first to fourth nonvolatile memories 1121 to 1124. The first to fourth nonvolatile memories 1121 to 1124 may be formed as packages separated from each other. The first to fourth nonvolatile memories 1121 to 1124 may be storage areas identified by different addresses in the nonvolatile memory device 1120. The nonvolatile memory device 1120 may be a second type memory 322 or 332.

The nonvolatile memory device 1120 may be a flash memory device, a phase change memory device, a ferroelectric memory device, a resistive memory device, or a magnetic memory device. And at least one of various nonvolatile memory devices such as magnetoregistive memory devices.

The media controller 1130 may receive a first command and address CA1, a first clock signal CK1, and a first control signal CTRL1 from the memory controller 311. The media controller 1130 may communicate the first to eighth data buffers 1141 to 1148 and the second data signals DQ2. The media controller 1130 accesses the volatile memory device 1110 or the nonvolatile memory device 1120 according to the first command and address CA1, the first clock signal CK1, and the first control signal CTRL1. can do.

The media controller 1130 transmits the second command and address CA2, the second clock signal CK2, and the second control signal CTRL2 to the volatile memory device 1110, and the volatile memory device 1110 and the first control signal CTRL2. The three data signals DQ3 may be communicated. The media controller 1130 transmits the third command and address CA3, the third clock signal CK3, and the third control signal CTRL3 to the nonvolatile memory device 1120, and transmits the nonvolatile memory device 1120. And the fourth data signals DQ4 may be communicated.

In exemplary embodiments, the first command and address CA1, the second command and address CA2, and the third command and address CA3 may have different formats. As another example, at least two of the first command and address CA1, the second command and address CA2, and the third command and address CA3 may have the same formats. For example, the format in which the media controller 1130 communicates with the volatile memory device 1110 and the format in which the media controller 1130 communicates with the nonvolatile memory device 1120 may be different.

The media controller 1130 may control the first to fourth data buffers 1141 to 1144 by transmitting the first buffer command CMD_B1. The media controller 1130 may control the fifth to eighth data buffers 1145 to 1148 by transmitting the second buffer command CMD_B2.

The first to eighth data buffers 1141 to 1148 may communicate with the memory controller 311 and the first data signals DQ1 in synchronization with the data strobe signals DQS. The first to eighth data buffers 1141 to 1148 may transfer the first data signals DQ1 received from the memory controller 311 to the media controller 1130 as the second data signals DQ2.

The first to eighth data buffers 1141 to 1148 may transfer the second data signals DQ2 received from the media controller 1130 to the memory controller 311 as the first data signals DQ1. The first to eighth data buffers 1141 to 1148 may be formed of packages separated from each other.

In exemplary embodiments, the volatile memory device 1110 may be used as a cache memory of the nonvolatile memory device 1120. Some of the storage space of the nonvolatile memory device 1120 may be mapped to the volatile memory device 1110.

When the first storage space indicated by the first command and the address CA1 received from the memory controller 311 is mapped in the volatile memory device 1110, that is, when a cache hit occurs, the media controller 1130 may read the volatile memory. The second command and the address CA2 may be transmitted to the device 1110. The volatile memory device 1110 may write or read according to the second command and the address CA2.

When the first storage space indicated by the first command and the address CA1 received from the memory controller 311 is not mapped in the volatile memory device 1110, that is, when a cache miss occurs, the media controller 1130 may delete the first command. The first storage space indicated by the first command and the address CA1 may be mapped to the volatile memory device 1110.

For example, a second storage space associated with the first storage space of the nonvolatile memory device 1120 may be secured in the volatile memory device 1110. If the storage space is insufficient in the volatile memory device 1110, the media controller 1130 discards another storage space mapped to the volatile memory device 1110 or returns another storage space to the nonvolatile memory device 1120. A storage space may be secured in the memory device 1110.

If data is stored in the first storage space of the nonvolatile memory device 1120, the media controller 1130 may copy the data of the first storage space to the second storage space of the volatile memory device 1110. Thereafter, the media controller 1130 can transfer the second command and address CA2 to the volatile memory device 1110. The volatile memory device 1110 may write or read the second storage space in response to the second command and the address CA2.

In exemplary embodiments, when the absence notification is transmitted through the first command and address CA1, the media controller 1130 may store a storage space of the nonvolatile memory device 1120 corresponding to the logical address or logical addresses included in the absence notification. May be mapped to the volatile memory device 1110. The absence notification may be delivered in a different form from the first command and address CA1 for the read operation or the first command and address CA1 for the write operation. For example, the media controller 1130 may receive the first command and address CA1 for the absence notification and perform a cache allocation.

When the second storage space is to be released in the volatile memory device 1110, the media controller 1130 may check whether the second storage space is dirty. For example, when writing to the second storage space is performed, the second storage space may be determined to be dirty.

If the second storage space is not dirty, the media controller 1130 may release the second storage space by discarding data in the second storage space. If the second storage space is dirty, the media controller 1130 may return the second storage space by writing data of the second storage space to the nonvolatile memory device 1120. After returning the second storage space, the media controller 1130 may release the second storage space by discarding the second storage space.

As another example, the volatile memory device 1110 and the nonvolatile memory device 1120 may be directly accessed by the memory controller 311. For example, when the first command and address CA1 or the first control signal CTRL1 points to the volatile memory device 1110, the media controller 1130 may include the second command and address CA2 and the second clock signal. The CK2 or the second control signal CTRL2 may be transmitted to the volatile memory device 1110.

When the first command and address CA1 or the first control signal CTRL1 points to the nonvolatile memory device 1120, the media controller 1130 may transmit the third command and address CA3 and the third clock signal CK3. Alternatively, the third control signal CTRL3 may be transmitted to the nonvolatile memory device 1120.

In exemplary embodiments, the number of volatile memories, nonvolatile memories, and data buffers is not limited. The number of volatile memories or nonvolatile memories may be equal to the number of data buffers. The number of data buffers can be changed to nine.

The media controller 1130 may store mapping information between the logical addresses LA and the physical addresses PA in the first meta storage area SA1_M (see FIG. 28) of the nonvolatile memory device 1120. The first command and address CA1 received from the memory controller 311 may be based on logical addresses LA of the nonvolatile memory device 1120.

When the media controller 1130 accesses the nonvolatile memory device 1120 according to the first command and address CA1, the media controller 1130 converts the logical addresses LA according to the mapping information into the physical addresses PA. Can be converted to). The media controller 1130 can access the nonvolatile memory device 1120 using the translated physical addresses PA. That is, the third command and address CA3 may be based on the physical addresses PA.

Cache allocation of the volatile memory device 1110 of the nonvolatile memory device 1120 may be performed according to logical addresses LA or physical addresses PA. That is, the second command and address CA2 may be based on logical addresses LA or physical addresses PA. The media controller 1130 may determine a cache hit or a cache miss using the logical addresses LA or the physical addresses PA.

41 is a block diagram illustrating a memory system 400 according to an example embodiment. For example, the memory system 400 may include a server such as an application server, a client server, and a data server. As another example, memory system 400 may include a personal computer or workstation.

Referring to FIG. 41, the memory system 400 includes a processor 410, first to fourth memory modules 420 to 450, a root complex 460, and a storage device 470. The processor 410 may control the components of the memory system 400 and the operations of the components. The processor 410 may execute an operating system and applications, and process data using the operating system or applications.

The processor 410 may include a memory controller 411 and a cache memory 412. The memory controller 411 may access the first through fourth memory modules 420 ˜ 450 through the main channels MCH and the auxiliary channels SCH. Cache memory 412 may include high speed memory, such as static random access memory (SRAM).

The first to fourth memory modules 420 to 450 may be connected to the memory controller 411 through the main channels MCH and the auxiliary channels SCH. The main channels MCH may be channels used to store data or read data in the memory modules 420 to 450. The main channels MCH may include channels provided for the first to fourth memory modules 420 to 450, respectively.

The auxiliary channels SCH may provide additional functions associated with the first to fourth memory modules 420 to 450 in addition to storing or reading data in the first to fourth memory modules 420 to 450. have. For example, the first to fourth memory modules 420 to 450 may provide their own information to the memory controller 411 through the auxiliary channels SCH. The auxiliary channels SCH may include channels provided for the first to fourth memory modules 420 to 450, respectively.

The first to fourth memory modules 420 to 450 may be used as a main memory of the memory system 400. The first to fourth memory modules 420 to 450 may include a memory controller according to one of standards of a memory module such as a dual in-line memory module (DIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), or the like. 411).

The root complex 460 can provide channels through which the processor 410 accesses various peripheral devices. For example, the storage device 470 may be connected to the root complex 460. The storage device 470 may include a hard disk drive, an optical disk drive, a solid state drive, or the like.

The processor 410 may hierarchically manage the cache memory 412, the first to fourth memory modules 420 to 450 which are main memories, and the storage device 470. For example, the processor 410 may load necessary data among data stored in the storage device 470 into the main memory including the first to fourth memory modules 420 to 450. The processor 410 may flush data to be backed up from the data stored in the main memory to the storage device 470.

Some of the storage areas of the main memory including the first to fourth memory modules 420 to 450 may be mapped to the cache memory 412. When the processor 410 needs to access a specific storage space of the main memory, the processor 410 may determine whether the specific storage space is mapped to the cache memory 412.

If a particular storage space is mapped to the cache memory 412, the processor 410 can access the specific storage space of the cache memory 412. If a particular storage space is not mapped to the cache memory, the processor 410 maps (or fetches) the specific storage space of the first to fourth memory modules 420 to 450 to the cache memory 412. Can be.

If the storage space of the cache memory 412 is insufficient, the processor 410 may release the storage space previously mapped to the cache memory 412. When data of the storage space to be released is updated, the processor 410 may flush the updated data to the first to fourth memory modules 420 to 450.

The first to fourth memory modules 420 to 450 may include heterogeneous memory modules. For example, the first and second memory modules 420 and 430 may be first type memory modules. The third and fourth memory modules 440 and 450 may be second type memory modules.

The first memory module 420 may include a first type memory 421, a second type memory 422, a media controller 423, and a serial presence detection (SPD) device 425. . The second memory module 430 may include a first type memory 431, a second type memory 432, a media controller 433, and a serial presence detection (SPD) device 435. . Hereinafter, the first type memory modules 420 and 430 will be described with reference to the first memory module 420.

The first type memory 421 may include a high speed volatile memory, for example, a dynamic random access memory (DRAM). The second type memory 422 may include a nonvolatile memory having a slower speed than the first type memory 421 and having a larger storage capacity than the first type memory 421. For example, the second type memory 422 may include a flash memory, a phase change memory, a ferroelectric memory, a magnetic memory, a resistive memory, and the like. .

The media controller 423 may issue an access command from an external host device, eg, the memory controller 411 or the processor 410, transmitted through a corresponding one of the main channels MCH to the first type memory 421. Alternatively, the data may be transferred to the second type memory 422. According to the access command, the media controller 423 may exchange data with an external host device, for example, the memory controller 411 or the processor 410, through a corresponding one of the main channels MCH.

 The media controller 423 may provide a storage capacity or storage space of the second type memory 422 to an external host device, for example, the memory controller 411 or the processor 410. The media controller 423 may use the first type memory 421 as a cache memory of the second type memory 422.

For example, the media controller 423 may map some of the storage spaces of the second type memory 422 to the first type memory 421. If the storage space associated with an access command from an external host device, such as the memory controller 411 or the processor 410, is mapped to the first type memory 421, the media controller 423 may issue the first access command. It may be transferred to the type memory 421.

If the storage space associated with an access command from an external host device, for example, the memory controller 411 or the processor 410, is not mapped to the first type memory 421, the media controller 423 may not be able to store the storage space. Mapping (or backing up) from the second type memory 422 to the first type memory 421 may be performed.

If the storage space of the first type memory 421 is insufficient, the media controller 423 may release the storage space previously mapped to the first type memory 421. When the data of the storage space to be released is updated, the media controller 423 may flush the updated data to the second type memory 422.

The media controller 423 can include a media switch (MSW). The media switch MSW may be implemented in the form of hardware included in the media controller 423 as part of an integrated circuit or firmware executed by the media controller 423. The media switch MSW may control communication with the first type memory 421 and the second type memory 422.

For example, in training, the media switch MSW may be configured to deliver training instructions from an external host device, such as the memory controller 411 or the processor 410, only to the first type memory 421. have. After the training is completed, the media switch MSW may transmit the access command to the first type memory 421 or the second type memory 422 according to an access command from an external host device.

The SPD device 425 may communicate with an external host device such as the memory controller 411 or the processor 410 through a corresponding channel among the auxiliary channels SCH. For example, when the first memory module 420 is initialized, the SPD device 425 transmits the stored information to an external host device, for example, the memory controller 411 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 410 may provide the processor 410.

For example, the SPD device 425 may store information about a storage capacity provided to an external host device, for example, the memory controller 411 or the processor 410 as a storage space of the first memory module 420. have. For example, the SPD device 425 may store information about a storage capacity of the second type memory 422. Upon initialization, the SPD device 425 may provide information about the storage capacity of the second type memory 422 to an external host device, for example, the memory controller 411 or the processor 410.

For example, the capacity information stored in the SPD device 425 may include information about a user capacity of the second type memory 422. The storage capacity of the second type memory 422 may include a user capacity, a meta capacity, and a spare capacity. The user capacity may be a storage capacity provided by the second type memory 422 to an external host device, for example, the memory controller 411.

The meta capacity stores various meta information for managing the second type memory 422, and may be a storage capacity not disclosed to an external host device, for example, the memory controller 411. The spare capacity is reserved for managing the second type memory 422 and may be a storage capacity that is not disclosed to an external host device, for example, the memory controller 411.

The capacity information stored in the SPD device 425 may include information about a user capacity of the second type memory 422. Hereinafter, the capacity of the second type memory 422 may be understood to indicate the user capacity of the second type memory 422.

The third memory module 440 may include a first type memory 441 and a serial presence detection (SPD) device 445. The fourth memory module 450 may include a first type memory 451 and a serial presence detection (SPD) device 455. Hereinafter, the second type memory modules 440 and 450 will be described with reference to the third memory module 440.

The first type memory 441 may include a dynamic random access memory like the first type memory 421 of the first memory module 420. The SPD device 445 may communicate with an external host device such as the memory controller 411 or the processor 410 through a corresponding channel among the auxiliary channels SCH. For example, when the third memory module 440 is initialized, the SPD device 445 transmits the stored information to an external host device, for example, the memory controller 411 through a corresponding channel among the auxiliary channels SCH. Alternatively, the processor 410 may provide the processor 410.

For example, the SPD device 425 may store information about a storage capacity provided to an external host device, for example, the memory controller 411 or the processor 410 as a storage space of the third memory module 440. have. For example, the SPD device 445 may store information about a storage capacity of the first type memory 441. At initialization, the SPD device 445 may provide information about the storage capacity of the first type memory 441 to an external host device, for example, the memory controller 411 or the processor 410.

When power is supplied to the memory system 400, the memory controller 411 may perform initialization with the first to fourth memory modules 420 to 450. For example, the SPD devices 425 to 455 of the first to fourth memory modules 420 to 450 may provide capacity information to the memory controller 411 through auxiliary channels SCH, respectively.

The SPD devices 425 and 435 of the first type memory modules 420 and 430 may provide the storage controllers of the second type memories 422 and 432 to the memory controller 411, respectively. The SPD devices 445 and 455 of the second type memory modules 440 and 450 may provide the storage controllers of the first type memories 441 and 451 to the memory controller 411, respectively. For example, the memory controller 411 may read the storage capacities from the SPD devices 425 ˜ 455, respectively.

After the initialization is performed, the memory controller 411 may perform training with the first to fourth memory modules 420 to 450. For example, the memory controller 411 may perform training by transmitting a training command to the first to fourth memory modules 420 to 450.

The training command may include two or more read commands or two or more write commands. During training, the memory controller 411 repeatedly transmits instructions to the first to fourth memory modules 420 to 450, thereby aligning timings of transmitting instructions in synchronization with a clock signal, and first to fourth memory. The integrity of the storage capacities of the modules 420-450 may be checked.

The storage spaces of the second type memory modules 440 and 450 identified by the memory controller 411 are the storage spaces of the first type memories 441 and 451. Accordingly, the training command of the memory controller 411 is transmitted to the first type memories 441 and 451.

The storage spaces of the first type memory modules 420 and 430 identified by the memory controller 411 are the storage spaces of the second type memories 422 and 432. Thus, the memory controller 411 may send a training command to storage spaces of the second type memories 422 and 432.

However, the training instruction of the memory controller 411 controlling the main memories is determined to correspond to the first type memory, i.e., dynamic random access. In order for the memory controller 411 to be able to perform training on the storage space of the second type memories 422 and 432, the structure or function of the memory controller 411 must be changed. However, changing the memory controller 411 that is used in the past incurs a large cost.

In order to solve this problem, the first type memory modules 420 and 430 according to an embodiment of the present invention provide storage space of the second type memories 422 and 432 to the memory controller 411, but do not provide training. To the first type memory 421. Accordingly, the storage spaces of the second type memories 422 and 432 may be provided to the memory controller 411 without affecting the training of the memory controller 411 or causing a malfunction.

In the above-described embodiment, the storage device 470 is shown connected to the root complex 460. However, the device connected to the root complex 460 is not limited to the storage device 470.

42 is a flowchart illustrating a method of operating a first type memory module 420 or 430 according to an embodiment of the present invention. For example, an operation method is described with reference to the first memory module 420. However, the operation method described with reference to FIG. 42 or the second memory module 430 may be performed.

41 and 42, in operation S311, during initialization, the first memory module 420 reports the capacity of the second type memory 422 as the total capacity of the first memory module 420. For example, the first memory module 420 may transfer the capacity information stored in the SPD device 425 to the memory controller 411. The capacity information may include capacity information of the second type memory 422.

In operation S312, during training, the first memory module 420 may transmit a training command for the second type memory 422 received from the memory controller 411 to the first type memory. The first type memory 421 may perform training with the memory controller 411 according to a training command.

By sending a training command for the second type memory 422 to the first type memory 421 rather than the second type memory 422, the first memory module 420 does not affect training and malfunctions in the training. Causing is prevented.

43 shows an example in which the memory controller 411 performs initialization with the first and third memory modules 420 and 440. Referring to FIG. 43, the first and third memory modules 420 and 440 may receive the first and second capacity information CI1 and CI2 through the first and second auxiliary channels SCH1 and SCH2, respectively. And transmit it to the memory controller 411. For example, the memory controller 411 may read the first and second capacity information CI1 and CI2 from the SPD devices 425 and 445, respectively.

The first capacity information CI1 may indicate the capacity of the second type memory 422 as the capacity of the first memory module 420. The capacity of the second type memory 422 indicated by the first capacity information CI1 may be associated with the capacity (hereinafter, referred to as a unit capacity) of the first type memory 421. For example, the capacity of the second type memory 422 included in the first capacity information CI1 may be N times the unit capacity (N is a positive integer).

The first capacity information CI1 may indicate that there are N memories having a unit capacity. For example, the first capacity information CI1 may indicate that there are N ranks having a unit capacity. For example, the first capacity information CI1 may represent the storage space of the second type memory 422 as N physical or logically distinct storage spaces (eg, virtually distinct memories). .

The memory controller 411 may identify the capacity of the first memory module 420 as the first identified capacity IC1 according to the first capacity information CI1. The memory controller 411 may assign identifiers to N virtually distinct memories having a unit capacity. For example, when N is 8, the memory controller 411 may assign first to eighth identifiers CID1 to CID8 to eight virtual memories having a unit capacity.

According to the first capacity information CI1, the memory controller 411 may identify that N memories (eg, virtually distinguished memories) exist in the first memory module 420. After initialization and training are complete, the memory controller 411 can access the N memories individually. After initialization and training are complete, the media controller 423 of the first memory module 420 may access the accesses to the N memories to the physical or logically distinct storage spaces of the second type memory 422. Can be identified.

The second capacity information CI2 may indicate the capacity of the first type memory 441 as the capacity of the third memory module 440. According to the second capacity information CI2, the memory controller 411 may identify the capacity of the third memory module 440 as the second identified capacity IC2. For example, one or more identifiers may be assigned to the second identified capacity IC2 according to the second capacity information CI2.

44 shows an example in which the media controller 423 configures a channel with the memory controller 411 during training after initialization is performed. Referring to FIG. 44, the medium may communicate with the memory controller 411 through the first main channel MCH1. The media switch MSW of the media controller 423 may configure a channel only with the first type memory 421 without configuring a channel with the second type memory 422.

Among the first identified capacities IC1 identified by the memory controller 411, capacities corresponding to the first type memory 421, for example, capacities given with the first identifier CID1 may have actual storage spaces. have. Among the first identified capacities IC1, capacities that do not correspond to the first type memory 421, for example, capacities to which the second to eighth identifiers CID2 to CID8 are assigned, do not have a real storage space. Can be.

Unlike the first memory module 420, the first type memory 441 of the third memory module 440 may form a direct channel with the memory controller 411 through the second main channel MCH2. The second identified capacitor IC2 may have a storage space of the first type memory 441 of the third memory module 440.

45 shows an example in which the media controller 423 controls training commands during training. Referring to FIG. 45, according to the first identified capacity IC1, the memory controller 411 may determine that memories having the first to eighth identifiers CID1 to CID8 exist in the first memory module 420. Recognize.

Therefore, the memory controller 411 may sequentially transmit the training commands T_CMDs having the first to eighth identifiers CID1 to CID8 to the first memory module 420. For example, the memory controller 411 may attempt to train the memory having the first identifier CID1 by transmitting a training command having the first identifier CID1 to the first memory module 420.

After the training for the memory having the first identifier CID1 is completed, the memory controller 411 transmits a training command having the second identifier CID2 to the first memory module 420 so as to receive the second identifier CID2. You can try training on a memory with. For example, the training command may include various commands, such as at least one write command, at least one read command, or at least one refresh command.

The media switch MSW may transfer all of the training commands T_CMDs to the first type memory 421. For example, regardless of the identifiers CID1 to CID8 included in the training commands T_CMDs, the medium switch MSW may repeatedly transfer the training commands T_CMDs to the first type memory 421. . For example, the medium switch MSW may recognize that the training commands T_CMDs all have the first identifier CID1.

As the memory controller 411 sequentially transmits the training commands T_CMDs having the first to eighth identifiers CID1 to CID8, the medium switch MSW performs the first to eighth identifiers CID1 to CID8. ) May repeatedly transmit training commands T_CMDs corresponding to the first type memory 421.

That is, in the first identified capacity IC1, the virtual capacities having the second to eighth identifiers CID2 to CID8 are not trained, but the capacity of the first type memory 421 having the first identifier CID1. This can be trained repeatedly.

The first type memory 421 corresponds to a training procedure of the first main channel MCH1. Accordingly, when training commands T_CMDs from the memory controller 411 are transmitted to the first type memory 421, the first memory module 420 may affect training with the memory controller 411 or cause malfunctions. Is prevented.

Initialization or training for the second type memory 422 may be performed by the media controller 423. Thus, initialization and training of the first type memory 421 and the second type memory 422 may be performed without malfunction.

A month from the first memory module 420, the training command T_CMD for the third memory module 440 is directly transmitted to the first type memory 441. The first type memory 441 corresponds to the training procedure of the second main channel MCH2. Thus, training for the third memory module 440 is performed without malfunction.

As described above, upon training, the medium switch MSW may block the training commands T_CMDs from the memory controller 411 from being transferred to the second type memory 422. In training, the medium switch MSW may transfer training commands T_CMDs from the memory controller 411 to the first type memory 421. Therefore, the training may be performed without malfunction in the first memory module 420 that provides the second type memory 422 that does not correspond to the training procedure of the first main channel MCH1 as a storage space.

46 shows an example in which the media controller 423 establishes a channel with the second type memory 422. 45 and 46, in step S321, the media controller 423 may detect the completion of training. When the completion of the training is detected, in step S322, the media controller 423 may set the second type memory 422 as the main memory and the first type memory 421 as the cache memory.

For example, according to the first identified capacity IC1, the memory controller 411 identifies the storage capacity of the first memory module 420 as the storage capacity of the second type memory 422. A portion of the storage space of the second type memory 422 may be mapped to the first type memory 421. When the storage space to be accessed by the memory controller 411 is mapped to the first type memory 421, the media controller 423 transmits an access command from the memory controller 411 to the first type memory 421. Can be.

When the storage space that the memory controller 411 attempts to access is not mapped to the first type memory 421, the media controller 423 stores the requested storage space from the second type memory 422 to the first type memory. Can be mapped to 421. Thereafter, the media controller 423 can transfer the access command from the memory controller 411 to the first type memory 421.

According to the present embodiment, the first memory module 420 may ensure a high access speed required by the memory controller 411 by transferring an access request of the memory controller 411 to the first type memory 421. . In addition, the first memory module 420 maps (eg, backs up) the storage space of the second type memory 422 to the first type memory 421, or stores the storage space of the first type memory 421. By flushing the second type memory 422, the large storage capacity and the nonvolatile function of the second type memory 422 can be provided to the memory controller 411.

47 shows an example where the media controller 423 detects the completion of the training. Referring to FIG. 47, initialization and training are performed by a BIOS (Basic Input Output System). When initialization and training are completed, the memory controller 411 may periodically transmit the refresh command R_CMD to the first memory module 420 and the third memory module 440.

The media controller 423 may detect that the training is complete when the refresh command R_CMD is received periodically (or continuously). For example, the media controller 423 may detect that training is complete when only the refresh command R_CMD is received periodically (or continuously) for a specific number of times without interrupting other commands.

When the completion of the training is detected, the medium switch MSW may establish a channel with both the first type memory 421 and the second type memory 422. In exemplary embodiments, the refresh command R_CMD may be received in the form of noise while training is performed. The media controller 423 determines whether only the refresh command R_CMD is received periodically or continuously, thereby performing a refresh command R_CMD received in the form of noise during training and a refresh command R_CMD received after the training is completed. Can be distinguished.

48 is a block diagram illustrating a first type memory module 1200 according to an embodiment of the present invention. In exemplary embodiments, the first type memory module 1200 may be a memory module based on the LRDIMM standard. For example, the first type memory module 1200 is illustrated with reference to the first memory module 420.

41 and 48, the first type memory module 1200 may include a first type memory 1210, a second type memory 1220, a media controller 1230, and first through eighth data buffers 1241. 1248), and a serial presence detection (SPD) device 1250.

The first type memory 1210, the second type memory 1220, the first to eighth data buffers 1241 to 1248, and the serial presence detection (SPD) device 1250 are described with reference to FIG. 40. It is configured and operates in the same manner as the first type memory 1110, the second type memory 1120, the first to eighth data buffers 1141 to 1148, and the serial presence detection (SPD) device 1150. . Therefore, redundant description is omitted.

The media controller 1230 can be configured and operate similarly to the media controller 1130 described with reference to FIG. 40. Unlike the media controller 1130 described with reference to FIG. 40, the media controller 1230 may include a media switch MSW.

As described above, when the first type memory module 1200 is initialized, the media switch MSW sends a training command to the second type memory 1220 from the memory controller 411 to the first type memory 1210. ) Can be delivered. When the training ends, the media switch MSW may provide the second type memory 1220 to the memory controller 411 as a storage space of the first type memory module 1200.

49 is a block diagram illustrating a computing device 500a according to an example embodiment. For example, computing device 500a may include a server such as an application server, a client server, and a data server. As another example, computing device 500a may include a personal computer or workstation.

Referring to FIG. 49, the computing device 500a may include a processor 510, a second cache memory 520, a memory controller 530a, a main memory 540a, a storage interface 550, and a storage device 560. Include.

The processor 510 may control the components of the computing device 500a and the operations of the components. The processor 510 may execute an operating system and applications, and process data using the operating system or applications. The processor 510 may include a first cache memory 511. The first cache memory 511 may include a high speed memory such as a static random access memory (SRAM).

The second cache memory 520 may communicate with the processor 510. The second cache memory 520 may include fast random access memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

The memory controller 530a may access the main memory 540a at the request of the processor 510. For example, the memory controller 530a may be based on one of memory standards such as a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM). In exemplary embodiments, the memory controller 530a may be disposed outside the processor 510 or included in the processor 510 as illustrated in FIG. 49.

Memory controller 530a includes a timeout controller 531 and a register 532. The timeout controller 531 may measure time when the memory controller 530a accesses the main memory 540a. Register 532 may store various parameters associated with memory controller 530a.

For example, register 532 may store various timeout values when memory controller 530a accesses main memory 540a. The timeout controller 531 may control the timeout when the memory controller 530a accesses the main memory 540a based on the timeout values stored in the register 532.

The main memory 540a may include a storage class memory (SCM) having a nonvolatile storage capability or a large capacity, and having an access speed and random access capability similar to that of a dynamic random access memory (DRAM).

In order to support compatibility with existing computing devices, main memory 540a may be implemented based on one of the standards of memory modules, such as DIMM, RDIMM, LRDIMM. The memory controller 530a and the main memory 540a may form a memory system.

The storage interface 550 can transfer a request or data from the processor 510 to the storage device 560. The storage interface 550 can transfer data transferred from the storage device 560 to the processor 510. The storage interface 550 may be based on one of various standards such as Peripheral Component Interconnect Express (PCIe), NonVolatile Memory Express (NVMe), Serial Advanced Technology Attachment (SATA), and the like.

The storage device 560 may store data transferred through the storage interface 550 according to a request delivered through the storage interface 550. The storage device 560 may transfer the stored data through the storage interface 550 according to a request delivered through the storage interface 550.

The storage device 560 may be implemented to include a nonvolatile storage medium and a controller to control the nonvolatile storage medium. The storage device 560 may include a hard disk drive (HDD), a solid state drive (SSD), and the like.

The processor 510 may process data hierarchically. For example, source data of an operating system, source data of an application, and user data used in the computing device 500a may be stored in the storage device 560. User data may include data generated by a user of an operating system, application, or computing device 500a.

When specific data (eg, source data or user data) needed by the processor 510 is stored in the storage device 560, the processor 510 reads the specific data from the storage device 560 in main memory. 540a. The processor 510 may back up specific data stored in the main memory 540a to the storage device 560.

Some of the storage areas of the main memory 540a may be mapped to the second cache memory 520. Some of the storage areas of the second cache memory 520 may be mapped to the first cache memory 511. In exemplary embodiments, at least one of the first and second cache memories 511 and 520 may be omitted from the computing device 500a.

In exemplary embodiments, the main memory 540a may have a structure described with reference to FIG. 26, and may operate as described with reference to FIG. 26. As another example, the main memory 540a has the structure described with reference to FIG. 40 and may operate as described with reference to FIG. 40.

50 shows an example in which the memory controller 530a performs a read operation on the main memory 540a. 49 through 50, in operation S411, the memory controller 530a may receive a first read request. For example, the memory controller 530a may receive a first read request from the processor 510.

In operation S412, the memory controller 530a may transmit a second read request to the media controller 1230. For example, the memory controller 530a may generate a second read request from the first read request. The format of the first read request and the format of the second read request may be the same or different. One or more second read requests may be generated from one first read request.

In operation S413, the memory controller 530a may determine whether normal data is received within the first time T1. For example, normal data may refer to data without errors or data with errors within a correctable range. The correctable range may be determined differently according to the type of error correction code used for communication between the memory controller 530a and the media controller 1230.

Unlike normal data, data with errors or data with errors outside the correctable range may be error data. If the normal data is received within the first time T1, in step S414, the read success is determined. The memory controller 530a may transfer the received normal data to the processor 510.

If normal data is not received within the first time T1, or if error data is received within the first time T1, the memory controller 530a sends the second read request back to the media controller 1230 at step S415. Can transmit For example, the second read request transmitted in step S415 may be the same as the second read request transmitted in step S412. The step S415 may be expressed as a read retry.

In operation S416, the memory controller 530a may determine whether normal data is received within the second time T2. The second time T2 may be the same as or different from the first time T1. If normal data is received within the second time T2, the read success may be determined in operation S414.

If normal data is not received within the second time T2, step S417 is performed. In operation S417, the memory controller 530a may determine whether the second read request has been retransmitted by the number N1 times of the first value N1. For example, the memory controller 530a may determine whether read retries have been performed a number of times of the first value N1.

If the read retry has not been performed as many times as the first value N1, the read retry may be performed in operation S415. If the read retry has been performed the number of times of the first value N1, step S418 is performed. In operation S418, if an uncorrectable error occurs, the memory controller 530a may determine that a read failure occurs.

51 illustrates a first example in which a read operation is performed according to the operating method of FIG. 50. For example, an example in which a first command and an address CA1 are associated with the volatile memory device 1210 and a read operation is performed in the volatile memory device 1210 is illustrated in FIG. 51.

49 to 51, the processor 510 may generate a first read request R1. In operation S421, the processor 510 may transmit a first read request R1 to the memory controller 530a. The memory controller 530a may generate a second read request R2 according to the first read request R1.

In operation S422, the memory controller 530a may transmit a second read request R2 to the media controller 1230. The second read request R2 may be transmitted to the media controller 1230 as the first command and the address CA1. As the second read request R2 is transmitted, the timeout controller 531 may start measuring (or counting) the first time T1 (step S413 of FIG. 50).

The media controller 1230 may generate a third read request R3 according to the second read request R2. In operation S423, the media controller 1230 may transfer the third read request R3 to the volatile memory device 1210. The third read request R3 may be transmitted to the volatile memory device 1210 as a second command and address CA2.

For example, the media controller 1230 may transfer the second read request R2 to the volatile memory device 1210 as the third read request R3 without processing the second read request R2. As another example, the media controller 1230 processes the second read request R2 into a form suitable for the volatile memory device 1210, and processes the processed result to the volatile memory device 1210 as the third read request R3. I can deliver it.

In response to the third read request R3, the volatile memory device 1210 may perform a read operation RD. Data read from the volatile memory device 1210 may be transferred to the media controller 1230. In operation S424, the read operation may be completed.

The media controller 1230 may perform a data transfer DT that transfers data read from the volatile memory device 1210 to the memory controller 530a. In operation S425, the data transmission DT is completed, and the data may be transferred to the memory controller 530a.

The memory controller 530a receives data from the main memory 540a after transmitting the second read request R2 but before the first time T1 elapses. For example, the received data may be normal data. Therefore, the memory controller 530a may determine the read success.

The memory controller 530a may perform a data transfer DT that transfers data transferred from the media controller 1230 to the processor 510. In operation S426, the data transmission DT is completed, and the data may be transferred to the processor 510. The processor 510 may determine read completion (RC).

52 is a view illustrating a modification of the read operation of FIG. 51. 49 to 50 and 52, steps S431 to S433 are performed in the same manner as steps S421 to S423 of FIG. 51. Therefore, redundant description is omitted.

When the volatile memory device 1210 performs the read operation RD, in operation S434, the read data is not controlled or buffered by the media controller 1230, and the media controller 1230 and the first to eighth data buffers are performed. It may be delivered directly to the memory controller 530a through the (1241 ~ 1248). Since the LRDIMM is based on dynamic random access memory (DRAM), the volatile memory device 1210 may directly communicate with the memory controller 530a.

Thereafter, step S436 may be performed in the same manner as step S426 of FIG. 51. When data read from the volatile memory device 1210 is directly transferred to the memory controller 530a, the time until the memory controller 530a receives the data after transmitting the second read request R2 may be shortened. .

53 illustrates a second example in which a read operation is performed according to the operating method of FIG. 50. For example, an example in which the first command and the address CA1 are associated with the nonvolatile memory device 1220 and a read operation is performed in the nonvolatile memory device 1220 is illustrated in FIG. 53.

49 to 50 and 53, the processor 510 may generate a first read request R1. In operation S441, the processor 510 may transmit a first read request R1 to the memory controller 530a. The memory controller 530a may generate a second read request R2 according to the first read request R1.

In operation S442, the memory controller 530a may transmit a second read request R2 to the media controller 1230. The second read request R2 may be transmitted to the media controller 1230 as the first command and the address CA1. As the second read request R2 is transmitted, the timeout controller 531 may start measuring (or counting) the first time T1 (step S413 of FIG. 50).

The media controller 1230 may generate a third read request R3 according to the second read request R2. In operation S443, the media controller 1230 may transfer the third read request R3 to the nonvolatile memory device 1220. The third read request R3 may be transmitted to the nonvolatile memory device 1220 as a third command and address CA3.

For example, the media controller 1230 may transfer the second read request R2 to the nonvolatile memory device 1220 as the third read request R3 without processing the second read request R2. As another example, the media controller 1230 processes the second read request R2 into a form suitable for the nonvolatile memory device 1212, and outputs the processed result as the third read request R3 to the nonvolatile memory device 1220. ) Can be delivered.

In response to the third read request R3, the nonvolatile memory device 1220 may perform a read operation RD. Data read from the nonvolatile memory device 1220 may be transferred to the media controller 1230.

In exemplary embodiments, the read speed of the nonvolatile memory device 1220 is lower than the read speed of the volatile memory device 1210. The time required to read data from the nonvolatile memory device 1220 is longer than the time required to read data from the volatile memory device 1210.

As mentioned above, LRDIMMs are based on dynamic random access memory (DRAM). Therefore, typically, the first time T1 and the second time T2 are determined according to the read time of the dynamic random access memory DRAM. The first time T1 and the second time T2 are shorter than the read time of the nonvolatile memory device 1220.

The read operation RD of the nonvolatile memory device 1220 may not be completed until the first time T1 elapses after the memory controller 530a transmits the second read request R2 in step S442. have. In operation S444, the memory controller 530a may transmit a second read request R2 back to the media controller 1230 to perform a read retry (operation S415 of FIG. 50).

The read operation RD of the nonvolatile memory device 1220 may not be completed until the second time T2 elapses after the memory controller 530a transmits the second read request R2 in step S444. have. In operation S445, the memory controller 530a may transmit a second read request R2 back to the media controller 1230 to perform a read retry (operation S415 of FIG. 50).

The read operation RD of the nonvolatile memory device 1220 may not be completed until the second time T2 elapses after the memory controller 530a transmits the second read request R2 in step S445. have. In operations S446 and S447, the memory controller 530a may transmit a second read request R2 back to the media controller 1230 to perform a read retry (operation S415 of FIG. 50).

The read operation RD of the nonvolatile memory device 1220 may not be completed until the read retry is performed the number of times of the first value N1. The memory controller 530a may determine that a read failure has occurred. The memory controller 530a may generate an error report ER and transmit the error report ER to the processor 510 in operation S448. According to the error report ER, the processor 510 may perform error handling EH.

In operation S449, a read operation of the nonvolatile memory device 1220 may be completed, and data may be transferred to the media controller 1230. However, the memory controller 530a has already determined a read failure. Therefore, when a read operation of the nonvolatile memory device 1220 of the main memory 540a occurs, the main memory 540a may differ due to a difference between the read speeds of the nonvolatile memory device 1220 and the volatile memory device 1210. The read operation may fail.

In order to solve such a problem, the memory controller 530a according to the embodiment of the present invention may perform an unlimited number of read retries. For example, the first value N1 may be stored in the register 532. According to an embodiment of the present disclosure, the memory controller 530a may invalidate the first value N1 stored in the register 532 or set it to infinity.

54 is a flowchart illustrating a method of operating a memory controller 530a according to an embodiment of the present invention. 49, 50, and 54, in step S451, the memory controller 530a may receive a first read request. For example, the memory controller 530a may receive a first read request from the processor 510.

In operation S452, the memory controller 530a may transmit a second read request to the media controller 1230. For example, the memory controller 530a may generate a second read request from the first read request. The format of the first read request and the format of the second read request may be the same or different. One or more second read requests may be generated from one first read request.

In operation S453, the memory controller 530a may determine whether normal data is received within the first time T1. If normal data is received within the first time T1, in step S454, the read success is determined. The memory controller 530a may transfer the received normal data to the processor 510.

If normal data is not received within the first time T1, or if error data is received within the first time T1, in operation S455, the memory controller 530a sends the second read request back to the media controller 1230. You can retry read by sending.

In operation S456, the memory controller 530a may determine whether normal data is received within the second time T2. The second time T2 may be shorter than the first time T1. If normal data is received within the second time T2, the read success may be determined in operation S454.

If normal data is not received within the second time T2, the memory controller 530a may perform a read retry in operation S455. That is, the memory controller 530a may retransmit an unlimited number of read requests.

55 is a view illustrating a first example in which a read operation is performed according to the operating method of FIG. 54. For example, an example in which the first command and the address CA1 are associated with the nonvolatile memory device 1220 and a read operation is performed in the nonvolatile memory device 1220 is illustrated in FIG. 55.

49, 50, 54, and 55, the processor 510 may generate a first read request R1. In operation S461, the processor 510 may transmit a first read request R1 to the memory controller 530a. The memory controller 530a may generate a second read request R2 according to the first read request R1.

In operation S462, the memory controller 530a may transmit a second read request R2 to the media controller 1230. The second read request R2 may be transmitted to the media controller 1230 as the first command and the address CA1. As the second read request R2 is transmitted, the timeout controller 531 may start measuring (or counting) the first time T1 (step S453 of FIG. 54).

The media controller 1230 may generate a third read request R3 according to the second read request R2. In operation S463, the media controller 1230 may transfer the third read request R3 to the nonvolatile memory device 1220. The third read request R3 may be transmitted to the nonvolatile memory device 1220 as a third command and address CA3.

In response to the third read request R3, the nonvolatile memory device 1220 may perform a read operation RD. Data read from the nonvolatile memory device 1220 may be transferred to the media controller 1230.

The read operation RD of the nonvolatile memory device 1220 may not be completed until the first time T1 elapses after the memory controller 530a transmits the second read request R2 in step S412. have. In operation S464, the memory controller 530a may transmit a second read request R2 back to the media controller 1230 to perform a read retry (operation S455 of FIG. 54).

The read operation RD of the nonvolatile memory device 1220 may not be completed until the second time T2 elapses after the memory controller 530a transmits the second read request R2 in operation S464. have. In operation S465, the memory controller 530a may retransmit the second read request R2 to the media controller 1230 to perform a read retry (operation S455 of FIG. 54).

Similarly, as the second time T2 elapses, the memory controller 530a may retransmit the second read request R2 to the media controller 1230 in steps S466 to S468 to perform read retry. . While the read operation RD is performed in the nonvolatile memory device 1220, the media controller 1230 may receive the second read requests (eg, in steps S464 to S468 that are received in association with the read operation RD). Received second read requests R2) may be ignored.

In operation S469, the read operation RD is completed in the nonvolatile memory device 1220, and the read data may be transferred to the media controller 1230. The media controller 1230 may perform a data transfer DT that transfers data read from the nonvolatile memory device 1220 to the memory controller 530a. In operation S470, the data transfer DT is completed, and the data may be transferred to the memory controller 530a.

The memory controller 530a receives data from the main memory 540a after the second time T2 elapses after transmitting the second read request R2 in step S468. For example, the received data may be normal data. Therefore, the memory controller 530a may determine the read success.

The memory controller 530a may perform a data transfer DT that transfers data transferred from the media controller 1230 to the processor 510. In operation S471, the data transmission DT is completed, and the data may be transferred to the processor 510. The processor 510 may determine read completion (RC).

As described above, by not limiting the number of times that the memory controller 530a performs read retries, normal data may be read from the nonvolatile memory device 1220.

FIG. 56 shows a second example in which a read operation is performed according to the operating method of FIG. 54. For example, an example in which the first command and the address CA1 are associated with the nonvolatile memory device 1220 and the volatile memory device 1210 is used as a cache memory of the nonvolatile memory device 1220 is illustrated in FIG. 56. .

40, 49, 54, and 56, in step S481, the processor 510 may transmit a first read request R1 to the memory controller 530a. The memory controller 530a may generate a second read request R2 according to the first read request R1.

In operation S482, the memory controller 530a may transmit a second read request R2 to the media controller 1230. The second read request R2 may be transmitted to the media controller 1230 as the first command and the address CA1. As the second read request R2 is transmitted, the timeout controller 531 may start measuring (or counting) the first time T1 (step S453 of FIG. 54).

The media controller 1230 can determine whether the storage space associated with the second read request R2 is mapped to the volatile memory device 1210 (ie, a cache hit). If the storage space associated with the second read request R2 is mapped to the volatile memory device 1210, that is, a cache hit, the media controller 1230 issues a third read request R3 to the second command and address CA2. Alternatively, the second control signal CTRL2 may be transmitted to the volatile memory device 1210.

The read operation of the volatile memory device 1210 may be performed in the same manner as described with reference to FIG. 51 or 52. Therefore, the read operation for the volatile memory device 1210 will not be redundantly described.

If the storage space associated with the second read request R2 is not mapped in the volatile memory device 1210, that is, if it is a cache miss, the media controller 1230 determines the storage space associated with the second read request R2. It may be mapped to 1210.

The media controller 1230 can generate a third read request R3 for the storage space associated with the second read request R2. In operation S483, the media controller 1230 may transfer the third read request R3 to the nonvolatile memory device 1220. The third read request R3 may be transmitted to the nonvolatile memory device 1220 as a third command and address CA3.

In response to the third read request R3, the nonvolatile memory device 1220 may perform a read operation RD. Data read from the nonvolatile memory device 1220 may be transferred to the media controller 1230.

As the first time T1 or the second time T2 elapses, the memory controller 530a may perform a read retry by transmitting a second read request R2 in steps S484 to S488.

As the read operation RD of the nonvolatile memory device 1220 is completed, in operation S489, data read from the nonvolatile memory device 1220 is transferred to the media controller 1230.

As data is transferred from the nonvolatile memory device 1220, in operation S490, the media controller 1230 may transfer a write request W to the volatile memory device 1210. The write request W may include data read from the nonvolatile memory device 1220 or may be transferred with the data.

For example, the write request W may be transmitted to the volatile memory device 1210 as the second command and the address CA2. As another example, the write request W may be transmitted to the volatile memory device 1210 as the second control signal CTRL2. For example, the media controller 1230 can activate a particular control signal, for example SAVEn.

While the specific control signal is activated, the media controller 1230 may output data read from the nonvolatile memory device 1220 to the volatile memory device 1210. In response to the activation of a particular control signal, the volatile memory device 1210 may write data transferred from the media controller 1230.

In response to the write request W, the volatile memory device 1210 may perform a write operation WR. When the volatile memory device 1210 performs a write operation WR, the first storage space of the nonvolatile memory device 1220 associated with the second read request R2 is mapped to (or stored in) the second storage space of the volatile memory device. Backup).

After the write operation WR is completed, in operation S491, the memory controller 530a may transmit a second read request R2 to the media controller 1230. In operation S492, the media controller 1230 transmits a third read request R3 to the volatile memory device 1210 in response to the second read request R2 received in operation S441 after the read operation RD is completed. Can be. The third read request R3 may request to read data mapped from the nonvolatile memory device 1220 to the volatile memory device 1210.

In response to the third read request R3, the volatile memory device 1210 may perform a read operation RD. When the read operation RD is completed, in operation S493, data associated with the second read request R2 is transferred to the media controller 1230. The media controller 1230 may perform data transfer DT.

As the data transfer DT is performed, in operation S494, the data is transferred to the memory controller 530a. Before the second time T2 elapses after the memory controller 530a transmits the second read request R2 in step S491, data associated with the second read request R2 is received by the memory controller 530a. . Therefore, the memory controller 530a may determine the read success (step S454 of FIG. 54).

The memory controller 530a may perform data transfer DT to transfer data to the processor 510 in operation S495. As the data is delivered, the processor 510 may determine the read completion.

FIG. 57 shows a modification of the read operation of FIG. 56. 40, 49, 54 and 57, steps S501 to S510 are performed in the same manner as steps S481 to S490 of FIG. 56. Therefore, redundant description is omitted.

In operation S511, the memory controller 530a may transmit a second read request R2 to the media controller 1230. In response to the second read request R2, in operation S512, the media controller 1230 may transmit a third read request R3 to the volatile memory device 1210. For example, the media controller 1230 may transfer the second read request R2 transmitted from the memory controller 530a as the third read request R3 to the volatile memory device 1210.

When the volatile memory device 1210 performs the read operation RD, in operation S513, the read data is not controlled or buffered by the media controller 1230, and the media controller 1230 and the first to eighth data buffers. It may be delivered directly to the memory controller 530a through the (1241 ~ 1248). Since the LRDIMM is based on dynamic random access memory (DRAM), the volatile memory device 1210 may communicate directly with the memory controller 530a.

Thereafter, step S514 may be performed in the same manner as step S495 of FIG. 56. When data read from the volatile memory device 1210 is directly transferred to the memory controller 530a, the time until the memory controller 530a receives the data after transmitting the second read request R2 may be shortened. .

58 shows an application example of the operation method of FIG. 54. 40, 49, and 58, steps S521 to S525 are performed in the same manner as steps S451 to S455 described with reference to FIG. 54. That is, the memory controller 530a may repeatedly perform read retries without limiting the number of times.

In operation S526, if normal data is not received within the second time T2, operation S527 is performed. In operation S527, it is determined whether a third time T3 has elapsed after the first transmission of the second read request (operation S522). If the third time T3 has not elapsed, the read retry is performed without limit in the number of steps S525.

If the third time T3 has elapsed, in operation S528, if an uncorrectable error occurs, the memory controller 530a may determine that a read failure has occurred. In exemplary embodiments, information of the third time T3 may be stored in the register 532.

The third time T3 may be determined according to a time required to perform a read operation in the nonvolatile memory device 1220 (eg, a read time). For example, the third time T3 may be determined to be longer than the read time (eg, more than twice).

59 shows an example of performing a read operation while measuring the third time T3. In comparison with FIG. 56, as the memory controller 530a transmits the second read request R2 to the media controller 1230 in step S482, the timeout controller 531 starts measuring the third time T3. Can be.

In exemplary embodiments, the third time T3 may be set longer than a time when a read operation is performed on the nonvolatile memory device 1220. When the timeout is measured according to the third time T3, an error (for example, a read error) occurs in the main memory 540a and the memory controller 530a repeats the read retry when normal data is not read. Is prevented. That is, a hang is prevented from occurring in the memory system including the memory controller 530a and the main memory 540a.

60 is a block diagram illustrating a computing device 500b according to another example of the present disclosure. Referring to FIG. 60, the computing device 500b may include a processor 510, a second cache memory 520, a memory controller 530b, a main memory 540b, a storage interface 550, and a storage device 560. Include.

The processor 510, the second cache memory 520, the storage interface 550, and the storage device 560 operate in the same manner as described with reference to FIG. 49. Therefore, redundant description is omitted.

Compared to FIG. 49, the memory controller 530b and the main memory 540b may further communicate through a system management bus (SMBus). Main memory 540b may include a Serial Presence Detect (SPD) device and a register updater 542.

The SPD device 541 may include information about the main memory 540b. When power is supplied to the memory controller 530b and the main memory 540b, the memory controller 530b accesses the SPD device 541 of the main memory 540b to obtain information about the main memory 540b. Can be.

Based on the obtained information, the memory controller 530b may set or adjust methods or parameters for accessing the main memory 540b. For example, the memory controller 530b may access the SPD device 541 through the system management bus SMBus.

The register updater 542 may update the register 532 of the memory controller 530b through the system management bus SMBus. For example, when the memory controller 530b accesses the SPD device 541 of the main memory 540b, the memory controller 530b causes the main memory 540b to register 532 through the system management bus SMBus. May allow access.

While the memory controller 530b accesses the SPD device 541, the register updater 542 may update some of the information stored in the register 532. For example, register updater 542 may update the information stored in register 532 such that the operations described with reference to FIGS. 54-59 are allowed.

61 shows an example of a main memory 1300 that includes an SPD device 541 and a register updater 542. Compared to FIG. 40, the media controller 1330 can include an SPD device 541 and a register updater 542.

The SPD device 541 may be provided within the media controller 1330 or may be provided outside the media controller 1330 to be distinguished from the media controller 1330. The SPD device 541 and the register updater 542 may communicate with the memory controller 530b through the system management bus SMBus.

62 is a flow chart illustrating how main memory 540b updates register 532. 60 to 62, in operation S531, the media controller 1330 may detect power on. In operation S532, the register updater 542 of the media controller 1330 may update the information stored in the register 532 through the system management bus SMBus.

For example, register updater 542 may invalidate or remove the times limit stored in register 532. The register updater 542 may update the third time T3 stored in the register 532 according to the read time of the nonvolatile memory device 1320. For example, the register updater 542 may update the register 532 such that the third time T3 is longer than the read time.

63 is a block diagram illustrating a computing device 500c according to another example of the present invention. 40 and 63, the computing device 500c may include a processor 510, a second cache memory 520, a memory controller 530c, a main memory 540c, a storage interface 550, and a storage device ( 560).

The processor 510, the second cache memory 520, the storage interface 550, and the storage device 560 operate in the same manner as described with reference to FIG. 49. Therefore, redundant description is omitted.

Compared to FIG. 49, the main memory 540c may output the write error signal WRCRC to the memory controller 530c. For example, the memory controller 530c may transfer a write request to the main memory 540c. The write data of the write request may be sent with parity generated by the error correction code.

The main memory 540c may use parity to check whether an error exists in the write data. If an error exists in the write data, the main memory 540c may activate (eg, adjust the low level) the write error signal WRCRC. When the write error signal WRCRC is activated, the memory controller 530c may resend the write request.

Main memory 540c may include a write error controller 543. As described with reference to FIG. 61, a write error controller 543 may be included in the media controller 1230. When writing to the nonvolatile memory device 1220 is performed, the write error controller 543 may control the write error signal WRCRC. For example, the write error signal WRCRC may include an ALERTn signal.

64 is a flowchart illustrating an example in which the memory controller 530c performs a write operation. 40, 63, and 64, in operation S541, the memory controller 530c may receive a first write request. For example, the memory controller 530c may receive a first write request from the processor 510.

In operation S542, the memory controller 530c may transmit a second write request to the media controller 1230. For example, the memory controller 530c may generate a second write request from the first write request. The format of the first write request and the format of the second write request may be the same or different. One or more second write requests may be generated from one first write request.

In operation S543, the memory controller 530c may check whether the write error signal WRCRC is activated. If the write error signal WRCRC is not activated, in operation S544, the memory controller 530c may determine that writing is successful.

When the write error signal WRCRC is activated, in operation S545, the memory controller 530c may perform restoration. For example, the memory controller 530c may perform restoration of a communication link between the memory controller 530c and the main memory 540c. Restoration may include ZQ calibration, write training, read training, and the like.

Thereafter, in operation S542, the memory controller 530c may transmit the second write request again. That is, the memory controller 530c may repeat the write retry without limiting the number of times.

65 is a flowchart illustrating an example in which the main memory 540c performs a write operation. 40, 63, and 65, in operation S551, the media controller 1230 may receive a second write request. For example, the media controller 1230 may receive a second write request as the first command and the address CA1 from the memory controller 530c.

In operation S552, the media controller 1230 may determine whether the second write request causes writing to the nonvolatile memory device 1220. If the second write request does not cause writing to the nonvolatile memory device 1220, in operation S553, the media controller 1230 may perform a write operation on the volatile memory device 1210 according to the second write request. have.

If the second write request causes writing to the nonvolatile memory device 1220, step S554 is performed. In operation S554, the media controller 1230 may activate the write error signal WRCRC. In operation S555, the media controller 1230 may perform a write operation on the nonvolatile memory device 1220.

After the write operation to the nonvolatile memory device 1220 is completed, when a second write request is received (step S556), in step S557, the media controller 1230 disables the write error signal WRCRC (eg, High level).

As described with reference to FIG. 53, a write operation on the nonvolatile memory device 1220 requires a longer time than a write operation on the volatile memory device 1210. The memory controller 530c is configured to control the main memory 540c based on the write speed of the volatile memory device 1210.

For example, the memory controller 530c forwards the second write request W2 to the main memory 540c, and if there is no separate reply from the main memory 540c, for example, activation of the write error signal WRCRC. It can be determined that the write operation is completed.

If the memory controller 530c determines that the write is completed while the write operation to the nonvolatile memory device 1220 is not completed, a write failure may occur. In order to solve this problem, the main memory 540c according to an embodiment of the present invention may activate the write error signal WRCRC until the write operation of the nonvolatile memory device 1220 is completed. Low level).

66 shows a first example in which a write operation is performed according to the operation method of FIG. 65. For example, an example in which the first command and the address CA1 are not associated with the nonvolatile memory device 1220 and a write operation is performed in the volatile memory device 1210 is illustrated in FIG. 66.

40, 63, 65, and 66, the processor 510 may generate a first write request W1. In operation S561, the processor 510 may transmit the first write request W1 to the controller 530c. The memory controller 530c may generate a second write request W2 according to the first write request W1.

In operation S562, the memory controller 530c may transfer the second write request W2 to the media controller 1230. The second write request W2 may be transmitted to the media controller 1230 as the first command and address CA1.

The media controller 1230 may generate a third write request W3 according to the second write request W2. In operation S563, the media controller 1230 may transfer the third write request W3 to the volatile memory device 1210. The third write request W3 may be transmitted to the volatile memory device 1210 as a second command and address CA2.

For example, the media controller 1230 may transfer the second write request W2 to the volatile memory device 1210 as the third write request W3 without processing the second write request W2. As another example, the media controller 1230 processes the second write request W2 into a form suitable for the volatile memory device 1210, and processes the processed result to the volatile memory device 1210 as the third write request W3. I can deliver it.

In response to the third write request W3, the volatile memory device 1210 may perform a write operation WR. For example, as described with reference to FIG. 52, the memory controller 530c may be configured to include the first to eighth data buffers 1241 without being controlled by the media controller 1230 or without buffering the media controller 1230. 1248) and the media controller 1230 may directly write data to the volatile memory device 1210.

If there is no error in the write data, the media controller 1230 may maintain the write error signal WRCRC in a high level inactive state. If there is an error in the write data, the media controller 1230 may control the write error signal WRCRC to a low level active state. In response to the activation of the write error signal WRCRC, the memory controller 530c may retransmit the second write request W2.

In exemplary embodiments, checking whether an error exists in the write data may be performed by the media controller 1230 or the volatile memory device 1210. The media controller 1230 or the volatile memory device 1210 may activate the write error signal WRCRC to a low level when an error exists in the write data.

For example, the write error signal WRCRC output by the volatile memory device 1210 may be included in the second control signal CTRL2 and transmitted to the media controller 1230. The media controller 1230 may transfer the write error signal WRCRC transmitted from the volatile memory device 1210 to the memory controller 530c.

67 is a view illustrating a second example in which a write operation is performed according to the operating method of FIG. 65. For example, an example in which the first command and the address CA1 cause a write operation to the nonvolatile memory device 1220 is illustrated in FIG. 67.

40, 63, 65, and 67, the processor 510 may generate a first write request W1. In operation S571, the processor 510 may transmit the first write request W1 to the controller 530c. The memory controller 530c may generate a second write request W2 according to the first write request W1.

In operation S572, the memory controller 530c may transmit a second write request W2 to the media controller 1230. The second write request W2 may be transmitted to the media controller 1230 as the first command and address CA1. The second write request W2 causes a write operation on the nonvolatile memory device 1220. Accordingly, as the second write request W2 is received, the media controller 1230 may activate the write error signal WRCRC to a low level.

The media controller 1230 may generate a third write request W3 according to the second write request W2. In operation S573, the media controller 1230 may transfer the third write request W3 to the nonvolatile memory device 1220. The third write request W3 may be transferred to the nonvolatile memory device 1220 as a third command and address CA3.

For example, the media controller 1230 may transfer the second write request W2 to the nonvolatile memory device 1220 as the third write request W3 without processing the second write request W2. As another example, the media controller 1230 processes the second write request W2 into a form suitable for the nonvolatile memory device 1220, and processes the processed result as the third write request W3 as the nonvolatile memory device 1220. ) Can be delivered.

In response to the third write request W3, the nonvolatile memory device 1220 may perform a write operation WR. As the write error signal WRCRC is activated, in operation S574, the memory controller 530c may perform a recovery RE. After the restoration is performed, in operation S575, the memory controller 530c may perform a write retry by transmitting the second write request S565 again.

Thereafter, while the write operation WR is performed in the nonvolatile memory device 1220, the memory controller 530c repeats the restoration and the write retry in steps S576 to S578 according to the activation of the write error signal WRCRC. can do.

In operation S579, the nonvolatile memory device 1220 may notify the media controller 1230 that the write operation WR is completed. For example, the nonvolatile memory device 1220 controls the ready / busy signal R / nB to indicate ready, thereby indicating that the write operation WR is completed. ) Can be informed.

In operation S580, the memory controller 530c may perform a write retry by transmitting the second write request W2 to the media controller 1230. As the second write request W2 is received in operation S580, the media controller 1230 may deactivate the write error signal WRCRC to a high level. As the write error signal WRCRC is deactivated, the memory controller 530c may identify that the write operation WR is completed.

As described above, when the write operation WR is performed on the nonvolatile memory device 1220, the media controller 1230 may activate the write error signal WRCRC even though no error occurs. By activating the write error signal WRCRC, the memory controller 530c may retransmit the write operation without limit. Therefore, the memory controller 530c is held until the write operation WR for the nonvolatile memory device 1220 is completed, and the write error is prevented.

FIG. 68 shows a second example in which a write operation is performed according to the operation method of FIG. 66. For example, an example in which the first command and the address CA1 are associated with the nonvolatile memory device 1220 and the volatile memory device 1210 is used as a cache memory of the nonvolatile memory device 1220 is illustrated in FIG. 68. .

40, 63, 66, and 68, the processor 510 may generate a first write request W1. In operation S591, the processor 510 may transmit the first write request W1 to the controller 530c. The memory controller 530c may generate a second write request W2 according to the first write request W1.

In operation S592, the memory controller 530c may transmit a second write request W2 to the media controller 1230. The second write request W2 may be transmitted to the media controller 1230 as the first command and address CA1. The media controller 1230 may determine whether the storage space associated with the first command and the address CA1 is mapped to the volatile memory device 1210.

For example, the storage space associated with the first command and the address CA1 may not be mapped in the volatile memory device 1210. In addition, the free storage space of the volatile memory device 1210 is insufficient to provide a storage space associated with the first command and the address CA1, which may cause a write operation to the nonvolatile memory device 1220.

The media controller 1230 may select a specific storage space among the storage spaces mapped in the volatile memory device 1210 and remove the selected storage space. For example, the selected storage space may be a dirty storage space. The media controller 1230 may return the selected storage space to the nonvolatile memory device 1220 to cause a write operation on the nonvolatile memory device 1220.

In operation S593, the media controller 1230 may transmit a read request R for the selected storage space to the volatile memory device 1210. The read request R may be transmitted to the volatile memory device 1210 as a second command and address CA2 or a second control signal CTRL2.

For example, the read request R may be transmitted to the volatile memory device 1210 as the second command and the address CA2. As another example, the read request R may be transmitted to the volatile memory device 1210 as the second control signal CTRL2. For example, the media controller 1230 can activate a particular control signal, for example SAVEn.

When a specific control signal is activated, the volatile memory device 1210 may output stored data, for example, data at a location (eg, a bank) designated by an internal schedule, or all data. The media controller 1230 may store data transferred from the volatile memory device 1210.

The volatile memory device 1210 may perform a read operation RD according to a read request R. FIG. Data read from the volatile memory device 1210 may be transferred to the media controller 1230 at step S594. As data of the selected storage space is read from the volatile memory device 1210, in operation S594, the media controller 1230 may transmit a third write request W3 to the nonvolatile memory device 1220. The third write request W3 may be transmitted to the nonvolatile memory device 1220 as the third command and address CA3 or the third control signal CTRL3.

In response to the third write request W3, the nonvolatile memory device 1220 may perform a write operation WR. While the nonvolatile memory device 1220 performs the write operation, the write error signal WRCRC is activated. Accordingly, while the nonvolatile memory device 1220 performs the write operation, the memory controller 530c may repeat the write retry of transmitting the restore RE and the second write request W2 in steps S596 to S600. Can be.

In operation S601, the nonvolatile memory device 1220 may notify the media controller 1230 that the write operation WR is completed. After the write operation WR is completed, in step S602, the memory controller 530c may transmit a second write request W2 to perform a write retry.

When the second write request W2 is received after the write operation of the nonvolatile memory device 1220 is completed (operation S602), the media controller 1230 may inactivate the write error signal WRCRC. The media controller 1230 may map the storage space associated with the first command and the address CA1 to the volatile memory device 1210 according to the second write request W2 in step S602.

In operation S603, the media controller 1230 may transmit a third write request W3 to the volatile memory device 1210. The third write request W3 may be transmitted as the second command and address CA2 or the second control signal CTRL2. In response to the third write request W3, the volatile memory device 1210 may perform a write operation WR.

69 is a view illustrating a modification of the read operation of FIG. 68. 40, 63, 66, and 69, steps S611 to S621 are performed in the same manner as steps S591 to S601 of FIG. 68. Therefore, redundant description is omitted.

After the write operation WR is completed in the nonvolatile memory device 1220, in operation S622, the memory controller 530c may transmit a second write request W2 to the media controller 1230. The media controller 1230 may transfer the second write request W2 as the third write request W3 to the volatile memory device 1210.

The data transferred from the memory controller 530c is not controlled or buffered by the media controller 1230, and the volatile memory device 1210 through the media controller 1230 and the first through eighth data buffers 1241-1248. Can be delivered directly. Since the LRDIMM is based on dynamic random access memory (DRAM), the volatile memory device 1210 may directly communicate with the memory controller 530a.

70 shows another modified example of the read operation of FIG. 68. 40, 63, 66, and 70, as the read operation RD is completed, the media controller 1230 waits without transmitting the third write request W3 to the nonvolatile memory device 1220. can do. After the read operation RD is completed, the second write request W2 may be transferred from the memory controller 530c in operation S597. In response to the second write request W2 in step S597, the media controller 1230 may transmit a third write request W3 to the nonvolatile memory device 1220 (step S604).

For example, in FIG. 60 and FIG. 61, the media controller 1230 has been described as including an SPD device 541 and a register updater 542. In addition, the media controller 1230 has been described in FIG. 63 as including a write error controller 543. The media controller 1230 according to an embodiment of the present invention may include the SPD device 541, the register updater 542, and the write error controller 543.

The register updater 542 may update the register 532 of the memory controller 530a, 530b, or 530c to perform read retries without limit. In addition, the register updater 542 may update the register 532 of the memory controller 530a, 530b, or 530c to perform a write retry without limit.

In the above-described embodiments, the components according to the embodiments of the present invention are referred to using the term "block". A "block" can be a variety of hardware devices, such as integrated circuits (ICs), application specific ICs (ASICs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., firmware running on hardware devices, applications, and the like. It may be implemented in software, or a combination of hardware devices and software. In addition, the "block" may include circuits or IP (Intellectual Property) composed of semiconductor elements in the IC.

In the above-described embodiments, the technical idea of the present invention has been described with reference to various embodiments and various drawings. However, the embodiments and the drawings separately described are intended to facilitate understanding of the spirit of the present invention by those skilled in the art, and are not intended to be separated from each other.

The above-described embodiments according to the spirit of the present invention and the above-described drawings may be combined with each other. Technical features described in at least one of FIGS. 1 to 70 or at least one of the above-described embodiments and at least another embodiment of at least another one of FIGS. 1 to 70 or the above-described embodiments. The described technical features may be combined to form an embodiment according to the spirit of the present invention.

The foregoing is specific embodiments for practicing the present invention. The present invention will include not only the above-described embodiments but also embodiments that can be simply changed in design or easily changed. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

100a: memory system
110: central control block
120: first memory module
130: second memory module
140: third memory module
150: fourth memory module
160: root complex
170: storage device
180: power management block
190: peripherals

Claims (10)

Random access memory;
Nonvolatile memory;
Buffer memory; And
A controller configured to perform a read operation on the buffer memory in response to activation of a control signal,
And in response to a result of the read operation, the controller is further configured to perform a flush operation of storing first data stored in the random access memory in the nonvolatile memory. The method of claim 1,
And when writing the first data to the random access memory in response to a request of an external host device, the controller is further configured to store the information of the first data in the buffer memory. The method of claim 2,
The controller is further configured to read the information from the buffer memory in the read operation, and
And the first data is data selected according to the information among data stored in the random access memory. The method of claim 3,
And after the first data is stored in the nonvolatile memory, the controller is further configured to remove the information from the buffer memory. The method of claim 1,
And second data not written by the external host device among the data stored in the random access memory are not stored in the nonvolatile memory during the flush operation. The method of claim 1,
And the random access memory is used as a cache memory of the nonvolatile memory. The method of claim 1,
The flush operation may include a first operation of reading the first data stored in the random access memory and storing the read first data in the buffer memory. The method of claim 7, wherein
The flush operation may further include second operations of writing second data stored in the buffer memory to the nonvolatile memory device. Random access memory;
Nonvolatile memory;
Buffer memory; And
In response to activation of a control signal, a read operation is performed on the buffer memory and the random access memory, the first data read from the buffer memory is stored in the nonvolatile memory, and the second data read from the random access memory. And a controller configured to perform a flush operation to store a buffer in the buffer memory. A semiconductor memory module including a random access memory, a nonvolatile memory, and a controller; And
A central control block configured to activate a control signal transmitted to the controller if an access error is detected when accessing the semiconductor memory module,
In response to the control signal being activated, the controller is configured to read first data of the data stored in the random access memory and store the first data as second data in the nonvolatile memory.

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