KR20190093475A - Operation method of host, operation method of memory module, and operation method of memory system - Google Patents

Abstract

According to an embodiment of the present invention, a memory module comprises: a RAM device including first and second storage areas; a nonvolatile memory device; and a controller configured to control the RAM device or nonvolatile memory device according to the control of a host. The controller includes a data buffer configured to temporarily store first data received from the host and a buffer transforming unit configured to transmit first release information to the host if first data is transferred from the data buffer to a first area or second area of the RAM device and transmit second release information to the host if the first data is transferred from the second area to the nonvolatile memory device. The host may manage resources of the memory module.

Description

Operation method of host, operation method of memory module, operation method of memory system {OPERATION METHOD OF HOST, OPERATION METHOD OF MEMORY MODULE, AND OPERATION METHOD OF MEMORY SYSTEM}

The present invention relates to a storage device, and more particularly, to a method of operating a host, a method of operating a memory module, and a method of operating a memory system.

The semiconductor memory is a volatile memory device such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. that loses its stored data when the power supply is cut off, read only memory (ROM), and programmable ROM (PROM). Power supplies, such as EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Even if it is blocked, it is classified as a nonvolatile memory device which retains the stored data.

Flash memory, a type of nonvolatile memory device, is widely used as a storage device in various fields due to its advantages such as large capacity, low noise, and low power. Recently, as data processed in a computing system increases, data bottlenecks occur due to more data throughput than data bandwidth or communication speed of an interface connected to SSD devices. These phenomena act as a factor that hinders the performance of the computing system, and various performance enhancement techniques have been developed to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of operating a host, a method of operating a memory module, and a method of operating a memory system, by the host managing resources of the memory module.

In an embodiment, a memory module may include a RAM device including a first storage area and a second storage area, a nonvolatile memory device, and a controller configured to control the RAM device or the nonvolatile memory device under control of a host. It includes. The controller is a data buffer configured to temporarily store the first data received from the host, and first release information when the first data is moved from the data buffer to the first region or the second region of the RAM device. And a buffer return unit configured to transmit second release information to the host when the first data is moved from the second area to the nonvolatile memory device.

A memory module according to an embodiment of the present invention includes a RAM device, a nonvolatile memory device, and a controller configured to control the RAM device and the nonvolatile memory device under control of a host. The controller is configured to temporarily store first data received from the host, and the first release information is transmitted to the RAM device or the nonvolatile memory device when the first data is moved from the data buffer to the host. It includes a buffer return configured to transmit to.

A method of operating a memory device including a RAM device and a nonvolatile memory device according to an embodiment of the present disclosure may include receiving a first write command from a host, receiving first data corresponding to the first write command, and Temporarily storing the received first data in a data buffer, moving the first data from the data buffer to the RAM device, and when the first data is moved from the data buffer to the RAM device, the host Transmitting first release information to the nonvolatile memory device, transferring the first data from the RAM device to the nonvolatile memory device, and when the first data is moved from the RAM device to the nonvolatile memory device. Sending the second release information to the host.

A method of operating a host configured to communicate with a memory module may include: transmitting a persistent write command to the memory module and indicating a number of available first unit buffers among the first unit buffers included in the memory module; Subtracting a first counter value and a second counter value indicating the number of available second unit buffers among the second unit buffers included in the memory module, respectively, of the first unit buffers released among the first unit buffers. Receiving first release information indicating a number from the memory module, adding the subtracted first counter value based on the received first release information, and a second unit released among the second unit buffers; Receiving second release information indicating the number of buffers from the memory module and adding the subtracted second counter value based on the received second release information; Including the step of producing.

According to an embodiment of the present disclosure, a host may manage resources (eg, WC, PC, etc.) of a memory module. When the resource is released, the memory module transmits release information to the host, and the host may update the resource based on the release information. Accordingly, a method of operating a host, a method of operating a memory module, and a method of operating a memory system having improved performance are provided.

1 is a block diagram illustrating a computing system according to an example embodiment.
2A through 2C are block diagrams for describing an operation between a host and a controller of FIG. 1.
3 is a flowchart illustrating an operation of the host of FIG. 1.
4 is a flowchart illustrating an operation of the controller of FIG. 1.
5A through 5C are timing diagrams for describing an operation of a host and a controller of FIG. 1.
6 is a block diagram illustrating a computing system according to an example embodiment.
7A to 7D and 8 are diagrams for describing an operation of a host and a controller of FIG. 6.
9 is a flowchart illustrating a method of operating a host of FIG. 6.
FIG. 10 is a flowchart illustrating a method of operating the memory module of FIG. 6.
FIG. 11 is a timing diagram for describing an operation of a host and a controller of FIG. 6.
12A and 12B are block diagrams for describing an operation of a host and a controller of FIG. 6.
13A through 13D are timing diagrams for describing an operation of a host and a controller according to the exemplary embodiment of FIGS. 12A through 12B.
14 is a diagram illustrating an example of a WC counter and a PC counter of FIG. 6.
15 is a block diagram illustrating a computing system according to an example embodiment.
16 is an exemplary block diagram of a memory module in accordance with the present invention.
17 is an exemplary block diagram of a memory module in accordance with the present invention.
18 is a block diagram illustrating a computing system to which a memory module according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that those skilled in the art can easily carry out the present invention.

Hereinafter, the terms "unit", "module" and the like refer to a configuration of a software configuration, a hardware configuration, or a combination thereof. For example, a "unit" performing a specific function may be a hardware configuration for performing a specific function. A “module” that includes a particular function or specific configurations may be a configuration that includes various hardware configurations.

1 is a block diagram illustrating a computing system 10 according to an example embodiment. Referring to FIG. 1, the computing system 10 may include a host 101 and a memory module 100. The host 101 may store data in the memory module 100 or read data stored in the memory module 100. For example, the host 101 may transmit an address ADDR, a command CMD, and data DATA to the memory module 100 to store data DATA in the memory module 100. In an example embodiment, the host 101 may be a central processing unit (CPU) for controlling the operation of the computing system 10.

The memory module 100 may include a controller 110, a RAM device 120, and a nonvolatile memory device 130. For example, the memory module 100 may communicate with the host 101 through a double data rate (DDR) interface, and may be an NVDIMM-P type memory module. For example, the controller 110, the RAM device 120, and the nonvolatile memory device 130 may be integrated on the same PCB substrate (not shown) to configure one memory module 100. In addition, the memory module 100 may further include various other components in addition to the illustrated components. However, the present invention is not limited thereto.

The controller 110 stores data DATA in the RAM device 120 or the nonvolatile memory device 130 under the control of the host 101, or is stored in the RAM device 120 or the nonvolatile memory device 130. Data DATA can be read.

In an example embodiment, the RAM device 120 may have a faster operating speed than the nonvolatile memory device 130. For example, the RAM device 120 may be a memory device that supports high-speed operation such as SRAM, DRAM, etc. The nonvolatile memory device 130 may maintain a data even when power supply is interrupted, such as a flash memory. It may be a device. However, the scope of the present invention is not limited thereto, and the RAM device 120 and the nonvolatile memory device 130 may be implemented with various storage devices.

In order to easily describe an embodiment of the present invention, the ram device 120 is shown as being separated from the controller 110, but the scope of the present invention is not limited thereto, the ram device 120 is a controller 110 ) May be included inside.

The controller 110 according to an embodiment of the present invention may include a data buffer 111 and a write credit (WC) return unit 112. The data buffer 111 may be a storage circuit for receiving data DATA from the host 101 or temporarily storing the received data DATA. For example, data DATA received from the host 101 may be first written to the data buffer 111. Thereafter, the data DATA stored in the data buffer 111 may be transferred to the RAM device 120 or the nonvolatile memory device 130.

That is, the data buffer 111 may be a high speed storage circuit that satisfies the interface speed between the host 101 and the controller 110. The data buffer 111 may be a register or a high speed memory included in an interface layer or a physical layer between the host 101 and the controller 110.

In exemplary embodiments, the data buffer 111 may include write credits (WCs) having a predetermined size. That is, the WC may cover a storage unit or a unit buffer of a predetermined unit. For example, when the data buffer 111 is 512 KB and one WC is 4 KB, the total number of WCs for the data buffer 111 may be 128.

Host 101 may include a WC counter 102. The WC counter 102 may include information about the number of available WCs among the WCs of the data buffer 111. The host 101 may perform a write operation on the memory module 100 based on the WC counter 102. For example, if a unit of one WC is 4 KB and the value of the WC counter 102 is "8", the host 101 transmits write data of "4 * 8 = 32 KB" to the memory module 100. Can be.

The host 101 may update the WC counter 102 based on the size of the write data transmitted (or the number of write commands issued or the number of units of write data transmitted). For example, if one WC has a unit of 4 KB and the host 101 transmits 16 KB of write data, the host 101 will use four WCs. In this case, the host 101 can subtract the value (ie, four) for the WC used from the current value of the WC counter 102. That is, when the host 101 transmits 16 KB of write data, the WC counter 102 may be updated from "8" to "4".

For example, if the value of the WC counter 102 is "0", since there is no WC available by the host 110, the host 101 may not be able to transmit write data to the controller 110.

For example, the WC returning unit 112 of the controller 110 may provide the WC release information RWC to the host 101. For example, when the first data stored in the first WC of the data buffer 111 is transferred to the RAM device 120 or the nonvolatile memory device 130, the first WC of the data buffer 111 is released. Can be "The first WC is released" means that the first WC can be used by the host 101. In other words, the released first WC may be used to store data received from the host 101. As described above, the WC returning unit 112 may transmit the WC release information RWC for the released WCs to the host 101.

The host 101 may update the WC counter 102 based on the WC release information RWC from the controller 110. For example, as described above, the WC release information RWC indicates the number of WCs released by the operation of the controller 110 among the WCs used in the data buffer 111. In other words, the WC release information RWC indicates the number of WCs available by the host 101. When the WC release information RWC indicates "4", the host 101 may add a value of "4" to the WC counter 102.

In exemplary embodiments, the WC release information RWC may be provided in an asynchronous manner. For example, when the release of the WC occurs, the controller 110 may transmit a return signal RTN to the host 101. The host 101 may receive the WC release information RWC from the controller 110 in response to the return signal RTN. In exemplary embodiments, the WC release information RWC may be provided through the same signal line as the data DATA. Alternatively, the WC release information RWC may be provided to the host 101 through a separate signal line or a separate communication channel.

Alternatively, the WC release information RWC may be transmitted by an explicit request from the host 101. Alternatively, the WC release information RWC may be transmitted to the host 101 together with the read data according to the read request of the host 101.

As described above, the host 101 may manage the available WCs of the data buffer 111 of the controller 110, and the controller 110 may transmit information about the released WC to the host 101. . Therefore, a speed decrease in data transmission between the host 101 and the controller 110 can be prevented.

2A through 2C are block diagrams for describing an operation between the host 101 and the controller 110 of FIG. 1. For the sake of brevity, a detailed description of the above-described components will be omitted.

Hereinafter, in order to clearly and concisely explain embodiments of the present invention, various expressions having specific meanings are used. For example, "use of the WC by the host" means that the host allocates or uses the write data to transmit the write data or the host transmits the write data to the WC. In addition, " release of WC " refers to a state in which write data stored in the WC is transferred to the RAM device or the nonvolatile memory device so that other write data can be received. Also, "the transfer of write data stored in the WC to the RAM device or the nonvolatile memory device" means that the write data stored in the WC is copied or moved to the RAM device or the nonvolatile memory device. The above-described expressions are intended to briefly and clearly describe the embodiments of the present invention, but the scope of the present invention is not limited thereto.

For convenience of explanation, it is assumed that the data buffer 111 includes eight WCs WC1 to WC8. In addition, it is assumed that each write data transmitted from the host 101 to the controller 110 corresponds to the size of one WC. That is, the size of one write data may be equal to the size of one WC, and one write data may be stored in one WC.

2A-2C, the computing system 10 includes a host 110 and a memory module 100. Host 101 includes a WC counter 102. The memory module 100 may include a controller 110, a RAM device 120, and a nonvolatile memory device 130. Since each component has been described above, a detailed description thereof will be omitted.

As shown in FIG. 2A, in the initial state, the value of the WC counter 102 may be "8". This indicates that eight WCs (ie, WC1 to WC8) are available in the data buffer 111.

Thereafter, as illustrated in FIG. 2B, the host 101 may perform a write operation on the first to fourth write data DT1 to DT4. In this case, the host 101 may use four WCs WC1 to WC4. That is, the first to fourth write data DT1 to DT4 received from the host 101 may be stored in the first to fourth WCs WC1 to WC4, respectively. The host 101 can subtract the value of the WC counter 102 by the number of WCs used (ie, four). In this case, the value of the WC counter 102 will be "8-4 = 4". This means that the number of WCs available in the data buffer 111 is four.

Although not shown in the drawing, the host 101 may update the WC counter 102 based on the number of write commands transmitted to the controller 110. For example, the size of write data for one write command may correspond to the size of one WC. In this case, when four write commands are transmitted to the controller 110, the host 101 may subtract "-4" from the value of the WC counter 102.

Next, as shown in FIG. 2C, some WCs may be released by the operation of the controller 110. For example, write data stored in the third and fourth WCs WC3 and WC4 may be transferred to the RAM device 120. In this case, the third and fourth WCs WC3 and WC4 will be released.

The WC returning unit 112 may transmit the WC release information RWC for the released WCs to the host 110. As shown in FIG. 2C, since the third and fourth WCs WC3 and WC4 have been released, the WC release information RWC may be information indicating that two WCs have been released. The host 110 may update the WC counter 102 in response to the WC release information RWC. For example, as described above, since the two WCs have been released, the host 101 can add the value of the WC counter 102 by " + 2 ". In this case, the value of the WC counter 102 will be "6". This means that six WCs of the WCs of the current data buffer 111 are available.

As described above, when the host 101 transmits write data to the controller 110, the WC counter 102 of the host 101 determines the number or size of write data transmitted or the number of write commands transmitted. It is updated (or subtracted) based on. In addition, when the WCs of the data buffer 111 are released by the operation of the controller 110, the controller 110 transmits the WC release information RWC to the host 101, and the host 101 transmits the WC release information ( The WC counter 102 may be updated (or added) based on the RWC. Therefore, since the resources of the memory module 100 can be recognized without the periodic polling operation of the host 101 or without any other checking operation, the write performance can be improved.

3 is a flowchart illustrating an operation of the host 101 of FIG. 1. 1 and 3, in step S111, the host 101 may determine whether the number of available WCs is greater than the reference value TH. For example, the value of the WC counter 102 of the host 101 may indicate the number of available WCs. The host 101 can determine whether the value of the WC counter 102 is greater than the reference value TH. In exemplary embodiments, the reference value TH may be “0” or an integer greater than “0” depending on the operation mode or the type of the write command.

For example, if the number of available WCs is not greater than the reference value TH, it may mean that the controller 110 does not include enough WCs to receive the write data transmitted from the host 101. In this case, even if the host 101 transmits the write data to the controller 110, the controller 110 may not normally receive the write data or the previously received data may be lost. In this case, the host 101 may not perform a write operation until available WCs are secured.

For example, if the number of available WCs is not greater than the reference value TH, in step S112, the host 101 may read the WC release information RWC from the controller 110. For example, the host 101 may transmit a return command for reading the WC release information RWC to the controller 110. At this time, the return command may be transmitted by the host 101's own operation or may be transmitted in response to the return signal RTN from the controller 110. In exemplary embodiments, the return command may be a command predefined by an interface between the host 101 and the memory module 100, a vendor command, or a combination of specific commands. Alternatively, the host 101 transmits a read command for reading general read data to the controller 110, and the controller 110 transmits WC release information RWC to the host 101 together with the read data corresponding to the read command. Can be. As described above, the host 101 may read the WC release information RWC from the controller 110 based on various schemes.

In operation S113, the host 101 may update the WC counter 102 based on the WC release information RWC. For example, as described above, the host 101 can add the value indicated by the WC release information RWC to the value of the WC counter 102. Thereafter, the host 101 may perform step S111.

When the comparison result of step S111 indicates that the number of available WCs is larger than the reference value TH, the host 101 may perform the operation of step S115. In operation S115, the host 101 may transmit write data to the controller 110 based on the WC counter 102, and may update the WC counter 102 based on the transmitted write data.

For example, the host 101 may transmit write data to the controller 110 based on the value of the WC counter 102. In this case, the size of the write data transmitted may be smaller than or equal to the size corresponding to the value of the WC counter 102. The host 101 may subtract the value of the WC counter 102 based on the size of the transmitted write data. In exemplary embodiments, the host 101 may subtract the value of the WC counter 102 based on the number of write commands transmitted.

4 is a flowchart illustrating an operation of the controller 110 of FIG. 1. 1 and 4, in step S121, the controller 110 may receive data from the host 101 and store the received data in the WC. In exemplary embodiments, the data receiving and data storing operations may be performed simultaneously or sequentially.

In operation S122, the controller 110 may determine whether data is moved from the WC to the RAM device 120 or the nonvolatile memory device 130. For example, as described above, the data stored in the WC may move to the RAM device 120 or the nonvolatile memory device 130 according to the operation of the controller 110. In this case, the WC in which data is stored will be released.

When data is moved from the WC to the RAM device 120 or the nonvolatile memory device 130, in step S123, the controller 110 supplies the WC release information RWC under the control of the host 101. Can be sent to. For example, the controller 110 may transmit the WC release information RWC to the host 101 in response to a return request from the host 101. In exemplary embodiments, the return request may be issued by the host 101 in response to the return signal RTN of the controller 110 or by the host 101's own operation. Alternatively, the controller 110 may transmit read data and WC release information RWC corresponding to the read command to the host 101 in response to the read command from the host 101.

5A through 5C are timing diagrams for describing operations of the host 101 and the controller 110 of FIG. 1. In the following, components unnecessary to describe the embodiment of the present invention are omitted. Further, assume that the value of the initial WC counter 102 is "4". In addition, it is assumed that the size of the write data D for one write command WR is the same as the size of one WC. That is, write data D for one write command may be stored in one WC. In other words, the host 101 may use one WC to transmit write data D for one write command.

First, referring to FIGS. 1 and 5A, the value of the initial WC counter 102 may be "4". This may indicate that four WCs WC of the WCs WC of the data buffer 111 are available.

The host 101 may perform a write operation based on the WC counter 102. For example, when the value of the WC counter 102 is "4", the host 101 controls four write commands WR1 to WR4 and four write data D1 to D4 corresponding to the controller 110. ) Can be sent.

Each time the host 101 transmits each of the write commands WR1 to WR4, the host 101 may update the WC counter 102. For example, when the host 101 transmits the first write command WR1, the host 101 may subtract the value of the WC counter 102 from "4" to "3" by "-1". When the host 101 transmits the second write command WR2, the host 101 may subtract the value of the WC counter 102 from "3" to "2" by "-1". That is, each time the host 101 transmits a write command, the host 101 may decrease the value of the WC counter 102 by one. This is because the host 101 uses the WC of the data buffer 111 to transmit write data. In other words, the corresponding write data is stored in any one WC of the data buffer 111 of the controller 110 by the write command of the host 101.

After the fourth write command WR4 is transmitted, the value of the WC counter 102 may be "0". In this case, since there is no WC available, the host 101 will not be able to send a write command or write data to the controller 110. In other words, the host 101 will not perform a write operation during the first time T1.

At the first time point t1, the WC may be released according to the operation of the controller 110. For example, as described above, according to the operation of the controller 110, some write data of the write data stored in the data buffer 111 may be transferred to the RAM device 120 or the nonvolatile memory device 130. have. In this case, the area (ie, WC) of the data buffer 111 in which some data is stored will be released.

The WC returning unit 112 of the controller 110 may detect the release of the WC at the first time point t1 and may transmit a return signal RTN to the host 101. In exemplary embodiments, the return signal RTN may be provided through a specific signal line, and the return signal RTN may have a logic low level. However, the scope of the present invention is not limited thereto.

The host 101 may transmit a return command RCM to the controller 110 in response to the return signal RTN. The return command RCM may be a command for reading the WC return information RWC. The controller 110 may provide the WC return information RWC to the host 101 through the data line DQ in response to the return command RCM.

The host 101 may update the WC counter 102 based on the received WC return information RWC. For example, if the WC return information RWC indicates that four WCs have been released, the host 101 may add the value of the WC counter 102 by "+4" from "0" to "4". .

Thereafter, the host 101 may perform a write operation based on the updated WC counter 102. For example, the host 101 may transmit four write commands WR5 to WR8 and four write data D5 to D8 corresponding to the controller 110 based on the WC counter 102. As described above, each time the write commands WR5 to WR8 are transmitted, the WC counter 102 can be updated (that is, subtracted by "-1").

In exemplary embodiments, the WC release information RWC may be provided in an asynchronous manner, as shown in FIG. 5. Alternatively, although not shown in the drawing, the WC release information RWC may be provided to the host 101 at a specific period.

By way of example, Table 1 shows an update method of the WC counter 102.

Number of write commands issued (m) Return of WC (n) WC counter change -m + n

Referring to Table 1, the WC counter 102 may be decremented by the number of write commands issued by the host 101 (m). This is because the WCs of the data buffer 111 of the controller 110 are used according to the number of write commands of the host 101. The WC counter 102 may be incremented by the return amount n of WCs (ie, the number of released WCs). This is because the released WCs are available by the host 101. As described above, the host 101 may manage the number of available WCs of the data buffer 111 of the controller 110. In addition, the controller 110 may provide the host 101 with WC release information RWC indicating the number of released WCs, and the host 101 may provide a WC counter 102 based on the received WC release information RWC. ) Can be updated. Therefore, the write operation performance of the host 101 is improved.

Next, referring to FIGS. 1 and 5B, the WC returning unit 112 may accumulate WC release information each time the WC is released. For example, at the first time point t1 of FIG. 5B, the first data D1 may move to the RAM device 120. In this case, the WC in which the first data D1 is stored will be released. Similarly, at each of the second to fourth time points t2, t3, and t4, each of the second to fourth data D2, D3, and D4 is transferred from the WC to the RAM device 120 according to the operation of the controller 110. I can move it. In this case, the WC returning unit 112 may accumulate WC return information RWC at each of the first to fourth time points t1, t2, t3, and t4. As a result, the WC return information RWC will have a value of "4" at the fourth time point t4. This indicates that the number of released WCs is four.

Thereafter, the host 101 may transmit a return command RCM to the controller 110. In exemplary embodiments, the return command RCM may be issued by the host 101 by itself without a separate signal (eg, a return signal) from the controller 110.

The controller 110 may transmit the WC release information RWC to the host 101 in response to the return command RCM. When the WC release information RWC is "4", the value accumulated in the WC returning unit 112 will be subtracted by "-4". That is, when the WC release information RWC is transmitted to the host 101, the value accumulated in the WC returning unit 112 may be reset.

The host 101 may update the WC counter 102 based on the received WC return information RWC. Thereafter, the host 101 transmits the fifth to eighth write commands WR5 to WR8 and the fifth to eighth data D5 to D8 corresponding to the controller 110, and the WC counter 102. Can be updated.

Next, referring to FIGS. 1 and 5C, the host 101 may transmit a read command RDC for reading read data to the controller 110. The controller 110 may transmit read data RD to the host 101 in response to the read command RDC. At this time, the controller 110 may transmit the accumulated WC release information RWC together with the read data RD. For example, the controller 110 may transmit a data packet including WC release information RWC and read data RD to the host 101.

The host 101 may update the WC counter 102 based on the received WC release information RWC. Since the rest of the operation has been described above, a detailed description thereof will be omitted.

6 is a block diagram illustrating a computing system 20 according to an embodiment of the present invention. Referring to FIG. 6, the computing system 20 may include a host 201 and a memory module 200. The memory module 200 may include a controller 210, a RAM device 220, a nonvolatile memory device 230, and a backup power source 240. Since the host 201, the memory module 200, the controller 210, the RAM device 220, and the nonvolatile memory device 230 have been described above, a detailed description thereof will be omitted.

The ram device 220 may include first and second regions 221 and 222. The first and second regions 221 and 222 may be storage spaces for storing data. When the power supply to the memory module 200 is stopped, data stored in the first area 221 may be lost. On the other hand, even when the power supply to the memory module 200 is stopped, the data stored in the second area 222 may be maintained.

For example, the backup power supply 240 may supply auxiliary power to the memory module 200 when the power supply to the memory module 200 is stopped (ie, sudden power off (SPO)). When the power supply is stopped, the data stored in the second area 222 may maintain the data by using the auxiliary power from the backup power source 240. Alternatively, when the power supply is interrupted, data stored in the second area 222 may be flushed to the nonvolatile memory device 230 using the auxiliary power from the backup power supply 240. That is, even if the power supply is stopped, the data stored in the second area 222 may be maintained using the backup power source 240. In other words, a portion of the RAM device 220 (ie, the second region 222) may be a power backed storage region.

The host 201 may include a WC counter 202 and a PC counter 203. The controller 210 may include a data buffer 211, a WC returner 212, and a PC (Persist Credit) returner 213. Since the WC counter 202, the data buffer 211, and the WC return unit 212 have been described above, a detailed description thereof will be omitted.

The PC counter 203 may manage the number of available PCs. For example, the second area 221 of the RAM buffer 220 may be divided into a plurality of PCs PC. A Persist Credit (PC) may refer to a unit storage space capable of storing data regardless of a power supply. That is, when the second region 221 of the RAM buffer 220 is 512 KB and one PC has a unit of 4 KB, the second region 221 of the RAM buffer 220 may include 128 PCs. For example, one PC of the RAM device 211 may have the same size as one WC of the data buffer 211, but the scope of the present invention is not limited thereto.

In an example embodiment, in a particular type of write operation, the host 201 may transmit write data to the controller 210 using a PC. For example, the host 201 may perform a persistent write operation. The passive write operation refers to an operation of ensuring the maintenance of write data provided from the host 201 even when power supply is interrupted. In other words, even if the power supply is interrupted, the data written to the memory module 200 by the write write operation should be maintained.

As described above, the second area 222 of the RAM device 220 indicates a storage area where data is maintained even when power supply is interrupted. Accordingly, in the write operation, the host 201 may write the write data using the second area 222 of the RAM device 220. In this case, the host 220 may transmit the write data using the PC of the RAM device 220 similarly to the use of the WC described above.

When the host 201 performs a write operation, the host 201 may update (or decrease) the PC counter 203 based on the size of write data or the number of write write commands.

In an exemplary embodiment, in a write write operation, write data received from the host 201 may be first stored in the WC of the data buffer 211, and then transferred to the PC of the second region 222. . That is, the host 201 may perform a write process using both the WC and the PC. In this case, the host 201 may update (or decrement) the WC counter 202 and the PC counter 203 based on the size of the write data or the number of the write write commands.

The PC return unit 213 of the controller 210 may provide the PC (Persist Credit) release information (RPC) of the second area 222 of the RAM device 220 to the host 201. For example, as described above, in a write write operation, the PCs of the second region 222 of the RAM device 220 may be used by the host 201. Thereafter, according to the operation of the controller 210, specific data stored in the second area 222 is transferred to the nonvolatile memory device 230, whereby the PC in which the specific data is stored may be released. The PC return unit 213 may provide the PC release information (RPC) indicating the information about the number of released PCs to the host 201. In exemplary embodiments, the PC release information RPC may be provided in an asynchronous scheme, similar to the WC release information RWC. Alternatively, the PC release information RPC may be provided to the host 101 by a return command or a read command of the host 101 similarly to the WC release information RWC.

The host 201 may update the PC counter 203 based on the PC release information (RPC). For example, the PC release information (RPC) may include information on the number of released PCs. The host 201 may add the value of the PC counter 203 by the number of released PCs.

As described above, the host 201 may manage the number of available WCs and available PCs of the memory module 200 based on the WC counter 202 and the PC counter 203.

Although the WC returning unit 212 and the PC returning unit 213 are shown as independent configurations, the scope of the present invention is not limited thereto. The WC return unit 212, the PC return unit 213, or a combination thereof may be implemented as one hardware configuration or one software configuration as a buffer return unit. The WC returner 212 and the PC returner 213 implemented in software may be driven by separate processors.

7A to 7D and 8 are diagrams for describing operations of the host 201 and the controller 210 of FIG. 6. For the sake of brevity, a detailed description of unnecessary components in each operation is omitted.

7A-7D and 8, the computing system 20 may include a host 201 and a memory module 200. The host 201 may include a WC counter 202 and a PC counter 203. The memory module 200 may include a controller 210, a RAM device 220, and a nonvolatile memory device 230. The controller 210 may include a data buffer 211, a WC return unit 212, and a PC return unit 213. Since each component has been described above, a detailed description thereof will be omitted.

For convenience of description, the data buffer 211 includes eight WCs (ie, WC1 to WC8), and the second area 222 of the RAM device 220 may include four PCs PC1 to PC4. It is assumed to be included. That is, as shown in FIG. 7A, in the initial state, the PCs PC1 ˜ included in the second regions 222 of the RAM device 220 and the WCs WC1 ˜WC8 included in the data buffer 211. PC4) is all available (ie, released or not storing data), so the value of WC counter 202 will be "8" and the value of PC counter 203 will be "4". .

Subsequently, as shown in FIG. 7B, the host 201 may perform write operations on the first and second data D1 and D2 and the first and second persisted data PD1 and PD2. have. Write operations on the first and second data D1 and D2 are normal write operations, and write operations on the first and second persistent data PD1 and PD2 are persistent write operations. Assume that it is (persist write operations). That is, the first and second pass data PD1 and PD2 may be stored in the second region 222 or the nonvolatile memory device 230 of the RAM device 220.

In other words, the host 201 may send two general write commands and two persistent write commands to the controller 210. In this case, the host 201 subtracts the value of the WC counter 202 based on two general write commands, and the value of the WC counter 202 and the value of the PC counter 203 based on two persistent write commands. You can subtract the value. For example, since two general write commands have been provided to the controller 210, the controller 210 can subtract the value of the WC counter 202 by "-2".

On the other hand, since the two write write commands are provided to the controller 210, the controller 210 may subtract the value of the WC counter 202 and the value of the PC counter 203 by "-2", respectively. In the case of a general write command, data can be transferred using the WCs of the data buffer 211. However, in the case of a write write command, a PC in the second area 222 of the RAM device 220 is used to maintain data. Because they must be used.

As a result, when two general write commands and two persistent write commands are sent to the controller 210, the host 201 may subtract the value of the WC counter 202 by "-4", and the PC The value of the counter 203 can be subtracted by "-2". Accordingly, as shown in FIG. 7B, the value of the WC counter 202 will be set to "4" and the value of the PC counter 203 will be set to "2".

In exemplary embodiments, the first and second pass data PD1 and PD2 and the first and second data D1 and D2 received from the host 201 may be transferred to the first to fourth WCs WC1 to WC4. May be stored first. Subsequently, some of the first to fourth WCs WC1 to WC4 may be released by the operation of the controller 210.

For example, as illustrated in FIG. 7C, according to the operation of the controller 210, the first and second data D1 and D2 stored in the third and fourth WCs WC3 and WC4 may be stored in the RAM device ( 220). In this case, as described above, the third and fourth WCs WC3 and WC4 may be released.

The WC returning unit 212 may provide the host 201 with WC release information RWC for the number of released WCs WC3 and WC4, and the host 201 may receive the received WC release information RWC. Based on the WC counter 202 may be updated. For example, in the example described above, the WC release information RWC may correspond to a value of "+2". The host 201 may increase the value of the WC counter 202 by "+2" based on the received WC release information RWC. In this case, the value of the WC counter 202 will be "6".

Thereafter, by the operation of the controller 210, the first and second pass data PD1 and PD2 stored in the first and second WCs WC1 and WC2 are stored in the first and second regions of the second area 222. The first and second write data DT1 and DT2 stored in the second PCs PC1 and PC2 and stored in the first and second PCs PC1 and PC2 may be stored in the nonvolatile memory device 230. Can be. In this case, the first and second PCs PC1 and PC2 may be released.

For example, in order to ensure the persistence of the first and second persistent data PD1 and PD2, the first and second persistent data PD1 and PD2 may be connected to the first and second PCs PC1. , PC2 may be received from the host 201. That is, the first and second pass data PD1 and PD2 are first stored in the first and second WCs WC1 and WC2 and then transferred to the first and second PCs PC1 and PC2. Can be.

Thereafter, the first and second pass data PD1 and PD2 stored in the first and second PCs PC1 and PC2 may be transferred to the nonvolatile memory device 230. In this case, since the first and second pass data PD1 and PD2 are transferred to the nonvolatile memory device 230, the first and second PCs in which the first and second pass data PD1 and PD2 are stored. (PC1, PC2) will be available to use by the host 201. That is, the first and second PCs PD1 and PD2 may be transferred to the nonvolatile memory device 230 so that the first and second PCs PC1 and PC2 may be released.

The PC return unit 213 may provide the PC release information (RPC) for the number of released PCs to the host 201, and the host 201 may determine a WC counter based on the received PC release information (PWC). 202 and the PC counter 203 can be updated. For example, as shown in FIG. 7C, when two PCs PC1 and PC2 are released, the PC release information RPC may correspond to a value of "+2". In this case, the host 201 may increase the value of the WC counter 202 and the value of the PC counter 203 by "+2" in response to the PC release information RPC.

In exemplary embodiments, the assist data for the write pass command may not be stored in both the WC and the PC. For example, as shown in FIG. 10, the first and second pass data PD1 and PD2 for the write write command may be stored in the first and second WCs WC1 and WC2. The first and second pass data PD1 and PD2 stored in the first and second WCs WC1 and WC2 may be transferred to the nonvolatile memory device 230 without passing through the PCs PC1 and PC2. Can be. In this case, it may be determined that the first and second PCs PC1 and PC2 used for the first and second write data DT1 and DT2 are released.

That is, when the write data for the persistent write command is stored in the nonvolatile memory device 230, the PC return unit 213 may determine that the PCs corresponding to the write data for the persistent write command are released. The PC return unit 213 may transmit PC release information (RPC) for the number of released PCs to the host 201. The host 201 may update the WC counter 202 and the PC counter 203 based on the received PC release information (RPC).

Table 2 shows how to update the WC counter 202 and the PC counter 203 according to each operation.

Normal write command
Number of publications (m) Persistent Write Command
Issue count (i) WC
Return count (n) PC
Return count (k) WC counter change -m -i + n + k PC counter change 0 -i 0 + k

The host 201 may update the WC counter 202 and the PC counter 203 based on the scheme described in Table 2. For example, a normal write command does not need a guarantee of data permanence, so no PC is used. Therefore, when the general write command is issued m times, the host 201 subtracts the value of the WC counter 202 by -m, and the PC counter 203 is not updated. Persistent write commands require data persistence, so PCs are used, and WCs are used for data transfer. Therefore, when the write write command is issued i times, the host 201 subtracts the value of the WC counter 202 and the value of the PC counter 203 by -i, respectively. If returned, the returned WCs can be used to transfer write data to the host 201, so the host 201 adds the value of the WC counter 202 by + n. When k PCs are returned from the controller 210, the returned PCs can be used to store write data for the host 201's write write command, so that the host 201 determines the value of the PC counter 203. Add each by + k.

9 is a flowchart illustrating a method of operating the host 201 of FIG. 6. 6 and 9, in step S211, the host 201 may determine whether a write command to be performed is a persistent write command.

If the write command to be performed is a sustain command, in step S212, the host 201 determines whether the value of the WC counter 202 is larger than the first reference value TH1 and the size of the PC counter 203 is the second reference value TH2. Can be determined to be greater than). In exemplary embodiments, each of the first reference value TH1 and the second reference value TH2 may be “0” or a positive integer based on the number of operation mode persistent write commands.

When the value of the WC counter 202 is not larger than the first reference value TH1 or the size of the PC counter 203 is not larger than the second reference value TH2, the host 201 may not perform an operation on the assist write command. You will not be able to perform it. This is because there is not enough WC or PC required to perform the write write command. In this case, in step S213, the host 201 may read the PC release information RPC from the controller 214. Since the method of receiving the PC release information (RPC) is similar to the method of receiving the WC release information (RWC) described above, a detailed description thereof will be omitted.

In operation S214, the host 201 may update the WC counter 202 and the PC counter 203 based on the PC release information (RPC). Since the updating method of the WC counter 202 and the PC counter 203 based on the PC release information (RPC) has been described with reference to FIGS. 7A to 7D, 8, and Table 2, a detailed description thereof will be omitted. After operation S214, the controller 210 may perform operation S212.

When the value of the WC counter 202 is larger than the first reference value TH1 and the size of the PC counter 203 is larger than the second reference value TH2, in operation S215, the host 201 writes data to the controller 210. Can be sent and the WC counter 202 or the PC counter 203 can be updated.

When the determination result of step S211 indicates that the write command is not a write command, the host 201 may perform operations of steps S216 to S218. Operations of steps S216 to S218 are similar to those of steps S111 to S113 of FIG. 3, and thus a detailed description thereof will be omitted.

10 is a flowchart illustrating a method of operating the memory module 200 of FIG. 6. 6 and 10, in step S221, the memory module 200 may determine whether a command received from the host 101 is a write write command. If the received command is not a write command, that is, a write command, the memory module 200 may perform operations of steps S221 to S223. Operations of steps S221 to S223 are similar to those of steps S121 to S123 of FIG. 4, and thus a detailed description thereof will be omitted.

When the received command is a write write command, the memory module 200 may perform operations of steps S224 to S229. In operation S224, the memory module 200 may receive data from the host 201 and store the received data in the WC.

In operation S225, the memory module 200 may determine whether data is moved from the WC to the PC. That is, the memory module 200 may determine whether the WC is released.

When the data moves from the WC to the PC, in step S226, the memory module 200 may accumulate the WC release information RWC.

In operation S227, the memory module 200 may determine whether data is moved from the PC to the nonvolatile memory device 230. That is, the memory module 200 may determine whether the PC is released.

When data moves from the PC to the nonvolatile memory device 230, the memory module 200 may accumulate the PC release information RPC.

In operation S229, the memory module 200 may transmit the WC release information RWC or the PC release information RPC to the host 201 under the control of the host 201.

For example, the operation of step S226 or step S228 may be omitted according to a transmission method of the WC release information RWC or the PC release information RPC. For example, whenever the release of the WC or the release of the PC occurs, when the memory module 200 uses the method of providing the return signal (RTN) to the host 201, the operations of the step S226 or the step S228 are omitted. Can be.

The operation method according to the above-described flowchart is exemplary, and the scope of the present invention is not limited thereto. The operation method of the memory module 200 according to the present invention may be variously modified without departing from the technical spirit of the present invention.

FIG. 11 is a timing diagram for describing an operation of the host 201 and the controller 210 of FIG. 6. 6 and 11, initially, the value of the WC counter 202 may be “4” and the value of the PC counter 203 may be “2”. This means that the number of WCs available by the host 201 is four, and the number of PCs is two.

The host 201 may perform a pass write operation or a general write operation based on the WC counter 202 and the PC counter 203. For example, the host 201 controls the controller 210 to control the first and second persistent write commands PWR1 and PWR2 and the corresponding first and second persistent data PD1 and PD2. ) Can be sent.

As described above, the host 201 may subtract the value of the WC counter 202 and the value of the PC counter 203, respectively, in response to the first and second persistent write commands PWR1 and PWR2. . That is, the host 201 may transmit the first write write command PWR1 and subtract the WC counter 202 and the PC counter 203 by "-1", respectively. The host 201 may transmit the second write write command PWR2 and subtract the WC counter 202 and the PC counter 203 by "-1", respectively.

At the time when the second write write command PWR2 is transmitted, the value of the PC counter 203 will be "0". In this case, since there is no PC usable by the host 201, the host 201 may not perform a pass write operation. On the other hand, since the value of the WC counter 202 is "2", the host 201 may perform a normal write operation. That is, the host 201 may transmit the first and second write commands WR1 and WR2 and the corresponding first and second data D1 and D2 to the controller 210.

At the time when the second write command WR2 is transmitted, since the values of the WC counter 202 and the PC counter 203 are "0", the host 201 may not perform a write operation or a data transfer.

At the first time point t1, as described above, some WCs may be released by the operation of the controller 210. In this case, the controller 210 may transmit a return signal RTN to the host 201.

The host 201 may transmit a return command RCM to the controller 210 in response to the return signal RTN, and the controller 210 may transmit the WC release information RWC in response to the read command RD. . It is assumed that the WC release information RWC corresponds to a value of "+2". The host 201 may add the value of the WC counter 202 by "+2" in response to the WC release information RWC.

At the time point when the WC release information RWC is received, since the value of the WC counter 202 is updated to "2", the host 201 may perform a normal write operation. Accordingly, the host 201 may transmit the third write command WR3 and the third data D3 corresponding thereto to the controller 210. As the third write command WR3 is transmitted to the controller 210, the host 201 may subtract the WC counter 202 by "-1".

At the second time point t2, some PCs may be released by the operation of the controller 210. For example, as described above, the first and second persistent data PD1 and PD2 for the first and second persistent write commands PWR1 and PWR2 are stored in the nonvolatile memory device 230. As such, two PCs can be released. In this case, the controller 210 may provide a return signal RTN to the host 201, and the host 201 may transmit a return command RCM to the controller 210 in response to the return signal RTN. have. The controller 210 may transmit the PC release information RPC to the host 201 in response to the return command RCM.

The host 201 may update the WC counter 202 and the PC counter 203 based on the PC release information (RPC). For example, if the PC release information (RPC) indicates that two PCs have been released, the host 201 may set the WC counter 202 and the PC counter 203 to "+2" based on the PC release information (RPC), respectively. You can add by ".

When the PC release information (RPC) is received, the value of the WC counter 202 is "3", and the value of the PC counter 203 is "2", so that the host 201 can perform a pass write operation or a normal write. You can perform the operation. For example, the host 201 may transmit the third write write command PWR3 and the sixth data DT6 corresponding thereto to the controller 210. As the third write write command PWR3 is transmitted to the controller 210, the host 201 may subtract the value of the WC counter 202 and the value of the PC counter 203 by "-1", respectively.

As described above, the host 201 according to the present invention manages the buffer resources of the memory module 200 by updating the WC counter 202 and the PC counter 201 in accordance with a pass write operation or a general write operation. can do. In addition, the host 201 may update the WC counter 202 and the PC counter 201 based on the WC release information RWC and the PC release information WPC returned from the controller 210.

For example, a scheme of transmitting the WC release information RWC and the PC release information RPC may be variously implemented. For example, similarly as described with reference to FIGS. 6 and 7, the WC returning unit 212 and the PC returning unit 213 are each WC release information and PC release information based on the released WC and released PC, respectively. May be accumulated, and the accumulated information may be transmitted in response to a return command or a read command from the host 201.

12A and 12B are block diagrams illustrating operations of the host 201 and the controller 210 of FIG. 6. For the sake of brevity, a detailed description of unnecessary components in each operation is omitted.

12A and 12B, the computing system 20 may include a host 201 and a memory module 200. The host 201 may include a WC counter 202 and a PC counter 203. The memory module 200 may include a controller 210, a RAM buffer device 220, and a nonvolatile memory device 230.

For convenience of description, it is assumed that the first and second WCs WC1 and WC2 and the first and second PCs PC1 and PC2 are used according to the write operation of the host 201. That is, before the configuration shown in Fig. 12A, the value of the WC counter 202 will be "6" and the value of the PC counter 203 will be "2". Thereafter, as shown in FIG. 12A, write data stored in the first and second WCs WC1 and WC2 is stored in the first and second PCs PC1 and PC2 according to the operation of the controller 210. Can be. In this case, the first and second WCs WC1 and WC2 will be released.

The WC returning unit 212 may provide the host 201 with WC release information RWC for the released first and second WCs WC1 and WC2, and the host 201 may receive the received WC release information. The WC counter 202 may be updated based on (RWC). In the embodiment of FIG. 12A, since the number of released WCs is two, as a result, the host 201 may add the value of the WC counter 202 by "+2".

Thereafter, as illustrated in FIG. 12B, write data stored in the first and second PCs PC1 and PC2 may be stored in the nonvolatile memory device 230 according to the operation of the controller 210. In this case, the first and second PCs PC1 and PC2 will be released.

The PC return unit 213 may transmit the PC release information RPC of the released first and second PCs PC1 and PC2 to the host 201, and the host 201 may receive the received PC release information ( The PC counter 203 may be updated based on the RPC. In the embodiment of FIG. 12B, since the number of released PCs is two, as a result, the host 201 may add the value of the PC counter 203 by "+2".

As described above, the host 201 may separately manage the WCs and the PCs of the memory module 200 and based on the WC release information RWC and the PC release information RPC received from the controller 210. The WC counter 202 and the PC counter 203 can be updated individually. Table 3 shows an update method of the WC counter 202 and the PC counter 203 according to the embodiments of FIGS. 14A and 14B.

Normal write command
Number of publications (m) Persistent Write Command
Issue count (i) WC
Return amount (n) PC
Return amount (k) WC counter change -m -i + n 0 PC counter change 0 -i 0 + k

Referring to Table 3, since the configuration for issuing a general write command and generating a write write command is the same as that in Table 2, the description thereof is omitted. When the number of WCs returned from the controller 210 is n, the host 210 may add the value of the WC counter 202 by "+ n", where the change amount of the PC counter 203 is " 0 ". When the number of PCs returned from the controller 210 is k, the host 210 may add the value of the PC counter 203 by "+ k", where the change amount of the WC counter 202 is " 0 ". That is, in the embodiments described with reference to FIGS. 7A to 7D, 8, and Table 2, the host 201 updates both the WC counter and the PC counter based on the amount of PCs returned, but FIGS. 14A and 14B. In the embodiments described with reference to Table 3, the host 201 updates only the WC counter 202 based on the WC release information RWC, and the PC counter 203 based on the PC release information RPC. It is configured to update only. That is, the host 201 may manage the WC counter 202 and the PC counter 203 based on the WC release information RWC and the PC release information RPC, respectively.

13A through 13D are timing diagrams for describing operations of the host 201 and the controller 210 according to the exemplary embodiment of FIGS. 12A through 12B. For the sake of brevity, a description overlapping with the components described above will be omitted.

6 and 13A, initially, the value of the WC counter 202 may be “4” and the value of the PC counter 203 may be “2”. Since the operation from the time when the host 201 transmits the first write write command PWR1 to the second time t2 is similar to the operation of FIG. 11, a detailed description thereof will be omitted. At the second time point t2, some PCs may be released according to the operation of the controller 210. The controller 210 may transmit a return signal RTN to the host 201. The host 201 transmits a read command RD to the controller 210 in response to the return signal RTN, and the controller 210 sends PC release information RPC in response to the read command RD. ) Can be sent.

As described with reference to FIG. 11, the host 201 may update only the PC counter 203 without updating the WC counter 202 based on the received PC release information (RPC). For example, the WCs released at the first time point t1 may be WCs released by the controller 210 transferring the first and second assist data PD1 and PD2 from the WCs to the PCs. The PCs released at the second time point t2 may be WCs released by the controller 210 transferring the first and second pass data PD1 and PD2 from the PCs to the nonvolatile memory device 230. Therefore, as described with reference to Table 3, the host 201 may update only the PC counter 203 based on the PC release information (RPC).

Next, in FIGS. 13B to 13D, the host 201 may include first and second persist commands PWR1 and PWR2, corresponding first and second persist data PD1 and PD2, and first and second values. The second general write commands WR1 and WR2 and the first and second data D1 and D2 corresponding thereto may be transmitted to the controller 210.

Similar to the embodiment described with reference to FIGS. 6 and 7, the WC return unit 212 stores the first and second pass data PD1 and PD2 and the first and second data D1 and D2. Each time the WC is released, the WC release information RWC can be accumulated. In addition, the PC return unit 213 may accumulate the PC release information RPC each time the PC is released.

For example, at each of the first to fourth time points t1, t2, t3, t4, the first and second persistent data PD1, PD2 may move from the WC to the PC, and the first and second The data D1 and D2 may move from the WC to the first region 221 of the RAM device 220 or the nonvolatile memory device 230. In this case, at each time point, the WC is released, and accordingly, the WC return unit 212 accumulates the WC return information RWC by "+1".

In addition, at each of the second and third time points t2 and t3, the first and second pass data PD1 and PD2 stored in the PC may move to the nonvolatile memory device 230. In this case, at each of the second and third time points t2 and t3, the PC is released, and the PC return unit 213 accumulates the PC return information RPC by "+1". As a result, at the fourth time point t4, the accumulated WC return information RWC and the accumulated PC return information RPC will be "4" and "2", respectively.

In FIG. 13B, the controller 210 may receive a first return command RCM1 from the host 201. The first return command RCM1 may be a command transmitted to the controller 210 to secure the available WC by the host 201.

The controller 210 may transmit the WC return information RWC to the host 201 in response to the first return command RCM1, and the host 201 may transmit a WC counter based on the received WC return information RWC. 202 can be updated.

The host 201 may transmit the third general write command WR3 and the third data D3. Thereafter, the host 201 may transmit a second return command RCM2 to the controller 210. The second return command RCM2 may be a command transmitted by the host 201 to the controller 210 to secure an available PC.

The controller 210 may transmit the PC release information RWC to the host 201 in response to the second return command RCM2, and the host 201 may transmit a PC counter based on the received PC release information RWC. 203 can be updated.

Next, referring to FIG. 13C, the host 201 may transmit a third return command RCM3 to the controller 210. Unlike the first and second return commands RCM1 and RCM2 described above, the third return command RCM3 is transmitted to the controller 210 to secure both the available WC and the available PC by the host 201. It may be a command.

The controller 210 may transmit the WC release information RWC and the PC release information RPC to the host 201 in response to the third return command RCM3, and the host 201 may receive the received WC release information ( The WC counter 202 and the PC counter 203 may be updated based on the RWC) and the PC release information (RPC), respectively.

Next, referring to FIG. 13D, the host 201 may transmit a read command RDC to the controller 210. The controller 210 may transmit the read data RD to the host 201 in response to the read command RDC. At this time, when the accumulated WC release information or accumulated PC release information exists, the controller 210 may host the WC release information RWC and the PC release information RPC together with the read data RD. The host 201 may update the WC counter 202 and the PC counter 203 based on the received WC release information RWC and PC release information RPC, respectively.

As described above, the WC returning unit 212 and the PC returning unit 213 of the controller 210 may accumulate the WC release information RWC and the PC release information RPC according to the release of the WC and the PC. The accumulated information may be transmitted to the host 201 in response to a return command or a read command from the host 201.

14 is a diagram illustrating examples of the WC counter 202 and the PC counter 203 of FIG. 6. For example, in the above-described embodiments, the WC counter 102, 202 or the PC counter 203 may determine the number of available WCs or the number of available PCs among the WCs or PCs of the controller 110, 210. It is configured to manage.

However, the scope of the present invention is not limited thereto, and as illustrated in FIG. 17, the WC counter 202 and the PC counter 203 may be implemented in a bitmap form, respectively. For example, the WC counter 202 may be implemented in the form of a bitmap, and each bit may correspond to the plurality of WCs WC1 to WCn of the data buffer 211, respectively. In the write operation, the host 201 may manage the used WC and the available WC, respectively, by changing the value of the bit corresponding to the used WC.

Similarly, the PC counter 203 may be implemented in the form of a bitmap, and each bit may correspond to the plurality of PCs PC1 to PCm of the second area 222 of the RAM device 220. In the write operation, the host 201 may manage the used PC and the available PC by changing the value of the bit corresponding to the used PC.

Configurations of the above-described bitmap type WC counter and PC counter are exemplary, but the scope of the present invention is not limited thereto. Configurations of the WC counter and the PC counter can be variously modified without departing from the spirit of the invention.

15 is a block diagram illustrating a computing system 30 according to an example embodiment. Referring to FIG. 15, the computing system 30 may include a host 310 and a memory module 300. The host 301 may include a WC counter 302 and a PC counter 303. The memory module 300 may include a controller 310, a nonvolatile memory device 330, and a backup power source 340. The controller 310 may include a first buffer 311, a WC return unit 312, a PC return unit 313, and a second buffer 320. The second buffer 320 may include first and second regions 321 and 322. Since each component of FIG. 15 has been described above, a detailed description thereof will be omitted.

In exemplary embodiments, the first buffer 311 may correspond to the data buffer described above, and the second buffer 320 may correspond to the RAM device described above. For example, the first buffer 311 may include the WCs WC described above, and the second buffer 320 (particularly, the second region 322) may include the PCs PC. Can be. That is, FIG. 18 illustrates a configuration in which the second buffer 320 is included in the controller 310. As described above, the controller 310 may comprise a PC and may operate similar to that described above.

16 is an exemplary block diagram of a memory module in accordance with the present invention. Referring to FIG. 16, the memory module 1000 may include a controller 1100, nonvolatile memory devices 1200, and DRAM devices 1300. The controller 1100 may include WCs WC and PCs PC. The controller 1100 may write data received through the data line DQ to the nonvolatile memory device 1200 or to the DRAM device 1300. In exemplary embodiments, the memory module 1000 or the controller 1100 may communicate with an external device through a DDR interface.

In exemplary embodiments, the controller 1200 may operate based on the method described with reference to FIGS. 1 to 15. For example, the controller 1200 may store write data received through the data line DQ in the WC, and when the WC is released, the WC release information RWC may be transferred to the external device through the data line DQ. Can provide. Alternatively, the controller 1200 may store the write data received through the data line DQ using the WC and the PC. When the WC or the PC is released, the controller 1200 may transmit the WC release information (RWC) or the PC release information (RPC). It may be provided to an external device through the data line DQ.

Although not shown in the drawing, the PC may be included in some areas of the DRAM devices 1300, and some areas may maintain data regardless of the power supply by using a separate backup power source.

17 is an exemplary block diagram of a memory module in accordance with the present invention. Referring to FIG. 17, the memory module 2000 may include a controller 2100, a plurality of memory devices 2210 ˜ 2280, and a plurality of data buffers DB. In example embodiments, the memory module 2000 may communicate with an external device (eg, a host) based on a DDR interface. For example, the controller 2100 of the memory module 2000 may be configured to control the plurality of memory devices 2210-2280 and the data buffers DB in response to a command CMD from the outside.

The plurality of data buffers DB may transmit and receive data to and from the external device through the data lines DQ and the data strobe lines DQS, and write data received from the outside to the plurality of memory devices 2210 ˜. 2280).

The configuration of the memory module 2000 shown in FIG. 17 is exemplary, and the scope of the present invention is not limited thereto. For example, the memory module 2000 may have an RDIMM structure in which a plurality of data buffers DB are omitted. Alternatively, the controller 2100 receives the plurality of data signals DQ and the data strobe signal DQS provided to the memory module 2000, and the controller 2100 receives the plurality of memory devices based on the received signal. 2210-2280).

18 is a block diagram illustrating a computing system to which a memory module according to the present invention is applied. Referring to FIG. 18, the user system 3000 may include a processor 3001 and a plurality of memories 3110 to 3140.

The processor 3001 may include a controller 3002. The controller 3002 may communicate with the plurality of memories 3110 to 3140 through the bus 3003. For example, the bus 3003 may include dedicated buses connected to each of the plurality of memories 3110 to 3140 or a shared bus shared with the plurality of memories 3110 to 3140. In exemplary embodiments, at least some of the plurality of memories 3110 to 3140 may be memory modules described with reference to FIGS. 1 to 17 or may be operated based on the operation methods described with reference to FIGS. 1 to 17. .

Alternatively, at least some of the plurality of memories 3110 to 3140 may include nonvolatile memories, and others may include volatile memories. The memory module including the volatile memory may be used as the cache memory or the buffer memory of the memory module including the nonvolatile memory. That is, some of the memories 3110 to 3140 may be used as a RAM device or a buffer including a PC. In exemplary embodiments, the controller 3002 may operate based on the operation method described with reference to FIGS. 1 to 17. Alternatively, the processor 3001 may manage WCs or PCs based on the method described with reference to FIGS. 1 through 17.

The foregoing is specific embodiments for practicing the present invention. The present invention will include not only the above-described embodiments but also embodiments that can be simply changed in design or easily changed. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

Claims (10)

A RAM device including a first storage area and a second storage area;
Nonvolatile memory devices; And
A controller configured to control the RAM device or the nonvolatile memory device under a control of a host,
The controller is:
A data buffer configured to temporarily store first data received from the host; And
When the first data is moved from the data buffer to the first region or the second region of the RAM device, first release information is transmitted to the host, and the first data is nonvolatile from the second region. And a buffer return unit configured to transmit second release information to the host when moved to the memory device. The method of claim 1,
The second storage area is physically separated from the first storage area,
And an auxiliary power supply configured to supply auxiliary power to the second storage area. The method of claim 1,
The data buffer includes a plurality of first unit buffers,
The second region of the RAM device includes a plurality of second unit buffers,
And the first data is temporarily stored in any one of the plurality of first unit buffers, and moves from one of the first unit buffers to any one of the plurality of second unit buffers. The method of claim 3, wherein
The first release information is information indicating that the first unit buffer in which the first data is stored among the plurality of first unit buffers is released. The method of claim 3, wherein
The second release information is information indicating that the second unit buffer, in which the first data is stored, of the plurality of second unit buffers is released. The method of claim 3, wherein
And a first count value of the host is updated based on the first release information, and a second count value of the host is updated based on the second release information. The method of claim 6,
The first count value indicates the number of available first unit buffers among the plurality of first unit buffers, and the second count value indicates the number of available second unit buffers among the plurality of second unit buffers. Memory module pointing. The method of claim 1,
When the first data moves from the data buffer to the first area or the second area, or when the first data moves from the second area to the nonvolatile memory device, the controller returns a signal to the host. Memory module to transmit. The method of claim 1,
In response to a return command from the host, the buffer return unit to transmit the first release information or the second release information to the host. The method of claim 1,
In response to a read command from the host, the buffer return unit transmits a data packet including the first release information or the second release information and read data corresponding to the read command to the host.

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