KR20190086366A - Redistribution system with uniform characteristic multi-layered homogeneous structure and method of manufacture thereof - Google Patents

Abstract

A redistribution system includes a substrate; and a plurality of redistribution layers on the substrate. The plurality of redistribution layers comprises conductive traces and a plurality of polymer layers surrounding the conductive traces. The thickness of each of the polymer layers is less than the thickness of each of the conductive traces. The polymer layers are free of invasive materials. It is possible to reduce costs and improve efficiency and performance.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redistribution system and a method for manufacturing the redistribution system,

[0001] This application claims the benefit of US patent application entitled " REDISTRIBUTION SYSTEM WITH HOMOGENEOUS NON-CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF " filed concurrently by Raymond W. Bae and Yingmei Zheng. A related application is assigned to AIS Technology, Inc. and is identified by Docket No. 50-002. The subject matter of which is incorporated herein by reference to the present invention.

[0002] This application claims the benefit of US Provisional Application Ser. No. 10 / 395,505, filed concurrently with Raymond W. Bae and Yingmei Zheng, entitled "REDISTRIBUTION SYSTEM WITH ROUTING LAYERS IN MULTI-LAYERED HOMOGENEOUS STRUCTURE AND METHOD OF MANUFACTURING THEREOF" . The relevant application is assigned to AIS Technology, Inc. and is identified by the Docket No. 50-004. The subject matter of which is incorporated herein by reference to the present invention.

[0003] This application claims the benefit of U.S. Provisional Application No. 60 / 032,504, filed concurrently herewith by Raymond W. Bae and Yingmei Zheng, entitled "REDISTRIBUTION SYSTEM WITH DENSE PITCH AND COMPLEX CIRCUIT STRUCTURES IN MULTI-LAYERED HOMOGENEOUS STRUCTURE AND METHOD OF MANUFACTURING THEREOF" And the like. The relevant application is assigned to AIS Technology, Inc. and is identified by the Docket No. 50-005. The subject matter of which is incorporated herein by reference to the present invention.

[0004] Embodiments of the present invention generally relate to redistribution systems, and more particularly to redistribution systems having multi-layered homogeneous structures.

[0005] Modern consumer and industrial electronic devices, cellular phones, mobile devices, and computing systems, including them, provide increasing levels of functionality to support modern life. Research and development of existing technologies can take a myriad of different directions.

[0006] As users are more empowered with the growth of computing devices, new and old paradigms begin to take advantage of this new device space. There are many technical solutions to take advantage of these new device capabilities and device miniaturization. However, reliable testing of wafers through new devices has become a concern for manufacturers.

[0007] Accordingly, there is still a need for a redistribution system for testing wafers through devices. It is becoming increasingly important to find solutions to these problems, in view of the ever-increasing commercial competitive pressures with increasing consumer expectations and decreasing opportunities for meaningful product differentiation in the marketplace. Additionally, the need to reduce costs, improve efficiencies and performance, and cope with competitive pressures adds even greater urgency to the critical need to find solutions to these problems.

[0008] Solutions to these problems have long been sought, but previous developments have not taught or suggested any solutions, and solutions to these problems have not been available to those skilled in the art for a long time.

[0009] An embodiment of the present invention is a semiconductor device comprising: a substrate; And a plurality of redistribution layers on the substrate, wherein the plurality of redistribution layers comprise conductive traces, and a plurality of polymer layers surrounding the conductive traces, wherein the polymer layer thickness of each of the polymer layers is greater than the thickness of the traces of conductive traces Less than the thickness; There are no intrusive materials in the polymer layers.

[0010] Embodiments of the present invention provide a method of manufacturing a redistribution system, the method comprising: providing a substrate; And forming a plurality of redistribution layers on the substrate, wherein forming the plurality of redistribution layers comprises: forming conductive traces comprising a trace thickness; And forming a plurality of polymer layers free of intrusion-resistant material and surrounding the conductive traces, wherein the polymer layer thickness for each of the polymer layers is less than the trace thickness of the conductive traces.

[0011] Certain embodiments of the invention have other steps or elements in addition to or instead of the above. Steps or elements will be apparent to those skilled in the art upon reading the following detailed description when taken in conjunction with the accompanying drawings.

[0012] FIG. 1 is a schematic side view of a redistribution system of an embodiment of the present invention.
[0013] FIG. 2 is a top view of the redistribution platform of FIG. 1 of a redistribution system.
[0014] FIG. 3 is a cross-sectional view of the redistribution platform of FIG. 2 along line 2--2 of FIG. 2;
[0015] FIG. 4 is a plan view of the substrate.
[0016] FIG. 5 is a cross-sectional view of the substrate of FIG. 4 taken along line 4--4 of FIG. 4;
[0017] Figure 6 is the substrate of Figure 4 with conductive traces formed.
[0018] FIG. 7 shows the structure of FIG. 6 in forming polymer layers.
[0019] FIG. 8 is the structure of FIG. 7 in forming one of the redistribution layers of FIG.
[0020] FIG. 9 shows the structure of FIG. 8 in forming a redistribution platform.
[0021] FIG. 10 is a schematic side view of the redistribution system of FIG. 2 of a further embodiment.
[0022] FIG. 11 is a flowchart of a method of manufacturing a redistribution system of an embodiment of the present invention.

[0023] The following examples are described in sufficient detail to enable those skilled in the art to practice and use the invention. It is to be understood that other embodiments will be apparent based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the embodiments of the present invention.

[0024] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent that the present invention may be practiced without these specific details. In order to avoid obscuring the embodiments of the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.

[0025] The drawings illustrating embodiments of the system are not necessarily drawn to scale, but some of the dimensions, in particular, are for clarity of presentation and are exaggerated in the drawings, . Similarly, for ease of illustration, the views of the drawings generally show similar orientations, but this description of the drawings is, in most cases, arbitrary. In general, the present invention can be operated in any orientation.

The designations and uses of the terms first, second, third, etc. are for convenience and clarity and are not intended to limit the particular order. The described steps or processes may be performed in any order to implement the claimed subject matter.

[0027] Referring now to FIG. 1, a schematic side view of redistribution system 100 of an embodiment of the present invention is shown. The redistribution system 100 is a system for providing interconnections between different devices. For example, the redistribution system 100 may be a component of the wafer testing system 120 or a substrate of an integrated circuit packaging system. As an example, the wafer testing system 120 may include a mechanical stiffener 102, a printed circuit board 104, a redistribution platform 106, and a probe card 108. The mechanical stiffener 102, the printed circuit board 104, the redistribution platform 106, and the probe card 108 are components for testing the semiconductor wafer 110. The semiconductor wafer 110 may be a processed silicon wafer on which electronic components (not shown), such as circuits, integrated circuits, logic, integrated logic, or a combination thereof, are fabricated.

[0028] The probe card 108 is an interface for contacting test locations on a semiconductor wafer 110, semiconductor dies 112, or a combination thereof. The probe card 108 includes probe heads 114 for contacting the testing points or chip contact pads (not shown) on components formed on the surface of a semiconductor wafer 110, a die, . ≪ / RTI >

[0029] The redistribution platform 106 is a structure for providing interconnections between two devices. For example, the redistribution platform 106 may be a space transformer, a package substrate for an integrated circuit package, a redistribution structure for a multi-die package, or a combination thereof. The redistribution platform 106 is shown as a component capable of providing an electrical connection between the probe card 108 of the wafer testing system 120 and the printed circuit board 104. For example, The redistribution platform 106 may provide electrical and functional connections between the semiconductor wafer 110, the semiconductor die 112, or a combination thereof for system testing, such as wafer testing, die testing, package testing, or inter-package testing .

[0030] Referring now to FIG. 2, a top view of redistribution platform 106 of FIG. 1 of redistribution system 100 is shown. The redistribution platform 106 may include routing traces 210 and a homogenous dielectric structure 212.

[0031] Routing traces 210 are one or more conductive structures extending through redistribution platform 106. One or more routing traces 210 may be all connected together to form one large routing trace 210, i.e., to form partly separate but connected routing traces 210 , Or may be isolated from each other to form individual and isolated routing traces 210 that are separate from any other routing traces 210.

[0032] The redistribution platform 106 of FIG. 1 may also provide a transition between the printed circuit board 104 of FIG. 1 and the probe card 108 of FIG. For example, routing traces 210 may be a multi-layered structure for providing electrical connections. As a specific example, the routing trace 210 may include electrical connections between connection points and wider geometric structures on the printed circuit board 104 of FIG. 1 and smaller geometries and connection points of the probe cards 108. [ Connection can be provided. The transitions may include different geometries of electrical connections, different densities, different connection points, sizes of connections, number of routing traces 210, signal assignments, ground assignments, power assignments, .

[0033] Routing traces 210 may comprise a conductive material. For example, routing traces 210 may include metals, such as elemental copper, silver, or gold, or metal alloys such as copper alloys, silver alloys, or gold alloys.

[0034] Routing traces 210 may be used to transmit electrical signals through redistribution platform 106. For example, in one embodiment, the routing traces 210 may facilitate transmission of electrical signals from the printed circuit board 104 to the probe card 108. Routing traces 210 may also provide shielding of electrical signals and provide grounds for routing traces 210 by surrounding other routing traces 210 used for signal transmission. For example, the routing traces 210 may achieve pitches 214 on the redistribution platform 106 with a scale in the range of less than or equal to 20 micrometers. As a result, electrical signals transmitted through one or more routing traces 210 may cause electromagnetic interference to each other. Pitch 214 refers to the shortest measurement between the center-to-center distances between the features of the redistribution platform 106, such as routing traces 210.

[0035] In one embodiment, one or more routing traces 210 may include other routing traces 210 that transmit signals to provide improved signal quality across the redistribution platform 106 May be used to serve as ground traces by providing grounding so that the resulting signals can be shielded from interfering with electromagnetic signals.

[0036] The homogenous dielectric structure 212 is a non-conductive material, such as a dielectric material, that surrounds the routing traces 210. The homogenous dielectric structure 212 may be an electrically insulating material that provides insulation between each of the routing traces 210. For example, the homogenous dielectric structure 212 may be a structure formed from a polymeric material. The homogenous dielectric structure 212 may be transparent or translucent and allows optical visibility of the routing traces 210 through the homogenous dielectric structure 212. Transparent or translucent refers to allowing light of the visible wavelength spectrum to pass through. As an example, the object may be at least partially visible through the translucent material. As another example, the object may be viewed as being potentially distinct through the transparent material. The details of the redistribution platform 106 will be discussed below.

[0037] Referring now to FIG. 3, there is shown a cross-sectional view of redistribution platform 106 of FIG. 2 along line 2--2 of FIG. The cross-sectional view shows a redistribution platform 106 that includes redistribution layers 320 on a substrate 330.

[0038] The homogenous dielectric structure 212 may be formed from a plurality of redistribution layers 320, as shown by dashed lines. Redistribution layers 320 are individual layers of non-conductive material chemically bonded together. Each of the redistribution layers 320 may include a layer of routing traces 210 embedded within itself.

[0039] The homogeneous dielectric structure 212 is a uniform structure formed from a single material. For example, the homogenous dielectric structure 212 can be a homogeneous polymer structure that does not include any intrusion-resistant materials, such as fiber reinforcements. The lack of interstitial or buried material allows the homogenous dielectric structure 212 to be translucent or transparent depending on the properties of the dielectric material used to form the homogeneous dielectric structure 212. Because the homogeneous dielectric structure 212 is formed of a single material, the homogenous dielectric structure 212 may have uniform structural and thermal properties, such as uniform thermal expansion coefficients.

As an example, the redistribution layers 320 may be formed to have a redistribution layer thickness 324. The redistribution layer thickness 324 may be in the range of 10 micrometers to 60 micrometers or more. More specifically, redistribution layer thickness 324 may be in the range of 10 microns to 30 microns. Each of the redistribution layers 320 may have a redistribution layer thickness 324 of the same or similar values or a redistribution layer thickness 324 of different values. The redistribution layer thickness 324 of the redistribution layers 320 may be measured in a direction perpendicular to the substrate first side 340 or the substrate second side 342. [

[0041] Substrate 330 may be a hard base or base layer for redistribution system 100. More specifically, the substrate 330 may provide structural support and rigidity for the homogenous dielectric structure 212 and the routing traces 210. The substrate 330 may be formed from an electrically insulating material, such as a ceramic-based or polymer composite-based material. The substrate 330 may include a substrate first side 340 and a substrate second side 342. The substrate first side 340 and the substrate second side 342 may be opposing surfaces of the substrate 330, such as one another.

[0042] The substrate 330 may include through substrate vias 332. The substrate through vias 332 are structures that extend from one surface of the substrate 330 to the opposite surface of the substrate. As an example, the substrate through vias 332 may be formed from an electrically conductive material, including metals, such as elemental copper, silver, or gold, or metal alloys, such as copper alloys, silver alloys, .

[0043] Routing traces 210 may extend from the substrate 330 through the homogenous dielectric structure 212. Portions of the routing traces 210 may be connected to components, such as contact pads 322, at the surface of the homogeneous dielectric structure 212 back to the substrate 330. The component may provide an electrical connection between the routing traces 210 and other devices, such as test devices, including as the probe card 108 of FIG. The routing traces 210 may be electrically connected to the substrate through vias 332 on the first side of the substrate 330.

[0044] A portion of the routing traces 210 of a particular instance of the redistribution layers 320 is a layer of routing traces 210. Each layer of routing traces 210 may include a trace plane portion 214, a trace interconnect portion 216, or a combination thereof. The trace plane portion 214 is a portion of the routing traces 210 that may provide routing or redistribution along a two dimensional plane parallel to the substrate first side 340 or the substrate second side 342.

The trace interconnecting portion 342 may include a plurality of routing traces 210 that may extend from the trace planar portion 316 in a direction perpendicular to the substrate first side 340 or the substrate second side 342. [ It is a part. As an example, the trace interconnect portion 316 may provide a connection to other layers of the routing traces 210.

[0046] The substrate 330 may provide additional rigid support for the redistribution platform 106. More specifically, for example, the substrate 330 may provide structural support and rigidity for the homogenous dielectric structure 212 and the routing traces 210. The substrate through vias 332 of the substrate second side 342 may be processed for electrical connection to other devices, such as the printed circuit board 104 of FIG.

[0047] For purposes of illustration, redistribution platform 106 is shown having redistribution layers 320 formed only on substrate first side 340, but it is understood that redistribution platform 106 may be configured differently do. For example, the redistribution platform 106 may include redistribution layers 320 formed on both the substrate first side 340 and the substrate second side 342.

[0048] As a further example, the substrate 330 may be a homogenous dielectric structure 212 previously formed. In this example, only the structures formed with the homogeneous dielectric structure 212 along with the routing traces 210 and the routing traces 210 are maintained, so that another instance of the homogenous dielectric structure 212 is formed, Can be removed. Multiple instances of homogeneous dielectric structure 212 may be the same or different.

[0049] Referring now to FIG. 4, a top view of substrate 330 is shown. The plan view shows a flat or planar surface of the substrate 330, such as the substrate first side 340 or the substrate second side 342 (both in FIG. 3). The flat or planar surface of substrate 330 may be used to attach, connect, mount, or a combination of different components or materials. For example, substrate 330 may be exposed to a flat or planar surface of substrate 330 to facilitate connections to optional pre-formed components, such as electrical connections, such as routing traces 210 of FIG. 2 Bonded metal contact or contact pads 322. As shown in FIG. For illustrative purposes, contact pads 322 are illustrated as having a round or circular shape, but it is understood that contact pads 322 may have different shapes. For example, contact pads 322 may have a rectangular or oval shape.

[0050] The substrate 330 may be provided as a prefabricated structure for forming the redistribution platform 106. The substrate 330 may be formed from a number of different materials. For example, the substrate 330 may be formed from a ceramic-based material, such as a high temperature co-fired ceramic (HTCC) or a low temperature co-fired ceramic (LTCC). As another example, the substrate 330 may be formed from a polymer composite based material, such as a fiber reinforced polymer. As a specific example, the polymer-based composites may comprise fiber glass reinforced epoxy laminates, such as FR-4 (Flame Retardant-4) grade printed circuit boards. As a further example, the substrate 330 may be another instance or design similar to the redistribution platform 106.

[0051] For illustrative purposes, a top view shows a substrate 330 having a circular or hemispherical shape, but it is understood that the substrate 330 may have a different shape. For example, the substrate 330 may have an elliptical or polygonal shape, such as square, rectangular, or other polygonal shapes.

[0052] Referring now to FIG. 5, there is shown a cross-sectional view of the substrate 330 of FIG. 4 along line 4--4 of FIG. The cross-sectional view shows a portion of a substrate 330 having substrate through vias 332.

[0053] The substrate 330 may include a substrate first side 340 and a substrate second side 342. The substrate first side 340 and the substrate second side 342 may be opposing surfaces of the substrate 330, such as one another. The substrate first side 340 and the substrate second side 342 may be substantially parallel to each other.

[0054] The substrate 330 may include a substrate thickness 550. The substrate thickness 550 can be measured as the distance between the substrate first side 340 and the substrate second side 342. In general, the planar dimensions, such as width or diameter, of substrate first side 340 and substrate second side 342 may be greater than substrate thickness 550.

[0055] Substrate 330 may include substrate through vias 332. The substrate through vias 332 are structures that extend from one surface of the substrate 330 to the opposite surface of the substrate. For example, substrate through vias 332 may extend between the substrate first side 340 and the substrate second side 342.

In one example, the substrate through vias 332 are electrically conductive (eg, copper), including metals, such as elemental copper, silver, or gold, or metal alloys, such as copper alloys, silver alloys, Material. For example purposes, substrate through vias 332 are shown connected to contact pads 322, but contact pads 322 are optional and substrate through vias 332 are formed on substrate first side 340 ), The substrate second side 342, or a combination thereof. Optionally, a portion of the substrate through vias 332 exposed to the substrate first side 340, the substrate second side 342, or a combination thereof may be disposed on the substrate first side 340 or the substrate second side 342 ), Respectively.

[0057] The number, pattern, location, pitch, diameter, and size of the substrate through vias 332 are shown for illustrative purposes and are not exhaustive. For example, the substrate 330 may include through vias 332 having a pitch of the scale in the range of 10 micrometers to several hundred micrometers. As another example, the diameter of the through vias 332 can be measured on a scale of several tens of micrometers.

[0058] Referring now to FIG. 6, a substrate 330 on which conductive traces 660 are formed is shown. The conductive traces 660 are part of an electrical routing system. More specifically, the conductive traces 660 may be a single layer of the routing trace 210 of FIG. For example, the conductive traces 660 may be a single layer of a larger electrical routing system. As a specific example, the conductive traces 660 may be part of the routing trace 210 formed as a single layer.

[0059] Conductive traces 660 may be formed through a trace formation process, which may be a multi-phase process for patterning and forming conductive traces 660. For example, the trace formation process may include a masking phase, a sedding phase, a deposition phase, a planarization phase, and a mask removal phase.

The conductive traces 660 may be formed from a conductive material that may include metals, such as elemental copper, silver, or gold, or metal alloys, such as copper alloys, silver alloys, or gold alloys . As a specific example, the conductive traces 660 may be formed from the same or similar material as the material of the substrate through vias 332 of FIG.

[0061] Generally, the conductive traces 660 may be formed on a two-dimensional plane, such as a plane or surface parallel to the substrate first side 340, the substrate second side 342, or a combination thereof.

[0062] Conductive traces 660 may be formed to include trace plane portion 314, trace interconnect portion 316, or a combination thereof. For example, a first implementation of the trace formation process may be implemented to form trace plane portion 314, and a subsequent implementation of the trace formation process may be implemented to form trace interconnect portion 316 on trace plane portion 314 .

[0063] The trace plane portion 314 may include a planar portion thickness 662. The trace interconnect portion 316 may include an interconnect portion thickness 664. Both the planar portion thickness 662 and the interconnecting portion thickness 664 can be a linear dimension perpendicular to the substrate first side 340 or the substrate second side 342. Generally, the planar portion thickness 662 may be greater than the interconnect portion thickness 664. [ The sum of the planar portion thickness 662 and the interconnect portion thickness 664 is the thickness of the conductive trace that may be the same or similar to the redistribution layer thickness 324 of Figure 3 for the corresponding instance of redistribution layer 320 .

[0064] Conductive traces 660 may be formed on the substrate 330. For example, the conductive traces 660 may be formed directly on the substrate first side 340 or the substrate second side 342. Conductive traces 660 may be formed to electrically connect with the substrate through vias 332. The conductive traces 660 may be formed by a number of different processes. For example, conductive traces 660 may be formed by an electrolytic deposition process. Each of the conductive traces 660 may be formed using different geometric patterns and dimensions, as illustrated in FIG.

[0065] For illustrative purposes, a trace forming process for forming conductive traces 660 directly on the surface of the substrate 330 is illustrated in the figures. It is understood, however, that the trace formation process described herein can be implemented to form conductive traces 660 on the surfaces of other surfaces, such as the redistribution layers 320 of FIG.

[0066] Referring now to FIG. 7, the structure of FIG. 6 at the time of forming polymer layers 770 is shown. The polymer layer 770 is a layer of polymer material formed to cover the conductive traces 660. The polymer layer 770 can be an electrically insulating material that covers portions of the conductive traces 660 and can electrically isolate each instance of the conductive traces 660.

[0067] In general, each of the polymer layers 770 may be formed through a polymer formation process. As an example, the polymer forming process may include an application phase and a curing phase. In the application phase of the polymer build process, all or a portion of the conductive traces 660 may be covered by application of a liquid dielectric precursor material (not shown).

[0068] The liquid dielectric precursor material may be an organic solution or an organic suspension. For example, the liquid dielectric material may be a solution of monomers or oligomer molecules to the polymer suspended or dissolved in a solvent. The liquid dielectric precursor material may be a solution comprising monomers or oligomer molecules as precursors to one of a variety of different polymer materials. For example, the liquid dielectric precursor material may be a precursor to polyimide-based polymers, epoxy-based polymers, or other types of polymers. As a specific example, the liquid dielectric precursor material may comprise monomers or oligomer molecules that can be polymerized via a condensation reaction. In a further specific example, the liquid dielectric precursor material may comprise cross-linked or end-cap monomer units which may be involved in cross-linking of the subsequent cure phase.

Terminal-cap monomer units are molecules that can terminate or terminate the polymerization reaction of a particular molecule. More specifically, once each end of a linear polymer molecule, or a polymer molecule that does not include branching into a plurality of polymer chains, reacts with one of the terminal-cap monomer molecules, the polymer molecule is no longer in a different non-terminal- It may not react with cap monomer or oligomer molecules. In other words, once each end of the polymer molecule reacts with the end-cap molecule, the polymer molecule may no longer increase the molecular weight outside of the cross-linking reaction, as will be discussed in detail below.

[0070] The liquid dielectric precursor material may be applied in a number of ways. For example, the liquid dielectric precursor material may be applied through a spin-coating process to cover portions of the conductive traces 660. As another example, the liquid dielectric precursor material may be applied through a method that can provide a uniform distribution and thickness of the liquid dielectric precursor material across the substrate 330.

[0071] Following the application phase, the polymer formation process can proceed to a cure phase. In the curing phase, the liquid dielectric precursor material may be heated to form an instance of the polymer layers 770. Generally, the liquid dielectric precursor material can be heated to the polymerisation temperature for a period of time to promote the formation of a polymer molecular chain from the monomer or oligomer molecules. However, the polymerisation temperature differs from the cross-linking temperature, which is the temperature at which cross-linking occurs between the end-cap or cross-linking monomer molecules. More specifically, the polymerisation temperature may be lower than the temperature for cross-linking of the end-cap or cross-linking monomer molecules. The polymer molecules of the polymer layers 770 can be formed in length or molecular weight statistically proportional to the number of monomer units and end-cap units in the liquid dielectric precursor material.

[0072] Optionally, the curing phase may include a volatile removal or degassing phase to remove volatile components from the liquid dielectric precursor material. As an example, the volatile components may comprise evaporation solvent molecules, or molecules formed during the polymerization of the liquid dielectric precursor material. The optional volatile removal phase may include a gradual temperature increase to the boiling point of the solvent of the liquid dielectric precursor material or a temperature maintenance near its boiling point. The optional volatile removal phase may include agitation of the liquid dielectric precursor material through vibration, such as ultrasonic vibration, while facilitating removal of volatile components. The volatile removal phase can prevent the formation of voids due to the trapped gases at the interfaces between the polymer layers 770 and the conductive traces 660 and the polymer layers 770.

[0073] Each of the polymer layers 770 may include a polymer layer thickness 772. The polymer layer thickness 772 for each of the polymer layers 770 may be determined after the setting phase. As an example, since the polymer layers 770 are transparent, optical thickness measurement methods can be used to determine the polymer layer thickness 772 for each of the polymer layers 770. Each of the polymer layers 770 may have a different value for the polymer layer thickness 772. [ For example, the polymer layer thickness 772 for each of the polymer layers 770 can range from 1 micrometer to 20 micrometers. As a specific example, the polymer layer thickness 772 for each of the polymer layers 770 can range from 1 micrometer to 5 micrometers. Generally, the polymer layer thickness 772 for each of the polymer layers 770 may be less than the thickness of the conductive traces 770.

[0074] The polymer layers 770 can be formed sequentially through a repetitive implementation of the polymer forming process. Each of the polymer layers 770 may be formed directly on a previously formed instance of the polymer layers 770 until the conductive traces 660 are completely covered except for instances of the polymer layers 770 formed on the substrate 330. [ . For example, a first instance of the polymer layers 770 may surround and cover a portion of the sides of the trace planar portion 314 of the conductive trace. To continue the example, a second instance of polymer layers 770 formed directly on the first instance of the polymer layers 770 may be formed between the remaining exposed portions of the trace planar portion 314 of the conductive traces 660, And may cover a portion of the sides of the connecting portion 316. To develop the example, a third instance of the polymer layers 770 formed directly on the second instance of polymer layers 770 may cover the remaining exposed portions of the trace interconnect portion 316.

[0075] For purposes of illustration, the structure of FIG. 7 is shown having three instances of polymer layers 770 formed to cover the conductive traces, as indicated by the dashed lines. It is understood, however, that a different number of polymer layers 770 may be formed to cover the conductive traces 330.

[0076] Referring now to FIG. 8, there is shown the structure of FIG. 7 in forming one of the redistribution layers 320. One instance of redistribution layers 320 may be formed from the structure of FIG. 7, including conductive traces 660 embedded in the plurality of polymer layers 770 of FIG.

[0077] An instance of redistribution layers 770 may be formed by removing a portion of the outermost instance of polymer layers 770 to expose conductive traces 770. For example, portions of the surface of the instance of the polymer layer 770 that are formed farthest from the substrate 330 or that are back to the substrate 330 may be exposed when the trace interconnect portion 316 of the conductive traces 660 is exposed Can be removed. The surface of the polymer layer 770 on the substrate 330 may be planarized so as to be coplanar with portions of the conductive traces 660 exposed from the outermost instance of the polymer layers 770.

[0078] Portions of the polymer layers 770 can be removed to expose the conductive traces 660 by a number of different processes. For example, the removal process may include chemical polishing, chemical grinding, mechanical polishing, mechanical grinding, or a combination thereof.

[0079] As an example, redistribution layers 320 may be formed to have a redistribution layer thickness 550 in the range of 10 micrometers to 60 micrometers or more. 8, the thickness of the redistribution layers 320 may vary from the interface between the substrate 330 and the instances of redistribution layers 320, such as the substrate first side 340, to the substrate 330, Can be measured up to the surface of the instance of the layers 320.

[0080] Referring now to FIG. 9, there is shown the structure of FIG. 8 in forming redistribution platform 106 of FIG. The cross-sectional view shows the redistribution platform 106 formed subsequent to the sequential formation of a plurality of redistribution layers 320. For example, additional instances of conductive traces 660 may be formed directly on the contact surfaces of the previously formed redistribution layer 320. Additional instances of polymer layers 770 of FIG. 7 may be formed to cover additional instances of conductive traces 660 and previously formed instances of redistribution layers 320 to continue the example. The process may be repeated to form a plurality of redistribution layers 320 as shown in FIG.

Following formation of the final instance of redistribution layers 320, a plurality of polymer layers 770 of redistribution layers 320 may be further processed to form a homogeneous dielectric structure 212. For example, the homogenous dielectric structure 212 can be a homogeneous polymer structure that does not include any intrusion-resistant materials, such as fiber reinforcements. The absence or lack of interstitial or embedded material allows the homogenous dielectric structure 212 to be translucent or transparent depending on the properties of the dielectric material used to form the homogeneous dielectric structure 212.

[0082] The homogenous dielectric structure 212 may be formed through cross-linking between the polymer layers 770 of the redistribution layers 320. More specifically, the homogeneous dielectric structure 212 may be chemically coupled at the interface between the end-caps throughout the polymer layer 770 and between adjacent instances of the polymer layer 770 to form a single continuous structure. By heating the polymer layer 770 to a temperature or crosslinking-bonding temperature that facilitates or promotes the formation of the polymer layer 770. [ The cross-linking temperature may be different from the temperature for forming the polymer molecules of the polymer layers 770, as described in FIG. Generally, the cross-linking temperature is higher than the temperature for polymerizing the liquid dielectric precursor material of FIG. The cross-linking temperature may vary based on the end-cap unit used to form cross-linking bonds between the polymer molecules.

It has been found that a homogenous dielectric structure 212 formed by the cross-linking of polymer molecules between redistribution layers 320 eliminates the need for intervening bonding material. More specifically, the formation of cross-linking chemical bonds between the polymer molecules in adjacent instances of the polymer layer 770 eliminates the need for an adhesive or bonding material to form a homogeneous dielectric structure 212.

[0084] Routing traces 210 may be exposed from the surface of a homogenous dielectric structure 212 back to substrate 330. Alternatively, the exposed portions of the routing traces 210 may be added to be covered by contact pads 322 to provide electrical connections to other devices to the test devices, such as the probe card 108 of FIG. 1 Lt; / RTI > The routing traces 210 extend through the homogenous dielectric structure 212 and may be connected to the through vias 332 on the first side of the substrate 330. The routing traces 210 buried in the homogeneous dielectric structure 212 may provide interlocking functionality.

[0085] Substrate 330 may provide additional rigid support for redistribution platform 106. More specifically, the substrate 330 may provide structural support and rigidity for the homogenous dielectric structure 212 and the routing traces 210. The substrate through vias 332 of the substrate second side 342 may be processed for electrical connection to other devices, such as the printed circuit board 104 of FIG.

[0086] Referring now to FIG. 10, a schematic side view of the redistribution system 100 of FIG. 2 of a further embodiment is shown. In a further embodiment, redistribution system 100 may be implemented as a package substrate. In this example, redistribution system 100 may include redistribution platform 106, die 1012, die attach adhesive 1016, electrical interconnects 1020, and semiconductor cover 1022 of FIG. 1 have.

[0087] In this example, the die 1022 may be a semiconductor die, an integrated circuit, an optical device, or a combination thereof. The die 1012 may be attached directly to the semiconductor cover 1022 using a die attach adhesive 1016. [ In this example, the semiconductor cover 1012 can be a heat sink, hermetically sealing encapsulant, radio frequency shielding, or a combination thereof.

[0088] Electrical interconnections 1020 may be formed between the electrical components fabricated on the die 1012, such as circuits, integrated circuits, logic, integrated logic, and electrical connections on one side of the redistribution platform 106 Electrical connections may be provided between die 1012 and redistribution platform 106 by providing electrical connections. As an example, electrical interconnects 1020 may be solder balls or solder bumps.

The electrical interconnections 1020 are disposed on the second side of the redistribution platform 106 and include a redistribution platform 106 and external devices such as the probe card 108 of Figure 1, Substrate 104, or a combination thereof.

[0090] Referring now to FIG. 11, there is shown a flow diagram of a method 1100 of manufacturing a redistribution system 100 in an embodiment of the present invention. The method 1100 includes, at block 1102, providing a substrate; And forming a plurality of redistribution layers on the substrate, at block 1104, wherein forming the plurality of redistribution layers comprises: forming conductive traces at a block 1106, the conductive traces comprising a trace thickness; And at block 1108, forming a plurality of polymer layers free of intrusive material and surrounding the conductive traces, wherein the polymer layer thickness for each of the polymer layers is less than the trace thickness of the conductive traces.

The resulting method, process, apparatus, device, article, and / or system may be simple, cost-effective, not complex, highly versatile, accurate, sensitive, effective, And can be implemented by adapting known components for economical manufacture, application, and use. Another important aspect of embodiments of the present invention is that it valuablely supports and services historic trends that reduce costs, simplify systems, and increase performance.

[0092] Consequently, these and other valuable aspects of embodiments of the present invention develop the state of the art to at least the following levels.

[0093] While the invention has been described in conjunction with a specific best mode, it will be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the appended claims. All matters described in the specification or illustrated in the accompanying drawings shall be interpreted in an illustrative and non-limiting sense.

Claims (15)

As a redistribution system,
Board; And
A plurality of redistribution layers on said substrate,
Wherein the plurality of redistribution layers comprise conductive traces and a plurality of polymer layers surrounding the conductive traces,
The polymer layer thickness of each of the polymer layers being less than the trace thickness of the conductive traces; And
Wherein the polymer layers are free of interstitial material. The method according to claim 1,
Wherein the polymer layers are attached to each other without intervening material. The method according to claim 1,
Wherein the polymer layer thickness is from 1 micrometer to 15 micrometers. The method according to claim 1,
Wherein the trace thickness is between 5 micrometers and 15 micrometers. The method according to claim 1,
Wherein the plurality of redistribution layers each comprise a redistribution layer thickness of 10 micrometers to 30 micrometers. As a redistribution system,
A substrate, wherein the substrate includes through substrate vias in the substrate; And
A plurality of redistribution layers on said substrate,
Wherein the plurality of redistribution layers comprise conductive traces and a plurality of polymer layers covering the conductive traces,
The polymer layer thickness of each of the polymer layers being less than the trace thickness of the conductive traces; And
Wherein the polymer layers are attached to each other without intervening material. The method according to claim 6,
Wherein the conductive traces include trace interconnecting portions that connect the conductive traces in the redistribution layer of one of the redistribution layers to the conductive traces of adjacent instances of the redistribution layers. The method according to claim 6,
Wherein the conductive traces are electrically connected to the substrate through vias. The method according to claim 6,
Wherein the polymer layers are polyimide-based polymeric materials. The method according to claim 6,
Wherein the substrate comprises a ceramic substrate. A method of manufacturing a redistribution system,
Providing a substrate; And
And forming a plurality of redistribution layers on the substrate,
Wherein forming the plurality of redistribution layers comprises:
Forming conductive traces comprising a trace thickness; And
Forming a plurality of polymer layers free of intrusion-resistant material and surrounding said conductive traces,
Wherein the polymer layer thickness for each of the polymer layers is less than the trace thickness of the conductive traces. 12. The method of claim 11,
Wherein forming the redistribution layers comprises forming the redistribution layers with the polymer layers adhered to each other without intervening material. 12. The method of claim 11,
Wherein forming the polymer layers comprises forming the polymer layers to a polymer layer thickness of from 1 micrometer to 15 micrometers. 12. The method of claim 11,
Wherein forming the conductive traces comprises forming the conductive traces to a trace thickness of between 5 micrometers and 15 micrometers. 12. The method of claim 11,
Wherein forming the redistribution layers comprises forming the redistribution layers with a redistribution layer thickness of 10 micrometers to 30 micrometers.

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