KR20190085457A - Interface circuit for multi rank memory - Google Patents

Abstract

An electronic circuit of the present invention comprises a first delay line circuit and a sampling circuit. The first delay line circuit delays a first data strobe and generates a second data strobe such that an edge of the second data strobe is arranged within a first time interval in which a first data signal having a timing shifted by a first time length with respect to a reference timing of a reference data strobe represents one logic value. The sampling circuit performs sampling on the first data signal in response to the edge of the second data strobe. The first data signal and a second data signal are included in data signals which are shifted by time lengths with respect to the reference timing, respectively. In addition, an edge of the first data strobe is arranged within a second time interval in which the second data signal shifted by the shortest time length from among the time lengths with respect to the reference timing, represents one logic value.

Description

[0001] INTERFACE CIRCUIT FOR MULTI RANK MEMORY [0002]

The present invention relates to electronic circuits, and more particularly to interface circuits for memory.

BACKGROUND ART [0002] In recent years, a large amount of information is stored and processed by an information device in accordance with the development of information devices such as a computer, a mobile phone, and a smart phone. Therefore, memory devices with further improved performance are required as components of information devices. Memory semiconductors are widely used in memory devices because they can operate at low power.

Multi-rank memory systems using multiple ranks are being used as high capacity memory systems are required. In a multi-rank memory system, multiple ranks may share a single channel. Thus, without increasing the number of channels, the overall capacity of the memory system can increase.

In order to operate a multi-rank memory system, a design of an interface circuit that merges data signals generated in a plurality of ranks is required. In order to reduce the power consumed by the memory system, it is necessary to reduce the power consumed by the interface circuit. In addition, for efficiency of the memory system design, it is necessary to reduce the area in which the interface circuits are arranged.

The present invention can provide an interface circuit for constituting a memory system which is arranged in a small area and consumes a small amount of power.

An electronic circuit according to an embodiment of the present invention may include a first delay line circuit and a sampling circuit. The first data strobe is delayed so that the edge of the second data strobe is arranged in the first time period in which the first data signal having the timing shifted by the first time length with respect to the reference timing of the reference data strobe indicates one logical value , A second data strobe can be generated. And may sample the first data signal in response to an edge of the second data strobe. The first data signal and the second data signal may be included in data signals having timings that are each shifted by time lengths with respect to the reference timing. The edge of the first data strobe may be arranged in a second time period in which the second data signal having the timing shifted by the shortest time length of the time lengths with respect to the reference timing indicates one logical value.

According to embodiments of the present invention, the power consumed by the memory system can be reduced and the area of the interface circuit for the memory system can be reduced.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
2 is a block diagram illustrating an exemplary configuration of the memory of FIG.
3 is a block diagram illustrating an exemplary configuration of the interface circuit of FIG.
4 is a block diagram illustrating an exemplary configuration of the DQS split circuit of FIG.
5 is a block diagram illustrating an exemplary configuration of the merge circuit of FIG.
Figure 6 is a block diagram illustrating an exemplary configuration of the sampling circuit of Figure 5;
7 is a timing diagram illustrating training for determining the delay for the data signal and data strobe of FIG.
8 is a timing diagram illustrating exemplary variations of signals generated by the memory system of FIG.
Figure 9 is a timing diagram showing exemplary changes of signals generated by the memory system of Figure 1;
10 is a block diagram illustrating an exemplary memory and interface circuit according to the configuration of the merge circuit of FIG.
11 is a block diagram illustrating an exemplary configuration of the merge circuit of FIG.
Figure 12 is a timing diagram showing exemplary changes of signals generated by the memory system of Figure 1;
13 is a timing diagram showing exemplary changes in signals generated by the memory system of FIG.
14 is a block diagram showing an exemplary memory and interface circuit according to the configuration of the merge circuit of Fig.
15 is a flow chart illustrating an exemplary operation of the memory system of FIG.
16 is a block diagram illustrating an exemplary electronic device including the memory system of FIG.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.

Referring to FIG. 1, a memory system 100 may include a memory 110 and a memory controller 10. The memory controller 10 may include an interface circuit 120, and a control circuit 130.

The memory 110 may store data, and may input and output data. Memory 110 may receive command signals from control circuitry 130 via interface circuitry 120. [ The memory 110 can perform a read operation by controlling a command signal. The memory 110 can read the data stored by the read operation. The memory 110 may generate a data signal DQ representing the read data. By way of example, the data signal DQ may have a logic value to represent data. The memory 110 may output the data signal DQ to the interface circuit 120.

The data signal DQ may represent m-bit data corresponding to the period of the data strobe DQS (where m is a natural number). By way of example, the data signal DQ may comprise m data signals. Each of the m data signals may represent one bit of data corresponding to the period of the data strobe (DQS). As will be described with reference to FIG. 2, the memory 110 may include one or more ranks. In this specification, a rank means a unit of memory configured to input / output data of a specific size. As an example, one rank may be implemented by one memory module or the like. Each of the ranks of the memory 110 may generate one or more data signals included in the data signal DQ.

For example, the memory 110 may be a volatile memory such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), or the like configured to support a multi-rank system, volatile memory such as a random access memory (RAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), a ferro-electric RAM (FRAM), or the like. Alternatively, the memory 110 may comprise heterogeneous memories.

Each of the ranks of the memory 110 may generate a data strobe DQS to be used to read the data signal DQ. The memory 110 may output the data strobe (DQS) generated from the ranks to the interface circuit 120.

By way of example, the data strobe DQS may have a logic high value and a logic low value periodically. The data strobe DQS may include a period in which the logical value of the data strobe DQS changes from a logical low value to a logical high value (hereinafter referred to as a rising edge). The data strobe DQS may include a period in which the logical value of the data strobe DQS changes from a logical high value to a logical low value (hereinafter referred to as a falling edge). The configuration and operation of the memory will be described in more detail with reference to Fig.

The interface circuit 120 can receive the data signal DQ and the data strobe DQS from the memory 110. [ The interface circuit 120 may receive the signal SLC and the signal SLD from the control circuit 130. By way of example, the interface circuit 120 may delay the data strobe DQS based on the signal SLC. As an example, the interface circuit 120 may delay the data signal DQ or the data strobe DQS based on the signal SLD.

The interface circuit 120 may sample the data signal DQ generated from one or more ranks of the memory 110 in response to a data strobe DQS. By way of example, the interface circuit 120 may sample the data represented by the data signal DQ in response to the rising and falling edges of the data strobe DQS. The interface circuit 120 may generate a data signal high (DQH) and a data signal low (DQL) through sampling.

 The data signal high DQH and the data signal row DQL each correspond to the period of the data strobe DQS because the data signal DQ represents m bits of data corresponding to the period of the data strobe DQS m bits of data can be represented. The data signal high (DQH) may include m data signal highs. The data signal row (DQL) may comprise m data signal rows. Each of the m data signal highs and m data signal lines may represent one bit of data corresponding to the period of the data strobe (DQS).

Data signal high (DQH) and data signal row (DQL) may have logic values of data signal (DQ). Thus, the data signal high (DQH) and the data signal row (DQL) may represent data of the data signal (DQ). The interface circuit 120 may output the data signal high (DQH) and data signal low (DQL) to the control circuit 130. The configuration and operation of the interface circuit 120 will be described in more detail with reference to FIG.

Figure 1 shows an example in which the interface circuit 120 is separate from the control circuit 130 to enable a better understanding. However, in other embodiments, some or all of the interface circuit 120 may be included within the control circuitry 130.

The control circuit 130 may receive the data signal high (DQH) and the data signal low (DQL) from the interface circuit 120. The control circuit 130 may obtain the data indicated by the data signal high (DQH) and the data signal low (DQL). The acquired data may be used by a processing device such as a processor (see FIG. 16).

The control circuit 130 may store information related to the delays of the data signal DQ and the data strobe DQS. By way of example, the control circuit 130 may store information related to delays of the data signal DQ and the data strobe DQS, which are determined based on the training. The control circuit 130 may generate a signal SLC that is used to delay the data strobe DQS based on the stored information. The control circuit 130 may generate a signal SLD used to delay the data signal DQ or the data strobe DQS based on the stored information.

The delays determined based on the training may be related to the rising and falling edges of the data strobe DQS and the data signal DQ. By way of example, as the rising and falling edges of the data strobe DQS are located in a particular time interval, by delay, the interface circuit 120 can sample the data signal DQ with sufficient margin. Referring to Figs. 8, 9, 12 and 13, the delays of the data strobe DQS and the data signal DQ will be described in more detail.

1, the signal SLC and the signal SLD are shown as one signal, but the signal SLC and the signal SLD may be one or more signals SLC and SLD, as will be described with reference to FIGS. 4, 5, And may include different signals.

2 is a block diagram illustrating an exemplary configuration of the memory of FIG.

Referring to FIG. 2, the memory 110 may include first through n-th ranks 111_1 through 111_n. FIG. 2 illustrates a memory 110 that includes three or more ranks 111_1 through 111_n, although the present invention may include all embodiments that include one or more ranks.

As described with reference to FIG. 1, the data signal DQ may include m data signals. By way of example, the data signal DQ of FIG. 1 may include the data signal DQ1. The data signal DQ1 may represent one bit of data corresponding to the period of the data strobe DQS. For better understanding, the data signal DQ1 among the m data signals included in the data signal DQ will be described with reference to Figs. 2 to 6. Fig.

1, the ranks 111_1 to 111_n are connected to the data signal DQ1 and the data strobe DQS by a command signal received from the control circuit 130 via the interface circuit 120, Lt; / RTI > The data signal DQ1 and the data strobe DQS can be selectively generated only by the rank of one of the ranks 111_1 to 111_n by the command signal.

As an example, during the first time period, the first rank 111_1 may generate the data signal DQ1 and the data strobe DQS. The first rank 111_1 does not generate the data signal DQ1 and the data strobe DQS and the second rank 111_2 does not generate the data signals DQ1 and DQ2 during the second time period that does not overlap with the first time period, ) And a data strobe (DQS). The data signal DQ1 and the data strobe DQS generated by one of the first to nth ranks 111_1 to 111_n may be output to the interface circuit 120. [

3 is a block diagram illustrating an exemplary configuration of the interface circuit of FIG. Referring to FIG. 3, the interface circuit 120 may include a DQS split circuit 121 and a merge circuit 122.

The DQS split circuit 121 may receive a data strobe (DQS) from the memory 110. The DQS split circuit 121 may receive the signal SLC from the control circuit 130. [ The DQS split circuit 121 can generate the data strobe DQS_R1 to DQS_Rn based on the data strobe DQS and the signal SLC.

By way of example, the DQS split circuit 121 may delay the data strobe DQS by certain times to generate the data strobe DQS_R1 to DQS_Rn. Referring to Fig. 4, an exemplary method for generating data strobe DQS_R1 through DQS_Rn will be described. The DQS split circuit 121 may output the first to the n-th data strobe DQS_R1 to DQS_Rn to the merge circuit 122. [

The merge circuit 122 may receive the data signal DQ1 from the memory 110. [ The merge circuit 122 may receive the data strobe DQS_R1 through DQS_Rn from the DQS split circuit 121. [

As an example, the merge circuit 122 may delay each of the data signal DQ or data strobe DQS_R1 to DQS_Rn based on the signal SLD. Referring to Fig. 5, an exemplary configuration of the merge circuit 122 configured to delay the data signal DQ1 is described. Referring to Fig. 11, an exemplary configuration of the merge circuit 122 configured to delay the data strobe DQS_R1 to DQS_Rn will be described.

The merge circuit 122 may sample the delayed data signal DQ1 based on the data strobe DQS_R1 through DQS_Rn (see FIG. 5). Alternatively, the merge circuit 122 may sample the data signal DQ1 based on the delayed data strobe (DQS_R1 to DQS_Rn) (see FIG. 11).

The merge circuit 122 may generate a data signal high (DQ1H) and a data signal row (DQ1L) through sampling. The data signal high (DQ1H) and the data signal row (DQ1L) may represent data of the data signal (DQ1). The merge circuit 122 may output the data signal high (DQ1H) and the data signal row (DQ1L) to the control circuit 130. Referring to Figs. 5 and 6, how the data signal high (DQ1H) and data signal row (DQ1L) are output by the merge circuit 122 will be described.

4 is a block diagram illustrating an exemplary configuration of the DQS split circuit of FIG. The DQS split circuit 121 of FIG. 3 may include the DQS split circuit 200 of FIG.

Referring to FIG. 4, the DQS split circuit 200 may include logic multiplication operators 210_1 to 210 - n and delay lines 220_1 to 220 - n. Each of the delay lines 220_1 through 220_n may comprise electronic circuits configured to delay the signal. By way of example, each of the delay lines 220_1 through 220_n may comprise one or more buffers.

4 shows a DQS split circuit 200 that includes three or more logical multiplication operators 210_1 to 210_n and delay lines 220_1 to 220_n, but the invention is applicable to one or more logical multiplication operations 210_1 to 210_n And delay lines 220_1 through 220_n, as shown in FIG. 4 shows the logical multiplication operators 210_1 to 210_n, but the present invention can be applied to various logic circuits that are configured to output, for a specific signal, a signal substantially the same as the signal output from the logical multiplication operators 210_1 to 210_n All embodiments of the circuits.

Although not shown in Figures 1 and 3, the DQS split circuit 200 may receive gate signals G1 through Gn from the control circuit 130. [ The logical product operators 210_1 to 210_n may respectively transmit the data strobe DQS to the delay lines 220_1 to 220_n in response to the first to nth gate signals G1 to Gn.

As described with reference to FIG. 2, the data signal DQ1 may be generated by one of the first to nth ranks 111_1 to 111_n of the memory 130. The memory 110 may output the data signal DQ1 by one of the first to the n-th ranks 111_1 to 111_n under the control of the control circuit 130. [ The gate signals G1 to Gn may be associated with a rank that generates the data signal DQ.

For example, the control circuit 130 may output a gate signal that corresponds to a logic high value corresponding to a rank that generated the data signal DQ1 among the first to n-th gate signals G1 to Gn. The AND gates 210_1 to 210_n output the data strobe DQS to the delay lines 220_1 to 220_n respectively in response to the logic high of the first to nth gate signals G1 to Gn .

By way of example, the first gate signal G1 may be associated with the first rank 111_1. The first rank 111_1 can generate the data signal DQ1 by the command signal received from the control circuit 130. [ In response to this, the control circuit 130 may output the first gate signal G1 having the logic high to the logical product operator 210_1. In addition, the control circuit 130 may output the second to n-th gate signals G2 to Gn having the logic value row to the logical multiplication operators 210_2 to 210_n, respectively.

The logical product operator 210_1 can transfer the data strobe DQS to the delay line 220_1 in response to the logic high of the first gate signal G1. The AND gates 210_2 to 210_n output signals having a logic low value to the delay lines 220_2 to 220_n, respectively, in response to a logic value row of the second to n-th gate signals G2 to Gn .

The delay lines 220_1 through 220_n may receive the data strobe DQS from the logical multiplication operators 210_1 through 210_n. The delay lines 220_1 to 220 - n may receive the first to n-th signals SLC 1 to SLC n, respectively. The signals SLC of FIGS. 1 and 3 may include first through n-th signals SLC 1 through SLC n. As described with reference to Figure 1, the signal SLC may be associated with delays of the data strobe (DQS). Therefore, the first to n-th signals SLC 1 to SLC n may be related to the delay of the data strobe DQS.

The delay lines 220_1 to 220_n can delay the data strobe DQS by a specific time based on the first to n-th signals SLC 1 to SLC n, respectively. How much the delay lines 220_1 to 220 - n delay the data strobe DQS, respectively, will be described with reference to FIGS. 8 and 12. FIG. The delay lines 220_1 to 220_n may delay the data strobe DQS to generate the data strobe DQS_R1 to DQS_Rn, respectively. The delay lines 220_1 to 220_n may output the data strobe DQS_R1 to DQS_Rn to the merge circuit 122 in Fig. 3, respectively.

As one of the gate signals G1 to Gn has a logic value high and the remainder has a logic value row, a data strobe DQS is output from one of the logical sum operators 210_1 to 210_n, A signal having a row can be output. Thus, the DQS split circuit 200 can selectively output one of the data strobe (DQS_R1 to DQS_Rn) in response to a logic high of one of the gate signals Gl to Gn.

Since the data strobe DQS_R1 is output based on the data strobe DQS output in response to the logic high of the first gate signal G1, the data strobe DQS_R1 may be associated with the first rank 111_1 . Similarly, the data strobe DQS_R2 to DQS_Rn may be associated with the second to the n-th ranks 111_2 to 111_n, respectively.

5 is a block diagram illustrating an exemplary configuration of the merge circuit of FIG. The merge circuit 122 of FIG. 3 may include merge circuit 300a of FIG.

5, the merge circuit 300a may include delay lines 310a_1 to 310a_n, sampling circuits 320a_1 to 320a_n, and logical sum operators 331a and 332a. Delay lines 310a_1-310a_n may comprise electronic circuits configured to delay the signal. By way of example, delay lines 310a_1-310a_n may comprise one or more buffers.

5 illustrates the logical sum operators 331a and 332a, but the present invention is applicable to various logic circuits that are configured to output, for a particular signal, a signal substantially the same as the signal output from the logical sum operators 331a and 332a All embodiments may be included.

Each of the delay lines 310a_1 to 310a_n may receive the data signal DQ1 from the memory 130. [ The delay lines 310a_1 to 310a_n may receive the first to n-th signals SLD_DQ 1 to SLD_DQ n from the control circuit 130, respectively. The signals SLD in FIGS. 1 and 3 may include first through n-th signals SLD_DQ 1 through SLD_DQ n. As described with reference to FIG. 1, the signal SLD may be associated with delays of the data signal DQ1. Therefore, the first to n-th signals SLD_DQ 1 to SLD_DQ n may be related to the delay of the data signal DQ1.

The delay lines 310a_1 to 310a_n can delay the data signal DQ1 by a specific time based on the first to n-th signals SLD_DQ 1 to SLD_DQ n, respectively. How much the delay lines 310a_1 to 310a_n delay the data signal DQ1, respectively, will be described with reference to Fig. The delay lines 310a_1 to 310a_n may delay the data signal DQ1 to generate the data signals DQ1_R1 to DQ1_Rn, respectively. The delay lines 310a_1 to 310a_n may output the data signals DQ1_R1 to DQ1_Rn to the sampling circuits 320a_1 to 320a_n, respectively.

The sampling circuits 320a_1 to 320a_n may receive the data signals DQ1_R1 to DQ1_Rn from the delay lines 310a_1 to 310a_n, respectively. The sampling circuits 320a_1 to 320a_n may receive the data strobe DQS_R1 to DQS_Rn from the DQS split circuit 121 or 200, respectively.

The sampling circuits 320a_1 to 320a_n may generate the data signal highs DQ1H_R1 to DQ1H_Rn and the data signal lines DQ1L_R1 to DQ1L_Rn respectively in response to the data strobe signals DQS_R1 to DQS_Rn.

1, the sampling circuits 320a_1 to 320a_n respectively sample the data signals DQ1_R1 to DQ1_Rn in response to the rising edges and the falling edges of the data strobe DQS_R1 to DQS_Rn, can do.

As an example, the sampling circuits 320a_1 to 320a_n generate data signal highs (DQ1H_R1 to DQ1H_Rn) from the data signals DQ1_R1 to DQ1_Rn, respectively, in response to rising edges of the data strobe DQS_R1 to DQS_Rn can do. The sampling circuits 320a_1-320a_n may respectively generate data signal lines DQ1L_R1 through DQ1L_Rn from the data signals DQ1_R1 through DQ1_Rn in response to the falling edges of the data strobe DQS_R1 through DQS_Rn .

The sampling circuits 320a_1 to 320a_n may output the data signal highs (DQ1H_R1 to DQ1H_Rn) to the OR gate 331a. The sampling circuits 320a_1 to 320a_n may output the data signal lines DQ1L_R1 to DQ1L_Rn to the OR gate 332a.

As described with reference to FIG. 4, the DQS split circuit 121 or 200 may selectively output one of the data strobe (DQS_R1 to DQS_Rn). Thus, in response to one of the data strobe DQS_R1 through DQS_Rn, one of the sampling circuits 320a_1-320a_n may operate. Thus, one of the sampling circuits 320a_1-320a_n may output a data signal high and a data signal low corresponding to the sampling circuit. The data signal high and the data signal row may represent data of the data signal DQ1.

The sampling circuits that do not receive the data strobe from the data split circuit 121 or 200 among the sampling circuits 320a_1 to 320a_n may not perform sampling. Sampling circuits for receiving signals having a logic low value from the data splitting circuit 121 or 200 among the sampling circuits 320a_1 to 320a_n are provided with data signal highs that do not represent data of the data signal DQ1, Can be output. By way of example, data signal highs and data signal lines that do not represent data of the data signal DQl may have a logic value of zero.

The OR operator 331a may receive one of the data signal highs (DQ1H_R1 to DQ1H_Rn) representing data of the data signal DQ1 from one of the sampling circuits 320a_1 to 320a_n. The logical sum operator 332a may receive one of the data signal lines DQ1L_R1 to DQ1L_Rn representing the data of the data signal DQ1 from one of the sampling circuits 320a_1 to 320a_n. The logical sum operator 331a can output the data signal high (DQ1H) to the control circuit 130 in response to the received data signal high. The OR operator 331a may output the data signal row DQ1L to the control circuit 130 in response to the received data signal row.

The data signal high (DQ1H) may indicate the data of the received data signal high. Thus, the data signal high (DQ1H) may have a logical value of the received data signal high. Data signal row DQ1L may represent data of a received data signal row. Thus, data signal row DQ1L may have a logic value of the received data signal row.

As described above, the merge circuit 300a includes one of the data signal highs (DQ1H_R1 to DQ1H_Rn) and data signal lines (DQ1L_R1 to DQ1L_Rn) in response to one of the selectively received data strobe (DQS_R1 to DQS_Rn) ). ≪ / RTI > The merge circuit 300a may output one of the data signal highs DQ1H_R1 to DQ1H_Rn and one of the data signal lines DQ1L_R1 to DQ1L_Rn to the control circuit 130. [

For example, referring to FIGS. 2 and 4 together with FIG. 5, the first rank 111_1 of the memory 110 can output the data signal DQ1 by the command signal of the control circuit 130. FIG. The control circuit 130 may output the first gate signal G1 to the logical product operator 210_1. The DQS split circuit 200 may output the data strobe DQS_R1 to the sampling circuit 320a_1 in response to the first gate signal G1. The sampling circuit 320a_1 may sample the data signal DQ1_R1 in response to the first data strobe DQS_R1. Through sampling, the sampling circuit 320a_1 can generate a data signal high (DQ1H_R1) and a data signal row (DQ1L_R1).

The sampling circuit 320a_1 can output the data signal high (DQ1H_R1) to the OR gate 331a. The sampling circuit 320a_1 can output the data signal row DQ1L_R1 to the OR gate 332a. The logical sum operator 331a can output the data signal high (DQ1H) to the control circuit 130 in response to the data signal high (DQ1H_R1). The OR operator 332a may output the data signal row DQ1L to the control circuit 130 in response to the data signal row DQ1L_R1.

As described with reference to Fig. 4, the data strobe DQS_R1 may be associated with the first rank 111_1. Therefore, the data signal DQ1H_R1 output based on the data strobe DQS_R1 may be associated with the first rank 111_1. Similarly, the data signals DQ1H_R2 to DQ1H_Rn may be associated with the second to the n-th ranks 111_2 to 111_n, respectively.

(DQ1H) and data (DQ1R) in response to the data strobe (DQS_R2 to DQS_Rn) by a method similar to how the data signal high (DQ1H) and data signal row (DQ1L) are generated in response to the data strobe Since the signal line DQ1L can be generated, the following description is omitted. Referring to Fig. 6, the operation of the sampling circuits 320a_1 to 320a_n will be described in more detail.

As described with reference to FIG. 1, the data signal DQ may include m data signals including the data signal DQ1. Thus, the merge circuit 122 of FIG. 3 may include m merge circuits each corresponding to m data signals. For example, if m is 8, the merge circuit 122 may include eight merge circuits having a similar configuration to the merge circuit 300a (see FIG. 10).

Figure 6 is a block diagram illustrating an exemplary configuration of the sampling circuit of Figure 5;

Each of the sampling circuits 320a_1 to 320a_n in FIG. 5 may include the sampling circuit 400 in FIG. Hereinafter, the sampling circuit 400 included in the sampling circuit 320a_1 will be described. The sampling circuit 400 may include a flip flop 410 and a flip flop 420.

Referring to FIGS. 4 and 5 together with FIG. 6, the flip-flop 410 may receive the data signal DQ1_R1 from the delay line 310a_1 as the input signal D. The flip-flop 410 may receive the data strobe DQS_R1 from the delay line 220_1 as a clock CK. The flip-flop 410 can output the data signal high (DQ1H_R1) having the logic value of the data signal DQ1_R1 in response to the rising edge of the data strobe DQS_R1. The logical value of the data signal high (DQ1H_R1) can be held for a time period in which the data strobe (DQS_R1) has a logic high.

The flip-flop 420 may receive the data signal DQ1_R1 from the delay line 310a_1 as the input signal D. The flip-flop 420 may receive the data strobe DQS_R1 from the delay line 220_1 as a clock CKN. The flip flop 420 may output the data signal row DQ1L_R1 having the logic value of the data signal DQ1_R1 in response to the falling edge of the data strobe DQS_R1. The logical value of the data signal row DQ1L_R1 may be held for a time period in which the data strobe DQS_R1 has a logic value row.

As described with reference to Figs. 4 and 5, the data signal DQ1_R1 and the data strobe DQS_R1 may be associated with the first rank 111_1. Therefore, the data signal high (DQ1H_R1) and data signal row (DQ1L_R1) output based on the data signal (DQ1_R1) and the data strobe (DQS_R1) may be related to the first rank 111_1.

7 is a timing diagram illustrating training for determining the delay for the data signal and data strobe of FIG.

The first to nth ranks 111_1 to 111_n of the memory 100 may generate a data signal DQi to perform training. As an example, the data signal DQi may be one of m data signals selectively generated in one of the first through n-th ranks 111_1 through 111_n.

The control circuit 130 may sequentially input the signals T1 to T4 to the sampling circuits included in the merge circuit 122 to perform the training. Signal T1 may have a rising edge at time " ts ". The signal T2 can be generated by delaying the signal T1 by the time length? Ts1. The signal T3 can be generated by delaying the signal T1 by the time length? Ts2. The signal T4 can be generated by delaying the signal T1 by the time length? Ts3. The time length? Ts3 may be longer than the time length? Ts2 and the time length? Ts2 may be longer than the time length? Ts1.

The sampling circuits included in the merge circuit 122 may sample the data signal DQi based on the signals T1 to T4. The data signal DQi can represent data from a specific point in time. The time point " ts " Therefore, the data of the data signal DQi may not be sampled in response to the signal T1. After the time point " ts1 " from the time point " ts ", the data signal DQi can represent data. Thus, the data of the data signal DQi can be sampled in response to the signal T2. After the time point " ts2 " to " ts2 ", the data signal DQi can represent data. Therefore, the data of the data signal DQi can be sampled in response to the signal T3. After the time point " ts3 " from the time point " ts ", the data signal DQi may not indicate data. Therefore, the data of the data signal DQi may not be sampled in response to the signal T4.

The control circuit 130 can determine how far the timing of the data signal DQi is deviated from the reference timing ts (i.e., skew of the data signal DQi) based on the training described with reference to Fig. 7 have. For example, the control circuit 130 can determine that the data signal DQi is shifted from the reference time point " ts " by the time length? Ts1. The control circuit 130 can determine the delay of the data signal DQi and the data strobe DQS based on the time lengths? Ts1,? Ts2, and? Ts3. For example, the control circuit 130 determines whether or not the edge of the data strobe DQS is at a time point after the time length? Ts1 from the reference time ts and a time point after the reference time ts? The delay can be determined. 8, 9, 12 and 13, an exemplary method by which the delay is determined by the control circuit 130 will be described in more detail.

8 is a timing diagram illustrating exemplary variations of signals generated by the memory system of FIG.

Hereinafter, with reference to FIG. 8, description will be given of signals related to the data signal DQ generated by the first rank 111_1 and the data signal DQ generated by the first rank 111_1 do. As described with reference to FIG. 1, the data signal DQ may include m data signals. The data signal DQx in FIG. 8 may be one of m data signals included in the data signal DQ. Therefore, the data signal DQx can be generated in the first rank 111_1. Since the change of the data signals generated in the second to the n-th ranks 111_2 to 111_n is similar to the change of the data signal generated in the first rank 111_1, the description will be omitted.

The specific time of the m data signals (included in the data signal DQ) generated from the memory 110 can be aligned with respect to the reference time point. For example, the specific time point may be a time point at which data represented by the data signal DQx and the data signal DQmax change. In the example of Fig. 8, the specific time may be the time point tb and the time point tc. The reference time point may be a time point at which the logical value of the data strobe DQS starts to change. In the example of Fig. 8, the reference time point may be the time point ta.

Skew may be caused by noise due to various causes in the process of transmitting the data signal DQx. By way of example, the data signal DQx generated by the first rank 111_1 may be shifted by various time lengths for the data strobe DQS. That is, the data signal DQx may lag or lead back a certain time length to the data strobe DQS. The time point " tb " of the data signal DQx may deviate from the reference time point " ta " of the data strobe DQS.

 Since the noise affecting the data signal DQx is variable over time, the data signals included in the data signal DQ may be shifted by different time lengths for the data strobe DQS. The data signal DQmax means a data signal which is shifted by the longest time length among the data signals included in the data signal DQ. The time point " tc " of the data signal DQmax may deviate from the reference time point " ta " of the data strobe DQS. In the example of Fig. 8, the length of the time of deviation of the data signal DQx with respect to the data strobe DQS may be? SK1. The longest time length of the time lengths deviated from the data strobe DQS of the data signal DQ, i.e., the time length of the data signal DQmax deviated from the data strobe DQS, may be? SK2.

The data strobe (DQS) of Fig. 8 may be the data strobe (DQS) of Figs. The data strobe DQS_R1 of FIG. 8 may be the data strobe DQS_R1 of FIGS. 3-6.

The data signal DQmax and the data signal DQx may have the length of the time interval PT1 as a period. Therefore, the data signal DQmax and the data signal DQx can represent 1-bit data in units of the length of the time interval PT 1. The length of time deviated from the data strobe DQS of the data signal DQmax is longer than the length of time deviated from the data strobe DQS of the data signal DQx, Can be lagged behind the length of the interval? T1.

The period of the data strobe DQS may be substantially the same as the period of the data signal DQx and the data signal DQSmax. As described with reference to Fig. 4, the delay line 220_1 can delay the data strobe DQS based on the signal SLC1 and output the data strobe DQS_R1. Therefore, the data strobe DQS_R1 can be lagged behind the data strobe DQS by the length of the time period tDQSC1. As described with reference to FIG. 1, the time interval tDQSC1 may have a length determined based on the training described with reference to FIG. The signal SLC1 may indicate the length of the time period tDQSC1.

As an example, the control circuit 130 may determine the length of the time interval tDQSC1 based on the skew (? SK2) of the data signal DQmax obtained through training. The time interval tDQSC1 may have a length for aligning the data strobe DQS with respect to the data signal DQmax. In the example of FIG. 8, the time period tDQSC1 indicates the rising edges and the falling edges of the data strobe DQS_R1 obtained by delaying the data strobe DQS so that the data signal DQmax has time periods Lt; / RTI > As an example, the rising edge of the data strobe DQS_R1 may be aligned within the time interval PT1. Therefore, the time at which the data strobe DQS_R1 starts having a logic high value can be aligned in the middle of the time interval PT1.

Figure 9 is a timing diagram showing exemplary changes of signals generated by the memory system of Figure 1;

The data signal DQmax, the data signal DQx, and the data strobe DQS_R1 in FIG. 9 may be the data signal DQmax, the data signal DQx, and the data strobe DQS_R1, respectively, in FIG. The data signal DQx_R1 in Fig. 9 can be generated by delaying the data signal DQx by the merge circuit 122 in Fig.

As described with reference to Fig. 5, data signals DQ1_R1 to DQ1_Rn can be generated from the data signal DQ1. Similarly, n data signals can be generated from the data signal DQx. The data signal DQx_R1 may be one of n data signals. The data signal DQx_R1 can be lagged behind the data signal DQx by the length of the time period tDQ. As described with reference to FIG. 1, the time interval tDQ may have a length determined based on the training described with reference to FIG. The signal SLD_DQ 1 may indicate the length of the time period tDQ.

As an example, the control circuit 130 may determine the length of the time period tDQSC1 based on the skew (? SK1) of the data signal DQx obtained through training. The time period tDQ may have a length for aligning the data signal DQx with respect to the data signal DQmax. In the example of Fig. 9, the time period tDQ is set to be the rising edge and the falling edge of the data signal DQx_R1 obtained by delaying the data signal DQx to the rising edges and the falling edges of the data signal DQmax And may have a length for aligning them. Therefore, a change with time of the data signal DQx_R1 may be similar to a change with time of the data signal DQmax.

Although the data strobe DQS_R1 arranged in the middle of the time interval PT1 has been described with reference to FIG. 9, the present invention is not limited to the data strobe DQS_R1 including the edges arranged in the time interval PT1 May comprise all embodiments of the merge circuit 122 or 300a generating.

8 and 9, the interface circuit 120 controls the data strobe DQS_R1 to DQS_Rn based on the signal SLC so that the data strobe DQS_R1 to DQS_Rn are aligned with respect to the data signal DQmax, (DQS_R1 to DQS_Rn). Similarly to the method in which n data signals DQ1_R1 to DQ1_Rn are generated from the data signal DQ1 by the delay lines 310a_1 to 310a_n, n data signals from the data signal DQx are delayed by the delay lines Lt; / RTI > The interface circuit 120 can delay n data signals so that n data signals generated from the data signal DQx are respectively aligned with the data strobe DQS_R1 through DQS_Rn based on the signal SLD have.

Through the process described with reference to FIGS. 8 and 9, the interface circuit 120 determines whether the rising edges and falling edges of the data strobe DQS_R1 are aligned with respect to time intervals in which the data signal DQx has a particular logical value So that the data signal DQx can be delayed. By a similar process, the rising edges and the falling edges of the data strobe DQS_R2 to DQS_Rn can be respectively aligned with respect to the data signals generated from the data signal DQx, and a description thereof will be omitted.

As the data strobe DQS_R1 is aligned with respect to the data signal DQx_R1, the sampling circuit 320a_1 of FIG. 5 can sample the data signal DQx_R1 with a sufficient margin based on the data strobe DQS_R1. Similarly, the sampling circuits 320a_2 to 320a_n in FIG. 5 can sample the data signals generated from the data signal DQx, respectively, with sufficient margin.

10 is a block diagram illustrating an exemplary memory and interface circuit according to the configuration of the merge circuit of FIG.

As described with reference to FIG. 1, the memory 110 may generate m data signals by n ranks. For better understanding, the eight data signals DQ1 to DQ8 generated by the two ranks 511 and 512 and the two ranks 511 and 512 are described.

The memory 110 of FIG. 1 may include the first and second ranks 511 and 512 of FIG. The DQS split circuit 121 of FIG. 3 may include the logical product operators 531 and 532 and the delay lines 533 and 534 of FIG. The merge circuit 122 of FIG. 3 includes delay lines 521_1 to 528_1, delay lines 521_2 to 528_2, sampling circuits 541_1 to 548_1, sampling circuits 541_2 to 548_2, 551_1 to 558_1, and logical sum operators 551_2 to 558_2.

The configurations and operations of the first and second ranks 511 and 512 of FIG. 10 are respectively similar to those described with reference to the first and second ranks 111_1 and 111_2 of FIG. 2, respectively, do. The configurations and operations of the logical multiplication operators 531 and 532 and the delay lines 533 and 534 of FIG. 10 refer to the logical product operators 210_1 to 210_n and delay lines 220_1 to 220_n of FIG. 4 And therefore the following description is omitted. The delay circuits 521_1 to 528_1, the delay lines 521_2 to 528_2, the sampling circuits 541_1 to 548_1, the sampling circuits 541_2 to 548_2, the logical sum operators 551_1 to 558_1, The configurations and operations of the operators 551_2 to 558_2 are the same as those described with reference to the delay lines 310a_1 to 310a_n, the sampling circuits 320a_1 to 320a_n, and the logical sum operators 331a and 332a, And therefore the following description is omitted.

One of the first and second ranks 511 and 512 may generate the data signals DQ1 to DQ8 under the control of the control circuit 130. [ The AND gates 531 and 532 and the delay lines 533 and 534 may generate data strobe DQS_R1 and DQS_R2 in response to the first and second gate signals G1 and G2, respectively. The delay lines 521_1 to 528_1 may delay the data signals DQ1 to DQ8, respectively, to generate the data signals DQ1_R1 and DQ8_R1. The delay lines 521_2 to 528_2 may delay the data signals DQ1 to DQ8, respectively, to generate the data signals DQ1_R2 and DQ8_R2.

The sampling circuits 541_1 to 548_1 sample the data signals DQ1_R1 to DQ8_R1 based on the data strobe DQS_R1 to generate the data signal highs DQ1H_R1 and DQ8H_R1 and the data signal lines DQ1L_R1 to DQ8L_R1 Can be generated. The sampling circuits 541_2 through 548_2 sample the data signals DQ1_R2 through DQ8_R2 based on the data strobe DQS_R2 to generate the data signal highs DQ1H_R2 and DQ8H_R2 and the data signal lines DQ1L_R2 through DQ8L_R2 Can be generated.

The logical multiplication operators 551_1 to 558_1 can generate the data signal levels DQ1H to DQ8H based on the data signal levels DQ1H_R1 to DQ8H_R1 and the data signal levels DQ1H_R2 to DQ8H_R2. The logical product operators 551_2 through 558_2 may generate the data signal lines DQ1L through DQ8L based on the data signal lines DQ1L_R1 through DQ8L_R1 and the data signal lines DQ1L_R2 through DQ8L_R2.

11 is a block diagram illustrating an exemplary configuration of the merge circuit of FIG. The merge circuit 122 of FIG. 3 may include merge circuit 300b of FIG.

11, the merge circuit 300b may include delay lines 310b_1 through 310b_n, an OR gate 320b, and a sampling circuit 330b. Delay lines 310b_1 through 310b_n may include electronic circuits configured to delay the signal. By way of example, delay lines 310b_1 through 310b_n may comprise one or more buffers.

11 illustrates the logical sum operator 320b, but the present invention includes all embodiments of various logic circuits that are configured to output, for a particular signal, a signal substantially the same as the signal output from the logical sum operator 320b .

Delay lines 310b_1 through 310b_n may receive data strobe DQS_R1 through DQS_Rn from DQS split circuit 121 or 200, respectively. The delay lines 310b_1 to 310b_n may receive the first to n-th signals SLD_DQS 1 to SLD_DQS n from the control circuit 130, respectively. The signals SLD of FIGS. 1 and 3 may include first through n-th signals SLD_DQS 1 through SLD_DQS n. As described with reference to Fig. 1, the signal SLD may be associated with delays for the data strobe DQS. Therefore, the first to n-th signals SLD_DQS 1 to SLD_DQS n may be related to the delay for the data strobe (DQS).

The delay lines 310b_1 to 310b_n can delay the data strobe DQS_R1 to DQS_Rn by a specific time, respectively, based on the first to n-th signals SLD_DQS1 to SLD_DQSn, respectively. How much the delay lines 310b_1 to 310b_n delay the data strobe DQS_R1 to DQS_Rn, respectively, will be described with reference to Fig. The delay lines 310b_1 to 310b_n may delay the data strobe DQS_R1 to DQS_Rn, respectively, to generate delay data strobe DQS1_R1 to DQS1_Rn, respectively. The delay lines 310b_1 to 310b_n can output the delay data strobe DQS1_R1 to DQS1_Rn to the OR operator 320b, respectively.

The OR operator 320b may receive the delay data strobe DQS1_R1 to DQS1_Rn. The OR operator 320b may output the delayed data strobe DQS1 to the sampling circuit 330b in response to the delayed data strobe DQS1_R1 to DQS1_Rn. The delay data strobe DQS1 may correspond to one of the delay data strobe DQS1_R1 to DQS1_Rn. By way of example, the delayed data strobe DQS1 may represent a logical value of one of the delayed data strobe DQS1_R1 through DQS1_Rn

The sampling circuit 330b may receive the data signal DQ1 from the memory 110. [ The sampling circuit 330b may generate the data signal high DQ1H and the data signal line DH1L having the logic value of the data signal DQ1 in response to the delay data strobe DQS1. That is, the sampling circuit 330b can sample the data signal DQ1 based on the delay data strobe DQS1_R1 to DQS1_Rn. The sampling circuit 330b may output the data signal high DQ1H and the data signal line DH1L to the control circuit 130. [ Since the configuration and operation of the sampling circuit 330b are similar to those described with reference to Fig. 6, the following description is omitted.

As described with reference to Fig. 4, the DQS split circuit 200 may selectively output one of the data strobe DQS_R1 to DQS_Rn. Thus, the merge circuit 300b may generate the delayed data strobe DQS1 in response to one of the selectively output data strobe DQS_R1 through DQS_Rn.

For example, referring to FIGS. 2 and 4 together with FIG. 11, the first rank 111_1 of the memory 110 can output the data signal DQ1 by the command signal of the control circuit 130. FIG. The control circuit 130 may output the first gate signal G1 to the logical product operator 210_1. The DQS split circuit 200 may output the data strobe DQS_R1 to the delay line 310b_1 in response to the first gate signal G1. The delay line 310b_1 may delay the data strobe DQS_R1 based on the first signal SLD_DQS1. Delay line 310b_1 may generate delayed data strobe DQS1_R1.

The delay line 310b_1 may output the delayed data strobe DQS_R1 to the logical sum operator 320b. The OR operator 320b may output the delayed data strobe DQS1 to the sampling circuit 330b in response to the delayed data strobe DQS_R1. The sampling circuit 330b may output the data signal high DQ1H and the data signal row DQ1L having the logic value of the data signal DQ1 to the control circuit 130 in response to the delay data strobe DQS1 .

(DQ1H) and data (DQ1R) in response to the data strobe (DQS_R2 to DQS_Rn) by a method similar to how the data signal high (DQ1H) and data signal row (DQ1L) are generated in response to the data strobe Since the signal line DQ1L can be generated, the following description is omitted.

Comparing FIG. 11 with FIG. 5, merge circuit 300b of FIG. 11 may include fewer sampling circuits than merge circuit 300a of FIG. By way of example, merge circuit 300a of FIG. 5 may include as many sampling circuits 320a_1-320a_n as the number of ranks of FIG. The merge circuit 300b of FIG. 11 may include one sampling circuit 330b. Therefore, the merge circuit 300b of Fig. 11 can be placed on less area than the merge circuit 300a of Fig. Further, the merge circuit 300b of Fig. 11 can consume less power than the merge circuit 300a of Fig.

As described with reference to FIG. 1, the data signal DQ may include m data signals including the data signal DQ1. Thus, the merge circuit 122 of FIG. 3 may include m merge circuits each corresponding to m data signals. For example, if m is 8, the merge circuit 122 may include eight merge circuits having a similar configuration to the merge circuit 300b (see FIG. 14).

Figure 12 is a timing diagram showing exemplary changes of signals generated by the memory system of Figure 1;

Hereinafter, with reference to Fig. 12, description will be given of signals related to the data signal DQ generated by the first rank 111_1 and the data signal DQ generated by the first rank 111_1 in Fig. 2 do. As described with reference to FIG. 1, the data signal DQ may include m data signals. The data signal DQx in FIG. 12 may be one of m data signals included in the data signal DQ. Therefore, the data signal DQx can be generated by the first rank 111_1. Since the change of the data signals generated in the second to the n-th ranks 111_2 to 111_n is similar to the change of the data signal generated in the first rank 111_1, the description will be omitted.

The specific time of the m data signals (included in the data signal DQ) generated from the memory 110 can be aligned with respect to the reference time point. For example, the specific time may be a time point at which data represented by the data signal DQx and the data signal DQmin change. In the example of Fig. 12, the specific time may be the time point te and the time point tf. The reference time point may be a time point at which the logical value of the data strobe DQS starts to change. In the example of Fig. 12, the reference time point may be the time point td.

As described with reference to Fig. 8, the data signal DQx generated by the first rank 111_1 may include skew having various lengths for the data strobe DQS. That is, the data signal DQx may lag behind or precede the data strobe DQS by a certain time length. The time point " te " of the data signal DQx may deviate from the reference time point " td " of the data strobe DQS.

The data signal DQmin means a data signal shifted by the shortest time length among m data signals included in the data signal DQ. The time point " tf " of the data signal DQmin may deviate from the reference time point " td " of the data strobe DQS. In the example of Fig. 12, the length of the time of deviation of the data signal DQx with respect to the data strobe DQS may be? SK4. The shortest time length among the time lengths deviated from the data strobe DQS among the data signals included in the data signal DQ, that is, the length of time that is deviated from the data strobe DQS of the data signal DQmin, .

The data strobe (DQS) of FIG. 12 may be the data strobe (DQS) of FIGS. The data strobe DQS_R1 of FIG. 12 may be the first data strobe DQS_R1 of FIGS. 3-6.

The data signal DQmin and the data signal DQx may have the length of the time period PT 2 as a period. Therefore, the data signal DQmin and the data signal DQx can represent 1-bit data in units of the length of the time period PT 2. The length of time deviating from the data strobe DQS of the data signal DQmin is shorter than the length of time deviating from the data strobe DQS of the data signal DQx so that the data signal DQmin has a time Can be advanced by the length of the interval? T2.

The period of the data strobe DQS may be substantially the same as the period of the data signal DQx and the data signal DQmin. As described with reference to Fig. 4, the delay line 220_1 can delay the data strobe DQS based on the signal SLC1 and output the data strobe DQS_R1. Therefore, the data strobe DQS_R1 can be lagged behind the data strobe DQS by the length of the time period tDQSC2. As described with reference to FIG. 1, the time interval tDQSC2 may have a length determined based on the training described with reference to FIG. The signal SLC1 may indicate the length of the time interval tDQSC2.

As an example, the control circuit 130 may determine the length of the time period tDQSC1 based on the skew (? SK4) of the data signal DQmin obtained through training. The time period tDQSC2 may have a length for aligning the data strobe DQS with respect to the data signal DQmin. In the example of FIG. 8, the time period tDQSC2 is a period during which the rising edges and the falling edges of the data strobe DQS_R1 obtained by delaying the data strobe DQS are synchronized with the rising edges and falling edges of the data strobe DQS, Lt; / RTI > As an example, the rising edge of the data strobe DQS_R1 may be aligned within the time period PT2. Thus, the time at which the data strobe DQS_R1 starts having a logic high value can be aligned in the middle of the time period PT2.

13 is a timing diagram showing exemplary changes in signals generated by the memory system of FIG.

The data signal DQmin, the data signal DQx, and the data strobe DQS_R1 in FIG. 13 may be the data signal DQmin, the data signal DQx, and the data strobe DQS_R1, respectively, in FIG. The delay data strobe (DQSx_R1) in Fig. 13 can be one of the delay data strobe (DQS1_R1 to DQS1_Rn) in Fig.

As described with reference to Fig. 11, the merge circuit 300b can generate the delayed data strobe DQS1_R1 by delaying the data strobe DQS_R1 based on the signal SLD_DQS1. Similarly, a merge circuit that includes a similar configuration to the merge circuit 300b of FIG. 11 can generate a data strobe DQSx_R1 by delaying the data strobe DQS_R1.

Therefore, the data strobe DQSx_R1 may be slower than the data strobe DQS_R1 by the time period tDQSD. As described with reference to FIG. 1, the time interval tDQSD may have a length determined based on the training process of FIG. The signal SLD_DQS 1 may represent data relating to the time period tDQSD.

As an example, the control circuit 130 may determine the length of the time period tDQSC1 based on the skew (? SK3) of the data signal DQx obtained through training. The time interval tDQSD may have a length for aligning the delay data strobe DQSx_R1 with respect to the data signal DQx. 13, the time period tDQSD is a period in which the rising edges and the falling edges of the delayed data strobe DQSx_R1 obtained by delaying the data strobe DQS_R1 are divided into the periods in which the data signal DQx has the specific logical value Lt; / RTI > As an example, the rising edge of the delayed data strobe DQSx_R1 may be aligned in the time period PT3. Thus, the time point at which the delayed data strobe DQSx_R1 starts having a logic high value can be aligned in the middle of the time interval PT3.

13, a delay data strobe DQSx_R1 arranged in the middle of the time interval PT3 has been described. However, the present invention is not limited to the case of generating the delay data strobe DQSx_R1 arranged in the time interval PT3 For example, all of the embodiments of the merge circuit 122 or 300b.

12 and 13, the interface circuit 120 controls the data strobe DQS_R1 to DQS_Rn based on the signal SLC so that the data strobe DQS_R1 to DQS_Rn are aligned with respect to the data signal DQmin, (DQS_R1 to DQS_Rn). As described with reference to FIG. 1, the data signal DQ may include m data signals. The interface circuit 120 generates the data strobe signals DQS_R1 to DQS_Rn so that the data strobe signals DQS_R1 to DQS_Rn are aligned with m data signals included in the data signal DQ based on the signal SLD, ). ≪ / RTI >

Through the process described with reference to FIGS. 12 and 13, the interface circuit 120 is configured such that the rising edges and falling edges of the data strobe DQS_R1 are respectively arranged in time intervals in which the data signal DQx has a specific logical value The data strobe DQS_R1 can be delayed. By a similar process, the rising edges and the falling edges of the data strobe DQS_R2 to DQS_Rn can be respectively aligned with respect to the data signals included in the data signal DQ, and a description thereof will be omitted.

As the delayed data strobe DQSx_R1 is aligned with respect to the data signal DQx, the sampling circuit 330b of Fig. 11 can sample the data signal DQx with sufficient margin, based on the delayed data strobe DQSx_R1 have. Similarly, the sampling circuit 330b of FIG. 11 can sample the data signal DQx based on delayed data strobe DQSx_R2 through DQSx_Rn, respectively, with sufficient margin.

14 is a block diagram showing an exemplary memory and interface circuit according to the configuration of the merge circuit of Fig.

As described with reference to FIG. 1, the memory 110 may generate m data signals by n ranks. For better understanding, the eight data signals DQ1 to DQ8 generated by two ranks 611 and 612 and two ranks 611 and 612 are described.

The memory 110 of FIG. 1 may include the first and second ranks 611 and 612 of FIG. The DQS split circuit 121 of FIG. 3 may include the AND logic operators 631 and 632 and the delay lines 633 and 634 of FIG. The merge circuit 122 of FIG. 3 includes delay lines 621_1 to 628_1, delay lines 621_2 to 628_2, logical sum operators 641 to 648, and sampling circuits 651 to 658 of FIG. 14 can do.

The configurations and operations of the first and second ranks 611 and 612 of FIG. 14 are respectively similar to those described with reference to the first and second ranks 111_1 and 111_2 of FIG. 2, respectively, do. The configurations and operations of the logical multiplication operators 631 and 632 and the delay lines 633 and 634 in FIG. 14 refer to the logical product operators 210_1 to 210_n and the delay lines 220_1 to 220_n in FIG. And therefore the following description is omitted. The configurations and operations of the delay lines 621_1 to 628_1, delay lines 621_2 to 628_2, the logical sum operators 641 to 648, and the sampling circuits 651 to 658 in Fig. 310b_n, the logical sum operator 320b, and the sampling circuit 320b, respectively, so that the following description is omitted.

One of the first and second ranks 611 and 612 may generate the data signals DQ1 to DQ8 under the control of the control circuit 130. [ AND logic operators 631 and 632 and delay lines 633 and 634 may generate data strobe DQS_R1 and DQS_R2 in response to the first and second gate signals G1 and G2, respectively.

Delay lines 621_1 to 628_1 can generate delayed data strobe DQS1_R1 to DQS8_R1 respectively by delaying data strobe DQS_R1. Delay lines 621_1 through 628_2 may generate delayed data strobe DQS1_R2 through DQS8_R2, respectively, by delaying data strobe DQS_R2. The logical sum operators 641 to 648 can generate the delay data strobe DQS1 to DQS8 respectively based on the delay data strobe DQS1_R1 to DQS8_R1 and the delay data strobe DQS1_R2 to DQS8_R2. The sampling circuits 651 to 658 sample the data signals DQ1 to DQ8 based on the delayed data strobe DQS1 to DQS8 to generate the data signal highs DQ1H to DQ8H and the data signal lines DQ1L to DQ8H, DQ8L).

14, the number of sampling circuits 651 to 658 for processing the data signals DQ1 to DQ8 generated from the two ranks 611 and 612 in Fig. May be less than the number of sampling circuits 551_1 to 558_1 and 551_2 to 558_2 for processing the data signals DQ1 to DQ8 generated from the two ranks 511 and 512. [ The sampling circuits 651 to 658, or 551_1 to 558_1 and 551_2 to 558_2, consume power and can be placed on a specific area. Therefore, the interface circuit 120 according to the configuration of Fig. 14 consumes less power than the interface circuit 120 according to the configuration of Fig. 10, and can be arranged in a small area.

15 is a flow chart illustrating an exemplary operation of the memory system of FIG.

In operation S110, the memory 110 may generate the data signal DQ and the data strobe DQS. By way of example, the memory 110 may generate the data signal DQ and the data strobe DQS by the first rank 111_1.

In operation S120, the interface circuit 120 may align the data strobe DQS with respect to the data signal DQ shifted by a specific time length with respect to the reference time. As described with reference to Fig. 12, the data signal DQ may be deviated with respect to the data strobe DQS by various time lengths for the data strobe DQS. The interface circuit 120 outputs the data signal DQmin (i.e., the data signal DQ minus the skew of the m data signals included in the data signal DQ) that is shifted relative to the data strobe DQS by the shortest time length among the various time lengths (E.g., a data signal having a data strobe DQS).

In operation S130, the interface circuit 120 may align the data strobe DQS with respect to the data signal DQ. As described with reference to FIG. 13, the interface circuit 120 may delay the data strobe (DQS) to generate the delay data strobe (DQSx). The delayed data strobe DQSx may be aligned with respect to the data signal DQ.

In operation S140, the interface circuit 120 may sample the data signal DQ based on the aligned data strobe in operation S130. As described with reference to FIG. 6, the interface circuit 120 may sample the data signal DQ in response to the rising and falling edges of the delayed data strobe DQSx. The interface circuit 120 may generate the data signal high DQH by sampling the data signal DQ in response to the rising edge of the delay data strobe DQSx. The interface circuit 120 may generate the data signal row (DQL) by sampling the data signal DQ in response to the falling edge of the delay data strobe DQSx.

In operation S150, the interface circuit 120 may output a data signal high (DQH) and a data signal row (DQL) to the control circuit 130

16 is a block diagram illustrating an exemplary electronic device including the memory system of FIG.

For example, the electronic device 1000 may be one of a personal computer (PC), a workstation, a notebook computer, a mobile device, and the like. 16, an electronic device 1000 may include a processor 1100, a memory 1200, a storage 1300, a communication device 1400, a user interface 1500, and a bus 1600. The electronic device 1000 may further include other components not shown in FIG. Alternatively, the electronic device 1000 may not include one or more of the components shown in FIG.

The processor 1100 may control the overall operations of the electronic device 1000. The processor 1100 may process the operations required for operation of the electronic device 1000 as a central control device. By way of example, processor 1100 may process data for controlling operations of electronic device 1000. By way of example, processor 1100 may include interface circuitry 120 and control circuitry 130 of FIG. The processor 1100 may be configured to control the overall operation of the memory 1200.

By way of example, processor 1100 may receive a data signal DQ and a data strobe DQS from memory 1200. The processor 1100 may sample the data signal DQ based on the data strobe DQS. The processor 1100 may generate a signal SLC and a signal SLD that are used to sample the data signal DQ. By way of example, processor 1100 may be one of a general purpose processor, a workstation processor, an application processor, or the like.

The memory 1200 may store data to be processed or processed by the processor 1100. By way of example, memory 1200 may support a multi-rank system. The memory 1200 may include the memory system 100 of FIG. By way of example, memory 1200 may include volatile memory or non-volatile memory. Alternatively, memory 1200 may comprise heterogeneous memories.

By way of example, memory 1200 may include an interface circuit and a memory controller configured to control the overall operation of memory 1200. [ By way of example, the interface circuit may include the interface circuit 120 of FIG. By way of example, the memory controller may include the control circuitry 130 of FIG.

The storage 1300 can store data regardless of the power supply. By way of example, the storage 1300 may be a recording medium including a nonvolatile memory. The communication device 1400 may include a transmitter and a receiver. The electronic device 1000 may communicate with other electronic devices by the communication device 1400 to transmit and / or receive data. The user interface 1500 may communicate input / output of commands or data between the user and the electronic device 1000.

The bus 1600 may provide a communication path between the components of the electronic device 1000. By way of example, processor 1100, memory 1200, storage 1300, communication device 1400, and user interface 1500 may exchange data with each other via bus 1600. [ By way of example, memory 1200 may carry a data signal DQ and a data strobe DQS via bus 1600. [ The bus 1600 may be configured to support various types of communication formats used in the electronic device 1000.

The above description is specific embodiments for carrying out the present invention. The present invention will also include embodiments that are not only described in the above-described embodiments, but also can be simply modified or changed easily. In addition, the present invention will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

Claims (10)

The first data strobe is delayed so that the edge of the second data strobe is arranged in the first time period in which the first data signal having the timing shifted by the first time length with respect to the reference timing of the reference data strobe indicates one logical value A first delay line circuit configured to generate the second data strobe; And
And a sampling circuit configured to sample the first data signal in response to the edge of the second data strobe,
Wherein the first data signal and the second data signal are included in data signals having timings deviated by time lengths with respect to the reference timing,
Wherein an edge of the first data strobe is arranged in a second time period in which the second data signal having a timing shifted by a shortest time length of the time lengths with respect to the reference timing indicates a logical value. The method according to claim 1,
Further comprising a DQS split circuit for delaying the reference data strobe so that the edge of the first data strobe is arranged within the second time interval. 3. The method of claim 2,
The DQS split circuit comprises:
A second logic circuit configured to output the reference data strobe in response to a gate signal received from a memory controller; And
And a second delay line circuit configured to delay the reference data strobe output from the second logic circuit to output the first data strobe. The method of claim 3,
Wherein the first data signal is generated by one of the ranks included in the memory. The first data strobe is delayed so that the edge of the second data strobe is arranged in the first time period in which the first data signal having the timing shifted by the first time length with respect to the reference timing of the reference data strobe indicates one logical value A merge circuit configured to generate the second data strobe and sample the first data signal in response to the edge of the second data strobe; And
The edge of the first data strobe is arranged in a second time period in which the second data signal having a timing shifted by a second time length with respect to the reference timing shows a logical value by delaying the reference data strobe, A DQS split circuit configured to generate a first data strobe,
Wherein the first data signal and the second data signal are included in data signals having timings deviating from the reference timing by time lengths,
And the second time length is the shortest of the time lengths. A first delay line circuit configured to adjust a timing of a first data strobe generated from a reference data strobe to generate a second data strobe; And
And a sampling circuit configured to sample a first data signal having a timing shifted by a first time length relative to the reference data strobe based on the second data strobe,
Wherein the first data signal is one of data signals having timings deviating from the reference data strobe by time lengths,
Wherein the first data strobe has a timing for sampling a second data signal having a timing shifted with respect to the reference data strobe by a time length that is at least one of the time lengths. The method according to claim 6,
A second delay line circuit configured to adjust a timing of a third data strobe generated from the reference data strobe to generate a fourth data strobe; And
Further comprising a first logic circuit configured to selectively output one of the second data strobe and the fourth data strobe to the sampling circuit,
Wherein the second data strobe is associated with a first rank included in the memory and the fourth data strobe is associated with a second rank included in the memory. 8. The method of claim 7,
Wherein the reference data strobe is generated from one of the first rank and the second rank,
When the reference data strobe is generated from the first rank, generating the first data strobe by adjusting the timing of the reference data strobe, and when the reference data strobe is generated from the second rank, Further comprising a DQS split circuit configured to adjust the timing of the third data strobe to generate the third data strobe. 9. The method of claim 8,
The DQS split circuit comprises:
A second logic circuit configured to output the reference data strobe in response to a first gate signal received from a memory controller when the reference data strobe is generated from the first rank;
A third logic circuit configured to output the reference data strobe in response to a second gate signal received from the memory controller when the reference data strobe is generated from the second rank;
A third delay line circuit configured to delay the reference data strobe output from the second logic circuit to generate the first data strobe; And
And a fourth delay line circuit configured to delay the reference data strobe output from the third logic circuit to generate the third data strobe. The method according to claim 6,
Wherein the first delay line circuit generates the second data strobe such that edges of the second data strobe are arranged in a time interval in which the first data signal indicates a logical value.

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