KR20190083383A - Display device - Google Patents

Abstract

Provided is a display device. The display device comprises: a base substrate including a first pixel area and a second pixel area; a first gate line located on the base substrate and extended in a first direction; a lower data line insulated from the first gate line and extended in a second direction crossing the first direction; a first switching element located on the base substrate, located in the first pixel area, and connected to the first gate line; an organic layer located on the first switching element and the lower data line; an upper data line located on the organic layer, extended in the second direction, overlapping the lower data line, and electrically connected to the first switching element; a planarization layer located on the organic layer and covering the upper data line; a first pixel electrode located on the planarization layer, located in the first pixel area, and connected to the first switching element; and a shielding electrode arranged on the planarization layer to be spaced apart from the pixel electrode, overlapping the upper data line, and extended in the second direction.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

Among the display devices, the liquid crystal display device is one of the most widely used display devices, and is composed of two substrates on which electric field generating electrodes such as a pixel electrode and a common electrode are formed and a liquid crystal layer interposed therebetween, To generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light to display an image.

The number of pixels arranged in the display area having the same area is relatively increased as the resolution of the display device is increased. In order to drive each pixel, at least one thin film transistor is required for each pixel, and a signal line such as a data line and a gate line for supplying a signal to the thin film transistor is required.

The ratio of the area occupied by the signal line in the display area of the display device is relatively increased as the resolution increases, which is one of the causes for lowering the aperture ratio of the high-resolution display device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device with improved aperture ratio.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing the same.

According to an aspect of the present invention, there is provided a display device including: a base substrate including a first pixel region and a second pixel region; A first gate line located on the base substrate and extending in a first direction; A lower data line which is insulated from the first gate line and extends in a second direction intersecting with the first direction; A first switching element located on the base substrate and located in the first pixel region and connected to the first gate line; An organic layer located on the first switching element and the lower data line; An upper data line located on the organic layer and extending in the second direction and overlapping the lower data line and electrically connected to the first switching device; A planarization layer located on the organic layer and covering the upper data line; A first pixel electrode located on the planarization layer and located in the first pixel region and connected to the first switching element; And a shielding electrode disposed on the planarization layer and spaced apart from the first pixel electrode, the shielding electrode overlapping the upper data line and extending along the second direction.

In the display device according to an embodiment of the present invention for solving the above problems, the shield electrode may further overlap with the lower data line.

In the display device according to an embodiment of the present invention for solving the above problems, the shield electrode may completely cover the lower data line and the upper data line on a plane.

According to an embodiment of the present invention, the organic layer may include a first color filter disposed in the first pixel region.

According to an aspect of the present invention, there is provided a display device including: a connection part located on the organic layer and located in the first pixel area and connected to the upper data line; And the connection portion may contact the source electrode of the first switching element through the organic layer.

According to an aspect of the present invention, there is provided a display device including: a second gate line located on a base substrate and extending in the first direction and spaced apart from the first gate line in the second direction; A second switching element located on the base substrate and located in the second pixel region and connected to the first gate line and the lower data line; And a second pixel electrode located in the second pixel region and connected to the second switching element; As shown in FIG.

According to an aspect of the present invention, there is provided a display device, wherein the first pixel region is located at one side of the shielding electrode along the first direction, And may be located on the other side of the shielding electrode.

According to an embodiment of the present invention, the first pixel region and the second pixel region may be located in different rows and different columns.

According to an embodiment of the present invention, the organic layer may be further located on the second switching element, and the second pixel electrode may be on the planarization layer.

According to an embodiment of the present invention, there is provided a display device including a first color filter disposed in the first pixel region and a second color filter disposed in the second pixel region, And a second color filter, and the first color filter and the second color filter may partially overlap to form an overlapping portion.

In the display device according to an embodiment of the present invention for solving the above problems, the overlapping portion may overlap the upper data line and the lower data line.

According to another aspect of the present invention, there is provided a display device including: a base substrate including a first pixel region and a second pixel region; First and second gate lines disposed on the base substrate and extending in a first direction and spaced apart from each other in a second direction intersecting with the first direction; A first lower data line and a second lower data line which are insulated from the first gate line and the second gate line and extend in the second direction and are spaced apart from each other along the first direction; A first switching element located on the base substrate and located in the first pixel region and connected to the first gate line; A second switching element located on the base substrate and located in the second pixel region and connected to the second gate line and the first lower data line; An organic layer located on the first switching element, the second switching element, the first lower data line, and the second lower data line; A first upper data line located on the organic layer and extending in the second direction and overlapping the first lower data line; A second upper data line located on the organic layer and extending in the second direction and overlapping the second lower data line; A planarization layer located on the organic layer and covering the first upper data line and the second upper data line; A first pixel electrode located on the planarization layer and located in the first pixel region and connected to the first switching element; A second pixel electrode located on the planarization layer and located in the second pixel region and connected to the second switching element; A first shielding electrode located on the planarization layer and overlapping the first upper data line; And a second shielding electrode located on the planarization layer and overlapping the second upper data line; And the first switching element is electrically connected to the second upper data line.

According to another aspect of the present invention, there is provided a display device including: a connection unit located on an organic layer and connected to a second upper data line; And the connection portion may contact the source electrode of the first switching element through the organic layer.

According to another aspect of the present invention, the first pixel region and the second pixel region may be adjacent to each other along the second direction.

In the display device according to another embodiment of the present invention for solving the above problems, the organic layer may include a vehicle.

In the display device according to another embodiment of the present invention for solving the above problems, a portion located in the first pixel region and a portion located in the second pixel region among the organic layers may include the same color agent .

According to another aspect of the present invention, there is provided a display device, wherein the first switching element includes a first gate electrode connected to the first gate line, the second switching element includes a second gate line, Wherein the shortest distance between the first lower data line and the first gate electrode measured along the first direction is shorter than the shortest distance between the first lower data line and the second lower data line measured along the first direction, And may be different from the shortest interval between the gate electrodes.

According to another embodiment of the present invention, the second gate electrode may be positioned adjacent to the first lower data line relative to the first gate electrode.

According to another aspect of the present invention, there is provided a display device including: a base substrate; A gate line located on the base substrate and extending in a first direction; A lower data line which is insulated from the gate line and extends in a second direction intersecting with the first direction; A divided voltage reference line spaced apart from the gate line and the lower data line; A first switching element located on the base substrate and including a first source electrode, a first drain electrode, and a first gate electrode connected to the gate line; A second switching element located on the base substrate and including a second source electrode connected to the first source electrode, a second drain electrode, and a second gate electrode connected to the gate line; A third switching element located on the base substrate and including a third source electrode connected to the voltage divider reference line, a third drain electrode connected to the second drain electrode, and a third gate electrode connected to the gate line; An organic layer located on the first switching element, the second switching element, the third switching element, the divided voltage reference line, and the lower data line; An upper data line located on the organic layer and overlapping the lower data line and electrically connected to the first source electrode of the first switching device; A planarization layer located on the organic layer and covering the upper data line; A first sub-pixel electrode located on the planarization layer and electrically connected to the first drain electrode; A second sub-pixel electrode located on the planarization layer and electrically connected to the third drain electrode; And a shielding electrode located on the planarization layer and overlapping the upper data line; .

The details of other embodiments are included in the detailed description and drawings.

According to the embodiments of the present invention, a display device having an improved aperture ratio can be provided.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a layout diagram schematically showing a pixel arrangement of a display device according to an embodiment.
2 is a cross-sectional view taken along the line X1-X1 'in FIG.
3 is a cross-sectional view taken along the line X3-X3 'in Fig.
4 is a cross-sectional view taken along the line X5-X5 'in Fig.
5 is a cross-sectional view taken along the line X7-X7 'in Fig.
6 is a plan view showing an exemplary structure of the first pixel electrode shown in FIG.
7 is a cross-sectional view showing a modification of Fig.
8 is a cross-sectional view of the display device according to another embodiment taken along line X1-X1 'in FIG.
9 is a cross-sectional view of the display device according to another embodiment taken along line X3-X3 'in FIG.
10 is a cross-sectional view taken along the line X5-X5 'of FIG. 1, illustrating a display device according to another embodiment.
FIG. 11 is a cross-sectional view taken along the line X7-X7 'in FIG. 1 of a display device according to another embodiment.
12 is an equivalent circuit diagram of one pixel of a display device according to another embodiment.
Fig. 13 is a layout diagram for one pixel located in the first pixel region in Fig. 1 in the display device according to another embodiment.
FIG. 14 is a layout diagram for one pixel located in the third pixel region of FIG. 1 in a display device according to another embodiment.
15 is a cross-sectional view taken along the line X9-X9 'in Fig.
FIG. 16 is a cross-sectional view taken along the line X11-X11 'in FIG.
17 is a cross-sectional view taken along the line X13-X13 'in Fig.
FIG. 18 is a cross-sectional view taken along line X9-X9 'in FIG. 13 of a display device according to still another embodiment.
FIG. 19 is a cross-sectional view of a display device according to still another embodiment taken along line X11-X11 'in FIG.
20 is a cross-sectional view of the display device according to still another embodiment taken along the line X13-X13 'in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

It will be understood that when an element or layer is referred to as being "on" of another element or layer, it encompasses the case where it is directly on or intervening another element or intervening layers or other elements. Like reference numerals refer to like elements throughout the specification.

Although the first, second, third, fourth, etc. are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it goes without saying that any one of the first to fourth components mentioned below may be another one of the first to fourth components within the technical spirit of the present invention.

Throughout the specification, the same reference numerals are used for the same or similar parts.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a cross-sectional view taken along line X1-X1 'in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line X3-X3' in FIG. 1 1 is a cross-sectional view taken along line X5-X5 'in FIG. 1, FIG. 5 is a cross-sectional view taken along line X7-X7' in FIG. 1, and FIG. 6 is a cross- Fig. 3 is a plan view showing an exemplary structure of an electrode.

1 to 6, a display device 1 according to an embodiment includes a first substrate 100, a second substrate 200, and a second substrate 200, which are disposed between the first substrate 100 and the second substrate 200 And a liquid crystal layer (300).

The first substrate 100 may be a thin film transistor array substrate having a switching element for driving liquid crystal molecules of the liquid crystal layer 300 such as a thin film transistor array. .

The liquid crystal layer 300 may include a plurality of liquid crystal molecules having a dielectric anisotropy. When an electric field is applied between the first substrate 100 and the second substrate 200, the liquid crystal molecules 310 rotate in a specific direction between the first substrate 100 and the second substrate 200 to transmit light Can be blocked. Here, the term 'rotation' may mean not only that the liquid crystal molecules actually rotate, but also that the arrangement of the liquid crystal molecules is changed by the electric field.

Hereinafter, the first substrate 100 will be described.

The first base substrate 110 may be formed of an insulating material such as glass, quartz, or a polymer resin. Examples of the polymeric material include polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate ), Polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The base substrate 110 may comprise a metallic material.

The first base substrate 110 may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, and the like. An example of the material constituting the flexible substrate is polyimide (PI), but is not limited thereto.

A plurality of pixel regions may be defined in the first base substrate 110. Illustratively, the first pixel region PA11, the second pixel region PA12, the third pixel region PA21, and the fourth pixel region PA22 may be defined on the first base substrate 110. In each pixel region, structures constituting one pixel are located.

The first pixel area PA11 and the second pixel area PA12 may be located on the same row in the plane. Illustratively, the first pixel area PA11 and the second pixel area PA12 may be located in the same first row R1 and may be adjacent to each other along the first direction x or the row direction. Hereinafter, the two pixel regions are adjacent along the first direction (x), meaning that no other pixel region is located between the two pixel regions along the first direction (x).

The third pixel area PA21 and the fourth pixel area PA22 may be located in the same second row R2 and adjacent to each other along the first direction x. The second row R2 may be adjacent to each other along the first direction R1 or the second direction y or the column direction in which the first pixel area PA11 and the second pixel area PA12 are located.

The first pixel area PA11 and the third pixel area PA21 may be located in the same column, for example, the first column C1, and the first pixel area PA11 and the third pixel area PA21 PA21 may be adjacent to each other along the second direction y. In other words, another pixel region may not be located between the first pixel region PA11 and the third pixel region PA21 along the second direction y.

The second pixel area PA12 and the fourth pixel area PA22 may be located in the same column, for example, the second column C2, and the second pixel area PA12 and the fourth pixel area PA22 may be located in the same column, May be adjacent to each other along the second direction (y).

A gate conductive layer may be located on the first base substrate 110. The gate conductive layer includes a first gate line G1, a second gate line G2, a first gate electrode GE11, a second gate electrode GE12, a third gate electrode GE21, GE22).

The first gate line G1, the second gate line G2, the first gate electrode GE11, the second gate electrode GE12, the third gate electrode GE21 and the fourth gate electrode GE22 are the same Layer and may be made of the same material. Hereinbelow, the meaning of being located in the same layer means that the layers immediately below each structure are the same, or that each structure is located at the same level.

The first gate line G1, the second gate line G2 and the gate line 121 may extend along the first direction x and may be spaced apart from each other along the second direction y.

The first gate electrode GE11 and the second gate electrode GE12 may be connected to the first gate line G1 and the first gate electrode GE11 may be located in the first pixel region PA11, GE12 may be located in the second pixel area PA12.

The third gate electrode GE21 and the fourth gate electrode GE22 may be connected to the second gate line G2 and the third gate electrode GE21 may be connected to the fourth pixel electrode PA21, GE22 may be located in the fourth pixel area PA22.

Hereinafter, the term " connected " means that two components are physically connected to each other or two components are physically connected to each other. The term " electrically connected " is a concept including not only a case where two components are physically connected but also a case where two components are electrically connected through another conductor even though they are not physically connected.

The gate conductive layer may include at least one selected from the group consisting of Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, And may include at least one metal selected from iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Further, the gate conductive layer may have a single-layer or multi-layer structure.

A gate insulating layer 124 may be disposed on the gate conductive layer. The gate insulating layer 124 may include an inorganic insulating material such as a silicon compound, a metal oxide, or the like. The gate insulating layer 124 may be a single film or a multilayer film composed of a laminated film of different materials.

A semiconductor layer may be located on the gate insulating layer 124. The semiconductor layer may include a first semiconductor pattern SM11, a second semiconductor pattern (not shown), a third semiconductor pattern SM21, and a fourth semiconductor pattern SM22 that are spaced apart from each other.

The first semiconductor pattern SM11 is arranged so as to overlap the first gate electrode GE11 in the first pixel area PA11 and the second semiconductor pattern SM11 is arranged to overlap the second gate electrode GE11 in the second pixel region PA12, The third semiconductor pattern SM21 is arranged so as to overlap with the third gate electrode GE21 in the third pixel area PA21 and the fourth semiconductor pattern SM22 is arranged so as to overlap with the fourth pixel SM21, And may overlap the fourth gate electrode GE22 in the region PA22.

The semiconductor layer may comprise polycrystalline silicon. As another example, the semiconductor layer may include monocrystalline silicon, low temperature polycrystalline silicon, amorphous silicon, and the like. However, the present invention is not limited thereto, and the semiconductor layer may include an oxide semiconductor.

A lower data conductive layer may be located on the gate insulating layer 124, and a part of the lower data conductive layer may be located on the semiconductor layer.

In some embodiments, the lower data conductive layer may be formed using a mask different from the semiconductor layer. Accordingly, a part of the lower data conductive layer may directly contact the gate insulating layer 124.

The lower data conductive layer includes a first lower data line LD1, a second lower data line LD2, a third lower data line LD3, a first source electrode SE11, a first drain electrode DE11, A second source electrode SE12, a second drain electrode DE12, a third source electrode SE21, a third drain electrode DE21, a fourth source electrode SE22 and a fourth drain electrode DE22. have. The structures of the lower data conductive layer may be made of the same material and may be located on the same layer.

The first lower data line LD1, the second lower data line LD2 and the third lower data line LD3 may extend along a second direction y which intersects the first direction x, May be spaced apart from each other along the first direction (x).

In some embodiments, data voltages of the same polarity are supplied to the first lower data line LD1 and the third lower data line LD3 while the first lower data lines LD1 and LD2 are supplied to the second lower data line LD2. 3 data voltage having a polarity different from that of the lower data line LD3 may be provided.

The first source electrode SE11 and the first drain electrode DE11 are located in the first pixel region PA11. The first source electrode SE11 may be electrically connected to the second upper data line HD2 to be described later and may be disposed on the first semiconductor pattern SM11 partially in contact with the first semiconductor pattern SM11, It can be overlapped with the pattern SM11. The first drain electrode DE11 may be partially located on the first semiconductor pattern SM11 and may be in contact with the first semiconductor pattern DE11 and overlap the first semiconductor pattern SM11. The first drain electrode DE11 is spaced apart from the first source electrode SE11 on the first semiconductor pattern SM11.

The first gate electrode GE11, the first semiconductor pattern SM11, the first source electrode SE11 and the first drain electrode DE11 constitute a first switching element T11 which is a thin film transistor.

And the second source electrode SE12 and the second drain electrode DE12 are located in the second pixel region PA12. The second source electrode SE12 may be electrically connected to the third upper data line HD3 to be described later, and may be disposed on the second semiconductor pattern (not shown) in part and may be in contact with the second semiconductor pattern (not shown) And overlap the second semiconductor pattern (not shown). The second drain electrode DE12 is disposed apart from the second source electrode SE12 on the second semiconductor pattern (not shown) and can contact the second semiconductor pattern (not shown).

The second gate electrode GE12, the second semiconductor pattern (not shown), the second source electrode SE12 and the second drain electrode DE12 constitute a second switching element T12 which is a thin film transistor.

The third source electrode SE21 and the third drain electrode DE21 are located in the third pixel region PA21. The third source electrode SE21 may be connected to the first lower data line LD1 and may partially be on the third semiconductor pattern SM21 and contact the third semiconductor pattern SM21. The third drain electrode DE21 may be disposed apart from the third source electrode SE21 on the third semiconductor pattern SM21 and may be in contact with the third semiconductor pattern SM21.

The third gate electrode GE21, the third semiconductor pattern SM21, the third source electrode SE21 and the third drain electrode DE21 constitute a third switching element T21 which is a thin film transistor.

The fourth source electrode SE22 and the fourth drain electrode DE22 are located in the fourth pixel region PA22. The fourth source electrode SE22 may be connected to the second lower data line LD2 and may partially be on the fourth semiconductor pattern SM22 and contact the fourth semiconductor pattern SM22. The fourth drain electrode DE22 may be disposed apart from the fourth source electrode SE22 on the fourth semiconductor pattern SM22 and may be in contact with the fourth semiconductor pattern SM22.

The fourth gate electrode GE22, the fourth semiconductor pattern SM22, the fourth source electrode SE22 and the fourth drain electrode DE22 constitute a fourth switching element T22 which is a thin film transistor.

In some embodiments, the first switching element T11 may be positioned adjacent to the second lower data line LD2 relative to the third switching element T21, and the third switching element T21 may be located adjacent to the second switching element T21, May be located adjacent to the first lower data line LD1 relative to the first lower data line LD1. For example, the shortest distance (or the shortest distance) between the first lower data line LD1 and the first gate electrode GE11 of the first switching element T11 is set to be shorter than the shortest distance between the first lower data line LD1 and the third switching element T11. May be longer than the shortest distance (or the shortest distance) between the third gate electrodes GE21 of the second transistor T21. The shortest distance (or the shortest distance) between the second lower data line LD2 and the first gate electrode GE11 of the first switching element T11 is determined by the distance between the second lower data line LD2 and the third switching element T21 may be shorter than the shortest distance (or the shortest distance) between the third gate electrodes GE21.

The lower data conductive layer may comprise a metal, and the metal may be opaque. The meaning of opaque here means to block the transmission of light. Illustratively, the lower data conductive layer is formed of at least one selected from the group consisting of Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The lower data conductive layer may be a silver single layer or a multilayer film. For example, the lower data conductive layer may have a stacked structure of silver Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti /

An organic layer 230 may be disposed on the lower data conductive layer. In some embodiments, the organic layer 230 may comprise a photosensitive organic material.

The organic layer 230 may include a plurality of color filters. Illustratively, the organic layer 230 includes a first color filter 230a, a second pixel area PA21, and a fourth pixel area PA22 that are located in the first pixel area PA11 and the third pixel area PA21. A third color filter 230b located on the left side of the third pixel area PA21 and a second color filter 230b positioned on the left side of the third pixel area PA21 with reference to the drawing, (230c).

In some embodiments, the first color filter 230a may include a colorant of a first color. The vehicle may be a color pigment or a color dye. The second color filter 230b includes a vehicle of a second color different from the first color and the third color filter 230c includes a vehicle of a third color different from the first color and the second color . Illustratively, the first color, the second color, and the third color may be red, green, and blue, respectively, but are not limited thereto.

The first color filter 230a and the second color filter 230b may overlap each other on the second lower data line LD2 to form the first overlapping portion OE1. That is, the first overlapping portion OE1 can overlap with the second lower data line LD2. The first color filter 230a and the third color filter 230c may overlap each other on the first lower data line LD1 to form the second overlapping portion OE2 and the second overlapping portion OE2 may overlap the second overlapping portion OE2. Can be overlapped with the first lower data line LD1.

A second contact hole CH11b may be formed in the first color filter 230a of the organic layer 230 to expose a portion of the first source electrode SE11. A fourth contact hole CH12b may be formed in the second color filter 230b of the organic layer 230 to expose a portion of the second source electrode SE12.

The upper data conductive layer may be located on the organic layer 230. The upper data conductive layer may include a first upper data line HD1, a second upper data line HD2, a third upper data line HD3, a first connection HC11, and a second connection HC12. have.

The first upper data line HD1, the second upper data line HD2 and the third upper data line HD3 may extend along the second direction y and may extend along the first direction x, Can be spaced apart.

In some embodiments, the first upper data line HD1 may be provided with a data voltage having the same polarity as that of the first lower data line LD1. Similarly, a data voltage of the same polarity as that of the second lower data line LD2 may be provided to the second upper data line HD2, and a data voltage of the same polarity as the third lower data line LD3 may be provided to the third upper data line HD3. A data voltage of polarity can be provided. Therefore, the data voltages supplied to the first upper data line HD1 and the third upper data line HD3 and the data voltages supplied to the second upper data line HD2 may have different polarities from each other.

The first upper data line HD1 may overlap with the first lower data line LD1. In some embodiments, the first upper data line HD1 may overlap a portion of the first lower data line LD1 as shown in FIGS. However, the present invention is not limited thereto, and in other embodiments, the first upper data line HD1 may overlap the entire first lower data line LD1.

Similarly, the second upper data line HD2 may overlap with the second lower data line LD2, and the third upper data line HD3 may overlap with the third lower data line LD3.

The second upper data line HD2 overlaps with a part of the second lower data line LD2 and the third upper data line HD3 overlaps with a part of the third lower data line LD3, It is not.

The first upper data line HD1 may be positioned on the second overlapping portion OE2 of the organic layer 230 and overlap the second overlapping portion OE2. Similarly, the second upper data line HD2 may be located on the first overlapping portion OE1 of the organic layer 230 and overlap the first overlapping portion OE1.

The first connection part HC11 can electrically connect the second upper data line HD2 and the first source electrode SE1. The first connection portion HC11 may extend from the second upper data line HD2 to the first pixel region PA11 and may be connected to the first source electrode SE1 through the second contact hole CH11b have.

Similarly, the second connection portion HC12 may extend from the third upper data line HD3 to the second pixel region PA12 and may be connected to the second source electrode SE2 through the fourth contact hole CH12b.

The upper data conductive layer may comprise a metal, and the metal may be opaque. Illustratively, the upper data conductive layer includes the same material as the lower data conductive layer, or may include at least one material selected from the materials exemplified by the constituent materials of the lower data conductive layer. The upper data conductive layer may be a single film or a multilayer film. For example, the upper data conductive layer may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, and Ti / Cu.

The first upper data line HD1, the first lower data line LD1, the second upper data line HD2 and the second lower data line LD2 are connected to the first pixel area PA11 and the third pixel area PA21 ) Can function as a light-shielding pattern for blocking light transmission on both sides.

The second upper data line HD2, the second lower data line LD2, the third upper data line HD3 and the third lower data line LD3 are connected to the second pixel region PA12 and the fourth pixel region PA22 can function as a shielding pattern for blocking light transmission on both sides.

A planarization layer 180 may be disposed on the upper data conductive layer. The planarization layer 180 may comprise an organic insulating material, and in some embodiments the organic insulating material may be a photosensitive organic insulating material.

A part of the first contact hole CH11a and the third drain electrode DE21 which expose a part of the first drain electrode DE11 are exposed to the first color filter 230a of the planarization layer 180 and the organic layer 230 A fifth contact hole CH21 may be formed. A part of the third contact hole CH12a and the fourth drain electrode DE22 which expose a part of the second drain electrode DE12 are formed in the second color filter 230b of the planarization layer 180 and the organic layer 230, The sixth contact hole CH22 may be formed.

The pixel conductive layer may be located on the planarization layer 180. The pixel conductive layer may be formed of a transparent conductive material such as ITO or IZO. The pixel conductive layer includes a first pixel electrode PE11, a second pixel electrode PE12, a third pixel electrode PE21, a fourth pixel electrode PE22, a first shielding electrode SH1, A shielding electrode SH2 and a third shielding electrode SH3.

The first pixel electrode PE11 may be located in the first pixel region PA11 and may be connected to the first drain electrode DE11 through the first contact hole CH11a.

6, the first pixel electrode PE11 includes a stripe portion PE11a, a plurality of branch portions extending outwardly from the stripe portion PE11a and spaced apart from each other with the slit PE11c interposed therebetween, PE11b).

In some embodiments, the stripe portion PE11a may divide the first pixel electrode PE11 into a plurality of sub-regions, for example, a plurality of domains. Illustratively, the stem portion PE11a may be provided in a cross shape. In this case, the first pixel electrode PE11 can be divided into four sub-regions, i.e., four domains, by the stripe portion PE11a. The branch portions (PE11b) are located in each sub-region, and the extending directions of the branch portions (PE11b) may be different from each other. For example, the branch PE11b located at the sub-area in the upper right direction with reference to Fig. 6 extends obliquely from the branch base PE11a in the upper right direction, and the branch PE11b located at the sub- Can be extended obliquely downward from the PE 11a. The branch PE11b located at the sub-area in the upper left direction extends obliquely from the stem base PE11a in the upper left direction and the branch PE11b located at the lower left subarea extends from the stem base PE11a in the left- As shown in FIG.

The second pixel electrode PE12 may be located in the second pixel region PA12 and may be connected to the second drain electrode DE12 through the third contact hole CH12a. The third pixel electrode PE21 may be located in the third pixel region PA21 and may be connected to the third drain electrode DE21 through the fifth contact hole CH21 and the fourth pixel electrode PE22 may be connected to the fourth pixel region PA21, And may be connected to the fourth drain electrode DE22 through the sixth contact hole CH22.

In some embodiments, the exemplary shape of the second pixel electrode PE12 may be substantially the same as or similar to the shape of the first pixel electrode PE11 shown in Fig. The shapes of the third pixel electrode PE21 and the fourth pixel electrode PE22 are different from the shapes of the first pixel electrode PE11 shown in FIG. 6 and the shape of the second pixel electrode PE11 shown in FIG. It can be symmetrical.

The first shielding electrode SH1, the second shielding electrode SH2 and the third shielding electrode SH3 are electrically connected to the first pixel electrode PE11, the second pixel electrode PE12, the third pixel electrode PE21 ) And the fourth pixel electrode PE22, respectively.

The first shielding electrode SH1 may extend in the second direction y and overlap the first upper data line HD1 and the first lower data line LD1. In some embodiments, the first shielding electrode SH1 may completely cover the first upper data line HD1 and the first lower data line LD1 when viewed from a plan view.

The second shielding electrode SH2 may extend in the second direction y and may overlap the second upper data line HD2 and the second lower data line LD2. In some embodiments, the second shielding electrode SH2 can completely cover the second upper data line HD2 and the second lower data line LD2 when viewed from a plan view.

Like the first shielding electrode SH1 and the second shielding electrode SH2, the third shielding electrode SH3 may extend in the second direction y, and the third upper data line HD3 and the third sub- Can be overlapped with the line LD3. In some embodiments, the third shielding electrode SH3 may completely cover the third upper data line HD3 and the third lower data line LD3 when viewed from a plan view.

The first shielding electrode SH1, the second shielding electrode SH2 and the third shielding electrode SH3 may be supplied with a voltage equal to the common voltage applied to the common electrode 270, which will be described later. An electric field is formed between the common electrode 270 and the first shielding electrode SHE1, between the common electrode 270 and the second shielding electrode SHE2, and between the third shielding electrode SH3 and the common electrode 270 . Therefore, the possibility that the liquid crystal molecules located on both sides of each of the pixel regions PA11, PA12, PA21 and PA22 are misaligned can be lowered, and the light leakage can be reduced. Further, a separate light shielding member for preventing light leakage can be omitted, and the aperture ratio of the display device 1 can be further increased.

Hereinafter, the second substrate 200 will be described.

The second substrate 200 may include a second base substrate 210 and a common electrode 270.

The second base substrate 210 may be an insulating substrate similar to the first base substrate 110. In addition, the second base substrate 210 may include a polymer or plastic having high heat resistance. In some embodiments, the second base substrate 210 may be flexible.

The common electrode 270 may be positioned on one side of the second base substrate 210 facing the first base substrate 110. The common electrode 270 may be formed of a transparent conductive material such as ITO, IZO, or the like. In some embodiments, the common electrode 270 may be formed entirely over the entire surface of the second base substrate 210. A common voltage is applied to the common electrode 270 to form an electric field together with the first pixel electrode PE11, the second pixel electrode PE12, the third pixel electrode PE21, and the fourth pixel electrode PE22 , The arrangement of the liquid crystal molecules in the liquid crystal layer 300 is changed according to the magnitude of the electric field, and the light transmittance can be controlled.

The above-described display device can reduce the area occupied by the data lines on the plane by superposing the two data lines. Thus, there is an advantage that the aperture ratio of the display device 1 can be improved, and in particular, the aperture ratio can be improved even if the display device 1 is implemented with a high-resolution structure.

7 is a cross-sectional view showing a modification of Fig.

7 shows only the overlapping relationship between each upper data line and each lower data line in the display device 1a according to the present embodiment is different from the display device 1 described above with reference to Figs. 1 to 6, The same or similar. Therefore, redundant contents are omitted.

Specifically, the second upper data line HD2 of the display device 1a can overlap with the entire second lower data line LD2. In some embodiments, the line width of the second upper data line HD2 may be substantially equal to or wider than the line width of the second lower data line LD2.

The first upper data line HD1 may overlap with the entire first lower data line LD1 and the third upper data line HD3 may overlap with the entire third lower data line LD3, can do.

FIG. 8 is a cross-sectional view taken along line X1-X1 'of FIG. 1, FIG. 9 is a cross-sectional view taken along line X3-X3' of FIG. 1, FIG. 10 is a cross-sectional view taken along the line X5-X5 'of FIG. 1, and FIG. 11 is a cross-sectional view taken along the line X7-X7' of FIG. 1 of a display device according to another embodiment .

8 to 11, the display device 2 according to the present embodiment can be formed by using the same mask as the lower data conductive layer and the semiconductor layer with respect to the structure of the first substrate 100b There is a difference from the display device 1 described above with reference to Figs. 1 to 6, and the other configurations are substantially the same or similar. Therefore, the differences are mainly described below.

The first source electrode SE11 and the first drain electrode DE11 of the first switching element T11-1 may not be in contact with the gate insulating layer 124 and all of the first source electrode SE11 and the gate electrode The first semiconductor pattern SM11-1 may further be positioned between the insulating layer 124 and between the entire portion of the first drain electrode DE11 and the gate insulating layer 124. [

A third semiconductor pattern SM21 is formed between the third source electrode SE21 and the gate insulating layer 124 of the third switching element T21-1 and between the third drain electrode DE21 and the gate insulating layer 124, -1) may be further provided, so that the third source electrode SE21 and the third drain electrode DE21 may not be in contact with the gate insulating layer 124. [

Likewise, the fourth semiconductor pattern SM22-B is formed between the fourth source electrode SE22 of the fourth switching device T22-1 and the gate insulating layer 124, and between the fourth drain electrode DE22 and the gate insulating layer 124, 1) may be further disposed, so that the fourth source electrode SE22 and the fourth drain electrode DE22 may not be in contact with the gate insulating layer 124. [

However, in the case of the second switching device, the first switching device T11-1 may have substantially the same structure as the first switching device T11-1.

Each lower data line may also be in non-contact with the gate insulating layer 124. The first data semiconductor pattern SP1 having substantially the same shape as the first lower data line LD1 may be positioned between the first lower data line LD1 and the gate insulating layer 124, The second data semiconductor pattern SP2 having substantially the same shape as the second lower data line LD2 may be positioned between the lower data line LD2 and the gate insulating layer 124. [ Although not shown in the figure, a third data semiconductor pattern (not shown) having the same shape as the third lower data line may be positioned between the third lower data line and the gate insulating layer 124.

In the display device 2 described above, since the lower data conductive layer and the semiconductor layer are patterned using the same mask, the number of masks used in the manufacturing process can be reduced, and the manufacturing cost can be reduced. .

12 is an equivalent circuit diagram of one pixel of a display device according to another embodiment.

Hereinafter, in order to more clearly describe the circuit structure of one pixel, reference numerals different from those in FIG. 1 to FIG. 11 will be used.

Referring to Fig. 12, the display device 3 according to the present embodiment includes a gate line GL, a data line DL, a divided voltage reference line CL, and a pixel PX. The pixel PX is connected to the gate line GL, the data line DL and the divided voltage reference line CL.

One pixel PX is located within one pixel region and includes a first sub-pixel PXa and a second sub-pixel PXb.

The first subpixel PXa includes a first liquid crystal capacitor Ca connected to the first switching element Ta and the first switching element Ta and the second subpixel PXb includes a second switching element Tb A second liquid crystal capacitor Cb connected to the second switching device Tb, and a third switching device Tc.

The first switching element Ta, the second switching element Tb and the third switching element Tc may be thin film transistors each of which is a three-terminal element.

The first terminal of the first switching element Ta is connected to the gate line GL, the second terminal of the first switching element Ta is connected to the data line DL, and the first switching element Ta May be connected to the first liquid crystal capacitor Ca. In particular, the third terminal of the first switching element Ta may be connected to the first sub-pixel electrode constituting the first liquid crystal capacitor Ca.

The first terminal of the second switching element Tb is connected to the gate line GL, the second terminal of the second switching element Tb is connected to the data line DL, and the second switching element Tb May be connected to the second liquid crystal capacitor Cb. In particular, the third terminal of the second switching element Tb may be connected to the second sub-pixel electrode constituting the second liquid crystal capacitor Cb.

The third terminal of the third switching element Tc is connected to the gate line GL and the second terminal of the third switching element Tc is connected to the divisional reference line CL and the third switching element Tc May be connected to the third terminal of the second switching element Tb. A reference voltage for partial pressure can be applied to the second terminal of the third switching element Tc through the divided voltage reference line CL.

When the gate-on voltage is applied to the gate line GL, the first switching element Ta and the second switching element Tb connected to the pixel PX are turned on, And the third switching element Tc are both turned on and the first liquid crystal capacitor Ca and the second liquid crystal capacitor Cb are charged by the data voltage transferred through the data line DL. At this time, the data voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are the same, and the first liquid crystal capacitor Ca and the second liquid crystal capacitor Cb have the same value as the difference between the common voltage and the data voltage Is charged.

At the same time, since the third switching element Tc is in the turned-on state, the data voltage transferred to the second sub-pixel PXb through the data line DL is connected in series with the second switching element Tb The divided voltage is applied through the third switching element Tc. At this time, the voltages are distributed according to the sizes of the channels of the second switching device Tb and the third switching device Tc. Therefore, even if the data voltages transferred to the first sub-pixel PXa and the second sub-pixel PXb are the same through the data line DL, the first liquid crystal capacitor Ca and the second liquid crystal capacitor Cb are charged The voltage is different. That is, the voltage charged in the second liquid crystal capacitor Cb becomes lower than the voltage charged in the first liquid crystal capacitor Ca.

Therefore, the voltages charged in the first liquid crystal capacitor Ca and the second liquid crystal capacitor Cb in one pixel PX can be different, thereby improving the side viewability. The level of the constant voltage applied to the second terminal of the third switching element Tc may be higher than the level of the common voltage applied to the common electrode. Illustratively, when the common voltage is about 7V, the constant voltage applied to the second terminal of the third switching element Tc may be about 8V to 11V, but is not limited thereto.

FIG. 13 is a layout diagram of one pixel located in the first pixel region in FIG. 1 in the display device according to yet another embodiment, and FIG. 14 is a layout diagram of a third pixel region Fig. 15 is a sectional view taken along line X9-X9 'in Fig. 13, Fig. 16 is a sectional view taken along line X11-X11' in Fig. 13, Sectional view taken along the line X13-X13 '.

In order to more clearly explain the structure of the display device 3, reference numerals different from those of FIG. 12 are used. In the case of the same configuration as that shown in FIG. 1 to FIG. 11, . In addition, duplicate content is omitted, and differences are emphasized.

13 to 17, the display device 3 according to the present embodiment may include a first substrate 100c, a second substrate 200, and a liquid crystal layer 300. [

Hereinafter, the first substrate 100c will be described.

The first switching element T11a, the second switching element T11b, the third switching element T11c, the divisional voltage reference line CL1, the first connection part T11b, the second switching part T11c, and the second connection part T11b are formed on the first base substrate 110 in the first pixel area PA11. HC11, the first sub-pixel electrode PE11a, and the second sub-pixel electrode PE11b.

The first switching element T11a includes a first gate electrode GE11a connected to the first gate line G1, a first semiconductor pattern SM11a located on the gate insulating layer 124, And a first source electrode SE11a and a first drain electrode DE11a which are located in the first semiconductor pattern SM11a and are connected to the first semiconductor pattern SM11a. The first source electrode SE11a may be electrically connected to the second upper data line HD2.

The second switching element T11b includes a second gate electrode GE11b connected to the first gate line G1, a second semiconductor pattern (not shown) located on the gate insulating layer 124, a gate insulating layer 124 And a second source electrode SE11b and a second drain electrode DE11b which are located on the first semiconductor layer (not shown) and connected to a second semiconductor pattern (not shown). The second source electrode SE11b may be connected to the first source electrode SE11a and the second drain electrode DE11b may be connected to a third drain electrode DE11c to be described later.

The third switching element T11c includes a third gate electrode GE11c connected to the first gate line G1, a third semiconductor pattern SM11c located on the gate insulating layer 124, And a third source electrode SE11c and a third drain electrode DE11c connected to the third semiconductor pattern SM11c. The third source electrode SE11c may be connected to a voltage divider reference line CL1 to be described later to be supplied with a reference voltage.

The partial pressure reference line CL1 may be located on the gate insulating layer 124. [ A reference voltage for voltage distribution is applied to the divided voltage reference line CL1. In some embodiments, the reference voltage applied to the divided voltage reference line CL1 may be different from the common voltage applied to the common electrode 270. [ Illustratively, the voltage divider line CL1 may be provided with a voltage higher than the common voltage.

The partial voltage dividing line CL1 may be at least partially parallel to the first lower data line LD1 and the second lower data line LD2. In some embodiments, the partial pressure-applying line CL1 may be disposed so as to overlap with the first sub-pixel electrode PE11a and the second sub-pixel electrode PE11b.

The organic layer 230 may be located on the first switching device T11a, the second switching device T11b, the third switching device T11c, and the voltage dividing reference line CL1. Illustratively, The color filter 230a may be positioned.

A third contact hole CH11-1c exposing a part of the first source electrode SE11a is formed in the organic layer 230. [

A first connection part HC11 connected to the second upper data line HD2 is located on the organic layer 230. The first connection part HC11 is connected to the first source electrode SE11a through the third contact hole CH11-1c, Lt; / RTI >

A planarization layer 180 is positioned on the organic layer 230. A part of the first contact hole CH11a and the third drain electrode DE11c exposing a part of the first drain electrode DE11a are exposed to the first color filter 230a and the planarization layer 180 of the organic layer 230 The second contact hole CH11c can be located.

The first sub-pixel electrode PE11a and the second sub-pixel electrode PE11b are located on the planarization layer 180. [ The first sub-pixel electrode PE11a is positioned above the first gate line G1 with reference to the drawing and the second sub-pixel electrode PE11b is positioned below the first gate line G1 with reference to the drawing .

The first sub-pixel electrode PE11a is connected to the first drain electrode DE11a via the first contact hole CH11a and the second sub-pixel electrode PE11b is connected to the third drain electrode DE11a through the second contact hole CH11b. And can be connected to the electrode DE11c.

Each of the first sub-pixel electrode PE11a and the second sub-pixel electrode PE11b may include a plurality of branch portions spaced apart by a stripe portion and a slit as described above with reference to FIG. In some embodiments, the area of the first sub-pixel electrode PE11a may be smaller than the area of the second sub-pixel electrode PE11b.

In the second pixel region PA21, the fourth switching device T21a, the fifth switching device T21b, the fifth switching device T21c, the divided voltage reference line CL1, the third sub- The electrode PE21a and the fourth sub-pixel electrode PE21b may be positioned.

The fourth switching element T21a includes a fourth gate electrode GE21a connected to the second gate line G2, a fourth semiconductor pattern SM21a located on the gate insulating layer 124, And a fourth source electrode SE21a and a fourth drain electrode DE21a connected to the fourth semiconductor pattern SM21a. And the fourth source electrode SE21a may be connected to the first lower data line LD1.

The fifth switching element T21b includes a fifth gate electrode GE21b connected to the second gate line G2, a fifth semiconductor pattern (not shown) located on the gate insulating layer 124, a gate insulating layer 124 And a fifth source electrode SE21b and a fifth drain electrode DE21b connected to a fifth semiconductor pattern (not shown). The fifth source electrode SE21b may be connected to the second source electrode SE21a and the fifth drain electrode DE21b may be connected to a sixth drain electrode DE21c to be described later.

The sixth switching element T21c includes a sixth gate electrode GE21c connected to the second gate line G2, a sixth semiconductor pattern (not shown) located on the gate insulating layer 124, a gate insulating layer 124 And a sixth source electrode SE21c and a sixth drain electrode DE21c connected to a sixth semiconductor pattern (not shown). The sixth source electrode SE21c may be connected to the divided voltage reference line CL1 to receive the reference voltage.

The divisional voltage reference line CL1 may extend from the first pixel area PA11 to the third pixel area PA21 and may be arranged to overlap with the third subpixel electrode PE21a and the fourth subpixel electrode PE21b. have.

The first pixel area PA11 and the third pixel area PA21 may be located in the same column. Accordingly, the organic layer 230 may be located on the fourth switching element T21a, the fifth switching element T21b, the sixth switching element T11c, and the voltage division reference line CL1 in the third pixel PA21, The first color filter 230a of the organic layer 230 may be positioned.

A planarization layer 180 is positioned on the organic layer 230. A part of the fourth contact hole CH21a and the sixth drain electrode DE21c exposing a part of the fourth drain electrode DE21a are exposed to the first color filter 230a and the planarization layer 180 of the organic layer 230 The fifth contact hole CH21c may be located.

On the planarization layer 180, the third sub-pixel electrode PE21a and the fourth sub-pixel electrode PE21b are located. The third sub-pixel electrode PE21a is positioned above the second gate line G2 with reference to the drawing and the fourth sub-pixel electrode PE21b is positioned below the second gate line G2 with reference to the drawing .

The third sub-pixel electrode PE21a is connected to the fourth drain electrode DE41a via the fourth contact hole CH21a and the fourth sub-pixel electrode PE21b is connected to the sixth drain electrode DE41a through the fifth contact hole CH21b. And can be connected to the electrode DE21c. The descriptions of the third sub-pixel electrode PE21a and the fourth sub-pixel electrode PE21b are substantially the same as those of the first and second sub-pixel electrodes PE11a and PE11b.

FIG. 18 is a cross-sectional view taken along line X9-X9 'of FIG. 13, and FIG. 19 is a cross-sectional view taken along line X11-X11' of FIG. Sectional view of the display device according to still another embodiment taken along the line X13-X13 'in FIG.

18 to 20, the display device 4 according to the present embodiment differs from the display device 3 described above with reference to FIGS. 13 to 17 only in the structure of the first substrate 100d, Are substantially the same or similar. Therefore, the differences are mainly described below.

The first source electrode SE11a and the first drain electrode DE11a of the first switching device T11-1a in the first pixel area PA11 are not in contact with the gate insulating layer 124 and the first source electrode The first semiconductor pattern SM11-1a may be further disposed between the gate insulating layer 124 and the entirety of the first drain electrode DE11a and between the gate insulating layer 124 and the entirety of the first drain electrode DE11a.

Similarly, a second semiconductor pattern SM11-1b is formed between the entire portion of the second source electrode SE11b of the second switching element T11b and the entire portion of the second drain electrode DE11b and the gate insulating layer 124 And a third semiconductor pattern SM11-1c is formed between the entire portion of the third source electrode SE11c of the third switching element T11c and the entire portion of the third drain electrode DE11c and the gate insulating layer 124 Can be located.

The three switching elements located in the second pixel area PA21 may have substantially the same structure as the three switching elements located in the first pixel area PA11 described above.

Illustratively, all of the fourth source electrode SM21-1a of the fourth switching device T21-1a located in the second pixel area PA21 and the gate insulating layer 124 and the fourth drain electrode DE21- The fourth semiconductor pattern SM21-1a may be positioned between the gate insulating layer 124 and the entirety of the first semiconductor pattern SM1-1a.

A first data semiconductor pattern SP1 may be disposed between the first lower data line LD1 and the gate insulating layer 124 and a second data semiconductor pattern SP1 may be formed between the second lower data line LD2 and the gate insulating layer 124. [ 2 data semiconductor pattern SP2 may be located as described above with reference to FIGS.

The display device according to the above-described embodiments is advantageous in that the ratio of the area occupied by the data lines in the display device can be reduced by superimposing the two data lines, thereby improving the aperture ratio of the display device . And has an advantage that the aperture ratio can be increased even if the display device is made high resolution.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be appreciated that many variations and applications not illustrated above are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (19)

A base substrate including a first pixel region and a second pixel region;
A first gate line located on the base substrate and extending in a first direction;
A lower data line which is insulated from the first gate line and extends in a second direction intersecting with the first direction;
A first switching element located on the base substrate and located in the first pixel region and connected to the first gate line;
An organic layer located on the first switching element and the lower data line;
An upper data line located on the organic layer and extending in the second direction and overlapping the lower data line and electrically connected to the first switching device;
A planarization layer located on the organic layer and covering the upper data line;
A first pixel electrode located on the planarization layer and located in the first pixel region and connected to the first switching element; And
A shielding electrode disposed on the planarization layer and spaced apart from the first pixel electrode, the shielding electrode overlapping the upper data line and extending along the second direction; . The method according to claim 1,
And the shielding electrode overlaps with the lower data line. 3. The method of claim 2,
Wherein the shielding electrode completely covers the lower data line and the upper data line in a plane. The method according to claim 1,
Wherein the organic layer includes a first color filter located in the first pixel region. The method according to claim 1,
A connection portion located on the organic layer and located in the first pixel region and connected to the upper data line; Further comprising:
And the connection portion is in contact with the source electrode of the first switching element through the organic layer. The method according to claim 1,
A second gate line located on the base substrate and extending in the first direction and spaced apart from the first gate line along the second direction;
A second switching element located on the base substrate and located in the second pixel region and connected to the first gate line and the lower data line; And
A second pixel electrode located in the second pixel region and connected to the second switching element; Further comprising: The method according to claim 6,
Wherein the first pixel region is located at one side of the shielding electrode along the first direction,
And the second pixel region is located on the other side of the shielding electrode along the first direction. The method according to claim 6,
Wherein the first pixel region and the second pixel region are located in different rows and in different columns. The method according to claim 6,
Wherein the organic layer is further located on the second switching element,
And the second pixel electrode is located on the planarization layer. 10. The method of claim 9,
Wherein the organic layer includes a first color filter located in the first pixel region and a second color filter located in the second pixel region and different from the first color filter,
Wherein the first color filter and the second color filter partially overlap to form an overlapping portion. 11. The method of claim 10,
Wherein the overlapping portion comprises:
And overlaps the upper data line and the lower data line. A base substrate including a first pixel region and a second pixel region;
First and second gate lines disposed on the base substrate and extending in a first direction and spaced apart from each other in a second direction intersecting with the first direction;
A first lower data line and a second lower data line which are insulated from the first gate line and the second gate line and extend in the second direction and are spaced apart from each other along the first direction;
A first switching element located on the base substrate and located in the first pixel region and connected to the first gate line;
A second switching element located on the base substrate and located in the second pixel region and connected to the second gate line and the first lower data line;
An organic layer located on the first switching element, the second switching element, the first lower data line, and the second lower data line;
A first upper data line located on the organic layer and extending in the second direction and overlapping the first lower data line;
A second upper data line located on the organic layer and extending in the second direction and overlapping the second lower data line;
A planarization layer located on the organic layer and covering the first upper data line and the second upper data line;
A first pixel electrode located on the planarization layer and located in the first pixel region and connected to the first switching element;
A second pixel electrode located on the planarization layer and located in the second pixel region and connected to the second switching element;
A first shielding electrode located on the planarization layer and overlapping the first upper data line; And
A second shielding electrode located on the planarization layer and overlapping the second upper data line; / RTI >
And the first switching element is electrically connected to the second upper data line. 13. The method of claim 12,
A connection portion located on the organic layer and connected to the second upper data line; Further comprising:
And the connection portion is in contact with the source electrode of the first switching element through the organic layer. 13. The method of claim 12,
Wherein the first pixel region and the second pixel region are adjacent along the second direction. 15. The method of claim 14,
Wherein the organic layer comprises a vehicle. 16. The method of claim 15,
Wherein a portion of the organic layer located within the first pixel region and a portion located within the second pixel region include the same vehicle. 13. The method of claim 12,
Wherein the first switching element includes a first gate electrode connected to the first gate line,
The second switching element includes a second gate electrode connected to the second gate line,
Wherein the shortest distance between the first lower data line and the first gate electrode measured along the first direction is shorter than the shortest distance between the first lower data line and the second gate electrode measured along the first direction, . 18. The method of claim 17,
And the second gate electrode is positioned adjacent to the first lower data line relative to the first gate electrode. A base substrate;
A gate line located on the base substrate and extending in a first direction;
A lower data line which is insulated from the gate line and extends in a second direction intersecting with the first direction;
A divided voltage reference line spaced apart from the gate line and the lower data line;
A first switching element located on the base substrate and including a first source electrode, a first drain electrode, and a first gate electrode connected to the gate line;
A second switching element located on the base substrate and including a second source electrode connected to the first source electrode, a second drain electrode, and a second gate electrode connected to the gate line;
A third switching element located on the base substrate and including a third source electrode connected to the voltage divider reference line, a third drain electrode connected to the second drain electrode, and a third gate electrode connected to the gate line;
An organic layer located on the first switching element, the second switching element, the third switching element, the divided voltage reference line, and the lower data line;
An upper data line located on the organic layer and overlapping the lower data line and electrically connected to the first source electrode of the first switching device;
A planarization layer located on the organic layer and covering the upper data line;
A first sub-pixel electrode located on the planarization layer and electrically connected to the first drain electrode;
A second sub-pixel electrode located on the planarization layer and electrically connected to the third drain electrode; And
A shielding electrode located on the planarization layer and overlapping the upper data line;
.

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