KR20190079603A - memory controller for use in access concentration decrease menagement and access concentration decrease method - Google Patents

Abstract

A spatial interference problem which occurs when access is concentrated in a specific memory area in a volatile semiconductor memory such as a DRAM or the like is properly solved by a memory controller apparatus. The memory control apparatus comprises: a concentration access detection unit generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of the volatile semiconductor memory; and a controller for preventing or mitigating data held by the memory cells of the specific memory area and/or the memory cells of adjacent memory areas adjacent to the specific memory area when the concentration access detection signal is generated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory control apparatus and an access concentration reduction method for access concentration reduction management,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field for preventing or mitigating cell data corruption in a volatile semiconductor memory, and more particularly, to a memory control device and an access concentration reduction method for access concentration reduction management.

A dynamic semiconductor memory such as a dynamic random access memory (hereinafter referred to as "DRAM") may be installed in a data storage device such as an SSD and controlled by a memory control device connected to the processor.

The DRAMs are further reduced in spacing between word lines, between bit lines, and between memory cells in response to demands for high speed, high capacity, and low power consumption.

Thus, when memory cells connected to a certain word line are accessed, memory cells connected to adjacent word lines of the accessed word line are subjected to spatial disturbance due to a coupling effect or the like. The cell data stored in the memory cells connected to the adjacent word lines is likely to be corrupted if access to a specific word line is intensively generated. That is, data 0 can be obtained at the time of reading the memory cell storing the data 1, or data 1 can be obtained at the time of reading the memory cell storing the data 0.

If deterioration of cell data occurs due to concentrated access of a specific word line or a specific memory area, a critical error of the data storage device may be caused.

SUMMARY OF THE INVENTION The present invention provides a memory control device capable of preventing or mitigating deterioration of cell data caused by concentrated access.

It is another object of the present invention to provide an access concentration reduction method capable of reducing intensive access to a specific memory area of a DRAM.

According to an aspect of the inventive concept to achieve the above object, the memory control apparatus comprises:

An intensive access detector for generating an intensive access detection signal when an address for accessing a specific memory area among the memory areas of the volatile semiconductor memory is intensively received; And

And a controller for preventing or mitigating alteration of data held in memory cells of the specific memory area and / or memory cells of adjacent memory areas adjacent to the specific memory area when the lumped-access detection signal is generated.

According to another aspect of the inventive concept to achieve the above object, the memory control device comprises:

An intensive access detector for generating an intensive access detection signal when a row address for accessing a specific word line among the word lines of the volatile semiconductor memory is intensively received;

A refresh counter for outputting a high-speed auto refresh period faster than the set normal auto refresh period when the concentrated access detection signal is generated; And

And a controller for controlling the memory cells connected to the specific word line to be refreshed to the high-speed auto refresh period in response to the output of the refresh counter in order to prevent or mitigate the deterioration of the data held in the memory cells connected to the specific word line do.

According to still another aspect of the present invention, there is provided a memory control apparatus comprising:

An intensive access detector for generating an intensive access detection signal when a row address for accessing a specific word line among the word lines of the volatile semiconductor memory is intensively received;

A refresh counter for outputting a high-speed auto refresh period faster than the set normal auto refresh period when the concentrated access detection signal is generated; And

Wherein memory cells coupled to adjacent word lines in response to an output of the refresh counter are coupled to the high speed auto refresh cycle in response to an output of the refresh counter to prevent or mitigate alteration of data held by memory cells connected to adjacent word lines adjacent to the particular word line. And includes a controller for refreshing.

According to another aspect of the concept of the present invention to achieve the above object,

Checking whether an address for accessing a specific memory area among the memory areas of the volatile semiconductor memory is intensively received to generate an intensive access detection signal upon centralized address reception;

And address concentration for the specific memory area is eliminated to prevent the data held by the memory cells of the specific memory area and / or the memory cells of adjacent memory areas adjacent to the specific memory area from being altered.

According to an embodiment of the present invention, even if access concentration occurs in a specific memory area by performing the access concentration reduction management, cell data corruption of the volatile semiconductor memory is prevented or mitigated.

1 is a block diagram showing a connection configuration of a memory control device according to the concept of the present invention;
Fig. 2 is a schematic circuit block diagram of the DRAM in Fig. 1,
Figure 3 is a detailed block diagram of one embodiment according to Figure 1,
FIG. 4 is a detailed block diagram of another embodiment according to FIG. 1;
Figure 5 is a detailed block diagram of another embodiment according to Figure 1,
Figure 6 is a detailed block diagram of another embodiment according to Figure 1,
Figure 7 is a detailed block diagram of another embodiment according to Figure 1,
FIG. 8 is a flowchart of operation control of the memory control device of FIG. 1,
Figure 9 is an exemplary block diagram of a data storage device to which the inventive concept is applied;
10 is a block diagram illustrating an application of the present invention applied to a memory system;
11 is a block diagram illustrating an application example of the present invention applied to a mobile device;
12 is a block diagram illustrating an application of the present invention applied to an optical I / O schema, and
13 is a block diagram illustrating an application of the present invention applied to a trough silicon via (TSV);

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent from the following description of preferred embodiments with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, without intention other than to provide an understanding of the present invention.

In this specification, when it is mentioned that some element or lines are connected to a target element block, it also includes a direct connection as well as a meaning indirectly connected to the target element block via some other element.

In addition, the same or similar reference numerals shown in the drawings denote the same or similar components as possible. In some drawings, the connection relationship of elements and lines is shown for an effective explanation of the technical contents, and other elements or circuit blocks may be further provided.

Each of the embodiments described and exemplified herein may also include its complementary embodiment, and details regarding the basic data access operation and the refresh operation and the internal function circuit for the DRAM will be described in detail in order to avoid obscuring the gist of the present invention Please note that it is not.

1 is a block diagram showing a connection structure of a memory control device according to the concept of the present invention.

Referring to FIG. 1, a memory controller (memory controller) 200 includes an intensive access detecting unit 210. The memory control device 200 may be connected to the processor 100 through a bus B1 and may be connected to the DRAM 300 through a bus B2. Meanwhile, the memory control device 200 may be embedded in the processor 100.

The centralized access detecting unit 210 in the memory control device 200 detects an intensive access detection when an address for accessing a specific memory area among the memory areas of the DRAM 300 is intensively received from the processor 100. [ And generates a signal CADS.

The lumped-access detecting unit 210 searches a memory area (or a word line) or memory areas (word lines) having a high access count for a set time or a set plurality of operation cycles. This search can be accomplished by comparing the currently applied row address, column address, block or bank address with a previously applied row address, column address, block or bank address, and then counting the number of times the same addresses are applied. Accordingly, the concentrated access detection signal CADS is generated when the number of times of application of an address frequently applied exceeds a predetermined threshold value.

The memory control device 200 can not corrupt the data held in the memory cells of the specific memory area or the memory cells of the adjacent memory areas adjacent to the specific memory area when the intensive access detection signal CADS is generated, (230 in Fig. 3) for preventing or mitigating the occurrence of a malfunction.

2 is a schematic circuit block diagram of the DRAM in FIG.

Referring to FIG. 2, the DRAM 300 includes a row decoder 310, a memory cell array 320, a sense amplifier circuit 330, a column decoder 340, an input / output buffer 350, a command buffer 360, And a refresh control circuit 370.

The DRAM 300 is a conventional DRAM and is illustrated without any intention except for an intention to facilitate understanding of access concentration in the embodiment of the present invention.

The memory cell array 320 includes a plurality of memory cells in the form of a matrix of rows and columns. Each memory cell MC is constituted by a storage capacitor SC of one access transistor AT. The gate of the access transistor (AT) is connected to the corresponding word line (WLi). The drain of the access transistor AT is connected to the corresponding bit line BLi. A plurality of memory cells connected to the same word line form a memory page.

The state of the cell data is determined as the amount of charge stored in the storage capacitor SC. Since the charge stored in the storage capacitor SC leaks over time, the DRAM 300 needs a refresh operation to restore the data before the state of the cell data changes.

The row decoder 310 decodes the row address to select the row line (word line) of the memory cell array 320.

The column decoder 340 decodes the column address to select a column line (bit line) of the memory cell array 320.

The sense amplifier circuit 330 senses and amplifies the data of the memory cell appearing on the bit line.

The input / output buffer 350 buffer external write data to be stored in the selected memory cell, buffer the data read from the memory cell, and output the buffered data to the outside.

The command buffer 360 buffers an externally applied command (CMD). The command is decoded to enable the operation of the DRAM 300 to be performed in accordance with the command.

The refresh control circuit 370 generates the refresh control signal RC so that the memory cells are refreshed.

The DRAM 300 performs an auto refresh operation in a memory access operation and a self refresh operation in a standby operation.

As the design rule is reduced, the spacing P between the word lines WL1 and WL2 to which the memory cells of the memory cell array 320 are connected is gradually reduced. For example, when a particular word line WL1 is accessed relatively frequently compared to other word lines, the particular word line WL1 may result in fatigue failure. In addition, the data held by the memory cells connected to the specific word line WL1 may be altered.

The data held in the memory cells connected to the adjacent word lines WL0 and WL2 adjacent to the specific word line WL1 are corrupted by a spatial disturbance due to a coupling effect, ).

In order to prevent or alleviate the deterioration of the cell data, the memory control device 200 may have the configuration and functions as shown in FIGS.

3 is a detailed block diagram of an embodiment according to FIG.

Referring to FIG. 3, the memory control apparatus 200 may include an intensive access detecting unit 210, a command decoder 220, a controller 230, and a page buffer 240 (or a register).

The memory control device 200 applies the interrupt signal to the processor 100 when the centralized access detection signal CADS is generated. Here, the interrupt signal may be the intensive access detection signal CADS, and may be provided to the interrupt controller 130 via a line L50. Meanwhile, when the memory control device 200 is embedded in the processor 100, the interrupt controller 130 may be configured in the memory control device 200.

The microprocessor 100 receives the interrupt request signal INT from the interrupt controller 130. The microprocessor 100 changes the address allocation in firmware or software when receiving the interrupt request signal INT.

The changed address allocation is applied to the memory control device 200 through the system bus 120 existing between the lines L10 and L30. As a result, when the centralized access detection signal CADS is generated, an access which has been concentrated in the specific memory area by the address change of the firmware or software performed by the processor is avoided.

For example, if access to the particular word line WL1 of FIG. 2 has been concentrated, another word line (e.g., WLn) is accessed by the address allocation change.

Therefore, the data held by the memory cells connected to the adjacent word lines WL0 and WL2 adjacent to the specific word line WL1 by the software address change by the interruption can be prevented from being affected by the spatial interference it is difficult to corruption because it no longer receives spatial disturbance. That is, data corruption is prevented or minimized.

3, when the lumped-access detection signal is generated, the interrupt signal can be stored in an internal register, such as the page buffer 240, without directly applying the interrupt signal to the interrupt controller 130. Accordingly, the interrupt controller 130 having checked the internal register outputs an interrupt request signal INT to the microprocessor 100 when the interrupt signal is present.

Likewise, the microprocessor 100 changes the address allocation in firmware or software when receiving the interrupt request signal INT. The changed address allocation is applied to the memory control device 200 through the system bus 120 existing between the lines L10 and L30.

As a result, in this case also, when the concentrated access detection signal CADS is generated, the processor changes the address allocation in firmware or software. Accordingly, accesses that have been concentrated in a specific memory area such as a word line, a bit line, a memory block, or a memory bank are avoided.

Thus, since the specific memory area is not accessed any more, the deterioration of the data held by the memory cells connected to the adjacent word lines WL0 and WL2 adjacent to the specific word line WL1 is prevented or minimized.

Firmware or software resolution, ie application-level access-intensive troubleshooting, requires that the cache or buffer be reallocated by software, thus eliminating or minimizing the installation of hardware.

4 is a detailed block diagram of another embodiment according to FIG.

4, the memory control device 201 may include an intensive access detection unit 210, a command decoder 220, a controller 230, and a refresh counter 250.

The memory control apparatus 201 may be configured to access the specific memory region of the DRAM 300-i through the refresh counter 250 when the centralized access detection signal is generated from the centralized access detecting unit 210 The auto refresh period for automatically refreshing the memory included therein is controlled to be faster than the normal auto refresh period.

In FIG. 4, assume that the microprocessor 100 has applied a physical address through the system bus 120 to intensively access the word line (WL1 in FIG. 2) of the DRAM 300-1.

Accordingly, the centralized access detecting unit 210 of the memory control device 201 generates the centralized access detection signal CADS. The refresh counter 250 outputs an auto refresh counting signal in which an auto refresh period is adjusted as fast as a certain rate in response to the centralized access detection signal CADS. The DRAM controller 230 applies the auto refresh command to the command buffer 360 of the DRAM 300-1 in accordance with the auto refresh counting signal. Thus, when the centralized access detection signal is generated, the auto refresh period of the volatile memory including the word line (WL1 in FIG. 2) of the DRAM 300-1 is shorter than the normal auto refresh period. As a result, the auto refresh operation is frequently performed corresponding to the concentration of addresses, thereby preventing deterioration of cell data.

Accordingly, a plurality of memory cells connected to the word line (WL1 in FIG. 2) of the DRAM 300-1 can secure the state of the cell data more securely despite the address concentration of the corresponding word line.

5 is a detailed block diagram of another embodiment according to FIG.

5, the memory control device 202 may include an intensive access detection unit 210, a command decoder 220, a controller 230, and a refresh controller 260.

The memory control device 202 is connected to an adjacent memory area (not shown) adjacent to the specific memory area of the DRAM 300-i via the refresh controller 260 when the centralized access detection signal is generated from the centralized access detecting part 210. [ So that a refresh command for refreshing can be generated. In this case, the word line address of the adjacent memory area is provided.

The memory control device 202 may also be configured to control the refresh operation of the DRAM 300-i when the lumped access detection signal is generated from the lumped access detection unit 210, It is possible to induce the memory area to be refreshed. That is, the controller 230 controls the word line of the adjacent memory area to be activated and controls the bit line of the adjacent memory area to be free-charged so that the refresh operation is performed on the adjacent memory area.

5, it is assumed that the microprocessor 100 has applied a physical address through the system bus 120 to intensively access the word line (WL1 in FIG. 2) of the DRAM 300-1.

Accordingly, the centralized access detecting unit 210 of the memory control device 202 generates the centralized access detection signal CADS. The refresh controller 260 outputs the refresh control signal through the line SL2 in response to the centralized access detection signal CADS. The DRAM controller 230 applies the refresh command for the adjacent word lines to the command buffer 360 of the DRAM 300-1 in accordance with the refresh control signal. Accordingly, adjacent word lines (WL0, WL2) adjacent to the word line (WL1 in FIG. 2) of the DRAM 300-1 are refreshed when an intensive access detection signal is generated. As a result, the adjacent word lines WL0 and WL2 are refreshed corresponding to the concentration of the address.

Thus, in the case where access to a specific word line is concentrated, memory cells connected to the adjacent word lines WL0 and WL2 are released or robust from spatial interference caused by a coupling effect or the like, so that deterioration of cell data is prevented Is minimized.

On the other hand, at the time of refreshing the adjacent word lines, a plurality of memory cells connected to the word line (WL1 in FIG. 2) of the DRAM 300-1 may be refreshed together.

Figure 6 is a detailed block diagram of another embodiment according to Figure 1;

Referring to FIG. 6, the memory control device 203 may include an intensive access detecting unit 210, a command decoder 220, a controller 230, an address converter 270, and a replacement buffer 280.

The memory control device 203 performs a data swap operation when an intensive access detection signal is generated from the centralized access detection unit 210. [ That is, the controller 230 reads the data stored in the memory cells connected to the specific word line WL1 of the DRAM 300-i and stores the read data in the replacement buffer 280. Also, the controller 230 reads the data stored in the memory cells connected to the word line WLn, which is not concentrated in the access, and stores the read data in the replacement buffer 280. The data stored in the replacement buffer 280 is swapped with each other and then stored in the memory cells connected to the specific word line WL1 and the memory cells connected to the word line WLn.

After completion of the swapping operation, the controller 230 causes the row address of the specific word line WL1 and the row address of the word line WLn to change with each other through the address converter 270. [ That is, the controller 230 performs address re-mapping to cause the word line WLn to be selected when a row address for selecting the specific word line WL1 is applied.

Here, data swapping can occur between rows in the same memory bank, but data swapping between rows in different memory banks may also be possible. The word line to be replaced is preferably not spatially adjacent to the word line to be replaced.

In FIG. 6, assume that the microprocessor 100 has applied a physical address through the system bus 120 to access the word line (WL1 in FIG. 2) of the DRAM 300-1 intensively.

Accordingly, the centralized access detecting unit 210 of the memory control device 203 generates the centralized access detection signal CADS. The address converter 270 receives the concentrated access detection signal CADS and applies an address conversion request signal to the DRAM controller 230.

The DRAM controller 230 causes the data stored in the memory cells connected to the specific word line WL1 and the data stored in the memory cells connected to the word line WLn to swap through the replacement buffer 280. [

After the completion of the swapping operation, the controller 230 causes the row address of the specific word line WL1 and the row address of the word line WLn to be interchanged through the address converter 270. The word line WLn is accessed instead when the row address for accessing the specific word line WL1 is applied by the address re-mapping control of the controller 230. [

Thus, when accesses to a particular word line are concentrated, the memory cells connected to the adjacent word lines WL0, WL2 are free from spatial interference due to coupling effects and the like. In addition, the memory cells connected to the access-concentrated word line are prevented or minimized in deterioration of cell data due to resolution of the access concentration.

Figure 7 is a detailed block diagram of another embodiment according to Figure 1;

Referring to FIG. 7, the memory control apparatus 204 may include an intensive access detecting unit 210, a command decoder 220, a controller 230, and a page cache 290.

The memory control device 204 stores the data stored in the memory cells connected to the specific access word line WL1 of the DRAM 300-i in the internal page cache 290 when the lumped-access detection signal is generated Caching. Then, the memory control device 204 prevents the specific word line WL1 from being accessed when a row address for accessing a specific word line WL1 is received after the difference. Instead, the memory control device 204 may provide the data stored in the page cache 290 to the access requesting processor 290.

In FIG. 7, assume that the microprocessor 100 has applied a physical address through the system bus 120 to access the word line (WL1 in FIG. 2) of the DRAM 300-1 intensively.

Accordingly, the centralized access detection unit 210 of the memory control device 204 generates the centralized access detection signal CADS. The DRAM controller 230 reads the data stored in the memory cells connected to the specific word line WL1 and stores the read data in the page cache 290. The page cache 290 may be made up of volatile memory cells which do not require a refresh operation, such as flip-flop or latch elements.

After completion of the page caching operation, the controller 230 causes the page cache 290 to be accessed when a row address of the specific word line WL1 is applied. When the data of the page cache 290 is updated, the updated data may be periodically stored in the specific word line WL1 or another word line.

Thus, when accesses to a particular word line are concentrated, the memory cells connected to the adjacent word lines WL0, WL2 are completely free from spatial interference due to coupling effects, and the like. In addition, the memory cells connected to the access-concentrated word line are prevented or minimized in deterioration of cell data due to resolution of the access concentration.

Although a page cache is used in FIG. 7, it is needless to say that a block or a bank cache may be provided in cases where the matter is different.

8 is a flowchart of operation control of the memory control device of FIG.

Referring to FIG. 8, in step S100, the memory control device 200 performs initialization. The internal registers and flags are set to the initial state at the time of initialization. In step S101, the input address is received and counted. The input address may be a virtual address or a physical address applied from the processor. The memory control device 200 receives the virtual address or the physical address to generate a DRAM address.

In this case, the memory control device 200 checks whether the specific address is frequently received through step S102 and detects the centralized access.

When a specific word line, a specific bit line, or a specific memory block of a volatile semiconductor memory such as a DRAM is intensively accessed, deterioration of memory cell data may be caused. That is, the memory cells of neighboring word lines adjacent to a specific word line, adjacent bit lines adjacent to a specific bit line, or memory cells of an adjacent memory block adjacent to a specific memory block can lose cell data due to centralized access. Various schemes for eliminating or avoiding such address concentration and preventing or mitigating loss of cell data are shown in step S103.

That is, the memory control device 200 can perform the control operation as described with reference to FIGS. 3 to 7 when the access to the specific memory area is concentrated.

That is, an interrupt is generated as described with reference to FIG. 3, causing the processor to change the address assignment at the application level.

In addition, as described with reference to FIG. 4, refreshing is performed more frequently in the auto refresh of the word line or the memory area to be intensively accessed.

Also, the adjacent word line or memory area of the word line or memory area to be intensively accessed as described with reference to FIG. 5 is refreshed.

Further, data swapping is performed through the replacement buffer as described with reference to FIG. 6, so that the concentrated address and the non-converged address are remapped to each other.

In addition, data caching as described with reference to FIG. 7 allows access to the concentrated memory area to be avoided.

9 is an exemplary block diagram of a data storage device to which the inventive concept is applied.

9, the data storage device may include a microprocessor 100, an input / output device 500, a memory controller 200, a DRAM 300, and a flash memory 400.

The memory controller 200 connected to the microprocessor 100 through the bus B1 is connected to the DRAM 300 via the bus B2. A flash memory 400 capable of flash erasing as a nonvolatile memory is connected to the memory controller 200 via a bus B3. The input / output device 500 is connected to the microprocessor 100 via a bus B4.

The memory controller 200 may use the DRAM 300 as a data buffer in a data storage device such as an SSD or the like.

The memory controller 200 may periodically invalidate the memory area of the DRAM 300 when a request for the same logical block address LBA is continuously generated from the host bus adapter HBA of the microprocessor 100 Can be reassigned. The memory controller 200 controls the refresh cycle, the address re-mapping, and the page refresh operation when the microprocessor 100 intensively accesses a specific word line of the DRAM 300 within the access operation cycle, Caching to prevent or minimize alteration of cell data held in victim memory cells of memory regions adjacent to the memory region being intensively accessed.

In this manner, deterioration of cell data can be prevented or mitigated at the application level and the memory controller level. Thus, the reliability of the data storage device is improved and the operation performance is improved.

10 is a block diagram illustrating an application of the present invention applied to a memory system.

Referring to FIG. 10, the memory system includes a controller 1000 and a memory device 2000. The controller 1000 includes an intensive access detecting unit 210 according to an embodiment of the present invention. Also, the memory device 2000 includes a refresh control circuit (RFCON) 2100 that is a refresh operation related block. The controller 1000 can apply commands, addresses, and write data to the memory device 2000 through a bus (BUS).

The centralized access detecting unit 210 of the controller 1000 has an address (row address) for accessing a specific memory area (a specific word line) among the memory areas (word lines) of the memory device 2000 And generates an intensive access detection signal at the time of centralized access reception.

The controller 1000 eliminates address concentration for the specific memory area (specific word line) at the time of generating the lumped-access detection signal. The resolution of the address concentration can be accomplished by changing the address allocation in software by the processor in response to an interrupt request. Thus, the data held by the memory cells of the specific memory area and / or the memory cells of adjacent memory areas adjacent to the specific memory area are prevented or minimized from being altered.

As other methods for address concentration, various schemes as described with reference to FIGS. 4-7 can be employed.

By the adoption of such schemes, even if accesses to any particular word line are intensively generated, the cell data stored in the memory cells connected to the adjacent word lines is difficult to deteriorate. That is, memory cells coupled to adjacent word lines of a word line are free or robust from spatial disturbance due to coupling effects and the like.

Thus, the reliability of the memory system is improved and the operation performance is improved.

11 is a block diagram showing an application example of the present invention applied to a mobile device.

11, a mobile device may include a transceiver and modem 1010, a CPU 1001, a DRAM 2001, a flash memory 1040, a display unit 1020, and a YUI interface 1030 .

The CPU 1001, the DRAM 2001, and the flash memory 1040 may be manufactured or packaged into one chip as the case may be. As a result, the DRAM 2001 and the flash memory 1040 may be embedded in the mobile device.

When the mobile device is a portable communication device, the transceiver and the modem 1010 perform communication data transmission / reception and data modulation / demodulation functions.

The CPU 1001 controls all operations of the mobile device according to a preset program. Here, the CPU 1001 may include a centralized address detection unit 210 according to an embodiment of the present invention.

The DRAM 2001 is connected to the CPU 1001 through a system bus 1100 and can function as a buffer memory or a main memory of the CPU 1001. [ The DRAM 2001 may include a refresh control circuit (RFCON) 2100 to control a refresh operation for memory cells.

The CPU 1001 can apply the command, address, and write data to the DRAM 2001 through the system bus 1100.

The centralized access detecting unit 210 of the CPU 1001 checks whether a row address for accessing a specific word line among the word lines of the DRAM 2001 is intensively received and outputs an intensive access detection signal .

The CPU 1001 resolves the address concentration for the specific word line by software or by functionally controlling the DRAM 2001 at the time of generating the centralized access detection signal.

Thus, deterioration, mitigation, or minimization of data held by memory cells connected to the specific word line and / or memory cells connected to adjacent word lines adjacent to the specific word line is prevented.

As a result, various schemes as described with reference to Figs. 3 to 7 can be adopted as methods for solving the address concentration.

With the adoption of such schemes, even if accesses to any particular word line occur intensively, the memory cells connected to adjacent word lines of the word line are free or robust from spatial interference due to coupling effects and the like.

Accordingly, the reliability of a mobile device such as a smart phone is improved and the operation performance is improved.

The flash memory 1040 may be a NOR type or a NAND type flash memory.

The display unit 1020 may have a touch screen as a liquid crystal having a backlight or an element such as a liquid crystal or an OLED having an LED light source. The display unit 1020 functions as an output device for displaying images such as characters, numbers, and pictures in color.

The user interface 1030 may be an input device including a numeric key, a function key, and the like, and functions to interface between the electronic device and a person.

Although the mobile device has been described as a mobile communication device, it may function as a smart card by adding or subtracting components when necessary.

The mobile device may be connected to an external communication device via a separate interface. The communication device may be a digital versatile disc (DVD) player, a computer, a set top box (STB), a game machine, a digital camcorder, or the like.

Although it is not shown in the drawing, the mobile device may be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Do.

The DRAM 2001 chip or the flash memory 1040 chip may be mounted using various types of packages, either individually or together. For example, the chip can be used as a package in package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC) ), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package Can be packaged as a package.

Although the flash memory is employed in Fig. 11, various types of nonvolatile storage can be used.

The non-volatile storage may store data information having various data types such as text, graphics, software codes, and the like.

The non-volatile storage may include, for example, an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM, a spin transfer torque MRAM, a conductive bridging RAM CBRAM), FeRAM (Ferroelectric RAM), PRAM (Phase Change RAM), OBR (Ovonic Unified Memory), Resistive RAM (RRAM or ReRAM), Nanotube RRAM, Polymer RAM ), A nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory .

12 is a block diagram showing an application example of the present invention applied to an optical I / O schema. Referring to FIG. 12, a memory system 30 employing a high-speed optic I / O includes a chipset 40 and memory modules 50 and 60 as a controller mounted on a PCB substrate 31. The memory modules 50 and 60 are inserted into the slots 35_1 and 35_2 provided on the PCB substrate 31, respectively. The memory module 50 includes a connector 57, DRAM memory chips 55_1 to 55_n, an optical I / O input section 51, and an optical I / O output section 53.

The optical I / O input unit 51 may include a photo-electric conversion element, for example, a photodiode, for converting an applied optical signal into an electrical signal. Therefore, the electric signal output from the photo-electric conversion element is received by the memory module 50. The optical I / O output unit 53 may include an electro-optical conversion element, for example, a laser diode, for converting an electric signal output from the memory module 50 into an optical signal. If necessary, the optical I / O output unit 53 may further include an optical modulator for modulating a signal output from the light source.

The optical cable 33 is responsible for optical communication between the optical I / O input unit 51 of the memory module 50 and the optical transmission unit 41_1 of the chipset 40. The optical communication may have a bandwidth of several tens of Gigabits per second or more. The memory module 50 may receive signals or data from the signal lines 37 and 39 of the chipset 40 through the connector 57 and transmit the signals or data through the optical cable 33 Speed data communication with the chipset 40. On the other hand, the resistors Rtm provided in the unshown lines 37 and 39 are termination resistors.

In the case of the memory system 30 employing the optical I / O structure as shown in FIG. 12, since the chipset 40 has the centralized access detecting unit 210, the centralized access canceling scheme according to the present invention is applied in various forms . When the DRAM memory chips 55_1 to 55_n of the memory modules 50 and 60 are accessed by memory page unit, column unit, or bank unit, the centralized access detecting unit 210 monitors access concentration .

When the centralized access detecting unit 210 monitors the concentration of each memory page, the centralized access detecting unit 210 can accumulate the row addresses in a cumulative manner and generate the centralized access detection signal when the same row address is greater than the set access frequency.

Also, the centralized access detecting unit 210 can generate the centralized access detection signal by cumulatively comparing the row addresses within a predetermined unit time range.

In the case where the memory system of Fig. 12 is referred to as an SSD, the DRAM memory chips 55_1-55_n may be used as a yaw data buffer.

The chip set 40 periodically invalidates or reallocates the internal buffer area of the DRAM memory chips when a request for the same logical block address (LBA) continues to be generated from the host bus adapter (HBA). Accordingly, address concentration of the DRAM memory chips to a specific WL or memory area is avoided, thereby improving the performance and reliability of the SSD.

13 is a block diagram illustrating an application example of the present invention applied to a trough silicon via (TSV).

Referring to the structure of the stacked memory device 500 of FIG. 13, a plurality of memory chips 520, 530, 540 and 550 are vertically stacked on the interface chip 510. Here, a plurality of through silicon vias 560 are formed through the memory chips 520, 530, 540 and 550. The three-dimensional stack package type memory device 500 vertically stacking a plurality of memory chips on the interface chip 510 using TSV technology is advantageous for high speed, low power consumption, and miniaturization while storing a large amount of data. Structure. 13, since the interface chip 510 may include the centralized access detecting unit 210, it is possible to prevent or mitigate deterioration of data in the DRAMs in the plurality of memory chips 520, 530, 540, Can be efficiently performed according to the concept of "

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. For example, various alterations and modifications may be made to implementation schemes that can prevent or mitigate deterioration of cell data due to centralized access without departing from the technical spirit of the present invention when the matter is different.

Description of the Related Art [0002]
100: Processor
200: Memory controller
210:
300: DRAM

Claims (10)

A controller for accessing the memory cells based on a first physical address corresponding to a first word line connected to memory cells of the volatile semiconductor memory device; And
Counting the number of times the first physical address is applied from the processor within a set time interval by comparing the first physical address and a second physical address applied to the controller prior to the first physical address, And an intensive access detector for generating an intensive access detection signal when the number of times exceeds a set value,
The lumped-access detection unit provides the lumped-access detection signal to an interrupt controller connected to the processor, and
Wherein the interrupt controller provides an interrupt signal to the processor based on the concentrated access detection signal. The method according to claim 1,
Wherein the processor alters the address allocation with respect to the first physical address based on the interrupt signal. The method according to claim 1,
And a page buffer for storing the concentrated access detection signal, and
Wherein the interrupt controller checks the page buffer and receives the centralized access detection signal. The method according to claim 1,
Wherein the memory control device is embedded in the processor. The method according to claim 1,
After the interrupt signal is provided to the processor, the processor applies the first physical address to the controller a number of times less than the number of times within the set time interval. A controller for accessing the memory cells based on a first physical address corresponding to a first word line connected to memory cells of the volatile semiconductor memory device;
Counting the number of times the first physical address is applied from the processor within a set time interval by comparing the first physical address and a second physical address applied to the controller prior to the first physical address, An intensive access detector for generating an intensive access detection signal when the number of times exceeds a set value; And
A page cache controlled by the controller,
The controller reads data stored in the memory cells connected to the first word line and stores the data in the page cache when the lumped-access detection signal is generated. The method according to claim 6,
Wherein the controller accesses the page cache instead of accessing the memory cells when the controller receives the first physical address from the processor after the data is stored in the page cache. 8. The method of claim 7,
Wherein the controller provides the data stored in the page cache to the processor. The method according to claim 6,
Wherein the controller refreshes the data stored in the memory cells and does not refresh the data stored in the page cache. 10. The method of claim 9,
Wherein the page cache comprises a flip-flop or latch and the volatile semiconductor memory device is a DRAM.

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