KR20190074695A - Apparatus and method for controlling dual-port memory - Google Patents

Abstract

Disclosed are a dual port memory and a control method thereof. According to the present invention, a shared data region includes a first data region and a second data region, and a region recording new data between two regions is set as an activation region to record data in an inactivation region when an MCU records data in a corresponding sharing memory unit region and to allow other MCUs to read the data recorded in the activation region even while the data is being recorded in the inactivation region, thereby solving conventional data collision and read delay problems.

Description

[0001] DESCRIPTION [0002] Dual-port memory and its control method [0002]

The present invention relates to a memory and a control method thereof, and more particularly, to a dual port memory and a control method thereof.

As a typical method for sharing data storage space in two or more MCUs, there is a method of adopting dual-port memory. The dual-port memory connects two data buses and address buses for input / output in one memory, allowing two or more MCUs to freely input and output data without being influenced by each other's states.

In the access control method of the memory, it is checked whether the current memory is being used by another MCU by using the Read / Write signal, and if it is in use, the use state of another MCU is terminated, Data is input / output.

This input / output control scheme prevents data collision by preventing another MCU from approaching the same space at the same time when one MCU is using a specific memory space. However, if the memory is being used by another MCU, it may be necessary to wait until the other MCU is used to access the memory, so that an unspecified time delay may occur. Which may degrade data processing performance.

Also, since this access control method is performed every time when accessing every byte or word, when accessing data composed of a plurality of bytes or words, data is changed by another MCU in the middle of reading or writing data, Data may be read out.

SUMMARY OF THE INVENTION The present invention provides a dual port memory and a control method thereof, which allow a plurality of MCUs using a dual port memory to access a memory in real time for data reading and writing without delay time.

According to a preferred embodiment of the present invention, there is provided a dual port memory including a first data area, a second data area, and a status area indicating an activated area of the first data area and the second data area, A shared memory area containing; Each of the plurality of MCUs is connected to one or more MCUs to receive a data read command or a data write command for the shared memory area and access the shared memory area according to the received command, Reads data from the activated data area out of the first data area and the second data area, writes data in the inactivated data area, and then writes the data area in which the status area is newly recorded with data A first interface and a second interface for changing data in the status area to indicate the first interface and the second interface; And a controller for checking access to the shared memory area from the first interface or the second interface to confirm access to the shared memory area when the access request (read request or write request) is received.

In addition, the control unit may immediately approve the access request when the access request received from the first interface or the second interface is a read request.

In addition, when the access request received from the first interface or the second interface is a write request, the control unit checks whether an access request is received from another interface for the same shared memory area, If the access request not received or received from the other interface is not an access request for recording, the access request can be approved.

When the access request for recording is received from another interface in the same shared memory area, the control unit approves the access request to any one of the first interface and the second interface in accordance with a predefined rule , The access request can be disapproved with the other one.

When the access request for recording is received from another interface in the same shared memory area, the control unit approves the access request to any one of the first interface and the second interface in accordance with a predefined rule , And the other can approve the access request after a predefined time delay.

In accordance with another aspect of the present invention, there is provided a dual port memory control method for controlling a dual port memory, which is implemented in a dual port memory including a first interface, a second interface, (A) receiving a control command and an address from a first MCU connected to the first interface; (b) converting, by the first interface, the address into an address corresponding to the shared memory area, and requesting access to the address translated into the control unit in accordance with the control command; (c) the control unit identifying an access request from the first interface; (d) if the access request is an access request for reading, the control immediately approving access to the first interface; (e) the first interface, which is approved for access, connects to the converted address to read the status area of the shared memory area, and reads the data recorded in the data area identified as the activated data area in the status area Wherein the shared memory area includes a first data area, a second data area, and a status area indicating an active area of the first data area and the second data area, have.

In the dual port memory control method, when the access request identified in the step (c) is an access request for recording, the controller transmits an access request from the second interface to the same shared memory area Confirming that it has been received; (g) if the access request from the second interface is not received, or if the access request received from the second interface is not an access request for recording, the control unit approves the access request to the first interface; And (h) the first interface, which has been granted access, accesses the converted address to read the status area of the shared memory area, writes data in the data area identified as the inactivated data area from the status area, And changing the data in the status area so that the status area indicates a data area in which data is newly recorded.

In the step (g), when an access request for recording is received from the second interface, the access request is approved by either the first interface or the second interface according to a predefined rule, One can approve the request for access.

In the step (g), when an access request for recording is received from the second interface, the access request is approved by either the first interface or the second interface according to a predefined rule, One can approve the access request after a predefined time delay.

The dual port memory control method may further include the steps of: (i) if an access request for reading from the second interface is received as a result of the checking in the step (f), the controller sends an access request to the second interface immediately The second interface accesses the converted address to read the status area of the shared memory area, reads the data recorded in the data area identified as the activated data area in the status area, To the second MCU.

According to the present invention, a shared data area includes a first data area and a second data area, and an area in which the latest data is recorded is set as an active area, so that the MCU tries to write data in the shared memory unit area , It is possible to record the data in the inactive area and to solve the data collision and read delay problem in the related art by allowing other MCUs to read the data recorded in the active area even if the data is being written in the inactive area can do.

1 is a diagram illustrating a configuration of a dual port memory according to a preferred embodiment of the present invention.
2 is a diagram illustrating a method of writing data into a shared memory and reading data in accordance with a preferred embodiment of the present invention.
3 is a diagram illustrating a process of reading data from a shared memory area by an MCU connected to a first interface or an MCU connected to a second interface according to a preferred embodiment of the present invention.
4 is a diagram illustrating a process in which an MCU connected to a first interface writes data to a shared memory area and an MCU connected to the second interface reads data from the shared memory area according to a preferred embodiment of the present invention.
5 is a diagram for explaining a processing procedure when an MCU connected to a first interface and an MCU connected to a second interface simultaneously record data in the same shared memory area according to a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a dual port memory 200 according to a preferred embodiment of the present invention.

Referring to FIG. 1, a dual port memory 200 according to an exemplary embodiment of the present invention includes a first interface 210, a shared memory area 230, a controller 240, and a second interface 220, do.

First, the structure of the shared memory area 230 of the present invention will be described.

The shared memory area 230 of the present invention includes data state areas 231-1 to 231-n of a predefined length, first data areas 232-1 to 232-n, and second data areas 233- 1 to 233-n constitute one shared memory unit area, and a plurality of such shared memory unit areas are gathered to constitute a shared memory area 230.

Referring to each shared memory unit area, the data state areas 231-1 to 231-n are divided into first data areas 232-1 to 232-n and second data areas 232-1 to 232- Indicates which of the areas 233-1 to 233-n is an active data area in which the latest data is recorded.

Therefore, when the data stored in the shared memory unit area is read by the first interface 210 and the second interface 220, the data stored in the status areas 231-1 to 231- As shown in FIG. When the first interface 210 and the second interface 220 are intended to write data in the corresponding shared memory unit area, the first interface 210 and the second interface 220 may transmit the activated data represented by the data recorded in the status areas 231-1 to 231- Data areas 231-1 to 231-n are written in the inactive data area, not in the area, and data areas 231-1 to 231-n -n) is changed.

2 is a diagram illustrating a method of writing data to and reading data from the shared memory area 230 according to a preferred embodiment of the present invention. 2, in the preferred embodiment of the present invention, the first data area 232-1 to 232-n and the second data area 233-1 to 233-n are composed of 4 bytes, The status areas 231-1 to 231-n are composed of one byte, and data is read and written in 4-byte units. That is, in the preferred embodiment of the present invention, a total of 9 bytes of storage space is required to store 4-byte data. Hereinafter, for convenience of explanation, one byte is represented by one digit.

1, 2, 3 and 4 are recorded in 4 bytes of the first data areas 232-1 to 232-n at timing [01], and 4, 2, 3 and 4 are recorded in 4 bytes of the second data areas 233-1 to 233- 6, 7, 8, and 9 are recorded in the byte, and 1 is recorded in the data status areas 231-1 to 231-n. Here, since 1 is recorded in the data status areas 231-1 to 231-n, the first data areas 232-1 to 232-n are currently active in the corresponding shared data unit area, The latest data stored in the area is the data stored in the first data areas 232-1 to 232-n, and each interface stores the latest data recorded in the activated first data area .

In the example shown in FIG. 2, at timing [01], when the second interface 220 approaches the area to read data stored in the shared data unit area, the data state area 231 is read first It is judged that the first data area 232 is the activated area and the first data area 232 is set to 1 , 2,3,4].

Thereafter, when the first interface 210 records data [3,4,5,6] in the shared memory unit area at the timing [02] - [06], the first interface 210 stores the data [ It is confirmed that the currently active data area is the data first data area 232 and the inactive area is the second data area 233 and the data is sequentially written in the second data area 233 .

Therefore, [3,4,5,6] is sequentially recorded in the second data area 233 at timing [02] - [05], and when data is recorded in the second data area 233 sequentially, The control unit 210 writes 2 in the data status area 231 at timing [06], indicating that the data activated in the shared memory unit area, i.e., the latest data is the data recorded in the second data area 233 .

When the second interface 220 accesses the corresponding shared memory unit area to read the stored data after 2 is written to the data status area 231, the second interface 220 reads the data stored in the data status area 231 2 is recorded, and the data [3,4,5,6] is read from the activated second data area 233.

In the case where the second interface 220 accesses and reads data at the timing [04], which is the middle of the first interface 210 writing data in the second data area 233, 220 accesses the shared memory unit area and checks the data status area 231. Since 1 is recorded in the data status area 231, it is determined that the first data area 232 is the activated area, [1, 2, 3, 4] is read out from the data area 232. Therefore, the present invention enables data to be read without data collision even while data is being written by another MCU.

Referring again to FIG. 1, the first interface 210 and the second interface 220 are connected to ports corresponding to each other. The first interface 210 and the second interface 220 are connected to one or more MCUs, Or a data write command and performs a received command on the shared memory area 230. [

Specifically, the first interface 210 and the second interface 220 may be connected to a plurality of MCUs via a bus, or may be directly connected to a dedicated MCU. The first and second interfaces 210 and 220 receive an address, a control command, a clock, and data (when recording data) of a memory to be accessed from the MCUs.

The first and second interfaces 210 and 220 convert addresses received from the MCUs 110 and 120 into row and column addresses in the shared memory area 230 and access the shared memory area 230 to the control part 240 request. When the control unit 240 approves the access, the first and second interfaces 210 and 220 access the shared memory area 230 to read the status areas 231-1 to 231-n, If the received control command is a data read command, the data stored in the activated data area is read and transmitted to the MCUs 110 and 120. If the received control command is a write command, Data is recorded in the inactivated data area, and the values recorded in the data status areas 231-1 to 231-n are changed to indicate the data area in which the new data is recorded.

When the control unit 240 receives an access request (read request or write request) to the shared memory area 230 from the first interface 210 and the second interface 220, Lt; RTI ID = 0.0 > 230 < / RTI >

In this case, when a write request for the same shared memory unit area is input from the first interface 210 and the second interface 220 at the same time, It may grant access to the interface, deny access to interfaces that are interfaced with other MCUs, or allow access after a sufficient time delay for an authorized interface to write data.

In this case, the control unit 240 may set the priority of the MCU periodically accessing the shared memory among the plurality of MCUs requesting data recording to be set to be higher or lower, so that access can be granted according to the priority. When accessing the shared memory area 230, the MCU to be granted access may be selected according to the shared memory access period.

As described above, in order to prevent data collision, the prior arts have the problem that while the data is being written to the shared memory area 230, the approach of another MCU is intrinsically blocked and an unexpected long- Respectively.

However, the present invention is characterized in that the shared data area 230 includes the first data areas 232-1 to 232-n and the second data areas 233-1 to 233-n, Writes the recorded area in the status areas 231-1 to 231-n as active areas, and when the MCU 110 and 120 intends to record data in the shared memory unit area, the data is once written in the inactive area, The problem of data collision and read delay in the prior art is solved by allowing other MCUs to read the data recorded in the activated data area, even if the data is being recorded in the inactive area.

The dual port memory 200 according to the preferred embodiment of the present invention has been described.

Hereinafter, a method of controlling the dual port memory 200 according to a preferred embodiment of the present invention will be described with reference to FIGS. 3 to 5, which illustrate a control method of the dual port memory 200. FIG.

3 illustrates a process of reading data from the shared memory area 230 by the MCU 110 connected to the first interface 210 or the MCU 120 connected to the second interface 220 according to a preferred embodiment of the present invention Fig.

Referring to FIG. 3, the first interface 210 or the second interface 220 receives a control command (read command) and a shared memory address from the MCUs 110 and 120 to which the first interface 210 or the second interface 220 is connected (S310).

The first interface 210 or the second interface 220 converts the received address into low and column addresses in the shared memory area 230 and outputs an access request for the converted address to the controller 240 ).

The control unit 240 receiving the address and access request confirms whether or not the access request is an access request for recording data at step S330. If the access request is not for data recording, the control unit 240 approves the access immediately at step S335.

The first interface 210 or the second interface 220 which has been granted access accesses the shared memory area 230 to read the state areas 231-1 to 231-n included in the shared memory area 230 The active areas indicated by the data recorded in the status areas 231-1 to 231-n are the first data areas 232-1 to 232-n and the second data areas 233-1 to 233- n) (S350).

The first interface 210 or the second interface 220 may be configured such that when the active areas indicated by the status areas 231-1 to 231-n are the first data areas 232-1 to 232-n, (S360), and the activation area indicated by the status areas 231-1 to 231-n is read from the second data area 233- 1 to 233-n), the data recorded in the second data areas 233-1 to 233-n are read and transmitted to the MCUs 110 and 120 (S370).

4 illustrates an exemplary embodiment of the present invention in which an MCU 110 connected to a first interface 210 writes data in a shared memory area 230 and an MCU 120 connected to a second interface 220 And reading data from the memory area 230. FIG.

4, the first interface 210 receives a control command (write command), a shared memory address, and data to be written from the MCU 110 to which the first interface 210 is connected (S410).

The first interface 210 converts the received address into low and column addresses in the shared memory area 230 and outputs an access request for the converted address to the controller 240 in step S420.

When receiving the address and access request, the control unit 240 checks whether the access request is an access request for data recording. If the access request is not for data recording, the control unit 240 proceeds to S335 in FIG. 3 to approve the access immediately ).

However, if the access request is for data recording, the control unit 240 checks whether an access request has been received from the second interface 220 for the same shared memory area 230 (S440) If the access request is not received from the second interface 220 or if the access request received from the second interface 220 is not an access request for data recording, the operation proceeds to operation S450, If it is an access request for recording, the process proceeds to step S550 of FIG. 5 described later (S445).

4, the second interface 220 performs the same steps as steps S310 and S320 of FIG. 3 to read data stored in the same shared memory area 230. In this case, (240) to access the shared memory area (230).

In step S450, the controller 240 accesses the first interface 210 and the second interface 220, respectively (S450). At this time, the second interface 220 reads the data stored in the shared memory area 230 by performing the same steps as steps S340 to 370 of FIG.

The first interface 210 that has been granted access accesses the converted address to read the status areas 231-1 to 231-n of the corresponding shared memory area 230 (S460) -1 to 231-n) (step S471).

The first interface 210 records data in the inactive data area (S473, S475), and the data in the status areas 231-1 through 231-n is written in the data area in which the first interface 210 newly records data The existing data stored in the state areas 231-1 to 231-n is changed (S480).

5 illustrates an exemplary embodiment of the present invention in which the MCU 110 connected to the first interface 210 and the MCU 120 connected to the second interface 220 simultaneously write data in the same shared memory area 230 And FIG. It should be noted that the example shown in FIG. 5 is described based on the first interface 210. FIG.

5, both the first interface 210 and the second interface 220 receive a control command (write command), a shared memory address, and data to be written from the MCUs 110 and 120 to which the first interface 210 and the second interface 220 are connected (S510) The first interface 210 and the second interface 220 convert the received address into low and column addresses in the shared memory and simultaneously transmit the access request for the converted address to the control unit 240 (S520) .

The controller 240 receiving the address and access request checks whether the access request is an access request for recording. If the access request is not for recording, the controller 240 proceeds to step S335 in FIG. 3 to approve the access immediately (S530).

However, if the access request is for data recording, the control unit 240 checks whether an access request has been received from the other interface (i.e., the second interface) for the same shared memory area 230, If the access request is not received from the second interface 220 or if the access request received from the second interface 220 is not an access request for data recording, the operation proceeds to operation S450, If it is an access request for recording, the MCU 110 or 120 to approve access according to a predefined rule is selected (S550).

The predefined rules may be set such that, for example, an MCU periodically accessing the shared memory area 230 among a plurality of MCUs 110 and 120 requesting data recording is set to have a higher or lower priority, If the MCUs 110 and 120 periodically access the shared memory area 230, the MCUs 110 and 120 may be selected according to the length of the cycle of accessing the shared memory area 230.

In step S550, when the first interface 210 is approved and the second interface 220 is disabled, the first interface 210 performs steps S460 through S480 in FIG. 230).

In step S550, instead of notifying the second interface 220 of the disapproval, after the first interface 210 delays the data for a time sufficient to write data in the shared memory area 230, Interface 220, in which case the second interface 220 may perform steps S460 through S480 after a time delay.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

110: First MCU
120: Second MCU
200: Dual port memory
210; The first interface
220: Second interface
230: Shared memory area
231-1 to 231-n: status area
232-1 to 232-n: first data area
233-1 to 233-n: second data area
240:

Claims (10)

A shared memory area including a first data area, a second data area, and a status area indicating an activated area of the first data area and the second data area;
Each of the plurality of MCUs is connected to one or more MCUs to receive a data read command or a data write command for the shared memory area and access the shared memory area according to the received command, Reads data from the activated data area out of the first data area and the second data area, writes data in the inactivated data area, and then writes the data area in which the status area is newly recorded with data A first interface and a second interface for changing data in the status area to indicate the first interface and the second interface; And
(A read request or a write request) for the shared memory area from the first interface or the second interface, and confirms access to the shared memory area by checking whether there is a data collision. Dual port memory. The apparatus of claim 1, wherein the control unit
And immediately approves the access if the access request received from the first interface or the second interface is a read request. The apparatus of claim 1, wherein the control unit
If an access request received from the first interface or the second interface is a write request, confirms whether an access request is received from another interface for the same shared memory area, and if no access request is received from another interface, If the access request received from the access point is not an access request for recording, approves the access request. 4. The apparatus of claim 3, wherein the control unit
When an access request for recording from another interface is received for the same shared memory area, the access request is approved by either the first interface or the second interface in accordance with a predefined rule, Dual port memory characterized by disapproval. 4. The apparatus of claim 3, wherein the control unit
When an access request for recording from another interface is received for the same shared memory area, the access request is approved by either the first interface or the second interface in accordance with a predefined rule, And accepts the access request after a defined time delay.
A dual port memory control method performed in a dual port memory including a first interface, a second interface, a shared memory area, and a control unit,
(a) receiving a control command and an address from a first MCU connected to the first interface;
(b) converting, by the first interface, the address into an address corresponding to the shared memory area, and requesting access to the address translated into the control unit in accordance with the control command;
(c) the control unit identifying an access request from the first interface;
(d) if the access request is an access request for reading, the control immediately approving access to the first interface;
(e) the first interface, which is approved for access, connects to the converted address to read the status area of the shared memory area, and reads the data recorded in the data area identified as the activated data area in the status area To the first MCU,
Wherein the shared memory area includes a first data area, a second data area, and a status area indicating an active area of the first data area and the second data area. The method according to claim 6,
(f) if the access request identified in step (c) is an access request for recording, the control unit confirms whether an access request has been received from the second interface for the same shared memory area;
(g) if the access request from the second interface is not received, or if the access request received from the second interface is not an access request for recording, the control unit approves the access request to the first interface; And
(h) the first interface, which is granted access, accesses the converted address to read the status area of the shared memory area, writes data in the data area identified as the inactivated data area from the status area, Further comprising changing data in the state area so that the area indicates a data area in which data is newly recorded. 8. The method of claim 7, wherein step (g)
Wherein when an access request for recording is received from the second interface, the access request is approved by any one of the first interface and the second interface and the access request is disallowed by the other one according to a predefined rule A dual port memory control method. 8. The method of claim 7, wherein step (g)
When receiving an access request for recording from the second interface, approving the access request to one of the first interface and the second interface according to a predefined rule, and the other accepting the access request after a predefined time delay And the access request is accepted. 8. The method of claim 7,
(i) when an access request for reading from the second interface is received as a result of the checking in the step (f), the control unit immediately approves the access request to the second interface, Reading the status area of the shared memory area, reading the data recorded in the data area identified as the activated data area in the status area, and transmitting the read data to the second MCU requesting the data reading Wherein the dual port memory control method comprises:

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