KR20190061823A - Organic light emitting display panel and organic light emitting display apparatus using the same - Google Patents

Abstract

According to an objective of the present invention, provided are an organic light emitting display panel and an organic light emitting display device using the same. The organic light emitting display panel comprises a structure of a driving transistor provided in a display region to control the amount of current flowing to an organic light emitting diode, a structure of a switching transistor provided in the display region and supplying data voltage to the driving transistor, and a structure of a non-display region transistor provided in a non-display region to supply a gate pulse to the switching transistor; and the structures are different from each other.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting display panel and an organic light emitting display using the organic light emitting display panel.

The present invention relates to an organic light emitting display panel and an organic light emitting display using the same.

An organic light emitting display apparatus uses a self-luminous element and has low power consumption, and thus is widely used as a flat panel display.

1 is a schematic view illustrating a pixel structure of a conventional organic light emitting display panel.

The organic light emitting display panel applied to the organic light emitting display includes a display region including pixels for outputting light and a non-display region provided around the display region.

As shown in FIG. 1, each of the pixels of the display region is provided with an organic light emitting diode (OLED) for outputting light and a driving transistor (Tdr) for controlling the amount of current flowing to the organic light emitting diode. Each of the pixels may further include transistors that perform various functions in addition to the driving transistor Tdr.

And a gate-in-panel (GIP) type gate driver for supplying a gate pulse to the pixels in the non-display area. The gate driver is composed of transistors that perform various functions.

In the conventional organic light emitting display panel, the transistors included in the display region and the transistors included in the non-display region all have the same structure.

However, since the transistors in the non-display region and the transistors in the display region have different functions, when transistors having the same structure and composed of the same material are provided in the non-display region and the display region, Can be reduced.

In recent years, in order to differentiate the external design of the organic light emitting display panel, development of an organic light emitting display panel in which the width of the non-display area is reduced is actively under development. However, if all the transistors included in the non-display region and the display region have the same structure, the width of the non-display region is hardly reduced.

That is, if the structures of the transistors included in the display region and the transistors included in the non-display region are the same, the width of the non-display region that can be reduced is limited.

For example, in order to reduce the width of the gate driver, the characteristics of the transistors constituting the gate driver must be improved. In particular, as the current capability of the transistors increases, the size of the transistors can be reduced. In order to increase the current capability of the transistors, a method of using a high-mobility semiconductor element as the material of the active layer can be used. However, this method has a disadvantage in that the process window is limited.

It is an object of the present invention, which is proposed to solve the above-mentioned problems, to provide a driving transistor having a structure in which a driving transistor is provided in a display region and controls an amount of current flowing to an organic light emitting diode, And a structure of a non-display region transistor provided in a non-display region and supplying a gate pulse to the switching transistor are different from each other, and an organic light emitting display using the same.

According to an aspect of the present invention, there is provided an OLED display panel including a display region for displaying an image, a substrate disposed at a periphery of the display region and divided into a non-display region in which a gate driver is embedded, A driving transistor connected to the organic light emitting diode, the driving transistor including a driving bottom gate, a driving active layer, and a driving top gate, the organic light emitting diode being provided in a pixel, A switching transistor connected to the driving top gate, the switching transistor including an active layer for switching and a switching gate, and a gate driver provided in the non-display region, wherein the gate driver includes a bottom gate, And a top gate for a pulse, wherein the gates supplied to the switching transistor And a non-display area, a transistor for generating a signal. A first buffer provided on the substrate and a second buffer provided on the first buffer are provided between the driving bottom gate and the driving active layer. And the second buffer is provided between the bottom gate for gate pulse and the active layer for gate pulse.

According to an aspect of the present invention, there is provided an organic light emitting display including a data driver for supplying data voltages to data lines provided in the organic light emitting display panel and the organic light emitting display panel, And a control unit for controlling the driver.

In the present invention, the non-display region transistor provided in the non-display region includes a top gate and a bottom gate, and the top gate and the bottom gate are electrically connected. Accordingly, in the gate pulse transistor provided in the non-display region, not only the top channel and the bottom channel are formed by the top gate and the bottom gate, but also the electric field between the top gate and the bottom gate becomes the gate pulse transistor Lt; / RTI > Therefore, the current flowing in the active layer of the gate pulse transistor is increased more than the current flowing in the active layer of the transistor composed only of the conventional top gate.

In the gate pulse transistor provided in the non-display area, the size of the output current is determined in consideration of the size, resolution, and load of the panel. Therefore, the current increase of the transistor in which the top gate and the bottom gate are electrically connected can reduce the size of the transistor. Thus, the area of the non-display area can be reduced, and therefore, the width of the non-display area can be reduced.

In the present invention, the driving transistor included in the display region includes a top gate and a bottom gate, and any one of the first terminal and the second terminal of the driving transistor is electrically connected to the top gate, The buffer layer between the active layer and the bottom gate of the non-display region is formed to be thicker than the buffer layer between the active layer and the bottom gate of the non-display region transistor provided in the non-display region. As a result, the width of the section where the driving transistor is turned on and the current rises is widened, thereby widening the voltage representing the gradation of the color, and thus the gradation representation performance of the driving transistor can be improved.

1 is a schematic view illustrating a pixel structure of a conventional organic light emitting display panel.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]
3 is a view illustrating a structure of a pixel included in an OLED display panel according to an exemplary embodiment of the present invention.
4 is a configuration diagram of a gate driver included in the organic light emitting display panel according to the present invention.
5 is an exemplary view showing the configuration of the stage shown in Fig.
6 is a cross-sectional view of an organic light emitting display panel according to the present invention.
7 is a view illustrating a structure of a transistor applied to an OLED display panel according to an exemplary embodiment of the present invention.
8 to 16 are views illustrating a method of manufacturing an organic light emitting display panel according to an exemplary embodiment of the present invention.
17 is a cross-sectional view of a non-display region transistor applied to an organic light emitting display panel according to the present invention.
18 is a graph showing an example of a change in off-state capacitance as a length of a overlap region of a bottom gate for a gate pulse of a non-display region transistor applied to an organic light emitting display panel according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims.

It should be noted that, in the specification of the present invention, the same reference numerals as in the drawings denote the same elements, but they are numbered as much as possible even if they are shown in different drawings.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The term " at least one " should be understood to include all possible combinations from one or more related items. For example, the meaning of 'at least one of the first item, the second item and the third item' means not only the first item, the second item or the third item, but also the second item, the second item and the third item, Means any combination of items that can be presented from more than one.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a view illustrating a structure of an organic light emitting display according to an embodiment of the present invention. FIG. 3 is a view illustrating a structure of a pixel included in the organic light emitting display panel according to the present invention. FIG. 5 is a diagram showing an example of the configuration of the stage shown in FIG. 4; FIG.

The organic light emitting display according to the present invention includes an organic light emitting display panel 100, a data driver 300, and a controller 400, as shown in FIGS.

Hereinafter, the above-described components will be described in order.

2, the OLED display panel 100 includes gate lines GL1 to GLg, data lines DL1 to DLd, pixels 110, and pixels 110 And a gate driver 200 for supplying gate pulses GP to the switching transistors Tsw1 provided in the gate driver 200. [

The organic light emitting display panel 100 includes a display area AA including the pixels 110 for displaying an image and a non-display area NAA surrounding the outer area of the display area AA.

Each of the pixels 110 includes an organic light emitting diode OLED for outputting light and a pixel driving unit PD for driving the organic light emitting diode OLED, as shown in FIG.

Each of the pixels 110 is formed with signal lines DL, GL, PLA, PLB, SL and SPL for supplying a driving signal to the pixel driver PD.

A data voltage Vdata is supplied to the data line DL, a gate pulse is supplied to the gate line GL, and a first driving voltage ELVDD is supplied to the first voltage supply line PLA. A second driving voltage ELVSS is supplied to the second voltage supply line PLB and a sensing voltage Vini is supplied to the sensing line SL. Tsw2) is turned on or off. The first driving voltage is supplied from the first driving voltage supply unit, and the second driving voltage is supplied from the second driving voltage supply unit.

The pixel driving unit PD includes a switching transistor Tsw1 connected to the gate line GL and the data line DL as shown in FIG. 3, data transmitted through the switching transistor Tsw1, A driving transistor Tdr for controlling the magnitude of a current output to the organic light emitting diode OLED in accordance with a voltage Vdata and a sensing transistor Tsw2 for sensing characteristics of the driving transistor Tdr. have. The sensing transistor Tsw2 may be a compensation circuit, and the compensation circuit may further include another transistor and a capacitor other than the sensing transistor Tsw2. In addition to the above-described components, the pixel driver PD may further include an emission transistor for controlling the light emitting time point of the driving transistor Tdr and transistors for other purposes.

A storage capacitor Cst is formed between the gate of the driving transistor Tdr and the anode of the organic light emitting diode OLED.

The switching transistor Tsw1 is turned on by a gate pulse supplied to the gate line GL and transmits the data voltage Vdata supplied to the data line DL to the gate of the driving transistor Tdr.

The driving transistor Tdr is turned on according to the data voltage Vdata and supplies a current corresponding to the data voltage Vdata to the organic light emitting diode OLED. The intensity of light output from the organic light emitting diode OLED can be changed according to the amount of current flowing through the driving transistor Tdr.

The sensing transistor Tsw2 is connected to the first node n1 and the sensing line SL between the driving transistor Tdr and the organic light emitting diode OLED and is turned on or off by the sensing pulse SP, And senses the characteristics of the driving transistor during a sensing period. The sensing transistor Tsw2 may be connected to the sensing line SL in a one-to-one manner, but two sensing transistors Tsw2 provided in the first and second pixels adjacent to each other may be connected to one sensing line SL, . In addition, for example, when red pixels, green pixels, blue pixels, and white pixels constitute unit pixels, the four sensing transistors Tsw2 included in one unit pixel are connected to one sensing line (SL).

The second node n2 connected to the gate of the driving transistor Tdr is connected to the switching transistor Tsw1. The storage capacitor Cst is formed between the second node n2 and the first node n1. The driving characteristic of the driving transistor Tdr can be improved and the sensing sensitivity of the sensing transistor Tsw2 can be improved as the capacitance of the storage capacitor Cst (hereinafter simply referred to as storage capacitance) .

In addition to the structure shown in FIG. 3, the pixel driver PD may further include transistors and capacitors, and may have a variety of structures.

The transistors included in the pixel driver PD may be, for example, oxide thin film transistors using oxide semiconductors.

The gate driver 200 is embedded in the non-display area NAA. The gate driver 200 is provided on the organic light emitting display panel 100 together with the transistors through a process of generating transistors included in the pixels. The gate driver 200 incorporated in the organic light emitting display panel 100 is referred to as a gate in panel (GIP) type gate driver 200.

The gate pulse GP includes a gate pulse for turning on the switching transistor Tsw1 and a gate low signal for turning off the switching transistor.

The gate driver 200 includes stages 210 to Stage 210 for supplying gate pulses GP1 to GPg to gate lines GL1 to GLg connected to the pixels, g).

Each of the stages 210 includes a plurality of non-display area transistors Tgip and the stage 210 having four non-display area transistors T1, T2, T3 and T4 Respectively.

For example, the first non-display area transistor T1 is turned on by the start signal Vst to supply the high voltage VD to the gate of the third non-display area transistor T3 through the Q node Q .

The third non-display region transistor T3 is turned on by the high voltage VD to output the clock CLK to the gate line. In this case, a gate pulse GP having a high value is output to the gate line.

The high voltage VD having passed through the first non-display region transistor T1 is converted to a low voltage by the inverter I and supplied to the gate of the fourth non-display region transistor T4 through the Qb node Qb . Thus, the fourth non-display region transistor T4 is turned off.

When the first non-display region transistor T1 is turned off and the second non-display region transistor T2 is turned on, the first low voltage VSS1 is applied to the third non-display region transistor T2 through the third non- Is supplied to the non-display region transistor T3, and thus the third non-display region transistor T3 is turned off.

The first low voltage VSS1 is converted into a high voltage by the inverter I and is supplied to the gate of the fourth non-display region transistor T4 through the Qb node Qb. Thus, the fourth non-display region transistor T4 is turned on. In this case, the second low voltage VSS2 is supplied to the gate line through the fourth non-display region transistor T4. The signal supplied to the gate line through the fourth non-display region transistor T4 is a gate low signal. The gate pulse GP and the gate low signal are generically referred to as the gate signal VG.

When the gate pulse GP is supplied to the gate of the switching transistor Tsw1, the switching transistor Tsw1 is turned on and when the gate-low signal is supplied to the switching transistor Tswl, Tsw1) are turned off.

The structure and function of the stage 210 may be variously modified in addition to the structure and function described in FIG. 5 and the above. Accordingly, the stage 210 may further include other non-display area transistors in addition to the non-display area transistors T1, T2, T3, and T4.

Among the non-display region transistors, the third non-display region transistor (hereinafter, referred to as a pull-up transistor) T3 performs the function of outputting the gate pulse GP to the gate line GL. That is, the pull-up transistor generates the gate pulse using the gate clock CLK and transmits the gate pulse to the gate of the switching transistor Tsw1. The gate pulse GP must have a square wave form and therefore the current passing through the pull-up transistor T3 must be large and therefore the pull-up transistor T3 is larger than the other non- desirable.

In the OLED display panel 100 according to the present invention, the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tsw1 are formed in different shapes. The specific structure and function of the non-display region transistor Tgip, the driving transistor Tdr and the switching transistor Tswl will be described in detail below with reference to FIGS. 6 to 18. FIG.

The function of the controller 400 is as follows.

The controller 400 controls a gate control signal GCS for controlling the gate driver 200 using a timing signal supplied from an external system, for example, a vertical synchronization signal, a horizontal synchronization signal, And outputs a data control signal DCS for controlling the data driver 300. The controller 400 rearranges the input image data input from the external system and supplies the rearranged digital image data Data to the data driver 300.

The functions of the data driver 300 are as follows.

The data driver 300 converts the image data Data input from the controller 400 into an analog data voltage and supplies the analog data voltage to the gate line GL every 1 horizontal period And transmits the data voltages Vdata of the horizontal lines to the data lines DL1 to DLd.

In the above description, the data driver 300 and the controller 400 are independently configured. However, the data driver 300 may be integrally formed with the controller 400.

FIG. 6 is a cross-sectional view of an organic light emitting display panel according to the present invention, FIG. 7 is a view illustrating the structure of a transistor applied to the organic light emitting display panel according to the present invention, and FIGS. FIG. 2 is a cross-sectional view illustrating a method of manufacturing an organic light emitting display panel according to an exemplary embodiment of the present invention. Particularly, FIG. 7A is a cross-sectional view showing the single gate structure described below, FIG. 7B is a cross-sectional view showing the contact structure described below, and FIG. Sectional view showing a double gate structure.

The organic light emitting display panel according to the present invention includes a substrate 101, an organic light emitting diode OLED, a driving transistor Tdr, a switching transistor Tsw1, and a non-display region transistor Tgip, . The substrate 101 is divided into a display area AA in which an image is displayed and a non-display area NAA in which a gate driver 200 is embedded. The organic light emitting diode (OLED) is provided in a pixel 110 provided in the display area AA. The driving transistor Tdr is provided in the pixel 110 and includes a driving bottom gate 126, a driving active layer 123 and a driving top gate 125 and is connected to the organic light emitting diode . The switching transistor Tsw1 is provided in the pixel 110 and includes a switching active layer 133 and a switching gate 135 and is connected to the driving transistor Tdr. The non-display region transistor Tgip is provided in the non-display region to constitute the gate driver 200. The non-display region transistor Tgip includes the gate pulse bottom gate 116, the gate pulse active layer 113, 115) and generates a gate signal (VG) supplied to the switching transistor (Tsw1).

A first buffer 102 provided on the substrate 101 and a second buffer 102 provided on the first buffer 102 are provided between the driving bottom gate 126 and the driving active layer 123. [ A buffer 103 is provided. The second buffer 102 is provided between the gate pulse bottom gate 116 and the gate pulse active layer 113.

The pixel of the organic light emitting display panel 100 may further include a sensing transistor Tsw2 for sensing a change in characteristics of the driving transistor Tdr in addition to the components. The structure of the sensing transistor Tsw2 may be the same as the structure of any one of the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl.

Hereinafter, the basic structure of the driving transistor Tdr, the switching transistor Tswl, and the non-display region transistor Tgip will be described.

The transistor applied to the organic light emitting display panel 100 may be formed using any one of oxide semiconductor, amorphous silicon, polysilicon, and low-temperature polysilicon.

The transistors Tdr, Tsw1, and Tgip used in the present invention use oxide semiconductors. The transistor using the oxide semiconductor has a staggered structure in which a gate, a gate insulating film, and an active layer are sequentially stacked, and a coplanar structure in which an active layer, a gate insulating film, and a top gate are sequentially stacked. And the staggered structure can be further classified into a Back Channel Etched (BCE) structure and an ES (Etch Stopper) structure.

The transistors Tdr, Tsw1, Tgip applied to the present invention have the coplanar structure as shown in FIG.

The manufacturing process of the organic light emitting display panel formed with the coplanar structure may be more complicated than the manufacturing process of the organic light emitting display panel having other structures. However, the device uniformity and reliability of the organic light emitting display panel formed with the coplanar structure, The device uniformity and reliability of the organic light emitting display panel of Fig.

The transistor of the coplanar structure again has a single gate (SG) structure in which a top gate (Gt) is provided and a bottom gate is not provided, as shown in FIG. 7 (a) As shown in the figure, a contact structure in which a top gate Gt and a bottom gate Gb are provided and a bottom gate Gb is connected to a source or a drain of the transistor, And a double gate (DG) structure in which a gate Gt and a bottom gate Gb are provided and a top gate Gt and a bottom gate Gb are connected to each other. In Fig. 7, reference numeral 101 denotes a substrate.

The amount of current passing through the transistor having the double gate (DG) structure can be large in the amount of current passing through the transistor having the single gate (SG) structure. When the amount of current passing through the non-display region transistor Tgip is large, the delay of the signal can be made small, so that a gate pulse having a normal waveform can be outputted. Therefore, the non-display region transistor Tgip (DG) structure as shown in FIG. 7 (c).

That is, in the non-display region transistor Tgip having the double gate (DG) structure, since the top gate 115 for the gate pulse and the bottom gate 116 for the gate pulse are driven by the same voltage, The current passing through the non-display region transistor Tgip is increased, so that the gate pulse GP without delay and distortion can be output from the stage 210. [

The driving transistor Tdr is highly affected by external light and does not require a large capacitor. Therefore, the driving transistor Tdr has the contact structure as shown in FIG. 7 (b). Here, the driving bottom gate 126 functions as a light shield for shielding external light.

The switching transistor Tsw1 is not much affected by external light, and does not require a large capacitor. Therefore, the switching transistor Tsw1 has the single gate (SG) structure as shown in FIG. 7 (a).

In other words, the oxide semiconductor applied to the present invention is light-sensitive. Therefore, the transistors applied to the present invention may be provided with a light shield for the purpose of blocking the influence of light. However, since the driving transistor Tdr is highly affected by external light among the transistors to which the present invention is applied, the driving bottom gate 126 must be provided in the driving transistor. Since the switching transistor Tsw1 is not affected by external light, it is not necessary to provide a light shield, and thus, it can have a single gate (SG) structure as described above. However, the switching transistor Tsw1 may have the contact structure like the driving transistor Tdr.

The bottom gate 116 for gate pulse is provided in the non-display region transistor Tgip for the purpose of forming the double gate DG, rather than for blocking light.

In the non-display region transistor Tgip having the double gate (DG) structure, the intensity of the electric field of the gate pulse top gate 115 and the gate pulse bottom gate 116 is the same as the intensity of the electric field of the gate pulse And the thickness of the insulating film between the active layer 113 for the gate pulse and the bottom gate 116 for the gate pulse.

As the thickness of the insulating film 114 for gate pulse and the thickness of the insulating film between the active layer 113 for gate pulse and the bottom gate 116 for gate pulse become thinner, the current increases.

Therefore, in the present invention, the thickness of the insulating film between the active layer 113 for the gate pulse and the bottom gate 116 for the gate pulse of the non-display region transistor Tgip is set to be larger than the thickness of the driving transistor Is smaller than the thickness of the insulating film between the driving active layer 123 and the driving bottom gate 126 of the driving transistor Tdr.

For this, only the second buffer 103 is provided between the gate pulse active layer 113 and the gate pulse bottom gate 116, and the driving active layer 123 and the driving bottom gate 126, the first buffer 102 and the second buffer 103 are both provided.

When the bottom gate 116 for the gate pulse is applied to the non-display region transistor Tgip, the capacitance of the non-display region transistor Tgip is increased by the bottom gate 116 for gate pulse .

However, in the present invention, the bottom gate for a gate pulse 116 and the top gate 115 for a gate pulse are overlapped at the ends of the bottom gate 116 for a gate pulse and the top gate 115 for a gate pulse By reducing the length of the region, the increase in capacitance can be minimized or reduced. Also, since the overall size of the non-display region transistor Tgip can be reduced by increasing the current in the non-display region transistor Tgip, the capacitance of the non-display region transistor Tgip can be reduced.

Therefore, in the present invention, the capacitance of the non-display region transistor Tgip is not greatly increased as compared with the conventional display, and may have a similar size to the conventional one.

Further, in the present invention, the driving bottom gate 126 of the driving transistor Tdr provided in the display region may be connected to the gate electrode of the non-display region transistor Tgip provided in the non- And has a different structure from the gate 116.

For example, when the resolution of the organic light emitting display panel is increased, the driving bottom gate 126 of the driving transistor Tdr may be used not only as a light blocking layer but also as signal transmission wiring. Thus, in the present invention, the driving bottom gate 126 has a dual structure composed of Cu and MoTi. Further, in order to prevent oxidation of Cu and buffer SiO2, the first buffer 102 formed of a material such as SiNx is added.

Hereinafter, a cross-sectional structure and a manufacturing method of an OLED display panel according to the present invention will be described with reference to FIGS. 6 to 16. FIG.

First, the substrate 101 may be a glass substrate or a plastic substrate. The substrate 101 is provided with a plurality of pixels 110.

Next, in a region where the driving transistor Tdr is provided in the display region AA of the substrate 101 and a region where the non-display region transistor Tgip is provided in the non-display region NAA, A bottom gate 126 and a bottom gate 116 for the gate pulse are formed.

8, a first metal material 127a and a second metal material 128a are coated on the substrate 101, and the driving bottom gate 126 and the gate pulse bottom Patterned photoresistors 501 and 502 are formed at positions corresponding to the gate 116. [

In this case, the photoresist deposited on the upper portion of the second metal material 128a with a constant thickness is exposed using a halftone mask, thereby forming a pattern having different heights The photo resistors 501 and 502 are formed. The height of the first patterned photoresist 501 formed at a position corresponding to the bottom gate for gate pulse 116 is set to a height of a second patterned photoresistor 502 formed at a position corresponding to the driving bottom gate 126 ).

When the first metal material 127a and the second metal material 128a are etched using the patterned photoresistors 501 and 502 as a mask, The resistors 501 and 502 and the first patterned metal material 127b and the second patterned metal material 128b remain.

10, the first patterned photoresist 501 is removed, and the thickness of the second patterned photoresist 502 is removed by a double thickness photoresist ashing process, .

The second patterned metal material 128b is removed using an etchant capable of etching the second patterned metal material 128b, as shown in FIG.

When the second patterned photoresist 502 is removed, the bottom gate 116 for the gate pulse and the bottom gate 126 for driving are formed as shown in FIG.

That is, the driving bottom gate 126 is provided on the substrate and includes a first metal 127 formed of the first metal material 127a and an upper end of the first metal 127, And a second metal 128 formed of a second metal material 128a.

The bottom gate for gate pulse 116 is formed of the first metal material 127a.

For example, the first metal material 127a may be an alloy of molybdenum and titanium (MoTi) (hereinafter, simply referred to as MoTi), and the second metal material 128a may be copper have. That is, the first metal 127 constituting the driving bottom gate 126 may be formed of MoTi, the second metal 128 constituting the driving bottom gate 126 may be copper (Cu ). Further, the bottom gate 116 for gate pulse may be MoTi.

In other words, in a high-resolution organic light-emitting display panel, various wirings can be formed of MoTi, but Cu is additionally deposited on top of the Moti because only Moti has a limitation in reducing the interval of wirings.

However, since the bottom gate 116 for the gate pulse is not necessarily Cu, it can be eliminated.

In the present invention, the length between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse is preferably set to 0 to 3 mu m. In order to maintain such an interval, it is preferable that a step between the bottom gate for gate pulse 116 and the substrate 101 is minimized. For this purpose, it is desirable that the height of the bottom gate for gate pulse 116 is minimized. Therefore, the bottom gate for gate pulse 116 is formed only of the first metal material 127a.

Next, a first buffer material 102a is applied to cover the bottom gate 116 for the gate pulse, the driving bottom gate 126, and the substrate 1201, as shown in Fig.

14, a photoresist 503 is deposited only on the display area provided with the driving bottom gate 126. Using the photoresist 503 as a mask, the first buffer material 102a are etched.

15, the driving bottom gate 126 is covered by the first buffer 102, and the bottom gate for gate pulse 116 is covered by the first buffer 102, Exposed. In order to prevent the movement of Cu constituting the driving bottom gate 126, the thickness of the first buffer 102 may be 300 to 2000 angstroms.

In the present invention, as described above, each of the driving bottom gate 126 and the wirings is composed of a double layer including the first metal (for example, Moti) and the second metal (for example, Cu) do.

In this case, in order to protect the second metal provided on the driving bottom gate 126 and the wirings and to prevent migration of copper constituting the second metal, the first buffer (102). However, the hydrogen constituting the SiNx reduces the uniformity of the device and increases the deterioration, and the non-display region transistor Tgip is more susceptible to shift of the threshold voltage due to deterioration.

Therefore, in the non-display region transistor Tgip, as described above, the second metal material Cu is removed and only the first metal material MoTi is used for the gate pulse bottom gate 116 . Further, since the second metal material Cu is not present, the first buffer formed of SiNx may not be provided in the non-display region provided with the non-display region transistor Tgip.

For this reason, the first buffer 102 may not be provided in a region of the display region where the switching transistor Tsw1 is provided. However, an organic light emitting display panel in which the first buffer 102 is provided in the entire display region and the first buffer 102 is not provided in the non-display region is described as an example of the present invention .

16, a second buffer 103 is coated to cover the first buffer 102, the bottom gate 116 for the gate pulse, and the substrate 101. In this case,

The second buffer 103 is formed of an organic material or an inorganic material, and may be formed of at least one layer.

In particular, the second buffer 103 may be formed of SiO 2. In this case, the second buffer 103 may be formed to a thickness of 4000 ANGSTROM or less.

The second buffer 103 can prevent uniformity and deterioration of the first buffer 102 formed of SiNx.

In particular, indium gallium zinc oxide (IGZO) (hereinafter, simply referred to as IGZO), which forms the active layer of the above transistors, is easily made conductive by hydrogen diffused from an adjacent insulating film. Thus, when the active layer is directly deposited in the first buffer 102 composed of SiNx, the active layer can be made conductive by increasing the carrier concentration.

Therefore, in the present invention, the second buffer 103 formed of SiO 2 is provided at the bottom of the active layer for gate pulse 113, the active layer for driving 123, and the switching active layer 133.

6, various elements constituting the non-display region transistor Tgip, the driving transistor Tdr and the switching transistor Tsw1 are provided on the upper side of the second buffer 102 .

For example, the first terminal 111 for a gate pulse, the second terminal 112 for a gate pulse, the active layer 113 for a gate pulse, the insulating film 114 (for a gate pulse) constituting the non-display region transistor Tgip And a top gate 115 for a gate pulse are provided at the upper end of the second buffer 102.

The driving first terminal 121, the driving second terminal 122, the driving active layer 123, the driving insulating film 124 and the driving top gate 125 constituting the driving transistor Tdr Is provided at the upper end of the second buffer 102.

The switching first terminal 131, the switching second terminal 132, the switching active layer 133, the switching insulating film 134, and the switching top gate 135, which constitute the switching transistor Tsw1, Is provided at the upper end of the second buffer 102.

The non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl are connected to the upper ends of the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl, And an insulating film 104 for protection is applied. The insulating layer 104 may be formed of an organic material or an inorganic material, and may be formed of at least one layer.

Next, a flattening film 105 is provided on the insulating film 104. The planarization layer 105 may be formed of an organic material or an inorganic material, and may be formed of at least one layer.

The planarization layer 105 may function to flatten the tops of the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl.

Lastly, the organic light emitting diode OLED is provided on the planarization film 105, and the organic light emitting diode OLED is connected to the driving first terminal 121 of the driving transistor Tdr.

The organic light emitting diode OLED includes an anode 141, a light emitting layer 142, and a cathode 143.

The anode 141 constituting the organic light emitting diode (OLED) is connected to the first terminal 121 for driving. The organic light emitting diode (OLED) is surrounded by a bank (106). Each of the pixels can be distinguished by the bank 106.

FIG. 17 is a cross-sectional view of a non-display region transistor applied to the organic light emitting display panel according to the present invention. FIG. 18 is a cross- State capacitance according to a change in length of the overlapping region of the first region. 18, the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse shown in FIG. 17 is The change in the turn-on current of the non-display region transistor Tgip at the time of the increase in the threshold voltage, and has a value corresponding to the axis shown on the left side of the graph. The turn-on current does not change greatly according to the length (A). The table shown at the lower end of the graph shown in FIG. 18 shows that the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse shown in FIG. 17 increases State capacitance, and has a value corresponding to the axis shown on the right side of the graph. The off-state capacitance gradually increases in accordance with the length (A).

Hereinafter, the characteristics of the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl will be described.

As described above, in the OLED display panel according to the present invention, the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl have different structures.

First, the non-display region transistor Tgip has a double gate (DG) structure in which the top gate 115 for the gate pulse and the bottom gate 116 for the gate pulse are electrically connected.

The non-display region transistor Tgip is affected by the hydrogen of the SiNx constituting the first buffer 102. Therefore, the non-display region transistor Tgip is formed between the gate pulse bottom gate 116 and the gate pulse active layer 113 Only the second buffer 103 is provided.

The first buffer 102 is provided to protect Cu constituting the driving bottom gate 126 and to prevent migration of the copper. The bottom gate 116 for gate pulse does not contain Cu and thus the first buffer 102 need not be provided at the top of the bottom gate 116 for gate pulse.

In order to maximize the current driving capability of the non-display region transistor Tgip having the double gate (DG) structure, it is preferable to provide the gate driving bottom gate 116 and the gate driving active layer 113 It is preferable that the thickness or the cap ratio of the insulating film for gate driving and the thickness or the cap ratio of the gate driving insulating film 114 are close to 1. In the present invention, only the second buffer 103 among the first buffer 102 and the second buffer 103 is provided between the gate driving bottom gate 116 and the gate driving active layer 113 Therefore, the current driving capability of the non-display region transistor Tgip can be maximized.

In other words, the current of the transistor having the double gate (DG) structure is proportional to the sum of the capacitances of the insulating film between the active and top gates and the insulating film between the active and bottom gates. In particular, when the thickness of the insulating film between the active and top gates is equal to the thickness of the insulating film between the active and bottom gates, the current of the transistor having the double gate (DG) structure can be maximized. In this case, the thickness of the insulating film between the active and top gates may be less than or equal to the thickness of the insulating film between the active and bottom gates.

Therefore, in the present invention, the thickness of the insulating film 114 for gate pulse may be smaller than or equal to the thickness of the second buffer 103, and in particular, The current of the non-display region transistor Tgip can be maximized when the thickness of the non-display region transistor Tgip is equal to the thickness of the non-display region transistor Tgip.

In the driving transistor Tdr, the driving bottom gate 126 is provided to secure optical reliability. Therefore, the width of the driving bottom gate 126 may be formed to be at least 3 um larger than the width of the driving active layer 123.

However, the gate pulse bottom transistor 116 provided in the non-display region transistor Tgip is not related to the optical reliability, and is provided for increasing the capacitance and securing the current capability.

17, the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse may be 0 to 3 um.

18, the length of the non-display region transistor Tgip between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse ( The off-state capacitance of the non-display region transistor Tgip is increased as the pixel A is increased to 0, 1, 3, 5, 7, 11, and 13 um, Thereby reducing the performance of the display region transistor Tgip.

Therefore, in the present invention, the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse is preferably minimized, and may be 0 to 3 um .

In other words, the gate pulse is deteriorated by the load of the organic light emitting display panel 100, and the load of the organic light emitting display panel is again divided into a load in the non-display area and a load in the display area. . ≪ / RTI >

The load in the non-display region is generated by the superposition of the wirings and the off-state capacitance of the non-display region transistor Tgip.

In the non-display region transistor Tgip having a double gate (DG) structure, the bottom gate 116 for a gate pulse is formed larger than the active layer 113 for the gate pulse. In the non-display region transistor Tgip, in addition to the overlap capacitance caused by the overlap of the top gate 115 for the gate pulse and the first terminal 111 for the gate pulse or the second terminal 112 for the gate pulse, The overlap capacitance due to the overlap of the bottom gate 116 for the gate pulse and the first terminal 111 for the gate pulse or the second terminal 112 for the gate pulse is generated. And the load in the non-display area is increased by the overlap capacitances.

Therefore, the overlapping region of the bottom gate 116 for the gate pulse and the first terminal 111 or the second terminal 112 for the gate pulse and the overlapping region of the bottom gate 116 and gate The overlap region of the pulse top gate 115 is preferably minimized. The reduction of the overlap region does not affect the current magnitude of the non-display region transistor Tgip.

Therefore, the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse may be set to 0 to 3 mu m.

In other words, the non-display region transistor Tgip has the double gate structure in order to increase the magnitude of the current and output a normal gate pulse. However, in the double gate structure, the parasitic capacitance can be increased by overlapping the bottom gate 116 and the first terminal 111 for the gate pulse or the second terminal 112 for the gate pulse.

Therefore, in the double gate structure, as the length of the bottom gate 116 increases, the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse increases So that the off-state capacitance increases, as shown in Fig.

When the length A between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse is 0 to 3 um as a result of various simulations and tests, The capacitance of the non-display region transistor Tgip having the same structure as the capacitance of the non-display region transistor having the single gate (SG) structure becomes the same or similar.

That is, when the length A between the end of the gate pulse top gate 115 and the end of the gate pulse bottom gate 116 is 0 to 3 mu m, the non-display region transistor The size of the current of the non-display region transistor Tgip may be greater than the current of the non-display region transistor having the single gate structure, and the capacitance of the non-display region transistor Tgip may be larger than that of the non- It may have the same or similar value as the capacitance performance. In this case, the top gate 115 for a gate pulse may be formed in the first terminal 111 for the gate pulse or the second terminal 112 for the gate pulse ). The length in which the gate pulse top gate 115 and the first terminal 111 for a gate pulse or the second terminal 112 for a gate pulse are overlapped is determined by the degree of doping of the gate pulse active layer 113 And the interfacial effect, and the like.

Therefore, the length of the top gate 115 for the gate pulse and the length of the first terminal 111 for the gate pulse or the second terminal 112 for the gate pulse overlaps the length of the active layer 113 for the gate pulse The length (A) between the end of the top gate 115 for the gate pulse and the end of the bottom gate 116 for the gate pulse is set to 0 to 3 μm .

If the length A between the end of the gate pulse top gate 115 and the end of the gate pulse bottom gate 116 is greater than 0, And is projected further than the end of the top gate 115 for the gate pulse.

As described above, the gate driver 200 provided in the non-display area NAA includes transistors that perform various functions.

All the transistors constituting the gate driver 200 may be the non-display region transistor Tgip. Particularly, in each stage 210 of the gate driver 200, a gate pulse is connected between a terminal to which a gate clock is inputted and the switching top gate 135, and a gate pulse is transmitted to the switching top gate 135 And the pull-up transistor T3 may be the non-display region transistor Tgip.

To be more specific, since the pull-up transistor T3 is the largest in each stage 210, the width of the non-display region can be greatly reduced by reducing the size of the pull-up transistor T3. Accordingly, the pull-up transistor T3 may have the same structure as the non-display region transistor Tgip. In this case, the other transistors included in the gate driver 200 may have the same structure as the structure of any one of the non-display region transistor Tgip, the driving transistor Tdr, and the switching transistor Tswl have.

Second, the driving transistor Tdr has a contact structure in which the driving top gate 125 is electrically connected to the driving first terminal 121 or the driving second terminal 122 .

An organic light emitting transistor composed of an oxide semiconductor tends to be deteriorated by light. The light is light incident or reflected directly or indirectly from the inside and the outside of the organic light emitting display panel.

Constant current stress is generally generated in the driving transistor Tdr, and deterioration is increased when light is introduced. Therefore, the driving bottom gate 126, which performs a function of blocking light, must be provided in the driving transistor Tdr. In this case, the characteristics of the driving transistor Tdr when the driving bottom gate 126 is connected to either the driving first terminal 121 or the driving second terminal 122 is And is superior to the characteristics of the driving transistor Tdr when the driving bottom gate 126 is kept in a floating state. Therefore, the driving transistor Tdr has the contact structure.

In the driving transistor Tdr, the thickness of the insulating film between the driving bottom gate 126 and the driving active 123 is not related to the current of the driving transistor Tdr. Therefore, the first buffer 102 and the second buffer 103 may be provided between the driving bottom gate 126 and the driving active 123, and the thickness of the first buffer 102 Can be freely set so as to sufficiently cover the driving bottom gate 126.

In order to prevent the copper constituting the driving bottom gate 126 from moving to the driving active layer 123 in the driving transistor Tdr, the first buffer 102 is connected to the driving bottom gate (Not shown). In order to prevent the hydrogen constituting the first buffer 102 from moving to the driving active layer 123 and making the driving active layer 123 conductive, The second buffer 103 formed of SiO 2 is provided.

Third, the switching transistor Tsw1 has a single gate (SG) structure without a bottom gate.

The driving condition of the switching transistor Tsw1 is different from the driving condition of the driving transistor Tdr. In particular, the switching transistor Tswl is mainly driven by pulses. Therefore, even if the switching transistor Tsw1 is deteriorated by light, the characteristics of the signal output from the switching transistor Tsw1 do not change greatly.

Therefore, the switching transistor Tsw1 may have a single gate (SG) structure without a bottom gate.

However, the switching transistor Tsw1 is formed in the display region together with the driving transistor Tdr. Therefore, for convenience of the process, the switching transistor Tsw1 may further include a bottom gate.

Since the switching transistor Tsw1 does not have a bottom gate, only the second buffer 103 may be provided at the lower end of the switching transistor Tsw1, like the non-display region transistor Tgip. However, for the convenience of the process, the first buffer 102 and the second buffer 103 may be provided at the lower end of the switching transistor Tsw1 as shown in FIG.

Hereinafter, the development background of the present invention will be summarized again, and the features of the present invention will be briefly described.

The non-display region of the OLED display panel is provided with the gate driver of the gate-in-panel type, and a main factor of the area of the gate driver is the pull-up transistor T3. Conventionally, the pull-up transistor T3 is formed in a single gate (SG) structure. Since the single gate (SG) structure has a small capacitance and a low mobility, an active layer is formed using a material having high mobility, and a double gate (DG) structure has been developed. However, in the organic light emitting display panel having the pull-up transistor of the double gate (DG) structure, there has been a problem that the load increases and the window of the high mobility material is narrow.

Further, since the functions and characteristics of the driving transistor Tdr and the switching transistor Tsw1 provided in the display region of the organic light emitting display panel and the non-display region transistor Tgip provided in the non-display region are different from each other, Are formed in the same structure, the characteristics of each transistor are hardly satisfied.

Accordingly, in the organic light emitting display panel according to the present invention, the driving transistor Tdr, the switching transistor Tsw1, and the non-display region transistor Tgip are formed in different structures.

Specific features of the present invention are as follows.

First, in the present invention, the bottom gate 126 for driving the driving transistor Tdr and the bottom gate 116 for gate pulse of the non-display region transistor Tgip are provided in the same layer, . Particularly, although the driving bottom gate 126 is composed of two layers, the bottom gate for gate pulse 116 is formed of any one of two layers constituting the driving bottom gate 126.

In the present invention, two buffers 102 and 103 are provided between the driving bottom gate 126 and the driving active layer 123. However, Only one of the two buffers 102 and 103 is provided between the active layer 113 for the gate pulse and the active layer 113 for the gate pulse. The first buffer 102 and the second buffer 103 may be provided below the switching active layer 133 of the switching transistor Tsw1. Only one of the second buffers 103 may be provided.

Third, in the present invention, in order to minimize the load of the non-display region transistor Tgip, the length between the end of the gate pulse top gate 115 and the end of the gate pulse bottom gate 116 is 0 to Lt; / RTI > That is, the end of the bottom gate 116 for gate pulse is more protruded than the end of the top gate 115 for the gate pulse, or coincides with the end of the top gate for the gate pulse.

In the present invention having such characteristics as described above, the element characteristics, the capacitance component, the processing element, and the gate pulse bottom gate 116 and the gate pulse for the non-display region transistor Tgip having the double gate (DG) The organic light emitting display panel 100 is manufactured in consideration of the size of the overlapping region between the top gate 115 and the like. Therefore, while the performance of the non-display region transistor Tgip is maximized, the size of the non-display region transistor Tgip can be reduced, whereby the width of the non-display region NAA can be reduced.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: organic light emitting display panel 110: pixel
200: gate driver 300: data driver
400:

Claims (10)

A substrate disposed on a periphery of the display region and divided into a non-display region in which a gate driver is embedded;
An organic light emitting diode included in a pixel included in the display region;
A driving transistor provided in the pixel and including a driving bottom gate, a driving active layer, and a driving top gate, the driving transistor being connected to the organic light emitting diode;
A switching transistor provided in the pixel and including a switching active layer and a switching gate, the switching transistor being connected to the driving top gate; And
A non-display region transistor which is provided in the non-display region to constitute the gate driver and includes a bottom gate for a gate pulse, an active layer for a gate pulse and a top gate for a gate pulse, Lt; / RTI >
A first buffer provided on the substrate and a second buffer provided on the first buffer are provided between the driving bottom gate and the driving active layer,
And the second buffer is provided between the bottom gate for gate pulse and the active layer for gate pulse. The method according to claim 1,
Wherein the material constituting the first buffer and the material constituting the second buffer are different from each other. The method according to claim 1,
Wherein the driving bottom gate comprises:
A first metal provided on the substrate and formed of a first metal material; And
A second metal disposed on the first metal and formed of a second metal material,
Wherein the bottom gate for the gate pulse is formed of the first metal material. The method according to claim 1,
And the first buffer and the second buffer are provided between the switching active layer and the substrate. The method according to claim 1,
And the second buffer is provided between the switching active layer and the substrate. The method according to claim 1,
And the length between the end of the top gate for the gate pulse and the end of the bottom gate for the gate pulse is 0 to 3 um. The method according to claim 1,
Wherein the non-display region transistor is a pull-up transistor connected between a terminal for inputting a gate clock used as a gate pulse and the switching top gate, and for transmitting a gate pulse to the switching top gate. The method according to claim 1,
The driving bottom gate is connected to a source or a drain constituting the driving transistor,
And the bottom gate for the gate pulse is connected to the top gate for the gate pulse. The method according to claim 1,
Wherein the driving transistor, the switching transistor, and the non-display region transistor are formed of an oxide semiconductor. An organic light emitting display panel according to claim 1;
A data driver for supplying data voltages to the data lines of the OLED display panel; And
And a control unit controlling the data driver and the gate driver.

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