KR20190061056A - Floating point instruction with selectable comparison properties - Google Patents

Abstract

Floating point instruction with selectable comparison properties
One instruction to perform a comparison of the first value and the second value is executed.
Based on one control of the instruction, a compare function to be performed is determined. The comparison function is one of a plurality of comparison functions configured for the instruction and the comparison function has a plurality of options for comparison. Wherein a comparison option based on the first value and the second value is selected from the plurality of options defined for the comparison function and wherein the comparison of the first value with the second value Is used. A result of the comparison is placed at the next selected location and the result is used for processing in the computing environment.

Description

Floating point instruction with selectable comparison properties

[0001] One or more embodiments of the present invention generally relate to processing within a computing environment, and in particular, to improving such processing.

[0002] In computing, floating point numbers are used to represent real numbers, and there are a number of representations used for floating point numbers. These representations include indications of how certain operations are to be handled with floating-point numbers. For example, the Institute of Electrical and Electronics Engineers (IEEE) provides a floating-point standard that specifies the behavior for minimum and maximum operations on floating-point numbers.

Although these standards exist, many programming languages and programmers have not followed these standards. Thus, there were many different standards and expressions within their libraries between different programming languages. Even within a language, it was the common convention to use a different language syntax that yields differing behavior, rather than using a library function. This has made it difficult to speed up these operations in hard air, and often requires a sequence of many instructions, including several conditional branches, to emulate.

[0004] The disadvantages of the prior art are overcome and additional advantages are provided through the provision of a computer program product for facilitating processing in a computing environment as claimed in claim 1.

[0005] The number of instructions used to perform comparison operations on other standards and / or representations has been reduced, thereby improving processing within the computing environment.

[0006] In one example, the plurality of options includes a plurality of pairs of selectable selectable cases for comparison. The particular cases of the plurality of pairs include at least one specific case selected from the group of specific cases, including an infinity, a not-a-number (NAN), and a signed zero And at least one pair of specific cases.

[0007] Also, in one example, the plurality of compare functions includes at least one of a plurality of maximum functions and a plurality of minimum functions. Wherein the plurality of maximum functions comprise a plurality of maximum techniques to perform a maximum comparison and the plurality of minimum functions are selected from a plurality of minimum values to perform a minimum comparison, Techniques. ≪ / RTI >

[0008] As examples, the first value and the second value are provided by the instruction, the first value has one element of one operand of the instruction, and the second value is And a corresponding element of another operand of the instruction.

[0009] Further, in one example, the size of the element is determined based on another control of the instruction. Also, by way of example, the first value and the second value are floating point values, and the size of the element is dependent on the floating-point format of the floating-point values. The other control indicates one selected floating-point format.

[0010] In one example, the control is provided in a mask field of the instruction.

[0011] Methods and systems related to one or more embodiments of the invention are also described herein and claimed. Also, services related to one or more embodiments of the present invention are also described herein and claimed.

[0012] Additional features and advantages are realized through the techniques described herein. Other embodiments are described in detail herein and are considered a part of the claims.

[0013] One or more embodiments of the present invention are specifically described and specifically claimed as examples in the claims at the end of this specification. The foregoing objects, features and advantages of one or more embodiments of the present invention are apparent from the following detailed description, taken in conjunction with the accompanying drawings.
Figure 1A illustrates an example of a computing environment for embodying and using one or more embodiments of the present invention;
Figure 1b shows additional details of the processor of Figure Ia, according to one embodiment of the present invention;
Figure 2a illustrates another example of a computing environment for embodying and using one or more embodiments of the present invention;
Figure 2b shows further details of the memory of Figure 2a;
Figure 3A illustrates an example of a Vector Floating Point Maximum instruction, according to one embodiment of the present invention;
Figure 3b illustrates one embodiment of a mask field of the vector floating point maximum instruction of Figure 3a according to one embodiment of the present invention;
Figure 3c illustrates an example of a Vector Floating Point Minimum instruction, according to one embodiment of the present invention;
FIG. 3D illustrates an example of a vector floating point maximum / minimum instruction, in accordance with one embodiment of the present invention;
Figures 4A-4T illustrate tables of comparison options of certain comparison functions, in accordance with embodiments of the present invention;
5 illustrates an example of a block diagram of processing associated with executing a vector floating-point maximum and / or minimum instruction, in accordance with one embodiment of the present invention.
6A-6B illustrate an example of facilitating processing in a computing environment, including the execution of vector floating-point min / max instructions, in accordance with an embodiment of the invention;
Figure 7 illustrates one embodiment of a cloud computing environment; And
Figure 8 shows an example of abstraction model layers.

[0014] One or more embodiments of the invention relate to improving processing within a computing environment by reducing multiple instructions to perform floating point maximum and minimum operations different from the standards and / or expressions. As mentioned herein, there are a number of different standards and expressions for floating point numbers among various programming languages. Even within a single language, the common convention may use some other language syntax that does not use a library function, but rather different processing. Some of the other aspects of the comparisons (i.e., special or specific cases) may be considered to consider a greater +0 than -0, or they will be considered equal, NaNs (not numbers) -Number), how to handle an exception to the SNaN (signaling NaN) (signaling NaN), how to handle the infinity, if all of the inputs are NaNs (NaN payload) has priority, and whether to convert the SNaN to a QNaN (quiet NaN) in the result.

[0015] Other floating-point maximum and minimum instructions have been developed over the years; However, these instructions do not capture all of the permutations for special cases for different expressions. Instead, for each of the maximum and minimum operations, a number of instructions including other permutations Lt; / RTI > Thus, in accordance with one embodiment of the present invention, a single instruction (e.g., a single architectured machine instruction in a hardware / software interface) is provided, which includes various minimum functions , Each of which processes various options to cover a large number of permutations. By using these two instructions to cover other permutations for maximum and minimum, the number of instructions for processing the permutations is reduced, thereby improving processing and performance.

[0016] In a further embodiment, a single instruction (eg, a single architectured machine instruction at the hardware / software level) is provided that supports various functions of the maximum and minimum operations and other options. By providing a single instruction for handling different permutations for both the maximum and minimum operations, the number of required instructions is further reduced to one instruction, thereby reducing the number of instructions to be encoded, .

[0017] One embodiment of a computing environment for implementing and using one or more embodiments of the invention is described with reference to FIG. In one example, the computing environment is based on z / architecture, which is supplied by International Business Machines Corporation, Armonk, NY, USA. One embodiment of the z / architecture is disclosed in IBM publication no. It is described in "z / Architecture Architecture Principles" of SA22-7832-10. Z / ARCHITECTURE is a registered trademark of International Business Machines Corporation, Armonk, NY, USA.

[0018] In another example, the computing environment is based on Power Architecture, which is supplied by International Business Machines Corporation, Ammonk, NY, USA. One embodiment of the Faure architecture is described in International Business Machines Corporation, " Power ISA (TM) Version 2.07B, " issued April 9, POWER ARCHITECTURE is a registered trademark of International Business Machines Corporation, Armonk, NY, USA.

[0019] The computing environment may also be based on other architectures including, but not limited to, the Intel x86 architecture. Other examples also exist.

1A, a computing environment 100 includes, for example, a node 10, which may include, for example, a number of other general purpose or special purpose computing system environments / RTI > computer system / server 12, which is operable with a computer system / server or configurations. Examples of well known computing systems, environments, and / or configurations that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients , Thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems , Distributed cloud computing environments that include any of the above systems or devices, and the like.

[0021] The computer system / server 12 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types . ≪ / RTI > The computer system / server 12 may be embodied in many computing environments including, but not limited to, distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0022] As shown in FIG. 1A, a computer system / server 12 is shown in the form of a general purpose computing device. The components of computer system / server 12 may include one or more processors or processing units 16, a system memory 28, and various system components including system memory 28, Bus 18, but is not limited thereto.

[0023] The bus 18 may be a processor using either a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and various types of bus architectures, or a local Bus, < / RTI > and the like. For example, these architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect But is not limited thereto.

[0024] Computer system / server 12 generally includes a variety of computer system readable media. Such media can be any available media that is accessible by computer system / server 12 and includes both volatile and non-volatile media, removable and non-removable media.

[0025] System memory 28 may include a computer system readable medium in the form of volatile memory, such as RAM 30 and / or cache memory 32. The computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be provided for reading from and writing to non-removable, nonvolatile magnetic media (not shown and generally referred to as a " hard drive "). Although not shown, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and a magnetic disk drive for reading from and writing to a CD- An optical disk drive for reading from or writing to a removable, nonvolatile optical disk, such as the optical disk drive, may be provided. In such cases, each may be connected to the bus 18 by one or more data media interfaces. As described below, the memory 28 may include at least one program product having a set of program modules (e.g., at least one) configured to perform the functions of the embodiments of the present invention.

[0026] Program / utility 40, having a set of (at least one) program modules 42, may be stored in memory 28, examples of which include operating systems as well as one or more application programs But are not limited to, program modules, program modules, and program data. An operating system, one or more application programs, other program modules, and program data, or a combination thereof, each may comprise an implementation of a networking environment. Program modules 42 generally perform the functions and / or methods of embodiments of the present invention as described herein.

[0027] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, and the like. These external devices 14 include one or more devices that allow a user to interact with the computer system / server 12; And / or any device (e.g., a network card, modem, etc.) that allows the computer system / server 12 to communicate with one or more other computing devices. Communication takes place via input / output (I / O) interfaces 22. The computer system / server 12 may also communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN) and / or a public network (e.g., the Internet) Communication can be performed. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. Although not shown, it should be understood that other hardware and / or software components may be used with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives and data archive storage devices.

[0028] For example, the processor 16 includes a plurality of functional components used to execute instructions. As shown in FIG. 1B, these functional components include, for example, an instruction fetch component 120 for fetching instructions to be executed; An instruction decode unit (122) for decoding the fetched instructions and obtaining operands of the decoded instructions; Instruction execution components (124) for executing decoded instructions; A memory access component 126 for accessing the memory for instruction execution, if necessary; And a writeback component 130 for providing the results of the executed instructions. One or more of these components may be implemented as floating point maximum / minimum operations with selectable options with selectable options, as described further below, in accordance with an embodiment of the present invention. Lt; RTI ID = 0.0 > 136 < / RTI >

[0029] The processor 16 also includes, in one embodiment, one or more registers 140 to be used by one or more functional components.

[0030] Another embodiment of a computing environment for implementing and using one or more embodiments is described with reference to FIG. 2A. In this example, computing environment 200 may include, for example, a central processing unit (CPU) 202, a memory 204, and, for example, one or more busses 208 and / One or more input / output devices and / or interfaces 206 coupled to each other. By way of example, computing environment 200 may include a PowerPC processor or pSeries server supplied by International Business Machines Corporation, Armonk, New York, USA; HP Superdome with Intel Itanium II processor from Hewlett Packard Co., Palo Alto, CA; And / or other machines based on architectures supplied by International Business Machines Corporation, Hewlett Packard, Intel, Oracle, or other companies.

[0031] Native central processing unit 202 includes one or more general registers and / or one or more native registers 210, such as one or more special purpose registers used during processing within the environment do. These registers contain information indicating the environmental condition at a particular point in time.

[0032] Further, the native central processing unit 202 executes the instructions and code stored in the memory 204. In one particular example, the central processing unit executes emulator code 212 stored in memory 204. This code allows a computing environment configured in one architecture to emulate a different architecture. For example, the emulator code 212 may be used by machines based on architectures other than z / architecture, such as PowerPC processors, pSeries servers, HP Superdome servers, or other servers emulating z / And to execute software and instructions developed on an architecture basis.

[0033] A more detailed description of the emulator code 212 is described with reference to Figure 2b. The guest instructions 250 stored in the memory 204 include software instructions (e.g., related to machine instructions) that are developed to execute on an architecture other than the architecture of the native CPU 202. For example, guest instructions 250 may be emulated on native CPU 202, which is designed to run on z / architecture processor, but is, for example, an Intel Itanium II processor. In one example, the emulator code 212 includes an instruction fetch routine 252 for obtaining one or more guest instructions 250 from the memory 204 and optionally providing local buffering for the obtained instructions do. And a command conversion routine 254 for determining the type of the acquired guest command and converting the guest command to one or more corresponding native commands 256. [ This conversion includes, for example, identifying the function to be performed by the guest command and selecting the native command (s) to perform the function.

[0034] Also, the emulator 212 includes an emulation control routine 260 that allows native instructions to be executed. The emulation control routine 260 causes the native CPU 202 to execute the routine of native instructions emulating one or more previously obtained guest instructions and at the end of such execution the next guest instruction or group of And return control to the instruction fetch routine to emulate acquiring guest instructions. Execution of native instructions 256 may include loading data from memory 204 into a register; Storing the data from the register back into the memory; Or performing any type of arithmetic or logical operation as determined by the conversion routine.

[0035] Each routine is implemented, for example, in software, and the software is stored in memory and executed by the native central processing unit 202. In other instances, one or more routines or operations are implemented in firmware, hardware, software, or a combination thereof. The registers of the emulated processor may be emulated using the registers 210 of the native CPU or using locations within the memory 204. [ In embodiments, guest instructions 250, native instructions 256 and emulator code 212 may reside within the same memory or be distributed among different memories.

[0036] As used herein, firmware includes, for example, microcode, millicode, and / or macrocode of a processor. The firmware includes, for example, the hardware-level instructions and / or the data structures used in the implementation of higher-level machine code. In one embodiment, the firmware includes, for example, a proprietary code, which is typically delivered in microcode, and may be trusted software specific to the underlying hardware It contains microcode and controls operating system access to system hardware.

The guest instruction 250 to be acquired, transformed and executed may be, for example, a Vector Floating Point Maximum instruction, a Vector Floating Point Minimum instruction, / Or a Vector Floating Point Maximum / Minimum instruction, which is described below. The instruction has one architecture (e.g., z / Architecture) and is fetched from memory and translated into a sequence of native instructions 256 of another architecture (e.g., PowerPC, pSeries, Intel, etc.). These native instructions are then executed.

[0038] The instructions, including the vector floating-point maximum instruction, the vector floating-point minimum instruction, and the fields of the vector floating-point maximum / minimum instruction and execution by one processor (native or emulated system wherever) A vector floating point maximum instruction may be used to perform comparisons of values to determine a larger value of the plurality of values and to perform a plurality of special comparison < RTI ID = 0.0 > Processes a plurality of special comparison cases (also referred to below as specific cases). By using a single instruction (e.g., a single architectured machine instruction) that handles multiple special cases in maximum comparisons, the number of instructions needed to handle special cases for maximum comparisons is reduced to one ; Thus improving computer processing.

[0039] Similarly, the vector floating-point minimum instruction performs comparisons of values to determine fewer of the plurality of values and processes a plurality of special comparison cases. By using a single instruction (e. G., A single < / RTI > architectured machine instruction) that handles multiple special cases in minimal comparisons, the number of instructions needed to handle special cases for minimum comparisons is reduced to one ; Thus improving computer processing.

Also, the vector floating-point maximum / minimum instruction may perform comparisons of values to determine a larger / smaller value of the plurality of values, respectively, and each of a plurality of special comparison cases comparison cases. By using a single instruction (e.g., a single architectured machine instruction), reducing the number of instructions required to process other permutations to one; Thus improving computer processing. Embodiments of the present invention are expressly associated with computer technology and relate to improvements in computer processing.

[0041] In one embodiment, one or more of the vector floating-point maximum instruction, the vector floating-point minimum instruction, and the vector floating-point maximum / minimum instruction may be, for example, a fixed size Which is a part of a vector facility that provides fixed sized vectors ranging from one to sixteen elements. Each vector includes data computed by vector instructions defined in the facility. In one embodiment, if the vector consists of multiple elements, each element is processed in parallel with the other elements. Command completion does not occur until processing of all elements is completed. In other embodiments, the elements are partially processed in parallel and / or sequentially.

Vector instructions may be implemented as part of various architectures, including, but not limited to z / Architecture, Power Architecture, x86, IA-32, IA-64 and the like. While the embodiments described herein are for z / Architecture, the vector instructions and one or more other embodiments described herein may be based on many different architectures. z / Architecture is just one example.

[0043] In one embodiment, in which the vector facility is implemented as part of z / Architecture, vector enablement control (a) in an explicit control register (e.g., control register 0) vector enablement control and register control are set, for example, to one. If the vector facility is installed and the vector instruction is executed without the enablement controls being set, a data exception is recognized. If the vector facility is not installed and the vector instruction is executed, an operation exception is recognized.

[0044] In one embodiment, the vector registers are 32 and other types of registers may be mapped to a quadrant of the vector registers. For example, a register file may contain 32 vector registers and each register may have a length of 128 bits. Sixteen floating point registers, of length 64 bits, may overlay the vector registers. Thus, as an example, if the floating-point register 2 is modified, the vector register 2 is also modified. Other mappings for other types of registers are also possible.

 [0045] The vector data is stored in, for example, storage in the same left-to-right sequence as the other data formats. The bits in the data format numbered 0-7 constitute the byte at the leftmost (lowest numbered) byte position in the store, and bits 8-15 form the byte at the next sequential position. In another example, the vector data may be stored in the repository in a different order, such as from right to left.

[0046] An example of a Vector Floating Point Maximum instruction is described with reference to FIG. As shown, the instruction may have a plurality of fields, and one field may have a subscript number associated with it. The subscript number associated with the field of the instruction indicates the operand that the field specifies. For example, the subscript number associated with the vector register V ₁ indicates that the register in V ₁ contains the first operand. A register operand has a register length of, for example, 128 bits.

[0047] Referring to FIG. 3A, in one embodiment, a Vector Floating Point Maximum instruction 300 includes opcode fields 302a and 302b indicating a vector floating point maximum operation; A first vector register field 304 used to specify a first vector register V ₁ ; A second vector register field 306 used to specify a second vector register V ₂ ; A third vector register field 308 used to specify a third vector register V ₃ ; A first mask field (M ₆ ) 309; A second mask field (M ₅₎ (310); The third mask field (M ₄₎ (312); And a register extension bit (RXB) field 314, each of which will be described later. In one embodiment, the fields are separate from each other and independent of each other. However, in other embodiments, one or more fields may be combined. Additional information on these fields is described below.

[0048] The vector register field 304 is used to indicate a vector register to store the first operand, which compares the values of the elements of both operands to obtain the larger of the two values of the elements It is the result of something. The operand elements are treated, for example, as (IEEE) binary floating point (BFP) numbers in the specified format. The two operands are the third operand contained in the specified vector register using the vector register field 306 and the third operand contained in the vector register specified using the vector register field 308. [ In one example, each of the vector register fields 304, 306, 308 is used with the RXB field 314 to specify the vector register.

[0049] For example, the RXB field 314 includes a most significant bit for a vector register designated operand. The bits for the register assignments not specified by the instruction are reserved and set to zero. The most significant bit is concatenated to the left of the 4-bit register designation of the vector register field, for example, to generate a 5-bit vector register designation.

[0050] In one example, the RXB field includes 4 bits (e.g., bits 0-3), and the bits are defined as follows:

0 - the most significant bit for the first vector register designation (eg, in bits 8-11) of the instruction.

1 - Most significant bit for the second vector register designation (eg, in bits 12-15) of the instruction, if any.

2 - The most significant bit for the third vector register designation (eg, in bits 16-19) of the instruction, if any.

3 - Most significant bit for the fourth vector register designation (eg, in bits 32-35) of the instruction, if any.

[0055] Each bit is set to 0 or 1, for example, by the assembler according to the register number. For example, for registers 0-15, the bit is set to zero, and for registers 16-31, the bit is set to one.

[0056] In one embodiment, each RXB bit is an extension bit for a particular position in the instruction that includes one or more vector registers. For example, bit 0 of RXB, for example, an extension bit for the, it positions 8-11 is assigned to V _1. In particular, for vector registers, the register containing the operand is specified using a 4-bit field of the register field, for example, which has its corresponding register extension bit (RXB) added to the most significant bit. For example, if the 4-bit field is 0110 and the extension bit is 0, the 5-bit field 00110 indicates register number 6. In another embodiment, the RXB field contains additional bits, and one or more bits are used as an extension to each vector or location.

[0057] The M ₆ field 309 specifies the handling of special cases (also referred to herein as specific cases) for comparison. A detailed description of the results for each element is shown in Figures 4A-4J. In one example, if a reserved value is specified, a specification exception is recognized,

[0058] M ₆ Maximum Function Performed [0058]

[0059] IEEE MaxNum

[0060] 1 Java Math.Max ()

[0061] 2 C-Style Max Macro

[0062] 3 C ++ Algorithm.max ()

[0063] 4 fmax ()

[0064] 5-7 Reserved

[0065] 8 IEEE MaxNumMag

[0066] 9 Absolute values of Java Math.Max ()

[0067] 10 Absolute values of C-Style Max Macro

[0068] C ++ Algorithm.max () of absolute values

[0069] The absolute values of fmax ()

[0070] 13-15 Reserved

[0071] The M ₄ field 312 specifies the floating-point format. The floating point format determines the size of the elements in the vector register operands. In one example, if the reserved value is specified, the specification exception is recognized.

[0072] M4 Floating Point Format

0-1  Reserved

[0074] 2 Short format

[0075] 3 Long format

[0076] 4 Extended format

[0077] 5-15 Reserved

[0078] The M ₅ field 310, in one example, includes the following controls, as shown in FIG. 3b.

Single Element Control (S) 316: If bit 0 is set to 1, the operation only occurs with respect to the zero-indexed element in the vector. In the example, in the absence of a trapping exception condition, the bit positions of all other elements in the first operand vector are unpredictable. The values of all other elements in the second and third operands are ignored. If bit 0 is set to 0, the operation occurs on all elements in the vector.

Reserved: Bits 1, 2, and 3 are reserved and become zero. Otherwise, in one example, a specification exception is recognized.

[0081] While various fields and registers have been described, one or more embodiments of the present invention may utilize other, additional, or fewer number of fields or registers, or other sizes of fields or registers, Can be used. Many variations are possible. For example, implied registers may be used in place of explicitly stated registers or fields of the instruction. In addition, registers other than vector registers may be used. In other words, other variations are also possible.

[0082] In an operation of one embodiment of the vector floating-point maximum instruction, the floating-point elements or elements of the second operand are compared against corresponding floating-point elements or elements of the third operand, as shown in Figures 4A-4J . The larger of the two values is placed in the corresponding element of the first operand. The operand elements are all treated as BFP numbers in the specified format.

[0083] The comparison made and the results thereof are determined according to the comparison options for the specific comparison function to be performed and the selected comparison function (denoted by M ₆ , for example). One comparison option For example, -∞, + ∞, -FN, + FN, -0, +0, QNAN, SNAN, where FN is a finite number) 2 and the third operand elements. Each comparison function may have other comparison options associated with it, and the result for one comparison option is determined according to the particular comparison function being performed. Different results can be specified for the same comparison options for different comparison functions. For example, if M ₆ = 0 and the compared second and third operand values are -0, +0, the result is +0 (see FIG. 4A); However, if M ₆ = 3 and the second and third operand values are still -0, +0, the result is -0 (see FIG. 4D). Many variations are possible.

[0084] In one embodiment, depending on the maximum function performed, if one or more of the floating-point elements in the second or third operand is NaNs, then an IEEE invalid-operation exception an IEEE invalid-operation exception may be acknowledged. If the IEEE invalid-operation mask bit is 1, then in one example, a program interruption with VXC set for IEEE invalid-operation and a corresponding element index occur and the operation is aborted.

[0085] In a further embodiment, one field of the instruction (eg, an explicit field of the instruction, such as M ₆ or another selected field, or an implied field of the instruction) contains a plurality of bits , And each bit is a selector that defines another comparison option when set (for example, 1). For example, bit 0 indicates that a sign will be ignored when set; Bit 1 indicates to signal about SNAN when set; Bit 2, when set, indicates which value to select, for example, +0, -0; Bit 3, when set, indicates which value to select, for example, ∞, -FN. Many different options can be represented by different bits. By having different bits corresponding to different options, one or more bits can be set to provide many different comparison options and results using a single instruction.

[0086] In a further embodiment, a Vector Floating Point Minimum instruction is provided and described with reference to FIG. 3c. In one embodiment, the vector floating-point minimum instruction 320 includes an opcode field 322a, 322b indicating a vector floating-point minimum operation; A first vector register field 324 used to specify a first vector register V ₁ ; A second vector register field 326 used to designate a second vector register (V ₂ ); A third vector register field 328 used to specify the vector register 3 (V _3); A first mask field (M ₆ ) 329; A second mask field (M ₅₎ (330); A third mask field (M ₄ ) 332; And a register extension bit (RXB) field 334, each of which will be described later. In one embodiment, the fields are separate from each other and independent of each other; However, in other embodiments, one or more fields may be combined. Additional information on these fields is described below.

[0087] The vector register field 324 is used to indicate the vector register to store the first operand, which compares the values of the elements of the two operands to obtain the smaller of the two values of the elements It is the result of something. The operand elements are treated as, for example, binary floating point numbers in the specified format. The two operands are the third operand contained in the specified vector register using the vector register field 326 and the third operand contained in the vector register specified using the vector register field 328. [ In one example, each of the vector register fields 324, 326, 328 is used with the RXB field 334 to specify the vector register, as described above.

[0088] The M ₆ field 329 specifies the handling of special cases (also referred to herein as specific cases) for comparison. A detailed description of the results for each element is shown in Figures 4k-4t. In one example, if a reserved value is specified, a specification exception is recognized,

[0089] M ₆ Minimum Function Performed [0089]

[0090] IEEE MinNum

[0091] 1 Java Math.Min ()

[0092] 2 C-Style Min Macro

[0093] 3 C ++ Algorithm.min ()

[0094] 4 fmin ()

[0095] 5-7 Reserved

[0096] 8 IEEE MinNum of absolute values

[0097] 9 Absolute values of Java Math.Min ()

[0098] 10 Absolute values of C-Style Min Macro

[0099] C ++ Algorithm.min () of absolute values

[00100] 12 The absolute values of fmin ()

[00101] 13-15 Reserved

[00102] The M ₄ field 332 specifies the floating-point format. The floating point format determines the size of the elements in the vector register operands. In one example, if the reserved value is specified, the specification exception is recognized.

[00103] M4 Floating Point Format

[00104] 0-1  Reserved

[00105] 2 Short format

[00106] 3 Long format

[00107] 4 Extended format

[00108] 5-15 Reserved

[00109] M ₅ field 330, in one example, as shown in Figure 3b, comprises the following control.

[00110] Single Element Control (S) 316: If bit 0 is set to 1, the operation only occurs with respect to the zero-indexed element in the vector. In the example, in the absence of a trapping exception condition, the bit positions of all other elements in the first operand vector are unpredictable. The values of all other elements in the second and third operands are ignored. If bit 0 is set to 0, the operation occurs on all elements in the vector.

[00111] While various fields and registers have been described, one or more embodiments of the present invention may utilize other, additional, or fewer number of fields or registers, or other sizes of fields or registers, Can be used. Many variations are possible. For example, implied registers may be used in place of explicitly stated registers or fields of the instruction. In addition, registers other than vector registers may be used. In other words, other variations are also possible.

[00112] In an operation of one embodiment of the vector floating-point minimum instruction, the floating-point elements or elements of the second operand are compared against corresponding floating-point elements or elements of the third operand. The smaller of the two values is placed in the corresponding element of the first operand. The operand elements are all treated as BFP numbers in the specified format.

[00113] The comparison made and the results thereof are determined according to the comparison options for the particular comparison function being performed with the selected comparison function (denoted by, for example, M ₆ ). One comparison option For example, -∞, + ∞, -FN, + FN, -0, +0, QNAN, SNAN, where FN is a finite number) 2 and the third operand elements. Each comparison function may have other comparison options associated therewith, and the result for one comparison option is determined according to the particular comparison function being performed. Different results can be specified for the same comparison options for different comparison functions.

[00114] In one embodiment, depending on the minimal function performed, if one or more of the floating-point elements in the second or third operand is NaNs, then an IEEE invalid-operation exception an IEEE invalid-operation exception may be acknowledged. If the IEEE invalid-operation mask bit is 1, then in one example, a program interruption with VXC set for IEEE invalid-operation and a corresponding element index occur and the operation is aborted.

[00115] In a further embodiment, one instruction may be provided, wherein the maximum / minimum is, for example, one selectable control of the instruction. An example of a Vector Floating Point Maximum / Minimum instruction 350 is described with reference to FIG. 3D. In one embodiment, vector floating-point maximum / minimum command 350 includes opcode fields 352a and 352b indicating vector floating-point maximum / minimum operations; A first vector register field 354 used to specify a first vector register V ₁ ; A second vector register field 356 used to specify a second vector register V ₂ ; A third vector register field 358 used to specify the vector register 3 (V _3); A first mask field (M ₆ ) 359; A second mask field (M ₅₎ (360); The third mask field (M ₄₎ (362); And a register extension bit (RXB) field 364, each of which will be described later. In one embodiment, the fields are separate from each other and independent of each other; However, in other embodiments, one or more fields may be combined. Additional information on these fields is described below.

[00116] The vector register field 354 is used to indicate a vector register to store a first operand, the first operand being a larger / smaller one of the two values of the elements, depending on whether the selected function is a maximum or a minimum Is the result of comparing the values of the elements of both operands to obtain a value. The operand elements are treated as, for example, binary floating point numbers in the specified format. The two operands are the third operand included in the specified vector register using the vector register field 356 and the third operand contained in the vector register specified using the vector register field 358. [ In one example, each of the vector register fields 354, 356, 358 is used with the RXB field 364 to specify the vector register, as described above.

[00117] The M ₆ field 359 specifies the handling of special cases (also referred to herein as specific cases) for comparison. A detailed description of the results for each element is shown in Figures 4a-4t. In one example, if a reserved value is specified, a specification exception is recognized. The function to be performed is determined depending on whether the maximum or minimum operation is performed, as well as the respective M ₆ values below.

[00118] M ₆ Function Performed

[00119] 0 IEEE MaxNum

[00120] 0 IEEE MinNum

[00121] 1 Java Math.Max ()

[00122] 1 Java Math.Min ()

[00123] 2 C-Style Max Macro

[00124] 2 C-Style Min Macro

[00125] 3 C ++ Algorithm.max ()

[00126] 3 C ++ Algorithm.min ()

[00127] 4 fmax ()

[00128] 4 fmin ()

[00129] 5-7 Reserved

[00130] 5-7 Reserved

[00131] 8 IEEE MinNumMag

[00132] 8 IEEE MinNum of absolute values

[00133] 9 Absolute values of Java Math.Max ()

[00134] 9 Absolute values of Java Math.Min ()

[00135] 10 Absolute values of C-Style Max Macro

[00136] 10 Absolute values of C-Style Min Macro

[00137] 11 C ++ Algorithm.max () of absolute values

[00138] 11 C ++ Algorithm.min () of absolute values

[00139] 12 The absolute values of fmax ()

[00140] 12 The absolute values of fmin ()

[00141] 13-15 Reserved

[00142] 13-15 Reserved

[00143] In a further embodiment, there may be separate numbers for each maximum / minimum function supported.

[00144] The M ₄ field 362 specifies the floating-point format. The floating point format determines the size of the elements in the vector register operands. In one example, if the reserved value is specified, the specification exception is recognized.

[00145] M4 Floating Point Format

[00146] 0-1  Reserved

[00147] 2 Short format

[00148] 3 Long format

[00149] 4 Extended format

[00150] 5-15 Reserved

[00151] The M ₅ field 360, in one example, includes the following controls, as shown in FIG. 3B.

Single Element Control (S) 316: If bit 0 is set to 1, the operation only occurs with respect to the zero-indexed element in the vector. In the example, in the absence of a trapping exception condition, the bit positions of all other elements in the first operand vector are unpredictable. The values of all other elements in the second and third operands are ignored. If bit 0 is set to 0, the operation occurs on all elements in the vector.

[00153] While various fields and registers have been described, one or more embodiments of the present invention may utilize other, additional, or fewer number of fields or registers, or other sizes of fields or registers, Can be used. Many variations are possible. For example, implied registers may be used in place of explicitly stated registers or fields of the instruction. In addition, registers other than vector registers may be used. In other words, other variations are also possible.

[00154] In an operation of one embodiment of the vector floating-point maximum / minimum instruction, the floating-point element or elements of the second operand are compared against corresponding floating-point elements or elements of the third operand. Depending on whether the maximum or minimum function is being performed, a larger or smaller value of the two values is placed in the corresponding element of the first operand. The operand elements are all treated as BFP numbers in the specified format.

[00155] The comparison made and the results thereof are determined according to the comparison options for the particular comparison function being performed with the selected comparison function (denoted by, for example, M ₆ ). One comparison option For example, -∞, + ∞, -FN, + FN, -0, +0, QNAN, SNAN, where FN is a finite number) 2 and the third operand elements. Each comparison function may have other comparison options associated therewith, and the result for one comparison option is determined according to the particular comparison function being performed.

[00156] In one embodiment, depending on the function performed, if one or more of the floating-point elements in the second or third operand is NaNs, then an IEEE invalid-operation exception ( an IEEE invalid-operation exception may be acknowledged. If the IEEE invalid-operation mask bit is 1, then in one example, a program interruption with VXC set for IEEE invalid-operation and a corresponding element index occur and the operation is aborted.

[00157] Further details regarding the operation of the vector floating point maximum, minimum and / or maximum / minimum instructions are described with reference to FIG. In one example, the processing of FIG. 5 is performed by at least one processor based on obtaining and executing one of the instructions.

[00158] Referring to FIG. 5, a first value and a second value to be initially compared are obtained in step 500. In one example, the first value has one element of the second operand and the second value has a corresponding element of the third operand. (In other embodiments, multiple values of multiple elements are compared in parallel or sequentially)

[00159] At step 502, a determination is made regarding the comparison function to be performed based on the control of the instruction. For example, if the instruction is a vector floating point maximum instruction and M ₆ = 0, the IEEE MaxNum function is performed. Similarly, if the instruction is a floating-point vector and a minimum command M ₆ = 0, the IEEE MinNum function is performed. Similarly, if the instruction is a vector floating-point maximum / minimum instruction and M ₆ = 0, then the IEEE MaxNum function is performed if the instruction is to perform a maximum operation, or if the instruction is to perform a minimum operation, Function is performed. Many other examples are possible.

[00160] Then, at step 504, for the selected comparison function (e.g., IEEE MaxNum, IEEE MinNum, etc.), one comparison option is calculated based on the first value and the second value , And a plurality of comparison options for the particular selected comparison function. For example, if the IEEE MaxNum function is performed (e.g., M ₆ = 0) and the first value is -0 (a) and the second value is + ∞ (b) (See Fig. 4A). The values are compared at step 506 using the selected comparison option to obtain one result. For example, in FIG. 4A, the comparison result for the IEEE MaxNum function is displayed at the intersection of the input values (-0, +?). Thus, the result obtained in this particular example is T (b), where the value of the third operand is displayed as the result of the comparison. This result is placed at the selected position in step 508. [ For example, it is placed in the specified register using V ₁ . In a further example, however, this result may be placed at a memory location or other location.

[00161] Further details relating to facilitating processing within a computing environment, including executing instructions for performing vector floating-point maximum, minimum and / or maximum / minimum instructions, are illustrated in Figures 6A-6B. .

6A, an instruction (e.g., a single architected machine instruction) to perform a comparison of a first value and a second value is obtained, at step 600, and stored at step 602, And executed by at least one processor. The executing step includes determining a comparison function to be performed based on, for example, one control of the instruction (step 604). The comparison function is one of a plurality of comparison functions configured for the command (step 606), and the comparison function has a plurality of options for comparison (step 608). One comparison option to be used to compare the first value and the second value is selected from a plurality of options for the comparison function (step 610). The comparison option is selected based on the first value and the second value. The first value and the second value are compared using the comparison option to obtain one result (step 612). The result is specific to the comparison option selected for the comparison function indicated by control of the instruction (step 614). The result is placed in the selected location and used for processing within the computing environment (step 616).

[00163] In one example, the plurality of options comprises a plurality of pairs of selectable cases (step 620), the plurality of pairs of specific cases being selected from the group consisting of an infinity, NAN And at least one particular case comprising at least one particular case selected from the group of specific cases, including a signed zero (step 622).

[00164] By way of example, referring to FIG. 6B, the plurality of comparison functions include at least one of a plurality of maximum functions and a plurality of minimum functions (step 630); The plurality of maximum functions include a plurality of maximum techniques to perform a maximum comparison (step 632); And the plurality of lowest functions include a plurality of minimum techniques to perform the lowest comparison (step 634).

[00165] In one embodiment, the first value and the second value are provided by the instruction (step 636), and the first value has one element of one operand of the instruction, The value has a corresponding element of the other operand of the instruction (step 638). By way of example, the size of the element is determined based on the other controls of the command (step 640).

[00166] In addition, in one example, the first value and the second value are floating point values (step 642) and the size of the one element is dependent on the floating point format of the floating point values Step 644), and the other control displays the selected floating point format (step 646). Additionally, in one example, the control is provided within the mask of the instruction (step 648).

[00167] The facility has been described herein for the use of a single architectured instruction to perform floating-point comparisons to handle special cases. This command replaces multiple instructions and improves computer processing and performance.

[00168] While various examples have been provided, various modifications are possible without departing from the scope of the claims. For example, the values contained in the registers and / or fields used by the instruction may, in other embodiments, be included in other locations, e.g., memory locations. Many other variations are also possible.

[00169] One or more embodiments of the invention may be related to cloud computing.

[00170] Although the specification includes detailed descriptions with respect to cloud computing, it should be understood that the implementation of such descriptions is not limited to a cloud computing environment. Rather, embodiments of the invention may be implemented with any other type of computing environment now known or later developed.

[00171] Cloud computing is a rapidly evolving and rapidly evolving environment that includes configurable computing resources (eg, network, network bandwidth, server, processing, memory, etc.) that can be quickly provisioned and released with minimal management effort or interaction with a service provider Service network that enables convenient on-demand network access to shared pools of applications, storage, applications, virtual machines, and services. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[00172] Cloud computing characteristics are as follows:

[00173] On-demand self-service: A cloud consumer has the ability to perform computing functions such as server time and network storage automatically, as needed, without requiring human interaction with the service provider It can be provisioned unilaterally.

Broad network access: standard mechanisms that encourage use by heterogeneous thin or thick client platforms (eg, mobile phones, laptops, and PDAs) The functions accessed through the network can be used through the network.

[00175] Resource pooling: The computing resources of the provider use a multi-tenant model to dynamically allocate and reallocate different physical and virtual resources according to demand , Pooled to serve multiple consumers. Consumers generally have position independence in that they are not able to control the exact location of the provided resources, or have no knowledge of it, but can specify the location at a higher level of abstraction (e.g., country, state, or data center).

[00176] Rapid elasticity: capabilities can be agile and resiliently provided (in some cases, automatically) to scale quickly and scale down quickly and resize quickly It can scale in. The possibilities that can be offered to consumers are often unlimited and seem to be able to buy at any time.

[00177] Measured service: The cloud system automatically controls and optimizes resource usage, and at a level of abstraction appropriate to the type of service (eg, storage, processing, bandwidth, and active user account) some level of abstraction). Resource usage can be monitored, controlled, and reported, thereby providing transparency to both the provider and the user of the service being used.

[00178] Service Models are as follows:

[00179] Software as a Service (SaaS): The service provided to the consumer allows the use of the provider's applications running on the cloud infrastructure. Applications are accessible from multiple client devices through a thin client interface, such as a web browser (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including network, server, operating system, storage, or individual application performance. However, limited user-specific application configuration settings are possible as an exception.

[00180] Platform as a Service (PaaS): A service provided to a consumer is a service that enables the placement of consumer-generated or acquired applications created using programming languages and tools supported by the provider in the cloud infrastructure will be. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or repositories. However, you can control for deployed applications and, where possible, for application hosting environment configurations.

Infrastructure as a Service (IaaS): A service provided to a consumer provides processing, storage, network, and other basic computing resources, where the consumer can deploy and execute arbitrary software The software may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure but can control for limited control of the operating system, storage, deployed applications, and possibly selected networking components (e.g., host firewalls).

[00182] Deployment Models are as follows:

[00183] Private cloud: A cloud infrastructure is operated for an organization only and can be managed by the organization or a third party and can be managed on-premises or on-premises ). ≪ / RTI >

[00184] Community cloud: A cloud infrastructure supports a specific community that is shared by multiple organizations and shares interests (eg, mission, security requirements, policy, and compliance audits) Or by a third party, and may be located on-premises or on-premises.

[00185] Public cloud: A cloud infrastructure is available to the general public or a large industrial group and is owned by an organization that sells cloud services.

[00186] Hybrid cloud: A cloud infrastructure is a hybrid configuration of two or more clouds (private, community, or public), which are unique entities, but have data and application portability. (E.g., cloud bursting for load balancing among the clouds) that allows for the availability of a standardized or proprietary technology.

[00187] The cloud computing environment is oriented toward services that focus on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes. One such node is the node 10 shown in Fig.

[00188] The computing node 10 is only one example of a suitable cloud computing node and is not intended to limit the scope of use or functionality of the embodiments of the invention described herein. In any case, the cloud computing node 10 is capable of implementing and / or performing all of the functions described above.

[00189] Referring now to FIG. 7, an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10, which may be, for example, a personal digital assistant (PDA) or mobile phone 54a, a desktop computer 54b, A laptop computer 54c, and / or an automotive computer system 54n. The nodes 10 can communicate with each other. Which may be physically or virtually grouped (not shown) in one or more networks, such as private, community, public, or hybrid clouds, or combinations thereof, as described herein. This allows the cloud computing environment 50 to provide infrastructure, platforms and / or software as a service so that the cloud consumer does not have to maintain resources on the local computing device. The types of computing devices 54a-N shown in FIG. 7 are described for illustrative purposes only and the computing nodes 10 and the cloud computing environment 50 may be any type of network and / or network addressable connections (E. G., Using a web browser) to communicate with any type of computerized device. ≪ RTI ID = 0.0 >

[00190] Referring now to FIG. 8, a set of functional abstraction layers provided by the cloud computing environment 50 (FIG. 7) are shown. It should be understood that the components, layers, and functions illustrated in FIG. 8 are for purposes of illustration only and that preferred embodiments of the invention are not so limited. As shown, the following layers and corresponding functions are provided:

[00191] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include main frames 61; Reduced Instruction Set Computer (RISC) architecture based servers 62; Servers 63; Blade servers 64; Storage devices 65; And network and networking components 66. In some embodiments, the software components include network application server software 67 and database software 68.

[00192] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 71; Virtual storage 72; Virtual networks 73, including virtual private networks; Virtual applications and operating systems 74; And virtual clients (75).

[00193] In one example, the management layer 80 provides the functions described below. Resource provisioning 81 provides dynamic procurement of computing resources and other resources used to perform tasks within a cloud computing environment. Metering and Pricing 82 provides cost tracking and billing for the consumption of these resources when they are used in a cloud computing environment. In one example, these resources may include application software licenses. Security provides identification of data and other resources as well as cloud consumers and operations. A user portal 83 provides consumers and system administrators access to the cloud computing environment. Service level management 84 provides cloud computing resource allocation and management to meet the required service levels. Service Level Agreement (SLA) planning and fulfillment (85) provides pre-arrangement and procurement of cloud computing resources that meet the anticipated future requirements for SLAs.

[00194] The workload layer 90 provides examples of functions in which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided in this layer are: mapping and navigation 91; Software Development and Lifecycle Management (92); Deliver virtual classroom education (93); Data analysis processing 94; Transaction processing 95; And command processing (96).

[00195] The present invention may be a computer program product at all possible technical levels of system, method, and / or integration. The computer program product may include a computer readable storage medium having computer readable program instructions for causing a processor to perform the embodiments of the present invention.

[00196] The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing, . A non-exhaustive list of more specific examples of computer-readable storage media may include: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable and programmable read- (ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, perforation-cards, or instructions may be written to a memory, such as a memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read- A mechanically encoded device such as elevated structures in the grooves, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium refers to a computer-readable medium having stored thereon an electromagnetic wave that propagates through radio waves or other freely propagating electromagnetic waves, waveguides or other transmission media (e.g., optical pulses transmitted through a fiber optic cable) It is not interpreted as transitory signals per se, such as electrical signals transmitted through a wire.

[00197] The computer-readable instructions described herein may be read from a computer-readable storage medium via a communication network such as, for example, the Internet, a local area network, a wide area network, and / Or from an external storage device to an external computer. The communication network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the communication network and transmits the computer readable program instructions for storage in a computer readable storage medium in a respective computing / processing device.

[00198] Computer-readable program instructions for carrying out the operations of the present invention may be stored in a conventional procedural programming language such as an object-oriented programming language such as Smalltalk, C ++, or the like, and a " C " (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-of-the-art instructions, Setting data, configuration data for an integrated circuit, or source code or object code. The computer-readable program instructions may be executed entirely on a user's computer, partly on a user's computer, as a stand-alone software package, partially on a user's computer and partially on a remote computer or entirely on a remote computer or server . In the last case above, the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or wide area network (WAN) (Via the Internet). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) The computer readable program instructions can be executed to utilize state information of the computer readable program instructions to customize the computer readable program instructions.

[00199] Embodiments of the present invention will now be described with reference to exemplary diagrams and / or block diagrams of methods, devices (systems), and computer program products in accordance with embodiments of the present invention. It will be appreciated that each block and sequence of flowchart illustrations and / or block diagrams and / or combinations of blocks within the block diagrams may be implemented by computer readable program instructions.

[00200] These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to create a machine so that the instructions may be processed by the computer or other programmable data processing May be implemented through a processor of the apparatus to generate means for implementing the functions / operations specified in the blocks or blocks of the flowchart and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium, and the computer-readable storage medium on which the instructions may be stored may be stored on a computer, a programmable data processing apparatus, and / Blocks may be made to function in a particular manner to include an article of manufacture including instructions that implement the features / acts specified in the blocks or blocks of the block diagrams.

[00201] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operating steps to be performed on the computer, other programmable apparatus, And thus the instructions that execute on the computer, other programmable apparatus, or other apparatus may implement the functions / acts specified in the flowchart and / or block or blocks of the block diagrams.

[00202] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products in accordance with various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a portion of a module, segment, or instruction that includes one or more executable instructions for implementing the specified logical function (s). In some other implementations, the functions referred to in the block may occur differently from the order noted in the figures. For example, two blocks shown in succession may actually be executed substantially concurrently, or the two blocks may sometimes be executed in reverse order, depending on the associated function. Each block of block diagrams and / or example illustrations, and combinations of blocks within the block diagrams and / or the example illustrations, are intended to include specific features or operations that perform the specified functions or operations of the special purpose hardware and computer instructions, It should also be noted that it may be implemented by any applicable hardware-based systems.

[00203] In addition to the foregoing, one or more embodiments of the present invention may be provided, provisioned, managed, and serviced by a service provider that provides management of customer environments. For example, a service provider may create, maintain, support, etc. computer code and / or computer infrastructure to perform one or more embodiments of the present invention for one or more customers. In return, the service provider may receive payment from the customer, for example, in accordance with a subscription and / or fee arrangement. Additionally or alternatively, the service provider may sell the ad content to one or more third parties and receive the payment.

[00204] In one example, one application may be deployed to perform one or more embodiments of the present invention. As an example, the deployment of one application may include providing a computer infrastructure operable to perform one or more embodiments of the present invention.

[00205] As a further example, a computing infrastructure may be deployed that includes integrating computer readable code into a computing system in which the code is coupled to the one or more of the invention Embodiments may be practiced.

[00206] As a further example, a process may be provided for integrating a computing infrastructure, including integrating computer readable code into a computer system. The computer system includes a computer readable medium in which the computer medium comprises one or more embodiments of the present invention. The code may be combined with the computer system to perform one or more embodiments of the invention.

[00207] While various embodiments have been described above, they are merely illustrative. For example, computing environments of different architectures can be used to include and use one or more embodiments of the present invention. In addition, different instructions, command formats, command fields, and / or command values may be used. Many variations are possible.

[00208] Other types of computing environments may also benefit and be used. By way of example, a data processing system suitable for storing and / or executing program code may be used, the system comprising at least two processors directly or indirectly coupled to memory elements via a system bus. The memory elements may include, for example, local memory used during the actual execution of the program code, bulk storage, and at least some of the program code's temporary storage to reduce the number of times code must be retrieved from the mass storage during execution. and a cache memory that provides storage.

Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives and other memory media, etc.) And may be coupled to the system through intervening I / O controllers. A network adapter may also be coupled to the system to enable it to be coupled to other data processing systems or remote pointers or storage devices via a private or public network mediated by the data processing system. Modems, cable modems, and ethernet cards are just some examples of the types of network adapters available.

[00210] The terminology used herein is for the purpose of describing particular embodiments of the invention only, and is not intended to be limiting. When used in this specification, a singular form is also intended to include plural forms, unless the context clearly dictates otherwise. Also, the words " comprises " and / or " comprising " when used in this specification specify the presence of stated features, integers, steps, operations, elements, and / Steps, operations, elements, components, and / or groups of elements, integers, steps, operations, elements, components, and / or groups.

[00211] In the following claims, corresponding structures, materials, acts, and equivalents of all means or step-plus functional elements, if any, There is an intention to include a structure, material, or action for performing the function with the claimed elements. The description of one or more embodiments of the invention is provided for the purposes of illustration and description, and is not intended to be exhaustive or to limit the invention to the precise form disclosed. It will be appreciated by those of ordinary skill in the art that many modifications and variations may be made. The embodiments of the invention are described in order to best explain the various features and practical applications and to enable those of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated , Were selected and described.

Claims (12)

In a computer-implemented method, the method includes obtaining (600) a command to be executed, the command performing (600) a comparison of a first value and a second value, -, said method comprising:
(602) of executing the instruction, wherein the instruction comprises at least a single architectural instruction (a) that supports various maximum functions or various minimum functions a single architected instruction), and the various maximum functions include at least a plurality of the following: IEEE MaxNum, Java Math.Max (), C-Style Max Macro, C ++ Algorithm.max (), fmax (), Math.Max (), C-Style Max Macro of absolute values, C ++ Algorithm.max () of absolute values and fmax () of absolute values, C-Style Min Macro, C ++ Algorithm.min (), fmin (), IEEE MinNumMag, Java Math.Min () of absolute values, C-Style Min Macro of absolute values, C ++ Algorithm.min (), and fmin () of absolute values, and executing the command includes:
Determining a compare function to be performed based on one control of the instruction (309, 329, 359), the comparison function determining whether the various maximum functions configured for the instruction or the various minimum Functions, the comparison function having a plurality of comparison options that are specific to the comparison function;
Selecting (610) a comparison option (a compare option) corresponding to the first value and the second value to be compared, from the plurality of comparison options for the comparison function;
Comparing (612) the first value and the second value using the comparison option to obtain a result, the result being compared to the comparison function indicated by the control of the instruction (612) specific to the comparison option selected for the comparison option; And
Placing the result at a selected location, the result being used for processing in the computing environment (616)
Computer implemented method.
2. The method of claim 1, wherein each of the plurality of comparison options comprises a pair of cases, the pair of cases having the following: -∞, + ∞, -FN, + FN, -0, +0, QNAN, SNAN, where FN is a finite number
Computer implemented method.
2. The method of claim 1, wherein at least one of the plurality of comparison options comprises a pair of cases, the pair of cases comprising: -∞, + ∞, -0 , ≪ / RTI > +0, QNAN, SNAN (622)
Computer implemented method.
2. The method of claim 1, wherein the single architectural instruction supports the various maximum functions, and the various maximum functions include IEEE MaxNum, Java Math.Max (), C-Style Max Macro, C ++ Algorithm.max (), IEEE MaxNumMag, Java Math.Max () of absolute values, C-Style Max Macro of absolute values, C ++ Algorithm.max () of absolute values, and fmax () of absolute values.
2. The method of claim 1, wherein the single architectured instruction supports the various minima functions, and the various minima are selected from IEEE MinNum, Java Math.Min (), C-Style Min Macro, C ++ Algorithm.min (), IEEE MinNumMag, Java Math.Min () of absolute values, C-Style Min Macro of absolute values, C ++ Algorithm.min () of absolute values, and fmin
Computer implemented method.
2. The method of claim 1, wherein the single architectural instruction further comprises:
It should be noted that all of the various minimum functions
Computer implemented method.
The method of claim 1, wherein the first value and the second value are provided by the instruction (636), the first value having one element of one operand of the instruction, With the corresponding element of the operand
Computer implemented method.
8. The method of claim 7, wherein the size of the element is determined based on another control of the command (640, 312, 332, 362)
Computer implemented method.
9. The method of claim 8,
The first value and the second value are floating point values 642 and the size of the element is dependent on the floating point format of the floating point values 644, The control displays the selected floating point format (646)
Computer implemented method.
2. The method of claim 1, wherein the control is provided in a mask of the command (309, 329, 359)
Computer implemented method.
Comprising means configured to perform all steps of the method according to the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth,
system.
11. A computer program comprising instructions for executing all steps of the methods according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11,
Computer program.

Images