KR20190060109A - Instruction-level data isolation method and apparatus - Google Patents

Abstract

Disclosed are a method and an apparatus for isolating instruction level data. A system control module sets a protection area at a non-privileged level in a kernel space of a memory, uses an access control function to restrict access to the protection area by an instruction executed at a privileged level, and allows a predetermined specific instruction executed at a non-privileged level to access to the protection area.

Description

≪ Desc / Clms Page number 1 > Instruction-level data isolation method and apparatus &

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for isolating a command level data, and more particularly, to a command level data isolation method and apparatus for protecting data of an OS (Operating System) kernel of a mobile device.

Mobile phones, smart phones, and the like, and are subject to cyber attacks. In order to cope with various cyber attacks such as malicious codes, a conventional mobile device uses a memory access control function of a memory management unit (MMU). The MMU sets read / write memory protection to isolate and protect sensitive data from the outside. However, it is inefficient to protect frequently accessed data such as a return address because the MMU must repeatedly release / set the memory protection function every time a normal command accesses data protected by the MMU.

Published Japanese Patent Application No. 10-2017-0067740 " Technique for protecting application confidentiality from operating system attack "

SUMMARY OF THE INVENTION The present invention is directed to a method and apparatus for isolating instruction level data.

According to another aspect of the present invention, there is provided an instruction level data isolation method comprising: setting a protection area of a non-privilege level in a kernel space of a memory; And restricting access to the protection area by an instruction executed at a privilege level using an access control function, and allowing a predetermined special instruction executed at a non-privilege level to access the protection area.

According to an aspect of the present invention, there is provided an instruction level data isolation apparatus comprising: a system control module having a privilege level for a page table and a register, and having a higher privilege than a kernel; And a non-privilege level protection area generated in a kernel space of the memory, wherein the system control module restricts access to the protection area from an instruction executed at a privilege level, The access control function is set so that the command can access the protection area.

According to the present invention, it is possible to implement data isolation at the instruction level without changing the memory protection setting of the MMU as in the prior art. Kernel developers can develop various security solutions using two kinds of memory access commands (general commands, special commands).

1 is a diagram illustrating an example of a method for isolating an instruction level data according to an embodiment of the present invention;
FIG. 2 illustrates an example of a special instruction word according to an embodiment of the present invention; FIG.
3 is a diagram illustrating an example of a page table mapping method according to an embodiment of the present invention.
4 is a diagram illustrating an example of a method of isolating an instruction level data according to an embodiment of the present invention,
5 is a diagram illustrating another example of a command level data isolation method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method and apparatus for isolating an instruction level data according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an example of a command level data isolation method according to an embodiment of the present invention.

Referring to FIG. 1, the kernel code 100 may include special instructions (e.g., ldtr, sttr, etc.) with general instructions (e.g., ldr, str, etc.). A special instruction is an instruction to perform a memory operation at an unprivileged level (or a user level) and may be provided in a processor architecture in which the present invention is implemented. An example of the special instructions provided by the ARM architecture is shown in FIG.

The kernel space 110 of the memory is divided into a safe region 112 for storing kernel data to be protected and a regular region 114 for storing general kernel data.

In the special instruction, the access to the protection area 112 of the kernel space 110 is controlled by the access control function. The access control function can be implemented by the Priviledged Access Never (PAN) 120 of the ARM architecture or the Supervisor Mode access Prevention (SMAP) of the x86 architecture. In addition, access control functions can be implemented in various ways. For convenience of description, this embodiment assumes that the access control function is implemented in the PAN 120 of the ARM architecture.

When the PAN bit is set to " 1 ", kernel code operating at a privileged level (or kernel level) is restricted access to non-privilege level protected areas where user data, etc. are stored . In the situation where the PAN bit is "1", a permission fault occurs when a general instruction attempts to access the protection area at privileged level.

The PAN bit can be set by directly setting or clearing the PAN bit belonging to the CPSR (Current Program Status Register) or clearing the SPAN bit of SCTLR (System Control Register). The PAN bit is set to "1" when an exception occurs for a privilege level.

In order to set the PAN bit to 1 and keep the protection area at a non-privileged level, the integrity of the page table and system registers must be protected. To this end, the present embodiment includes a system control module (hereinafter referred to as 'SC module') having an exclusive control authority with respect to a page table and a register. The SC module has higher privileges than the kernel and is separate from the kernel. The kernel can call SC modules only through dedicated gates. An SC module can be implemented as a kind of program code that is executed in a mode with higher privileges than the kernel.

For example, the ARM architecture provides a 'Hyp mode' which is a higher processor mode than the kernel level. Hyp mode has its own page table, which allows access to memory regardless of the access rights set by the kernel. In addition, Hyp mode has the highest processor mode, so you can set all system registers, set up hardware traps through special registers added for Hyp mode, monitor kernel access to system registers Can intervene. The kernel can enter Hyp mode by executing the HVC (Hypervisor Call) command, which is a call command defined in the ARM architecture.

The SC module can set up hardware traps to prevent the kernel from accessing system registers. All attempts by the kernel to change the system registers are monitored by the SC module so that the SC module can thoroughly validate changes to the kernel's system registers before making those changes.

In order for the SC module to have exclusive control of the page table and keep the protection area at a non-privileged level, the present embodiment may use an extended paging scheme. However, since the extended paging scheme results in degradation of the system performance, in another embodiment, a scheme similar to a shadow page table can be applied. First, the SC module sets the page table to read-only in the kernel's space in memory so that the kernel can not change its own page table. To update the contents of the page table, the kernel must call the SC module by calling the HVC command. The SC module then verifies the update request and then updates the contents of the page table on behalf of the kernel. In addition, the SC module prevents its own memory area from being mapped by the page table. Therefore, the kernel can not access the SC module without going through HVC commands.

The PAN bit should always be set to 1 while the kernel is running. To this end, instructions that clear the PAN bit (e.g., MSR PAN, <imm | reg> in the ARM architecture, etc.) may be removed from the kernel code. The SC module may remove the PAN bit release instructions from the kernel code or the user may remove the release instructions from the kernel code. The SC module can release the SPAN bit in the SCTLR (System Control Register) to turn on the PAN bit when control passes to the kernel. If the PAN bit is always set, the kernel can not access the user space as well as the protected area. In this case, some of the kernel functions that attempt to access user space may be interrupted, causing kernel panic. To solve this, the SC module includes functions for performing operations on the protection area or the user area, and allows the kernel to call the functions of the SC module via HVC instructions.

If the PAN bits are properly maintained, the protection area can be safeguarded while being set to a non-privileged level. Therefore, when the kernel sends a page table change request from the SC module, the SC module determines whether the change request meets predetermined conditions. Various conventional conditions for maintaining the integrity of the page table may exist. In addition, the SC module detects and prevents the double-mapping problem that occurs when the physical address of the protected area is mapped to another virtual address with a different access permission. The SC module blocks the kernel's attempt to disable protection of the protection area by disabling the MMU or by changing a register (eg, the Translation Table Base Register (TTBR) in the ARM architecture) that points to the base address of the page table.

2 is a diagram illustrating an example of a special instruction word according to an embodiment of the present invention.

Referring to FIG. 2, a special instruction word includes various kinds of Load instructions for reading data stored in a memory with instructions operating at a non-privileged level, and various types of Store instructions for storing data in the memory.

When a special instruction is executed at a privilege level, the special instruction is treated as if it were executed at a non-privileged level. In other words, if you use special commands to access the memory area, the access depends on the access privileges of the non-privileged levels described in the page table.

Although the present embodiment shows an example of a special instruction word provided in the ARM architecture, the present invention is not limited thereto. It is possible to use special instruction words that operate at a non-privilege level in various kinds of architectures including the x86 architecture have.

3 is a diagram illustrating an example of a page table mapping method according to an embodiment of the present invention.

Referring to FIG. 3, since the protection area 314 is set as non-privileged, there is a fear that a malicious user process may invade the protection area. In order to solve this, the protection area 314 is hidden or exposed depending on which of the user process or the kernel is operating. For example, the SC module may include a separate second kernel, which stores the address mapping of the area 302 excluding the protection area, in addition to the existing first kernel page table storing the address mapping of the entire kernel space 312, Create a page table.

For example, the ARM architecture provides two registers (for example, TTBR0 and TTBR1) with a base address of the current page table for virtual-to-physical address translation. TTBR0 is used to convert the virtual address corresponding to the user space 300, 310, and TTBR1 is used to convert the virtual address corresponding to the kernel space 302, 312, 314.

Thus, when the user process is performed, the SC module changes the TTBR1 to point to the second kernel page table to activate the second kernel page table. Since the second kernel page table does not include any mapping to the protection area 314, the user process can not read or change the contents of the protection area. The second kernel page table is used only when the user process has control authority. When an interrupt or exception causes control to pass to the kernel, the SC module activates the first kernel page table by changing TTBR1 to point to the original first kernel page table.

The address mapping of the protected area may be cached in the Translation Lookaside Buffer (TLB). In this case, the attacker can attempt to access the protected area using the TLB entry as a user process. To solve this problem, there is a way to invalidate a cached TLB entry before the kernel passes control to the user process.

Another way is to use an ASID (Address Space Identifier). The ARM architecture provides an identifier (i.e., ASID) tagging the TLB entry to reduce unnecessary TLB flushes each time the virtual address space is switched each time. In addition, the ARM architecture provides a non-Global (nG) flag in the page table descriptor, so you can disable it so that the ASID can be ignored on a particular page.

Using this feature, the SC module assigns two different ASIDs to the kernel and user processes, respectively, and activates the corresponding ASID depending on which of the kernel and user processes currently has control. Even if the mapping of the protection area is cached in the TLB entry in the situation where the kernel has control authority, the user process can not use the cached mapping of the protection area because it uses a different ASID than the ASID of the kernel. Since kernel space is mostly mapped to the entire area, ASID switching does not cause performance penalties. The TLB management kernel function operates twice with the ASID of the user process and the ASID of the kernel respectively.

4 is a diagram illustrating an example of a command level data isolation method according to an embodiment of the present invention.

Referring to FIG. 4, the SC module sets a protection area of a non-privilege level in the kernel space (S400). The SC module makes access to the protection area only by special commands through the setting of the access control function implemented by the PAN bits and so on.

For example, when the PAN bit is set and the protection area is maintained as non-privileged, if the command is a general kernel command (S410), access to the protection area is not possible (S430). On the other hand, if the instruction is a special instruction of a non-privilege level (e.g., FIG. 2), access to the protected area is allowed (S420). When the kernel is operating at a privilege level, special instructions are treated as if they are operated at a non-privileged level, so that if the PAN bit is set, the special instruction can determine whether to access the protected area have.

5 is a diagram illustrating another example of a command level data isolation method according to an embodiment of the present invention.

Referring to FIG. 5, in order to prevent a malicious user process from accessing the protection area, the SC module includes a first kernel page table for the kernel space, a second kernel page table for the space excluding the protection area in the kernel space, (S500).

When the control right passes to the user process (S510), the SC module changes the value of the register indicating the base address of the kernel page table to the base address of the second kernel page table (S530). When the control right passes to the kernel (S510), the SC module changes the value of the register indicating the base address of the kernel page table to the base address of the first kernel page table (S520).

In order to prevent the user process from accessing the protection area using the TLB cache, the SC module allocates the address space identifier (ASID) to the kernel and the user process, respectively, The ASID can be switched according to whether or not the ASID is changed.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like. The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (13)

Setting a protection area of a non-privilege level in a kernel space of the memory; And
And restricting access to the protection area by an instruction executed at a privilege level using an access control function and allowing a predetermined special instruction executed at a non-privilege level to access the protection area Level data isolation method. The method according to claim 1,
The access control function is implemented with the PAN bits of the ARM architecture,
Wherein the granting step permits only the special instruction to access the protection area if the PAN bit is a &lt; RTI ID = 0.0 &gt; 1. &lt; / RTI &gt; The method according to claim 1,
Wherein the special instruction word is a command for performing a read or a write operation on the protection area at a non-privilege level. The method according to claim 1,
Further comprising verifying a double-mapping problem that occurs when a physical address of a protected area is mapped to another virtual address having a different access right, in response to a page table change request of the kernel, Way. The method according to claim 1,
Generating a first kernel page table for a kernel space and a second kernel page table for a space excluding the protection area in the kernel space; And
Changing a value of a register indicating a base address of a kernel page table to a base address of the first kernel page table or a base address of the second kernel page table depending on which of a kernel and a user process is operating Wherein the instruction-level data isolation method comprises: The method according to claim 1,
(First ASID) and a second address space identifier (second ASID) that identify each entry of the Translation Lookaside Buffer (TLB) to the kernel and the user process, respectively A method for isolating instruction level data. A system control module with full privileges on page tables and registers, with higher privileges than the kernel; And
A protection area of a non-privilege level generated in a kernel space of the memory,
The system control module limits access of the instruction executed at the privilege level to the protection area and sets an access control function so that a predetermined special instruction executed at a non-privilege level can access the protection area. Command-level data isolation device. 8. The method of claim 7,
Wherein the page table is implemented in the kernel space as read-only. 8. The method of claim 7,
The access control function is implemented with the PAN bits of the ARM architecture,
Wherein the system control module performs access control on the protection area through the setting of the PAN bit. 8. The method of claim 7,
Wherein the system control module verifies a double-mapping problem that occurs when a physical address of a protected area is mapped to another virtual address having a different access right. 8. The method of claim 7,
A first kernel page table for kernel space; And
And a second kernel page table for the space excluding the protection area in the kernel space,
The system control module changes a value of a register indicating a base address of a page table to a base address of the first kernel page table or a base address of the second kernel page table depending on which of a kernel and a user process is operating Wherein the instruction-level data isolation device comprises: 8. The method of claim 7,
The system control module allocates a different first address space identifier (first ASID) and a second address space identifier (second ASID), which identify each entry of the TLB, to the kernel and the user process, respectively, And switches to a first ASID or a second ASID depending on which one is operating. A computer-readable recording medium storing a program for performing the method according to any one of claims 1 to 6.

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