KR20190058937A - Semiconductor Memory Device Having a Selector Element Pattern Confined in a Hole - Google Patents

Abstract

Described is an electronic device having a semiconductor memory element. The semiconductor memory element can comprise: a lower interlayer insulating layer having a hole; an upper interlayer insulating layer on the lower interlayer insulating layer; and a memory cell stack including a lower element confined within the hole of the lower interlayer insulating layer and an upper element surrounded by the upper interlayer insulating layer. The lower element can include a lower electrode and a selection element pattern on a bottom electrode. The upper element can include a memory pattern on the selection element pattern and a top electrode on the memory pattern.

Description

[0001] The present invention relates to a semiconductor memory device having a selection element pattern localized in a hole,

The present invention relates to a cross-point type semiconductor memory device, and more particularly to a cross-point type semiconductor memory device having a lower electrode and a selection device pattern localized in a hole.

A semiconductor memory device, for example, a variable resistance memory device, may include a memory element that switches between a low resistance state and a high resistance state. For example, the variable resistance memory device may include a Resistive Random Access Memory (ReRAM), a Phase Changeable Random Access Memory (PCRAM), a Spin Transfer Torque Magneto-resistive Random Access Memory (STT-MRAM) Particularly, since the cross-point arrangement type memory device has a simple structure and non-volatile characteristics as compared with DRAM (Dynamic Random Access Memory), it is attracting attention as a next generation semiconductor memory device.

A problem to be solved by the present invention is to provide a cross-point type semiconductor memory device having a selective element pattern localized or buried in a hole.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cross-point type semiconductor memory device including a select element pattern having a bowl shape.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cross-point type semiconductor memory device including an intermediate electrode having a flat upper surface.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory cell stack including a memory cell stack having an upper width greater than a lower width.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a cross-point type semiconductor memory device having a selective element pattern localized or buried in a hole.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a cross-point type semiconductor memory device including a select element pattern having a bowl shape.

A problem to be solved by the present invention is to provide a method of forming a cross-point type semiconductor memory device including an intermediate electrode having a flat upper surface.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a semiconductor memory device including a memory cell stack having an upper width larger than a lower width.

An object of the present invention is to provide an electronic device and a system including the above-described semiconductor memory device.

The various problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

An electronic device according to an embodiment of the present invention may include a semiconductor memory device. A semiconductor memory device according to an embodiment of the present invention includes a lower interlayer insulating layer having a hole, an upper interlayer insulating layer on the lower interlayer insulating layer, a lower element localized in the hole of the lower interlayer insulating layer, And a top element that is surrounded by a top layer. The lower element may include a lower electrode and a selection element pattern on the lower electrode. The upper element may include a memory pattern on the select element pattern, an upper electrode on the memory pattern.

The semiconductor memory device may further include an upper spacer on an outer surface of the upper element, and a lower spacer on an inner wall of the hole. The lower element may be confined by the lower spacer.

The outer surface of the upper portion of the lower spacer and the inner surface of the lower portion of the upper spacer may contact each other.

The lower spacer may be in the form of a disk in a top view. The upper spacer may be in the form of a disk or a polygonal ring in the top view.

The hole may be circular in the top view. The upper element may have a rectangular shape with rounded corners in the top view.

The lower element may further include a lower portion of the intermediate electrode between the selection element pattern and the memory pattern. The lower portion of the intermediate electrode may protrude downward to be positioned in the hole.

The upper element may further include an upper portion of the intermediate electrode. The upper portion of the intermediate electrode may have a flat upper surface.

The upper element may further include a reservoir pattern between the memory pattern and the upper electrode. The reservoir pattern may comprise a metal or a metal oxide.

The lower element may further include a self-current control unit pattern between the lower electrode and the selection element pattern.

The self-current control unit pattern may include a metal oxide.

The lower element may further include a buffer electrode pattern between the self-current control unit pattern and the selection element pattern.

The buffer electrode pattern may include at least one of a metal, a metal compound, a metal silicide, and a metal alloy.

The self-current control unit pattern and the buffer pattern may be in the form of a bowl having a concave top surface at the center.

The selection element pattern may be in the form of a bowl having a concave upper surface at the central portion.

The horizontal width of the upper element may be greater than the horizontal width of the lower element.

The electronic device may further comprise a processor. The processor includes a control section for receiving a signal including an instruction from the outside, performing extraction or decoding of the instruction, or input / output control of the signal of the processor, an operation section for performing an operation according to a result obtained by decoding the instruction, Data to be executed, data corresponding to a result of performing the operation, or a storage unit for storing an address of data to perform an operation. The storage unit may include the semiconductor memory device.

The electronic device may further comprise a processing system. A processor for interpreting the instruction and an auxiliary memory for storing information; a processor for executing the program when the processor is executing the program; And an interface device for performing communication with at least one of the processor, the auxiliary storage device, and the main storage device, and an interface device for performing communication with the external device, . Either the auxiliary memory device or the main memory device may include the semiconductor memory device.

The electronic device may further comprise a data storage system. The data storage system includes: a storage device for storing data and storing the stored data regardless of a supplied power source; a controller for controlling data input / output of the storage device according to an instruction input from the outside; A temporary storage device for temporary storage, and an interface for performing communication with at least one of the storage device, the controller, and the temporary storage device with the outside. Either the storage device or the temporary storage device may include the semiconductor memory device.

An electronic device according to an embodiment of the present invention may include a semiconductor memory device. The semiconductor memory device comprising: a lower interlayer insulating layer having a hole; A lower spacer in the hole of the lower interlayer insulating layer; A lower pillar defined by said lower spacer in said hole; An upper pillars on the lower pillars; An upper spacer on a sidewall of the upper pillar; And an upper interlayer insulating layer surrounding the upper spacer on the lower interlayer insulating layer. The lower pillars may include a lower electrode and a selection device pattern on the lower electrode. The upper pillars may include a memory pattern, and an upper electrode on the memory pattern. The horizontal width of the upper pillars may be greater than the horizontal width of the lower pillars.

The lower pillars may further include a self-current control unit pattern between the lower electrode and the selection element pattern and a buffer electrode pattern. The upper pillars may further include an intermediate electrode between the selection pattern of the lower pillars and the memory pattern, and a reservoir pattern between the memory pattern and the upper electrode. The self-current control unit pattern, the buffer electrode pattern, and the selection element pattern may have a bow shape whose top surface is concave.

The outer side wall of the lower spacer and the inner side of the upper spacer may be vertically flat. The lower spacer and the upper spacer may be spaced apart. The lower interlayer insulating layer may have a rim-like protrusion between the lower spacer and the upper spacer.

The details of other embodiments are included in the detailed description and drawings.

According to the technical idea of the present invention, since the memory cell stack has a selective element pattern of a buried structure that is localized in the hole, the total height of the cell stack can be reduced. Thus, the manufacturing process can be facilitated.

According to the technical idea of the present invention, since the selection element pattern of the memory cell stack has a buried structure localized in the hole, it can be prevented from being attacked by the etching gas in the process of forming the memory cell stack. Therefore, the selection element pattern of the memory cell stack can have excellent characteristics.

The effects of various embodiments of the present invention not otherwise mentioned will be mentioned in the text.

1 is a conceptual circuit diagram of a semiconductor memory device according to an embodiment of the present invention.
2 is a conceptual three-dimensional perspective view of a semiconductor memory device according to an embodiment of the present invention.
FIG. 3A is a vertical sectional view taken along line II 'of FIG. 2, and FIG. 3B is a vertical sectional view taken along line II-II' of FIG.
Figures 3a and 3b through 6a and 6b are longitudinal cross-sectional views conceptually illustrating semiconductor memory devices according to various embodiments of the present invention. 3A to 6A are longitudinal sectional views taken along the line II 'in FIG. 2, and FIGS. 3B to 6B are longitudinal sectional views taken along line II-II' in FIG.
FIGS. 7A and 7B to FIGS. 21A and 21B are views illustrating a method of manufacturing the semiconductor memory device 100A according to an embodiment of the present invention. Figs. 7A to 21A are longitudinal sectional views taken along line II 'of Fig. 2, and Figs. 7B to 21B are longitudinal sectional views taken along line II-II' of Fig.
Figures 22A and 22B are top views conceptually showing top elements of memory cell stacks and top spacers surrounding top elements according to various embodiments of the present invention.
Figures 23A-23C are layout diagrams of the bottom and top elements of memory cell stacks of memory elements according to various embodiments of the invention.
Figures 24-28 are electronic devices or electronic systems that include one or more of the semiconductor memory devices according to various embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

It is to be understood that one element is referred to as being 'connected to' or 'coupled to' another element when it is directly coupled or coupled to another element, One case. On the other hand, when one element is referred to as being 'directly connected to' or 'directly coupled to' another element, it does not intervene another element in the middle. &Quot; and / or " include each and every one or more combinations of the mentioned items.

Like reference numerals refer to like elements throughout the specification. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

1 is a conceptual circuit diagram of a semiconductor memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor memory device 100 according to an embodiment of the present invention includes word lines WL, word lines WL, and word lines WL extending in parallel in a first direction, for example, , Bit lines BL extending in parallel in a second direction intersecting the memory cell stacks (e.g., column direction), and memory cell stacks (not shown) disposed in intersecting regions of the word lines WL and bit lines BL MC). The memory cell stacks MC may include a variable resistance element. The word lines WL may extend parallel to the second direction, e.g., the column direction, and the bit lines BL may extend parallel to the first direction, e.g., the row direction.

2 is a conceptual three-dimensional perspective view of a semiconductor memory device 100 according to an embodiment of the present invention. 2, a semiconductor memory device 100 according to an embodiment of the present invention may include lower conductive wirings 15, upper conductive wirings 60, and memory cell stacks MC .

The lower conductive wirings 15 may extend in parallel in the first horizontal direction. With further reference to Fig. 1, the lower conductive wirings 15 may be word lines WL. In another embodiment of the present invention, the lower conductive wirings 15 may be bit lines BL.

The upper conductive wirings 60 may extend in parallel in a second horizontal direction perpendicular to the first horizontal direction. That is, in the top view, the lower conductive wirings 15 and the upper conductive wirings 60 may be orthogonal to each other like a mesh shape. With further reference to Fig. 1, the upper conductive wirings 60 may be bit lines BL. In another embodiment of the present invention, the upper conductive wirings 60 may be word lines WL.

The memory cell stacks MC may be vertically disposed in regions where the lower conductive wirings 15 and the upper conductive wirings 60 intersect. The memory cell stacks MC may have a columnar shape.

Figures 3A and 3B through 6A and 6B are longitudinal cross-sectional views conceptually illustrating semiconductor memory devices 100A-100D according to various embodiments of the present invention. 3A to 6A are longitudinal sectional views taken along the line I-I 'of FIG. 2, and FIGS. 3B to 6B are longitudinal sectional views taken along line II-II' of FIG.

3A and 3B, a semiconductor memory device 100A according to an embodiment of the present invention includes a lower conductive wiring 15 on a lower layer 10, a memory cell stack (not shown) stacked on a lower conductive wiring 15 MC, and an upper conductive interconnect 60 on the memory cell stack MC. The memory cell stack MC includes a lower element UE including a lower electrode 20, a self-current control unit pattern 25, a buffer electrode pattern 30, and a selection element pattern 35, ), A memory pattern 45, a reservoir pattern 50, and an upper electrode 55, as shown in FIG.

The semiconductor memory device 100A may further include a lower spacer 70 surrounding the sidewalls of the lower element LE of the memory cell stack MC and an upper spacer 75 surrounding the sidewalls of the upper element UE. The upper portion of the lower spacer 70 and the lower portion of the upper spacer 75 can be in contact with each other.

The semiconductor memory device 100A may further include a lower interlayer insulating layer 80 surrounding the outer surface of the lower spacer 70 and an upper interlayer insulating layer 85 surrounding the outer surface of the upper spacer 75. [ The lower interlayer insulating layer 80 can contact the lower surface of the upper spacer 75. The upper interlayer insulating layer 85 may cover a part of the upper surface of the memory cell stack MC.

The lower interlayer insulating layer 80 may have a hole H. [ The lower spacer 70 may be formed on the inner wall of the hole H. [ In the hole H, the lower electrode 20, the self-current control unit pattern 25, the buffer electrode pattern 30, and the selection element pattern 35 are defined and limited to the lower spacer 70 confine. A part of the lower portion of the intermediate electrode 40 in the hole H can also be formed. The lower element LE may further include a portion of the lower portion of the intermediate electrode 40 formed in the hole H. [ The lower spacer 70 may have a cylindrical shape surrounding the lower element LE of the memory cell stack MC and a part of the intermediate electrode 40. The upper spacer 75 may have a cylindrical shape surrounding the upper element UE of the memory cell stack MC. For example, the lower spacer 70 and the upper spacer 75 may each have a circular disk or polygonal ring shape in the top view. The lower spacer 70 and the upper spacer 75 may comprise silicon nitride or silicon oxynitride. The lower spacer 70 may be formed on the inner wall of the hole H to face the center of the hole H or inwardly and the upper spacer 75 may be formed on the inner wall of the memory cell stack MC, And may be formed to face outward. That is, the lower spacer 70 may have a flat outer surface, and the upper spacer may have a flat inner surface. The lower interlayer insulating layer 80 may contact the outer surface of the lower spacer 70 and the bottom surface of the upper spacer 75. The upper interlayer insulating layer 85 may contact the upper surface of the upper spacer 75 and the upper surface of the lower interlayer insulating layer 80. The upper interlayer insulating layer 85 may be formed thick enough to sufficiently cover the memory cell stack MC and the upper spacer 75. The lower interlayer insulating layer 80 and the upper interlayer insulating layer 85 may include silicon oxide. The upper end of the lower spacer 70 may protrude upward so as to be located at a higher level than the lower interlayer insulating layer 80.

The lower element LE of the memory cell stack MC can be formed in the hole H and localized by the lower spacer 70 and the upper element LE of the memory cell stack MC, May be formed on the upper portion of the hole H and surrounded by the upper spacer 75.

The lower layer 10 may be a substrate or a base insulating layer. For example, if the lower layer 10 is a substrate, the lower conductive wirings 15 may be embedded in the lower layer 10. [ When the lower layer 10 is a base insulating layer, the lower conductive wirings 15 may be embedded in the base insulating layer, or may be disposed on the base insulating layer.

The lower conductive wirings 15 may be in the shape of a line extending in the first horizontal direction in the top view. The lower conductive wirings 15 may be formed of a metal such as tungsten W, aluminum Al or copper Cu, a metal compound such as titanium nitride Or a conductive material such as a metal alloy. A part of the upper surface of the lower conductive wiring 15 can be exposed by the hole H. [

The lower electrode 20 may be formed on the lower conductive wiring 15 exposed in the hole H. [ The lower electrode 20 may be formed in a via plug shape, for example, a circular or polygonal mesa shape. In another embodiment of the present invention, the lower electrode 20 may be formed in the shape of a bowl having a concave upper surface at the center. The lower surface of the lower electrode 20 can be in contact with the lower conductive wiring 15 and the side surfaces of the lower electrode 20 can be in contact with the lower spacer 70. The lower electrode 20 may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN) Alloys, and the like.

The self current control unit pattern 25 may be formed on the lower electrode 20 in the hole H by being limited by the lower spacer 70. [ The self-current control unit pattern 25 may have a bowl shape having a concave upper surface at the central portion. In another embodiment of the present invention, the self-current control unit pattern 25 may be formed in a mesa shape whose top surface is flat. The self-current control unit pattern 25 may comprise a hafnia material such as hafnium oxide (HfOx). The self-current control unit pattern 25 can block the overcurrent flowing in the memory cell stack MC.

The buffer electrode pattern 30 may be formed on the self-current control unit pattern 25 in the hole H by being limited by the lower spacer 70. [ The buffer electrode pattern 30 may also have a bowl shape having a concave upper surface at the central portion. In another embodiment of the present invention, the buffer electrode pattern 30 may be formed in a mesa shape having a flat upper surface. The buffer electrode pattern 30 may block diffusion of atoms between the self-current control unit pattern 25 and the selection element pattern 35. [ (E.g., a diffusion barrier layer). The buffer electrode pattern 30 can be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride WN), conductive materials such as metal silicides or metal alloys, and the like.

The selection element pattern 35 may be formed on the buffer electrode pattern 30 in the hole H by being limited by the lower spacer 70. [ The selection element pattern 35 may also have a bowl shape having a concave upper surface at the central portion. In another embodiment of the present invention, the selection element pattern 35 may be formed in a mesa shape whose top surface is flat. The selection element pattern 35 may generate or block current flow in the memory cell stack MC by voltage or current. Selective device pattern 35 may comprise one or more of ion doped silicon, ion doped oxide, or ion doped nitride. For example, the ions may be boron, carbon, carbon, nitrogen, arsenic, phosphorous, silicon, germanium, Ge, germanium), or gallium (Ga, gallium). The oxide may comprise one of silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), or other oxides. The nitride may include silicon nitride (Si3N4) or the like. For example, the select device material layer 35a may comprise silicon oxide doped with As, Arsenic ions.

The intermediate electrode 40 may have a lower portion formed inside the hole H and an upper portion formed at the upper portion of the hole H. [ That is, a part of the lower portion of the intermediate electrode 40 may be disposed on the concave center portion of the selection element pattern 35 in the hole H. [ The lower portion of the intermediate electrode 40 can protrude downward to be located in the hole H. [ In another embodiment of the present invention, the lower surface of the intermediate electrode 40 may be flat. The upper portion of the intermediate electrode 40 may be located at a higher level than the upper surface of the lower interlayer insulating layer 80 and the upper end of the lower spacer 70. The upper portion of the intermediate electrode 40 may have a flat upper surface. The intermediate electrode 40 may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN) Alloys, and the like.

As described above, the lower electrode 20, the self-current control unit pattern 25, the buffer electrode pattern 30, and the selection element pattern 35 are formed in the hole H in such a manner as to be limited by the lower spacer 70, and may be formed in a bowl shape. That is, the lower electrode 20 may also be formed in a bowl shape.

The memory pattern 45 may be laminated in the form of a mesa on the intermediate electrode 40. The memory pattern 45 may comprise a variable resistive cell of variable resistance semiconductor elements. The resistance value of the memory pattern 45 may vary depending on the oxygen content. For example, the memory pattern 45 may include a metal oxide such as hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO), or zinc oxide (ZnO) A phase change material such as GST (GeSbTe) or a chalcogenide material, a mechanical variable resistance material such as a conductive bridging material, or a memristor material.

The reservoir pattern 50 may be laminated on the memory pattern 45 in the form of a mesa. The reservoir pattern 50 may comprise a material capable of providing or storing oxygen atoms or oxygen ions. For example, the reservoir material layer 50a may comprise a metal such as tantalum or titanium. The memory pattern 45 and the reservoir pattern 50 can form a variable resistive element. For example, as the oxygen atoms in the memory pattern 45 move to and are stored in the reservoir pattern 50, or the oxygen atoms that were stored in the reservoir pattern 50 move into the memory pattern 45, The device may have a high resistance state and a low resistance state.

The upper electrode 55 may be laminated on the reservoir pattern 50 in a mesa shape. The upper portion of the upper electrode 55 may have a flat upper surface. A part of the upper surface of the upper electrode 55 can be recessed. A part of the upper surface of the recessed upper electrode 55 can contact the upper electrode 55. [ The upper electrode 55 may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride Alloys, and the like.

The upper conductive wiring 60 may vertically penetrate the upper interlayer insulating layer 85 and may be connected to the upper electrode 55 of the memory cell stack MC. The upper conductive wiring 60 may be in the form of a line extending in a second horizontal direction perpendicular to the first horizontal direction in the top view. The lower end of the upper conductive wiring 60 may protrude downward from the upper surface of the upper electrode 55 to the inside. The upper conductive wirings 60 may be formed of a metal such as tungsten W, aluminum Al or copper Cu, a metal compound such as titanium nitride Or a conductive material such as a metal alloy.

The semiconductor memory device 100A may further include an upper conductive wiring 60 and a capping insulating layer 65 on the upper interlayer insulating layer 85. [ The capping insulating layer 65 physically and mechanically fixes the upper conductive interconnection 60 and the upper interlayer insulating layer 85 and protects the upper conductive interconnection 60 and the upper interlayer insulator 85 from electrical, The layer 85 can be protected. The capping insulating layer 65 may comprise a denser, more solider material, such as silicon nitride or silicon oxynitride, than the upper interlayer insulating layer 85.

The current control unit pattern 25 surrounded by the lower spacer 70 in the hole H of the lower interlayer insulating layer 80, for example, the lower element of the memory cell stack MC, The electrode pattern 30 and the selection element pattern 35 may have a bowl shape with a concave upper surface and may be formed in the upper elements of the memory cell stack MC, The intermediate electrode 40 surrounded by the spacer 75, the memory pattern 45, the reservoir pattern 50, and the upper electrode 55 may have a mesa shape whose top surface is flat. In one embodiment of the present invention, the lower electrode 20 may also have a bowl shape with a concave upper surface.

The memory cell stack MC may have a pillar shape. The lower element LE including the lower conductive wiring 15 formed in the hole H, the self-current control unit pattern 25, the buffer electrode pattern 30, and the selection element pattern 35, And the upper element UE including the intermediate electrode 40, the memory pattern 45, the reservoir pattern 50, and the upper electrode 55 may have an upper pillar shape. The average horizontal width of the upper element (UE) in the form of an upper pillar may be greater than the average horizontal width of the lower element (LE) in the lower pillar shape. The maximum horizontal width of the lower element LE of the lower pillar type may be equal to the average horizontal width or the minimum horizontal width of the upper element UE of the upper pillar type.

4A and 4B, the semiconductor memory device 100B according to the embodiment of the present invention is different from the semiconductor memory device 100A shown in FIGS. 3A and 3B in that the self current control unit pattern 25 and the buffer The electrode pattern 30 can be omitted. Thus, the lower element LE may include a lower electrode 20, and a selection element pattern 35 formed directly on the lower electrode 20. The lower electrode 20 may be formed in a mesa shape or a bowl shape in the hole H by being limited by the lower spacer 70.

5A and 5B, the semiconductor memory device 100C according to the embodiment of the present invention is different from the semiconductor memory device 100A shown in FIGS. 3A and 3B in that the self-current control unit The pattern 25, the buffer electrode pattern 30, and the selection element pattern 35 may have flat top surfaces and / or bottom surfaces. That is, the self-current control unit pattern 25, the buffer electrode pattern 30, and the selection element pattern 35 of the lower element LE are limited by the lower spacer 70, And may be formed in a plug shape.

In this embodiment, the lower element LE and the lower spacer 70 of the memory cell stack MC can form a bowl shape having a flat upper surface.

3A and 3B, the lower electrode LE of the memory cell stack MC, for example, the lower electrode 20 surrounded by the lower spacer 70 in the hole H of the lower interlayer insulating layer 80 ), The self-current control unit pattern 25, the buffer electrode pattern 30, and the selection element pattern 35 may each optionally have one of a bowl shape or a mesa shape.

6A and 6B, a semiconductor memory device 100D according to an embodiment of the present invention is different from the semiconductor memory device 100A shown in FIGS. 3A and 3B in that the upper element (not shown) of the memory cell stack MC The width W1 of the upper electrode 55, the reservoir pattern 50, the memory pattern 45 and the intermediate electrode 40 is larger than the width H2 of the lower hole H (or diameter) . Alternatively, the inner width W1 of the upper spacer 75 of the memory cell stack MC (or the distance or diameter between the inner walls of the upper spacer 75) may be greater than the outer width W2 of the lower spacer 70 The distance or diameter between the outer sidewalls of the lower spacer 70). For example, the lower interlayer insulating layer 80 may have a rim R protruding upwardly between the lower spacer 70 and the upper spacer 75. The rim portion R may have a disk shape or a rectangular shape in a top view. The upper end of the lower spacer 70 may protrude so as to be located at a higher level than the lower end of the upper spacer 75. The protruding upper end of the lower spacer 70 and the upper end of the protruded rim portion R of the lower interlayer insulating layer 80 may be substantially the same. The upper portion of the lower spacer 70 and the lower portion of the upper spacer 75 may be spaced apart.

The technical features shown and described in Figs. 3A and 3B to Figs. 6A and 6B can be compatible with each other.

FIGS. 7A and 7B to FIGS. 20A and 20B are views illustrating a method of manufacturing the semiconductor memory device 100A according to an embodiment of the present invention. Figs. 5A to 20A are longitudinal sectional views taken along the line I-I 'of Fig. 2, and Figs. 5B to 20B are longitudinal sectional views taken along line II-II' of Fig.

7A and 7B, a method of manufacturing a semiconductor memory device 100A according to an embodiment of the present invention includes forming lower conductive wirings 15 on a lower layer 10 and forming lower conductive wirings Forming the lower interlayer insulating layer 80 covering the lower interconnection lines 15 and the holes H vertically penetrating the lower interlayer insulating layer 80 to expose portions of the upper surface of the lower conductive interconnection lines 15 .

The lower layer 10 may be a substrate or a base insulating layer. For example, if the lower layer 10 is a substrate, the lower conductive wirings 15 may be embedded in the lower layer 10. [ When the lower layer 10 is a base insulating layer, the lower conductive wirings 15 may be embedded in the base insulating layer, or may be disposed on the base insulating layer.

Forming the lower conductive wirings 15 is performed by performing a deposition process to form a conductive layer on the lower layer 10 and performing a photolithography process and an etching process to pattern the conductive layer to form the lower conductive wirings 15 ). ≪ / RTI > Alternatively, in another embodiment of the present invention, forming the lower conductive wirings 15 may be accomplished by forming trenches in the lower layer 10, filling the trenches with a layer of conductive material, (15). ≪ / RTI > The lower conductive wirings 15 may be formed of a metal such as tungsten W, aluminum Al or copper Cu, a metal compound such as titanium nitride Or a conductive material such as a metal alloy.

Forming the lower interlayer insulating layer 80 may include performing a deposition process or a coating process to form a layer of insulating material covering the lower conductive wirings 15. [ The lower interlayer insulating layer 80 may include silicon oxide, or silicon oxide containing carbon (C) and / or hydrogen (H).

The formation of the holes H may include forming a mask pattern on the lower interlayer insulating layer 80 and performing an etching process using the mask pattern as an etching mask.

8A and 8B, the method may include forming lower spacers 70 in holes H. Forming the lower spacers 70 may include performing a deposition process to form a layer of insulating material to fill the holes H, and performing an etch-back process. The lower spacers 70 may have a cylindrical shape. For example, the lower spacers 70 may have a ring shape that exposes the upper surface of the lower conductive wirings 15 in a top view.

Referring to Figures 9A and 9B, the method may include forming the lower electrodes 20 in the holes H. [ Forming the lower electrodes 20 may include performing a deposition process to form a lower electrode material layer filling the holes H and performing an etch-back process to recess the lower electrode material layer . For example, the upper surfaces of the lower electrodes 20 may be located at an intermediate level of the holes H. [ The lower electrode material layers and lower electrodes 20 may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride A metal silicide, or a metal alloy. ≪ RTI ID = 0.0 > [0040] < / RTI >

10A and 10B, the method includes performing a deposition process to deposit the lower electrodes 20 and lower spacers 70 in the holes H and the self-current control unit SCU , self-compliance unit material layer 25a conformally. The self-current control unit material layer 25a may comprise a hafnia material such as hafnium oxide (HfOx).

11A and 11B, the method includes forming SCU self-compliance unit patterns 25 on lower electrodes 20 and lower spacers 70 in holes H . Forming the self-current control unit patterns 25 may include performing an etch-back process. The self current control unit patterns 25 may be formed in a bowl shape. The top end portions of the self-current control unit patterns 25 may be located in the holes H. That is, portions of the holes H may be filled with the lower electrodes 20 and the self-current control unit patterns 25. [ In the etch-back process, the self-current control unit patterns 25 can be minimally exposed to the etching gas. Therefore, degradation of the electrical and physical properties of the self-current control unit patterns 25 can be minimized.

12A and 12B, the method includes performing a deposition process to conform the buffer electrode material layer 30a on the self-current control unit patterns 25 in the holes H and the lower interlayer dielectric layer 80 . ≪ / RTI > The buffer electrode material layer 30a may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride Or a conductive material such as a metal alloy.

Referring to FIGS. 13A and 13B, the method may include performing an etch-back process to form the buffer electrode patterns 30 on the self-current control unit patterns 25. The buffer electrode patterns 30 may also be formed in a bowl shape in the holes H. [ The top end portions of the buffer electrode patterns 30 may be located in the holes H as well. In the etch-back process, the buffer electrode patterns 30 can be minimally exposed to the etching gas. Therefore, degradation of the electrical and physical properties of the buffer electrode patterns 30 can be minimized.

14A and 14B, the method may include performing a deposition process to conformally form the selection device material layer 35a on the buffer electrode patterns 30 and the lower interlayer dielectric layer 80 . Selective device material layer 35a may comprise one or more of ion doped silicon, ion doped oxide, or ion doped nitride. For example, the ions may be boron, carbon, carbon, nitrogen, arsenic, phosphorous, silicon, germanium, Ge, germanium), or gallium (Ga, gallium). The oxide may comprise one of silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), or other oxides. The nitride may include silicon nitride (Si3N4) or the like. For example, the select device material layer 35a may comprise silicon oxide doped with As, Arsenic ions.

Referring to FIGS. 15A and 15B, the method may include performing an etch-back process to form the selection element patterns 35 on the buffer electrode patterns 30. Forming the selection element patterns 35 may include performing an etch-back process. The selection element patterns 35 may also be formed in a bowl shape. The upper ends of the selection element patterns 35 may be located at the same or lower level as the upper ends of the holes H or the lower spacers 70 in the figure. For example, the upper ends of the selection element patterns 35 may be located in the holes H. [ In the etch-back process, the selection element patterns 35 can be minimally exposed to the etching gas. Therefore, degradation of the electrical and physical properties of the selection element patterns 35 can be minimized. In this process, a lower element LE including the lower electrode 20, the self-current control unit pattern 25, the buffer electrode pattern 30, and the selection element pattern 35 may be formed. The lower element LE can be confined by the lower spacer 70 in the hole H. [

16A and 16B, the method may include performing a deposition process to form the intermediate electrode material layer 40a on the select element patterns 35 and the lower interlayer dielectric layer 80. After the intermediate electrode material layer 40a is deposited, performing a CMP process. The intermediate electrode material layer 40a may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride Or a conductive material such as a metal alloy.

17A and 17B, the method includes depositing a memory material layer 45a, a reservoir material layer 50a, and an upper electrode material layer 55a on the intermediate electrode material layer 40a by performing a deposition process, And forming mask patterns M on the upper electrode material layer 55a. The memory material layer 45a may comprise a variable resistive material. For example, the memory material layer (45a) is a hafnium oxide (HfO _2), tantalum oxide (Ta ₂ O _5), titanium oxide (TiO _2), zirconium oxide-metal oxide, such as (ZrO), or zinc oxide (ZnO) , A phase change material such as GST (GeSbTe) or a chalcogenide material, a mechanical variable resistance material such as a conductive bridging material, or a memristor material. Memory material layer (45a) according to the technical features of the present invention may include a metal oxide such as hafnium oxide (HfO _2).

The reservoir material layer 50a may comprise a material capable of providing or storing oxygen atoms or oxygen ions. For example, the reservoir material layer 50a may comprise a metal such as tantalum or titanium.

The upper electrode material layer 55a may be formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride Or a conductive material such as a metal alloy.

The mask patterns M may comprise photoresist patterns or hard mask patterns. The hard mask patterns may include silicon nitride, silicon oxynitride, silicon containing carbon, or other inorganic materials. The mask patterns M may overlap vertically with the holes H.

18A and 18B, the method includes performing an etching process using the mask pattern M as an etch mask to form the upper electrode material layer 55a, the reservoir material layer 50a, the memory material layer 45a, And patterning the material layer 40a to form the intermediate electrodes 40, the memory patterns 45, the reservoir patterns 50, and the upper electrodes 55. [ The upper surfaces of the lower interlayer insulating layer 80 can be recessed. That is, the outer surfaces of the upper ends of the lower spacers 70 can be exposed. The mask pattern M can be removed. In the figure, the side surfaces of the intermediate electrode 40, the memory pattern 45, the reservoir pattern 50, and the upper electrode 55, and the inner walls of the holes H or the outer surface of the lower spacers 70 Are shown as vertically aligned, but this is ideal. In this process, an upper element UE including intermediate electrodes 40, memory patterns 45, reservoir patterns 50, and upper electrodes 55 may be formed. Therefore, the lower elements (LEs) including the lower electrodes 20, the self-current control unit patterns 25, the buffer electrode patterns 30, the selection element patterns 35, And memory cell stacks MC including upper elements UE including memory patterns 45, reservoir patterns 50, and upper electrodes 55 may be formed. 6A and 6B, the width of the upper element UE, including the intermediate electrode 40, the memory pattern 45, the reservoir pattern 50, and the upper electrode 55, W1 may be larger than the width W2 of the hole H. [ In this process, an etching gas with strong reactivity such as chlorine ion (Cl < " >) can be used. The etching gas having a strong reactivity may adversely affect the selection element pattern 35. [ For example, the chlorine ion (Cl < - >) may penetrate into the selection element pattern 35 or may combine with the selection element pattern 35 to lower the electrical characteristics of the selection element pattern 35. In the embodiment of the present invention, the selection element pattern 35 is not in contact with the etching gas. Therefore, according to the embodiment of the present invention, the selection element pattern 35 can maintain excellent electrical characteristics.

In the etching process, a halogen-based gas such as Cl ₂ may be used. Halogen gases such as Cl ₂ can degrade the electrical and physical properties of the selective element pattern 35 in particular. It is therefore preferable that the selection element pattern 35 is not exposed to the etching gas in the etching process for patterning the upper electrode 55, the reservoir pattern 50, the memory pattern 45, and the intermediate electrode 40 It is very important to maintain the electrical and physical properties of the device pattern 35 excellent. The selective element pattern 35 is not exposed in the etching process for patterning the upper electrode 55, the reservoir pattern 50, the memory pattern 45, and the intermediate electrode 40 according to an embodiment of the present invention Do not. In other words, the selective element pattern 35 is not attacked by the etching gas. Thus, the selection element patterns 35 having excellent electrical and physical properties can be obtained.

Referring to Figs. 19A and 19B, the method may include forming top spacers 75 on the sides of the top elements UE of the memory cell stacks MC. Forming the upper spacers 75 may include performing a deposition process to form a layer of insulating material covering the memory cell stacks MC and performing an etch-back process. The upper spacers 75 may have a cylindrical shape. For example, the upper spacers 75 may have a ring shape surrounding the sides of the memory cell stacks MC in a top view. The inner surfaces of the lower ends of the upper spacer 75 can contact the outer surfaces of the upper ends of the lower spacers 70. In another embodiment of the present invention, referring to Figures 6A and 6B, the upper spacer 75 and the lower space 70 may be spaced apart. That is, the lower interlayer insulating layer 80 may protrude between the inner surfaces of the lower ends of the upper spacer 75 and the upper surfaces of the upper ends of the lower spacers 70.

Referring to FIGS. 20A and 20B, the method may include forming an upper interlayer dielectric layer 85, and forming trenches T. Forming the upper interlayer insulating layer 85 may include forming a layer of an insulating material sufficiently covering the memory cell stacks MC and the upper spacers 75. [ For example, the layer of insulating material may comprise silicon oxide. The trenches T may vertically penetrate the upper interlayer insulating layer 85 to expose portions of the upper electrodes 55 and portions of the upper spacers 75. The trenches T may extend in the form of a line in the horizontal direction perpendicular to the lower conductive wirings 15 in the top view.

Referring to FIGS. 21A and 21B, the method can include forming the upper conductive interconnects 60 by filling conductive material in the trenches T. The conductive material may be a metal such as tungsten (W), aluminum (Al) or copper (Cu), a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), metal silicide or metal alloy And may include one or more of conductive materials. Forming the upper conductive interconnects 60 may include performing a deposition or plating process, the method including filling the trenches T, and performing a CMP process.

Thereafter, the method may include forming a capping insulating layer 65 on the upper conductive wirings 60 and the upper interlayer insulating layer 85, with reference to Figs. 3A and 3B. The capping insulating layer 65 may include a material that is more dense and harder than the upper interlayer insulating layer 85. For example, the capping insulating layer 65 may comprise silicon nitride or silicon oxynitride.

22A and 22B illustrate a top view conceptually showing top elements UE of memory cell stacks MC and top spacers 75 surrounding top elements UE according to various embodiments of the present invention. admit. 22A, in the top view, the upper element UE of the memory cell stack MC and the upper spacer 75 surrounding the upper element UE according to an embodiment of the present invention may be formed of rounded corners Or the like. 22B, in the top view, the upper element UE of the memory cell stack MC and the upper spacer 75 surrounding the upper element UE according to an embodiment of the present invention may have a circular shape have.

22C is a top view conceptually showing a lower element LE of a memory cell stack MC and a lower spacer 70 surrounding a lower element LE according to an embodiment of the present invention. Referring to FIG. 22C, the lower element LE of the molecular cell stack MC and the lower spacer 70 surrounding the lower element LE according to an embodiment of the present invention may have a circular shape. The outer peripheral surface of the lower spacer 70 may be the same as the width (or diameter) of the hole H. [

Figures 23A-23C are top views of the bottom elements LE and top elements UE of the memory cell stacks MC of the memory elements 100E-100G according to various embodiments of the present invention. 23A, the lower element LE of the memory cell stack MC of the memory element 100E according to an embodiment of the present invention may have a circular shape, and the upper element UE may have a rectangular shape, For example, a square shape having rounded corner portions. In addition, the width (or diameter) of the lower element LE and the width of the upper element UE may be the same in the first direction, for example, in the same horizontal or vertical direction. In detail, the maximum width (or diameter) of the lower element LE and the minimum width of the upper element UE can be the same. The width (or diameter) of the lower element LE in the second direction, for example, the oblique direction, may be less than the width of the upper element UE. 23B, the maximum width (or diameter) of the lower element LE of the memory cell stack MC of the memory element 100F according to an embodiment of the present invention is larger than the minimum width of the upper element UE Can be small. Referring to FIG. 23C, the lower element LE and the upper element UE of the memory cell stack MC of the memory element 100G according to an embodiment of the present invention may have a circular shape. For example, the lower element LE and the upper element UE may have a concentric shape. Further, the diameter of the lower element LE may be smaller than the diameter of the upper element UE. 23A to 23C, the lower element LE includes a lower electrode 20, a self-current control unit 25, a buffer electrode pattern 30, a selection element pattern 35, and / or a lower spacer 70 can do. The upper element UE may include an intermediate electrode 40, a memory pattern 45, a reservoir pattern 50, an upper electrode 55, and / or an upper spacer 75. For example, the width (or diameter) of the lower element LE may be equal to the width (or diameter) of the hole H or the width (or diameter) of the outer or inner peripheral surface of the lower spacer 70.

The semiconductor memory devices 100A-100G according to various embodiments of the present invention may be used in various electronic devices or electronic systems. 24 to 28 are electronic devices or electronic systems that include at least one of semiconductor memory devices 100A-100G according to various embodiments of the present invention.

Figure 24 is a block diagram conceptually illustrating a microprocessor including at least one of semiconductor memory devices 100A-100G according to various embodiments of the present invention. Referring to FIG. 24, the microprocessor 1000 according to an exemplary embodiment of the present invention can control and adjust a series of processes of receiving data from various external devices, processing the data, and transmitting the result to an external device And may include a storage unit 1010, an operation unit 1020, and a control unit 1030. The microprocessor 1000 may be any of a variety of devices such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP), an application processor Data processing apparatus. The storage unit 1010 may be a processor register, a register or the like and may store data in the microprocessor 1000 and may include a data register, an address register, a floating point register, And may include various registers. The storage unit 1010 may temporarily store data for performing operations in the operation unit 1020, addresses for storing execution result data, and data for execution. The storage unit 1010 may include one of the semiconductor memory devices 100A-100G according to various embodiments of the present invention. The operation unit 1020 can perform various arithmetic operations or logical operations according to the result of decoding the instruction by the control unit 1030. [ The operation unit 1020 may include one or more arithmetic and logic units (ALUs) and the like. The control unit 1030 receives a signal from a storage unit 1010, an operation unit 1020 and an external device of the microprocessor 1000 and performs extraction and decoding of the instruction and control of signal input / output of the microprocessor 1000 , And can execute the processing represented by the program. The microprocessor 1000 according to the present embodiment may further include a cache memory unit 1040 that can input data input from an external device or temporarily store data to be output to an external device. In this case, the cache memory unit 1040 can exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

25 is a block diagram conceptually illustrating a processor including at least one of semiconductor memory devices 100A-100G in accordance with various embodiments of the present invention. 25, the processor 1100 includes various functions in addition to the functions of a microprocessor for controlling and adjusting a series of processes of receiving and processing data from various external devices and sending the results to an external device Performance, and versatility. The processor 1100 includes a core unit 1110 serving as a microprocessor, a cache memory unit 1120 serving to temporarily store data, and a bus interface 1430 for transferring data between the internal and external devices . The processor 1100 may include various system on chips (SoCs) such as a multi core processor, a graphics processing unit (GPU), an application processor (AP) have. The core unit 1110 of the present embodiment is a part for performing arithmetic logic operations on data input from an external apparatus and may include a storage unit 1111, an operation unit 1112, and a control unit 1113. [ The storage unit 1111 may be a processor register, a register or the like and may store data in the processor 1100 and may include a data register, an address register, a floating point register, It may contain various registers. The storage unit 1111 may temporarily store an address in which data for performing an operation, execution result data, and data for execution in the operation unit 1112 are stored. The arithmetic operation unit 1112 performs arithmetic operations in the processor 1100. The arithmetic operation unit 1112 can perform various arithmetic operations and logical operations according to the result of decoding the instructions by the control unit 1113. [ The operation unit 1112 may include one or more arithmetic and logic units (ALUs) and the like. The control unit 1113 receives signals from a storage unit 1111, an operation unit 1112, an external device of the processor 1100, etc., extracts or decodes a command, controls signal input / output by the processor 1100, The processing represented by the program can be executed. The cache memory unit 1120 temporarily stores data to compensate for a difference in data processing speed between the core unit 1110 operating at a high speed and an external device operating at a low speed. The cache memory unit 1120 includes a primary storage unit 1121, A secondary storage unit 1122, and a tertiary storage unit 1123. In general, the cache memory unit 1120 includes a primary storage unit 1121 and a secondary storage unit 1122, and may include a tertiary storage unit 1123 when a high capacity is required. have. That is, the number of storage units included in the cache memory unit 1120 may vary depending on the design. Here, the processing speeds for storing and discriminating data in the primary, secondary, and tertiary storage units 1121, 1122, and 1123 may be the same or different. If the processing speed of each storage unit is different, the speed of the primary storage unit may be the fastest. One or more of the primary storage unit 1121, the secondary storage unit 1122 and the tertiary storage unit 1123 of the cache memory unit 1120 may be connected to the semiconductor memory devices 100A -100G). ≪ / RTI > 25 shows the case where the primary, secondary, and tertiary storage units 1121, 1122, and 1123 are all configured in the cache memory unit 1120, the primary, secondary, and tertiary storage units 1121, The tertiary storage units 1121, 1122, and 1123 are all formed outside the core unit 1110 to compensate for the difference in processing speed between the core unit 1110 and the external apparatus. Alternatively, the primary storage unit 1121 of the cache memory unit 1120 may be located inside the core unit 1110, and the secondary storage unit 1122 and the tertiary storage unit 1123 may be located inside the core unit 1110 So that the function of compensating the processing speed difference can be further strengthened. Alternatively, the primary and secondary storage units 1121 and 1122 may be located inside the core unit 1110, and the tertiary storage unit 1123 may be located outside the core unit 1110. The bus interface 1430 connects the core unit 1110, the cache memory unit 1120, and an external device, thereby enabling efficient transmission of data. The processor 1100 according to the present embodiment may include a plurality of core units 1110 and a plurality of core units 1110 may share the cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or may be connected through a bus interface 1430. The plurality of core portions 1110 may all have the same configuration as the core portion described above. When the processor 1100 includes a plurality of core units 1110, the primary storage unit 1121 of the cache memory unit 1120 includes a plurality of core units 1110 corresponding to the number of the plurality of core units 1110, And the secondary storage unit 1122 and the tertiary storage unit 1123 may be configured to be shared within the plurality of core units 1110 through a bus interface 1130. [ Here, the processing speed of the primary storage unit 1121 may be faster than the processing speed of the secondary and tertiary storage units 1122 and 1123. In another embodiment, the primary storage unit 1121 and the secondary storage unit 1122 are configured in the respective core units 1110 corresponding to the number of the plurality of core units 1110, and the tertiary storage unit 1123 May be configured to be shared by a plurality of core units 1110 via a bus interface 1130. [ The processor 1100 according to the present embodiment includes an embedded memory unit 1140 that stores data, a communication module unit 1150 that can transmit and receive data wired or wirelessly with an external apparatus, A memory control unit 1160, a media processing unit 1170 for processing data output from the processor 1100 or data input from an external input device to the external interface device, and the like. Modules and devices. In this case, a plurality of modules added to the core unit 1110, the cache memory unit 1120, and mutual data can be exchanged through the bus interface 1130. The embedded memory unit 1140 may include a nonvolatile memory as well as a volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), and a memory having a similar function. The nonvolatile memory may include a read only memory (ROM) , NAND flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), STTRAM (Spin Transfer Torque Random Access Memory), MRAM (Magnetic Random Access Memory) . The communication module unit 1150 may include a module capable of connecting with a wired network, a module capable of connecting with a wireless network, and the like. The wired network module may be a wired network module such as a LAN (Local Area Network), a USB (Universal Serial Bus), an Ethernet, a Mower Line Communication (PLC) ), And the like. The wireless network module may be implemented as an Infrared Data Association (IrDA), a Code Division Multiple Access (CDMA), a Time Division Multiple Access (CDMA), or the like, as well as various devices that transmit and receive data without a transmission line. (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID) , Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (WIBRO), High Speed Downlink Packet Access (HSDPA) Wideband CDMA (WCDMA), Ultra Wide Band (UWB), and the like. The memory control unit 1160 is used for processing and managing data transmitted between the processor 1100 and an external storage device operating according to a different communication standard. The memory control unit 1160 may include various memory controllers, for example, an IDE (Integrated Device Electronics) Such as Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Redundant Array of Independent Disks (RAID), Solid State Disk (SSD), External SATA (eSATA), Military Computer Memory Card International Association (PCMCIA) Universal Serial Bus, Secure Digital (SD), mini Secure Digital (mSD), micro Secure Digital (SD), Secure Digital High Capacity (SDHC) A Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC), an Embedded MMC (eMMC) When card (Compact Flash; CF) may include a controller for controlling the like. The media processing unit 1170 processes data processed by the processor 1100, data input from an external input device, video data, voice data, and the like, and outputs the data to the external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high definition audio (HD Audio), a high definition multimedia interface ) Controller and the like.

Figure 26 is a block diagram conceptually illustrating an electronic system including at least one of semiconductor memory devices 100A-100G according to various embodiments of the present invention. Referring to FIG. 26, the system 1200 is an apparatus for processing data, and can perform input, processing, output, communication, storage, and the like in order to perform a series of operations on data. The system 1200 may include a processor 1210, a main memory 1220, an auxiliary memory 1230, an interface device 1240, and the like. The system 1200 of the present embodiment may be a computer, a server, a PDA (Personal Digital Assistant), a portable computer, a web tablet, a wireless phone, a mobile phone A mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, Such as a voice recorder, a telematics, an audio visual system, a smart television, or the like. The processor 1210 can control the processing of the input instruction and the processing of the data stored in the system 1200. The microprocessor unit includes a microprocessor unit (MPU), a central processing unit (CPU) ), A single / multi core processor, a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like . The main storage unit 1220 is a storage unit that can move and store program codes and data from the auxiliary storage unit 1230 when the program is executed. The stored contents can be preserved even when the power is turned off. Main memory 1220 may include one of semiconductor memory devices 100A-100G according to various embodiments of the present invention. The main memory 1220 may further include volatile memory type static random access memory (SRAM), dynamic random access memory (DRAM), or the like, all of which are erased when the power is turned off. Alternatively, the main memory 1220 may be a static random access memory (SRAM) of a volatile memory type, a dynamic random access memory (DRAM), or the like, which does not include the semiconductor device of the above- And the like. The auxiliary storage device 1230 refers to a storage device for storing program codes and data. It is slower than main memory 1220 but can hold a lot of data. The auxiliary memory 1230 may include one or more of the semiconductor memory devices 100A-100G according to various embodiments of the present invention. The auxiliary storage device 1230 may be a magnetic tape, a magnetic disk, a laser disk using light, a magneto-optical disk using the two, a solid state disk (SSD), a USB memory (Universal Serial Bus Memory) USB memory, Secure Digital (SD), mini Secure Digital card (mSD), micro Secure Digital (micro SD), Secure Digital High Capacity (SDHC) A Smart Card (SM), a MultiMediaCard (MMC), an Embedded MMC (eMMC), a Compact Flash (CF) (See 1300 in FIG. 27). Alternatively, the auxiliary storage device 1230 may be a magnetic tape, a magnetic disk, a laser disk using light, a magneto-optical disk using both of them, a solid state disk (DVD) SSD), a USB memory (Universal Serial Bus Memory), a Secure Digital (SD) card, a mini Secure Digital card (mSD), a microSecure digital card (microSD) A Secure Digital High Capacity (SDHC), a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC), an Embedded MMC (eMMC ), Compact Flash (CF), and the like. The interface device 1240 may be for exchanging commands, data, and the like between the system 1200 and the external device of the present embodiment. The interface device 1240 may include a keypad, a keyboard, a mouse, a speaker, A microphone, a display, various human interface devices (HID), communication devices, and the like. The communication device may include a module capable of connecting with a wired network, a module capable of connecting with a wireless network, and the like. The wired network module may be a wired network module such as a LAN (Local Area Network), a USB (Universal Serial Bus), an Ethernet, a Mower Line Communication (PLC) ), And the like. The wireless network module may include various devices for transmitting and receiving data without a transmission line, such as an Infrared Data Association (IrDA), a Code Division Multiple Access (CDMA) (TDMA), a frequency division multiple access (FDMA), a wireless LAN, a Zigbee, a Ubiquitous Sensor Network (USN), a Bluetooth ), Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (WIBRO) , High Speed Downlink Packet Access (HSDPA), Wideband Code Division Multiple Access (WCDMA), Ultra Wide Band (UWB), and the like.

Figure 27 is a block diagram conceptually showing a data storage system including at least one of semiconductor memory devices 100A-100G according to various embodiments of the present invention. 27, the data storage system 1300 includes a storage device 1310 having a nonvolatile property for storing data, a controller 1320 for controlling the storage device 1310, an interface 1330 for connection to an external device, And temporary storage 1340 for temporary storage of data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read only memory (CDROM), a digital versatile disk (DVD), a solid state disk (USB) memory, Secure Digital (SD), mini Secure Digital card (mSD), microSecure digital card (micro SD), high capacity secure digital card Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC), Embedded MMC (eMMC) And may be in the form of a card such as a flash card (Compact Flash; CF). The storage device 1310 may include a non-volatile memory that semi-permanently stores the data. The nonvolatile memory includes a ROM (Read Only Memory), a NOR Flash Memory, a NAND Flash Memory, a PRAM (Mhase Change Random Access Memory), an RRAM (Resistive Random Access Memory), a MRAM . The controller 1320 may control the exchange of data between the storage device 1310 and the interface 1330. To this end, controller 1320 may include a processor 1321 that performs operations, such as operations, to process instructions entered via interface 1330 outside data storage system 1300. The interface 1330 is for exchanging commands, data, and the like between the data storage system 1300 and an external device. When the data storage system 1300 is a card, the interface 1330 may be a USB (Universal Serial Bus) memory, a Secure Digital (SD) card, a mini Secure Digital card (mSD) A micro SD card, a Secure Digital High Capacity (SDHC) card, a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC) Compatible with the interfaces used in devices such as a hard disk, an embedded MMC (eMMC), a compact flash (CF), or the like, or compatible with interfaces used in devices similar to these devices . When the data storage system 1300 is in the form of a disk, the interface 1330 may be an integrated device electronics (IDE), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), an external SATA (eSATA) Memory Card International Association), Universal Serial Bus (USB), and the like, or compatible with interfaces similar to these interfaces. Interface 1330 may be compatible with one or more interfaces having different types. The temporary storage device 1340 may temporarily store data in order to efficiently transfer data between the interface 1330 and the storage device 1310 in accordance with diversification and high performance of the interface with the external device, . The temporary storage device 1340 may include one or more of the semiconductor memory devices 100A-100G according to various embodiments of the present invention.

28 is a block diagram conceptually illustrating a memory system 1400 including at least one of semiconductor memory devices 100A-100G according to various embodiments of the present invention. 28, the memory system 1400 includes a memory 1410 having a nonvolatile characteristic, a memory controller 1420 for controlling the memory 1420, an interface 1430 for connecting to an external device, and the like, . The memory system 1400 may be a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a secure digital (SD), a mini Secure Digital card (mSD) ), A microsecure digital card (micro SD), a secure digital high capacity (SDHC), a memory stick card, a smart media card (SM), a multi media Card, an MMC, an embedded MMC (eMMC), and a compact flash (CF) card. Memory 1410 for storing data may include one or more of the semiconductor memory devices 100A-100G according to various embodiments of the present invention. In addition, the memory of the present embodiment may be a non-volatile memory such as a ROM (Read Only Memory), a NOR Flash Memory, a NAND Flash Memory, a PRAM (Phase Change Random Access Memory), an RRAM (Resistive Random Access Memory) Memory) and the like. Memory controller 1420 may control the exchange of data between memory 1410 and interface 1430. [ To this end, the memory controller 1420 may include a processor 1421 for processing instructions entered through the interface 1430 outside the memory system 1400. The interface 1430 is for exchanging commands and data between the memory system 1400 and an external device and includes a USB (Universal Serial Bus), a Secure Digital (SD) card, a mini Secure Digital card (mSD), microsecure digital card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), MultiMediaCard Compatible with interfaces used in devices such as a MultiMediaCard (MMC), an embedded MMC (eMMC), a Compact Flash (CF), and the like, It can be compatible with the interface used. Interface 1430 may be compatible with one or more interfaces having different types. The memory system 1400 of the present embodiment includes a buffer memory (not shown) for efficiently transmitting and receiving data between the interface 1430 and the memory 1410 in accordance with diversification and high performance of an interface with an external device, a memory controller, 1440). The buffer memory 1440 for temporarily storing data may include one or more of the semiconductor memory elements 100A-100G according to various embodiments of the present invention. In addition, the buffer memory 1440 of the present embodiment may be a static random access memory (SRAM) having a characteristic of being volatile, a dynamic random access memory (DRAM), a read only memory (ROM) having nonvolatile characteristics, a NOR flash memory, A flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer random access memory (STTRAM), and a magnetic random access memory (MRAM). Alternatively, the buffer memory 1440 may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and a read only memory (ROM) having nonvolatile characteristics, instead of the semiconductor device of the above- Memory, a NOR flash memory, a NAND flash memory, a PRAM (Phase Change Random Access Memory), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM) have.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100, 100A-100G: semiconductor memory device
10: Lower layer
15: Lower conductive wiring
20: Lower electrode
25: Self-current control unit pattern
30: buffer electrode pattern
30a: buffer electrode material layer
35: Selective element pattern
35a: Selective device material layer
40: intermediate electrode
40a: intermediate electrode material layer
45: Memory pattern
45a: memory material layer
50: Leisure pattern
50a: reservoir material layer
55: upper electrode
55a: upper electrode material layer
60: upper conductive wiring
65: capping insulating layer
70: Lower spacer
75: upper spacer
M: mask pattern
MC: Memory cell stack
LE: Lower element
UE: upper element
ILD1: Lower interlayer insulating layer
ILD2: upper interlayer insulating layer
T: Trench
H: hole

Claims (20)

A lower interlayer insulating layer having a hole;
An upper interlayer insulating layer on the lower interlayer insulating layer; And
A memory cell stack including a lower element localized in the hole of the lower interlayer insulating layer and an upper element surrounded by the upper interlayer insulating layer,
Wherein the lower element includes a lower electrode and a selection element pattern on the lower electrode,
The upper element including a memory pattern on the select element pattern, and an upper electrode on the memory pattern.
The semiconductor device according to claim 1,
An upper spacer on the outer surface of the upper element,
Further comprising a lower spacer on the inner wall of the hole,
Wherein the lower element is confined by the lower spacer.
3. The method of claim 2,
Wherein the outer surface of the upper portion of the lower spacer and the inner surface of the lower portion of the upper spacer are in contact with each other.
3. The method of claim 2,
The lower spacer is disk shaped in top view, and
Wherein the upper spacer is shaped like a disk or polygonal ring in the top view.
The method according to claim 1,
The hole is circular in top view, and
Wherein the upper element is rectangular in shape with rounded corners in the top view.
The method according to claim 1,
Wherein the lower element further comprises a lower portion of the intermediate electrode between the selection element pattern and the memory pattern,
And the lower portion of the intermediate electrode protrudes downward to be positioned in the hole.
The method according to claim 6,
Wherein the upper element further comprises an upper portion of the intermediate electrode, and
And an upper portion of the intermediate electrode has a flat upper surface.
The method according to claim 1,
Wherein the upper element further comprises a reservoir pattern between the memory pattern and the upper electrode,
Wherein the reservoir pattern comprises a metal or a metal oxide.
The method according to claim 1,
Wherein the lower element further comprises a self-current control unit pattern between the lower electrode and the selection element pattern, and
Wherein the self-current control unit pattern comprises a metal oxide.
10. The method of claim 9,
Wherein the lower element further comprises a buffer electrode pattern between the self-current control unit pattern and the selection element pattern, and
Wherein the buffer electrode pattern comprises at least one of a metal, a metal compound, a metal silicide, or a metal alloy.
11. The method of claim 10,
Wherein the self-current control unit pattern and the buffer pattern have a bowl shape having an upper surface concave at the center.
The method according to claim 1,
Wherein the selection element pattern has a bowl shape having a concave upper surface at a central portion thereof.
The method according to claim 1,
Wherein a horizontal width of the upper element is greater than a horizontal width of the lower element. The method according to claim 1,
The electronic device further includes a processor,
The processor comprising:
A control unit that receives a signal including an instruction from outside the processor, and extracts or decodes an instruction or performs input / output control of a signal of the processor;
An operation unit for performing an operation according to a result of decoding the instruction by the control unit; And
And a storage unit for storing data for performing an operation, data corresponding to a result of performing the operation, or addresses of data for performing the operation,
And the storage section includes the semiconductor memory element.
The method according to claim 1,
The electronic device further includes a processing system,
The processing system comprising:
A processor for interpreting a received command and controlling an operation of information according to a result of interpreting the command;
A program for interpreting the command and an auxiliary memory for storing the information;
A main memory for moving and storing the program and the information from the auxiliary memory so that the processor can perform the calculation using the program and the information when the program is executed; And
And an interface device for performing communication with at least one of the processor, the auxiliary memory device, and the main memory device,
Wherein either the auxiliary memory device or the main memory device includes the semiconductor memory device.
The method according to claim 1,
The electronic device further includes a data storage system,
The data storage system comprising:
A storage device for storing data and storing the stored data irrespective of a supplied power source;
A controller for controlling data input / output of the storage device according to an instruction input from the outside;
A temporary storage device for temporarily storing data exchanged between the storage device and the outside; And
And an interface for performing communication with at least one of the storage device, the controller, and the temporary storage device,
Wherein either the storage device or the temporary storage device comprises the semiconductor memory device.
A lower interlayer insulating layer having a hole;
A lower spacer in the hole of the lower interlayer insulating layer;
A lower pillar defined by said lower spacer in said hole;
An upper pillars on the lower pillars;
An upper spacer on a sidewall of the upper pillar; And
And an upper interlayer insulating layer surrounding the upper spacer on the lower interlayer insulating layer,
The lower pillar includes a lower electrode and a selection device pattern on the lower electrode,
Wherein the upper pillar includes a memory pattern and an upper electrode on the memory pattern,
Wherein the horizontal width of the upper pillars is larger than the horizontal width of the lower pillars.
18. The method of claim 17,
Wherein the lower pillar further comprises a self-current control unit pattern and a buffer electrode pattern between the lower electrode and the selection element pattern,
Wherein the upper pillar further comprises an intermediate electrode between the select element pattern and the memory pattern of the lower pillar and a reservoir pattern between the memory pattern and the upper electrode.
19. The method of claim 18,
Wherein the self-current control unit pattern, the buffer electrode pattern, and the selection element pattern have a bowl shape whose top surface is concave.
18. The method of claim 17,
The outer side wall of the lower spacer and the inner side of the upper spacer are vertically flat,
Wherein the lower spacer and the upper spacer are spaced apart, and
Wherein the lower interlayer insulating layer has a rim-like protrusion between the lower spacer and the upper spacer.

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