KR20190049126A - Package of electromechanical devices and method thereof - Google Patents

Abstract

A method of manufacturing a package of electromechanical devices comprises the following steps of: (a) depositing a lower sacrificial layer on the top of a first passivation layer on the top of a substrate; (b) etching a portion of the lower sacrificial layer, and forming a metal layer by embedding the remainder of the lower sacrificial layer; (c) forming an electromechanical device by machining the metal layer; (d) depositing a second passivation layer on the top of the electromechanical device to form an active region of the electromechanical device; and (f) forming a through hole on the second passivation layer to remove the lower sacrificial layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an electromechanical device package,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electromechanical device packaging technique, and more particularly, to an electromechanical device package capable of realizing an electromechanical device package capable of three-dimensional integration on a semiconductor chip at a high degree of integration and a method of manufacturing the same.

The area of the chip is continuously being reduced due to the continuous development of the technology to implement the reconfiguration logic of the semiconductor. However, there is a problem in that performance decreases, yield decreases, increase in metal wiring layer, and heat loss are caused by such area decrease. In order to overcome this problem, three-dimensional integration between transistors and other devices has been studied. Among them, CMOS-NEM reconfiguration logic has advantages such as low energy consumption, low manufacturing cost, and high integration.

1 is a schematic diagram illustrating the three-dimensional integration of CMOS (Complementary Metal-Oxide Semiconductor) -NEM (Nano ElectroMechanical) -based reconfiguration logic presented in the prior art.

In FIG. 1, the prior art can form a beam and an electrode, which are components of an electromechanical device, by cutting a pre-formed metal wiring layer using a Focus Ion Beam technique. Thereafter, a discharge process of the sacrificial layer is required to form a blank space for the mechanical operation of the NEM device in the CMOS-NEM reconfiguration logic, and this discharge process is performed using vapor HF etching at the end of the process to cover the electromechanical structure Intermetal dielectric (IMD) can be removed. However, the prior art has a disadvantage in that the IMD and the metal interconnection layer are structurally unstable due to the possibility of structural collapse due to damage to the IMD and the metal interconnection layer in this process.

Korean Patent No. 10-0884260 relates to a method of packaging a microelectromechanical system element and a package thereof, and a method of packaging a microelectromechanical system element comprises the steps of: (a) forming a microelectromechanical system (MEMS) (B) forming a porous anodic oxide layer on the sacrificial layer; (c) forming a sacrificial layer on the sacrificial layer through a plurality of pores formed in the porous anodic oxide layer; And (d) forming a shielding layer on the etched sacrificial layer.

Korean Patent Laid-Open Publication No. 10-2017-0064188 relates to a packaging method of an electric element, which comprises: forming a bonding material on a part of a lower surface of a cap manufactured in advance; Bonding the cap to the device wafer on which the electronic device is mounted; bonding the liquid adhesive material to the fine gap so that the liquid adhesive material penetrates into the minute gap formed between the cap and the device wafer; And a curing step of curing the liquid adhesive material filled in the fine gap.

1. Korean Patent No. 10-0884260 2. Korean Patent Publication No. 10-2017-0064188

An embodiment of the present invention is to provide an electromechanical device package capable of realizing an electromechanical device package capable of three-dimensional integration on a semiconductor chip at a high degree of integration, and a method of manufacturing the same.

One embodiment of the present invention is a method of vacuum packaging an active area for the operation of an electromechanical device between metallization layers to produce an electromechanical device package capable of fabricating an electromechanical device package within a specific area of one metal layer without affecting the other metal layer Mechanical device package and a method of manufacturing the same.

One embodiment of the present invention relates to an electromechanical device package capable of manufacturing an electromechanical device package based on TEOS (Tetraethyl orthosilicate) used in a back end of a CMOS process, Method.

An embodiment of the present invention is to provide an electromechanical device package capable of realizing a high degree of directivity with a metal wiring layer lower than an existing semiconductor chip and a method of manufacturing the same.

An embodiment of the present invention is to provide an electromechanical device package and a method of manufacturing the same that can utilize a conventional CMOS process and can be manufactured at low cost with high compatibility.

An embodiment of the present invention is to provide an electromechanical device package capable of implementing a structurally stable CMOS (Complementary Metal-Oxide Semiconductor) -NEM (Nano ElectroMechanical) reconfiguration logic and a method of manufacturing the same.

An embodiment of the present invention seeks to provide an electromechanical device package and a method of manufacturing the same that can implement a vacuum packaging that protects electromechanical elements from physical or chemical external environmental factors.

In embodiments, a method of manufacturing an electromechanical device package includes the steps of: (a) depositing a lower sacrificial layer on top of a first passivation layer on top of a substrate; (b) etching a portion of the lower sacrificial layer, (C) forming the electromechanical device by machining the metal layer; (d) forming an upper portion of the electromechanical device by etching the upper portion of the electromechanical device Depositing a second passivation layer on the second passivation layer; and (f) forming a through hole in the second passivation layer to remove the lower sacrificial layer.

The step (a) may include etching a part of the insulating layer formed as an interlayer insulating layer on the substrate, and depositing the first passivation layer on the etched insulating layer.

The first passivation layer may be formed on the transistor metallization layer connected to the transistor.

The first passivation layer may be composed of aluminum oxide having a corrosion resistance to steam HF etching of not less than a first reference value and a selectivity ratio to the lower sacrificial layer and the vapor HF etching not less than a second reference value.

The step (b) includes etching both ends of the center portion of the lower sacrificial layer to expose the center portion of the lower sacrificial layer, and depositing the metal layer on the upper portion of the first passivation layer so as to surround the central portion of the exposed lower sacrificial layer Step < / RTI >

Wherein the step (c) comprises patterning or ion beam processing an upper region of the metal layer in contact with the remainder of the lower sacrificial layer to form a conductive beam line spaced from the first passivation layer on the same vertical plane, And forming the electromechanical element including mutually opposing electrodes on both sides.

(D) depositing a top sacrificial layer on top of the electromechanical device to bring the top sacrificial layer and the bottom sacrificial layer into contact with each other, and (d-2) And depositing the second passivation layer on the top sacrificial layer such that the remainder of the top sacrificial layer is buried.

The step (f) may include etching the upper and lower sacrificial layers through the through-holes to form the active region for mechanically switching the electromechanical device.

The step (f) may include forming the active region through a vapor HF etching process.

(G) depositing a shielding layer on top of the second passivation layer to package the active region formed through removal of the lower sacrificial layer in a vacuum or a vacuum state can do.

The step (g) may include depositing the shielding layer at a deposition rate higher than a third reference value through a sputtering process so that the constituent material of the shielding layer does not flow into the active region.

In embodiments, a method of manufacturing an electromechanical device package includes the steps of: (a) depositing a lower sacrificial layer on top of a first passivation layer formed on a substrate, forming an electromechanical device on top of the lower sacrificial layer, (b) depositing a top sacrificial layer on top of the electromechanical device in contact with the bottom sacrificial layer, and depositing a second passivation layer on top of the top sacrificial layer; and (f) Forming a through hole in the first layer and removing the upper and lower sacrificial layers through the through hole to form an active region of the electromechanical device.

In embodiments, the electromechanical device package includes a substrate, a sacrificial layer formed on the substrate at the top of the substrate to remove the sacrificial layer, and a conductive beam line formed in the active region spaced apart from the substrate, And a first and a second passivation layers formed on lower and upper portions of the metal layer to fill the metal layer.

The disclosed technique may have the following effects. It is to be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, as it is not meant to imply that a particular embodiment should include all of the following effects or only the following effects.

An electromechanical device package and a manufacturing method thereof according to an embodiment of the present invention can realize an electromechanical device package capable of three-dimensional integration on a semiconductor chip with high degree of integration.

An electromechanical device package and a method of manufacturing the same according to an embodiment of the present invention can be achieved by vacuum-packaging an active area for operation of an electromechanical device between metallization layers to form a metal film in a specific region of one metal layer An electromechanical device package can be manufactured.

An electromechanical device package and a manufacturing method thereof according to an embodiment of the present invention can manufacture an electromechanical device package based on TEOS (Tetraethyl orthosilicate) used in a back end of a CMOS process, .

The electromechanical device package and the method of manufacturing the same according to an embodiment of the present invention can realize a high degree of directivity with a metal wiring layer lower than a conventional semiconductor chip.

The electromechanical device package and the manufacturing method thereof according to an embodiment of the present invention can use a conventional CMOS process and can be manufactured at low cost with high compatibility.

The electromechanical device package and the method of fabricating the same according to an embodiment of the present invention can realize a structurally stable CMOS (complementary metal-oxide semiconductor) -NEM (Nano ElectroMechanical) reconfiguration logic.

An electromechanical device package and a manufacturing method thereof according to an embodiment of the present invention can realize a vacuum packaging that protects electromechanical elements from physical or chemical external environmental factors.

1 is a schematic diagram illustrating the three-dimensional integration of CMOS (Complementary Metal-Oxide Semiconductor) -NEM (Nano ElectroMechanical) -based reconfiguration logic presented in the prior art.
2 is a process diagram illustrating a method of manufacturing an electromechanical device package according to an embodiment of the present invention.
3 is a schematic diagram illustrating the three-dimensional integration of the CMOS-NEM reconstruction logic in accordance with one embodiment of the method of manufacturing the electromechanical device package illustrated in FIG.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas. Also, the purpose or effect of the present invention should not be construed as limiting the scope of the present invention, since it does not mean that a specific embodiment should include all or only such effect.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms " first ", " second ", and the like are intended to distinguish one element from another, and the scope of the right should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected to the other element, but there may be other elements in between. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that there are no other elements in between. On the other hand, other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

It is to be understood that the singular " include " or " have " are to be construed as including the stated feature, number, step, operation, It is to be understood that the combination is intended to specify that it does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In each step, the identification code (e.g., a, b, c, etc.) is used for convenience of explanation, the identification code does not describe the order of each step, Unless otherwise stated, it may occur differently from the stated order. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used predefined terms should be interpreted to be consistent with the meanings in the context of the related art and can not be interpreted as having ideal or overly formal meaning unless explicitly defined in the present application.

2 is a process diagram illustrating a method of manufacturing an electromechanical device package according to an embodiment of the present invention. More specifically, Fig. 2 shows a specific cross-section for an electromechanical device package centered on a mechanical switching operating region, such as the A-A 'cross section shown in Fig.

Hereinafter, an embodiment of an electromechanical device package manufacturing method for manufacturing an electromechanical device package will be described with reference to the electromechanical device package shown in Fig.

2A to 2D schematically show a process of forming a lower sacrificial layer in the process of manufacturing an electromechanical device package.

In FIG. 2A, a substrate 205 is prepared and an insulating layer 210 may be laminated to the substrate 205. In one embodiment, the insulation layer 210 may correspond to a silicon oxide (SiO _2).

In one embodiment, the substrate 205 may correspond to a substrate comprising integrated circuits fabricated in a CMOS (Complementary Metal-Oxide Semiconductor) process. More specifically, the substrate 205 includes at least one transistor element formed on a silicon substrate before the process, and an element layer including an inter-layer dielectric (ILD) deposited on the transistor element And at least one intermediate layer formed on top of the device layer and including an intermediate metal layer, a middle via contact, and an inter-metal dielectric (IMD) layer. At this time, the insulating layer 210 may be deposited as an interlayer insulating layer on the intermediate layer or the upper portion of the device layer, and the first via contact 215 may include an intermediate metal layer located at a lower portion and an insulating layer 210 May be etched and deposited by via contact material. In another embodiment, the substrate 205 corresponds to a bulk silicon substrate, and the insulating layer 114 may correspond to a buried oxide (BOX) deposited on the substrate 205.

Hereinafter, for the sake of convenience, it is assumed that the substrate 205 includes an element layer including a formed transistor and a lower insulating film, and the insulating layer 210 corresponds to an interlayer insulating film formed on the element layer.

In FIG. 2B, the insulating layer 210 may be etched to form holes as voids for forming electromechanical elements, and in one embodiment, etched to a width and depth determined based on the unit size of the electromechanical element .

In FIG. 2C, the first passivation layer 220 may be formed on top of the insulating layer 210. In one embodiment, the first passivation layer 220 may be deposited as an interlayer insulating film on top of the substrate 205 and thinly deposited on a partially etched insulating layer 210 below a certain reference thickness. In one embodiment, the first passivation layer 220 may be formed on a lower metal layer connected to the transistor elements, and may be connected to the lower metal layer via the insulating layer 210.

In one embodiment, the first passivation layer 220 may be deposited through an Atomic Layer Deposition (ALD) process and may correspond to aluminum oxide (Al ₂ O ₃ ). In one embodiment, the first passivation layer 220 is formed of aluminum oxide having a corrosion resistance to vapor HF etching of at least a first reference value and a selectivity to a lower sacrificial layer 225 and a vapor HF etch of at least a second reference value Lt; / RTI > That is, it is preferable that a material having a corrosion resistance and a wear resistance higher than a reference value is used in the deposition process of the first passivation layer 220. At this time, the first and second reference values may be set by a designer.

In FIG. 2d, a lower sacrificial layer 225 may be deposited on top of the first passivation layer 220 at the top of the substrate 205. In one embodiment, the lower sacrificial layer 225 is deposited on the first passivation layer 220 by plasma enhanced chemical vapor deposition (" Plasma ") as a sacrificial layer for etching the region in a later step for the fabrication of the electromechanical device -enhanced Chemical Vapor Deposition (PECVD) process, and the deposition thickness can be adjusted according to the unit size of the electromechanical device and the distance from the packed layer. In one embodiment, the lower sacrificial layer 225 may correspond to silicon oxide.

In one embodiment, the first passivation layer 220 may be partially etched for connection between the bottom metal layer and the top metal layer prior to formation of the bottom sacrificial layer 225. More specifically, the first passivation layer 220 may be partially etched to contact the first via contact 215 to expose the upper surface of the first via contact 215, A part of the metal layer 230 and the upper surface of the first via contact 215 are brought into contact with each other and interconnected when the remainder of the etched lower sacrificial layer 225 is buried in the metal layer 230.

2E to 2F schematically illustrate the process of forming the metal layer 230 during the process of manufacturing the electromechanical device package.

In FIG. 2E, the lower sacrificial layer 225 may be partially etched, and in FIG. 2F, the remainder may be buried to form the metal layer 230. In one embodiment, the lower sacrificial layer 225 may be etched at both ends of its center to expose its center portion, and the first passivation layer 220 may be formed to surround the central portion of the exposed lower sacrificial layer 225, A metal layer 230 may be deposited on top of the metal layer 230. More specifically, the lower sacrificial layer 225 is etched at both ends or edge regions so as to have a width and a length within a specific reference range based on the central portion in consideration of the unit size of the electromechanical device and the operation range for the mechanical switch And the metal layer 230 may be deposited on top of the first passivation layer 220 such that the remainder of the lower sacrificial layer 225 is buried except for the etched region. In one embodiment, the metal layer 230 may correspond to aluminum (Al). In one embodiment, the metal layer 230 may be in contact with the upper surface of the first via contact 215 and the lower surface of the opposite ends, respectively, through this process, as previously described.

FIG. 2G schematically shows a process of forming an electromechanical device in an electromechanical device package manufacturing process.

The metal layer 230 can form an electromechanical element through processing. In one embodiment, the metal layer 230 may be patterned or topped with an electron beam or ion beam to contact the remainder of the lower sacrificial layer 225 to form a first passivation layer 220 The electromechanical device including the conductive beam line 230a spaced apart and the electrodes 230b and 230c facing each other on both sides of the conductive beam line 230a can be formed. In one embodiment, the metal layer 230 is scanned through the focused ion beam process to focus the focused ion beam onto the upper surface of the lower sacrificial layer 225 to form two perforated holes thereon And a portion of the upper surface of the lower sacrificial layer 225 may be exposed through the through holes. Through this process, the first passivation layer 220 and the lower sacrificial layer 225 may be formed on a specific vertical surface A conductive beam line 230a spaced apart from the electrodes 230b and 230c may be formed. In one embodiment, the metal layer 230 may be patterned through a photoetching process, such as imprint lithography, or may simultaneously generate the conductive beam line 230a and the electrodes 230b and 230c through a nano-plasma process.

In one embodiment, each of the opposing electrodes 230b, 230c on opposite sides of the conductive beam line 230a extend along the surface of the first passivation layer 220 in opposite mutually opposite directions, Contact 215 and may be formed to include at least one bending region for contact with the first via contact 215 located on a different horizontal plane.

Figures 2h to 2i schematically illustrate the process of forming the upper sacrificial layer 235 during the fabrication of the electromechanical device package.

In Fig. 2H, an upper sacrificial layer 235 may be deposited on top of the electromechanical element and contacted with the lower sacrificial layer 125. In one embodiment, top sacrificial layer 235 is deposited over the top of the electromechanical device such that at least some of the pre-formed conductive beam line 230a and electrodes 230b, 230c are buried through previous steps, And can be deposited into the two through holes formed in the metal layer 230 and contacted at the top and bottom of the bottom sacrificial layer 125. [ In one embodiment, upper sacrificial layer 235 may correspond to silicon oxide as the same material as lower sacrificial layer 125. The upper sacrificial layer 235 may be stacked and then planarized through a CMP (Chemical Mechanical Polishing) process.

2I, the upper sacrificial layer 235 may be partially etched. In one embodiment, the upper sacrificial layer 235 may be etched to expose portions of the upper portions of the upper sacrificial layer 235 that are in contact with the upper surfaces of the electrodes 230b and 230c so that the upper sacrificial layer 235 extends without the lower portion and the curved surface. In one embodiment, the top sacrificial layer 235 may have a width that is within a certain reference range, in consideration of the unit size of the electromechanical device and the operating range for the mechanical switch for forming the active area 245 of the electromechanical device A part of the both ends may be etched so as to have a predetermined width. The distance between the mechanical switch region of the electromechanical device and the second passivation layer 240 at the top when the active region 245 is formed at a later stage depending on the thickness of the upper sacrificial layer 235, May be formed differently, and this thickness may be adjusted according to the target size of the switch.

FIGS. 2J to 2L schematically show a process in which the second passivation layer 240 is formed and the lower sacrificial layer 225 is removed during the process of manufacturing the electromechanical device package.

2J, a second passivation layer 240 may be deposited on top of the electromechanical device to form the active region 245 of the electromechanical device. In one embodiment, the second passivation layer 240 may be deposited on the top sacrificial layer 235 such that once a portion of the top sacrificial layer 235 is etched, the remainder may be deposited, And can be deposited on the area to be protected. In one embodiment, the second passivation layer 240 may be deposited via an atomic layer deposition process and may be the same material as the first passivation layer 220, for example, can do. The second passivation layer 240 may be deposited and then planarized through a CMP process.

In FIG. 2K, the second passivation layer 240 may form through holes 240a and 240b for removing the lower sacrificial layer 225. In one embodiment, the second passivation layer 240 is formed by removing the upper and lower sacrificial layers 235 and 225 in the upper region that is in contact with the upper surface of the upper sacrificial layer 235, And at least one through hole 240a and 240b for forming the through holes 240a and 240b and fine patterning the through holes 240a and 240b so as to have a width within a specific reference width, The shielding layer 250 can be prevented from flowing into the active region 245 when the shielding layer 250 is stacked on top of the active regions 241 and 240b.

In one embodiment, the second passivation layer 240 may be patterned together with a portion of the second passivation layer 240 at a location corresponding to the first via contact 215 located at the bottom during the formation of the through-holes 240a and 240b , The patterned region may be utilized as a space for forming the second via contact 255 in a subsequent step.

In FIG. 21, the lower sacrificial layer 225 may be removed through the through holes 240a and 240b formed in the second passivation layer 240. FIG. In one embodiment, the upper and lower sacrificial layers 235, 225 that are in contact with each other may be etched through the through-holes 240a, 240b to form an active region 245 for the electromechanical device to mechanically switch . In one embodiment, the upper and lower sacrificial layers 235, 225 may be selectively removed through a vapor HF etch process to form the active region 245. In this removal process, the removal efficiency of the residue can be improved in consideration of the selectivity between the sacrificial layers and the materials forming the first and second passivation layers 220 and 240. Accordingly, the conductive beam line 230a having the active region 245 formed therein is structured such that the lower portion thereof is not supported by the first passivation layer 220, so that the conductive beam line 230a can be flexibly bent during the switching process.

In one embodiment, the upper and lower sacrificial layers 235 and 225 may be etched according to the following formula (1). More specifically, the upper and lower sacrificial layers 235 and 225 are formed by depositing the first and second passivation layers 220 and 240 and the vapor HF The selectivity for etching may be less than the second reference value, and thus may be etched in response to HF. On the other hand, the first passivation layer 220 and the second passivation layer 240 are formed of a material having a durability, corrosion resistance, and abrasion resistance higher than a reference value to HF injected during the etching process, Can be protected.

[Chemical Formula 1]

SiO ₂ + 4HF? SiF ₄ (g) + 2H ₂ O

When the active region 245 is formed according to the above embodiments, the conductive beam line 230a may be spaced apart from the first passivation layer 220 located below to form a cavity for mechanical switching. More specifically, one end of the conductive beam line 230a for mechanical switching is spaced apart from the first passivation layer 220 at the bottom thereof, as shown in FIG. 21, and the electrodes 230b and 230c at both sides And the other end may contact the first passivation layer 220 through the beam including a beam supporting the load as a horizontal structural member, although not shown in FIG.

In one embodiment, the active region 245 may be packaged with the shielding layer 250 stacked on top such that the interior is in a vacuum, vacuum, or vacancy state, and in another embodiment, a nitrogen gas or an inert gas The shielding layer 250 may be stacked on the upper portion of the substrate 210 and then may be packaged.

2M-2O schematically illustrate the process of forming the shield layer 250 and the second via contact 255 during the process of manufacturing the electromechanical device package.

2M, a shield layer 250 may be deposited on top of the second passivation layer 240 to package the active region 245 formed through removal of the bottom sacrificial layer 225 in a vacuum or in a vacuum state . More specifically, the shield layer 250 may be formed on top of the second passivation layer 240 to seal the active region 245 in a vacuum or a pneumatic state, and may be formed by sputtering or ion implantation processes, Through the through holes 240a and 240b formed at a width equal to or less than the width of the through holes 240a and 240b. In one embodiment, the shield layer 250 may be deposited at a deposition rate above a third reference value through a sputtering process so that its constituent materials do not enter the active region 245. In one embodiment, the shielding layer 250 may correspond to a silicon oxide having a high strength and a property of being easier to deposit than a common metal, and thus can withstand pressure due to the pressure difference between the inside and the outside of the package have.

In Figure 2n, the shield layer 250 may be etched in a portion corresponding to the underlying first via contact 215 and the etched region may be etched in the second passivation layer 240 As a patterned region of the second via contact 255 in a later step.

2O, the second via contact 255 is formed in a portion of the shielded layer 250 that is etched to correspond to the underlying first via contact 215 and in a portion of the second passivation layer 240 Can be deposited. In one embodiment, the second via contact 255 may correspond to a material that is different or the same as the via contact material of the first via contact 215.

The method of manufacturing an electromechanical device package according to an embodiment of the present invention can manufacture an electromechanical device package in a specific region of one metal layer without affecting other metal layers, It is possible.

The method of manufacturing an electromechanical device package according to an embodiment of the present invention can manufacture an electromechanical device package based on TEOS (Tetraethyl orthosilicate), which is mainly used in a back end of a CMOS process, .

The method of fabricating an electromechanical device package according to an embodiment of the present invention can implement a field programmable gate array (FPGA) for low power, high integration, and high performance.

The method of fabricating an electromechanical device package according to an embodiment of the present invention can implement a memory / non-memory capable of low off state current and low standby power by three-dimensionally integrating a CMOS base line device using an electromechanical device Do.

The method of manufacturing an electromechanical device package according to an embodiment of the present invention can be implemented to have high durability insensitive to the external environment by vacuum packaging the active region of the electromechanical device.

3 is a perspective view showing the structure of an electromechanical device package manufactured in accordance with an embodiment of the method of manufacturing an electromechanical device package illustrated in FIG.

Referring to FIG. 3, an electromechanical device package 300 includes a substrate 205, a metal layer 230, and first and second passivation layers 220 and 240.

The metal layer 230 is removed from the substrate 205 by removing the sacrificial layer (including at least one of the lower sacrificial layer 225 and the upper sacrificial layer 235) And an electromechanical device consisting of a conductive beam line 230a formed in the active region 245 spaced apart and electrodes 230b and 230c facing each other on both sides of the conductive beam line 230a.

The conductive beam line 230a is spaced apart from the first and second passivation layers 220 and 240 through the sacrificial layer removal to form a barrier layer 230a that is directed toward one of the electrodes 230b and 230c during the mechanical switching process of the electromechanical device. It can be bent. More specifically, when the electrostatic force is generated between one of the electrodes 230b and 230c during the switching process, the conductive beam line 230a may be bent, and the voltage difference between the electrodes 230b and 230c When the switching process is started based on the generated electrostatic force, an electrical path between the conductive beam line 230a and the electrodes 230b and 230c can be generated or changed.

The electrodes 230b and 230c are horizontally opposed to each other with respect to the conductive beam line 230a, and they may be applied with different voltages during the switching process.

The first and second passivation layers 220 and 240 are formed under and over the metal layer 230 to fill the metal layer 230.

In one embodiment, the electromechanical device package 300 can be fabricated in a specific area of one metal layer without affecting other metal layers, and can be three-dimensionally integrated with high density on existing semiconductor chips.

In one embodiment, the electromechanical device package 300 is capable of structurally and stably manufacturing an active area 245 of an electromechanical device without damaging the IMD and metallization layer, as compared to the prior art shown in FIG. 1 There is an advantage.

Although the electro mechanical device package 300 including the electromechanical device composed of the conductive beam line 230a and the electrodes 230b and 230c and the active region 245 of the type shown in FIG. 3 has been described above, It is needless to say that various other types of electromechanical devices can be applied.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

205: substrate 210: insulating layer
215: first via contact 220: first passivation layer
225: lower sacrificial layer 230: metal layer
235: upper sacrificial layer 240: second passivation layer
245: active area 250: shield layer
255: second via contact

Claims (13)

(a) depositing a lower sacrificial layer on top of a first passivation layer on top of a substrate;
(b) etching a portion of the lower sacrificial layer and burying the remainder of the lower sacrificial layer to form a metal layer;
(c) processing the metal layer to form an electromechanical device;
(d) depositing a second passivation layer on top of the electromechanical device to form an active area of the electromechanical device; And
(f) forming a through hole in the second passivation layer to remove the lower sacrificial layer.
The method of claim 1, wherein step (a)
Etching a part of the insulating layer formed as an interlayer insulating film on the substrate, and depositing the first passivation layer on the etched insulating layer.
The method of claim 2, wherein the first passivation layer
Wherein the transistor is formed on a metallization layer of the transistor connected to the transistor.
The method of claim 1, wherein the first passivation layer
Wherein the aluminum oxide has a corrosion resistance to steam HF etching of not less than a first reference value and a selectivity to the lower sacrificial layer and the vapor HF etching is not less than a second reference value.
2. The method of claim 1, wherein step (b)
Etching both ends of the center portion of the lower sacrificial layer to expose the center portion of the lower sacrificial layer; And
Depositing the metal layer on top of the first passivation layer to surround the center of the exposed lower sacrificial layer.
2. The method of claim 1, wherein step (c)
An upper region of the metal layer in contact with the remainder of the lower sacrificial layer is patterned or ion beam processed to form a conductive beam line spaced apart from the first passivation layer on the same vertical plane, And forming the electromechanical element including at least one of the first electrode and the second electrode.
2. The method of claim 1, wherein step (d)
(d-1) depositing an upper sacrificial layer on the electromechanical device to make the upper sacrificial layer and the lower sacrificial layer contact with each other; And
(d-2) etching the portion of the upper sacrificial layer and depositing the second passivation layer on the upper sacrificial layer so that the remainder of the upper sacrificial layer is buried. Method of manufacturing a package.
8. The method of claim 7, wherein step (f)
And etching the upper and lower sacrificial layers through the through holes to form the active region for mechanically switching the electromechanical element.
9. The method of claim 8, wherein step (f)
And forming the active region through a vapor HF etch process.
The method according to claim 1,
(g) depositing a shielding layer on top of the second passivation layer to package the active region formed through removal of the lower sacrificial layer in a vacuum or a vacuum state. < RTI ID = 0.0 > Method of manufacturing a package.
11. The method of claim 10, wherein step (g)
Depositing the shielding layer at a deposition rate greater than or equal to a third reference value through a sputtering process so that the constituent material of the shielding layer does not flow into the active region.
(a) depositing a lower sacrificial layer on top of a first passivation layer formed on a substrate, and forming an electromechanical device on top of the lower sacrificial layer;
(b) depositing a top sacrificial layer in contact with the bottom sacrificial layer on top of the electromechanical device, and depositing a second passivation layer on top of the top sacrificial layer; And
(f) forming a through hole in the second passivation layer, and removing the upper and lower sacrificial layers through the through hole to form an active region of the electromechanical device Way.
Board;
An electromechanical switch which is composed of a conductive beam line formed in an active region spaced apart from the substrate by removing a sacrificial layer formed on the substrate at the upper portion of the substrate and electrodes facing each other at both sides of the conductive beam line, A metal layer comprising a device; And
And first and second passivation layers formed on lower and upper portions of the metal layer to fill the metal layer.

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