KR20190048569A - Organic Light Emitting Display Device - Google Patents

Abstract

According to the present invention, the present invention relates to an organic light emitting display device comprising: first to fourth pixels provided on a substrate and including a capacitor region; a first data line transferring a data signal to the first and second pixels; a second data line transferring the data signal to the third and fourth pixels; a first scan line transferring a scan signal to the second and third pixels; and a second scan line transferring the scan signal to the first and fourth pixels. The first and second data lines include a data line hole formed for supplying data voltage to each pixel. The first and second scan lines are located between the data line hole and the capacitor region. Therefore, the present invention can optimize an aperture ratio to extend a lifetime and save a drive IC to reduce manufacturing costs.

Description

[0001] The present invention relates to an organic light emitting display device,

The present invention relates to an organic light emitting display.

The OLED display has a structure in which a light emitting layer is formed between a cathode for injecting electrons and an anode for injecting holes, and electrons generated in the cathode and holes generated in the anode are injected into the light- Injected electrons and holes combine to form an exciton, and the generated exciton emits light while falling from an excited state to a ground state.

The organic light emitting display includes a bottom gate structure in which a gate electrode is located below an active layer, a top gate structure in which a gate electrode is located on an active layer, Respectively.

The OLED display includes a scan driver for driving the scan lines and a data driver for driving the data lines. As the OLED display becomes larger and higher in resolution, the number of drive ICs required increases.

In recent years, various methods for reducing the number of drive ICs have been researched and developed in order to lower the production cost of organic light emitting display devices. A DRD (Double Rate Driving) driving method has been proposed which reduces the number of data lines by half, reducing the number of drive ICs required by half, while realizing the same resolution as the conventional one.

The contents of the background art described above are technical information acquired by the inventor of the present application for the purpose of deriving the present application or acquired in the process of deriving the present application, There is no number.

The present invention provides an organic light emitting diode (OLED) display device that optimizes an aperture ratio in an organic light emitting display device of a DRD driving type.

According to an aspect of the present invention, there is provided an OLED display device including first to fourth pixels provided on a substrate and including a capacitor region, first data for transmitting a data signal to first and second pixels, A first scan line for transferring a scan signal to the second and third pixels, a second scan line for transferring a scan signal to the first and fourth pixels, Wherein the first and second data lines include a data line hole formed to supply a data voltage to each pixel, and the first and second scan lines are located between the data line hole and the capacitor region.

The organic light emitting display according to the present application can extend the life span by the DRD driving method that optimizes the aperture ratio, and can reduce the manufacturing cost by saving the drive IC.

In addition to the effects of the present application discussed above, other features and advantages of the present application will be set forth below, or may be apparent to those skilled in the art to which the present application belongs from such description and description.

1 is a schematic plan view of an OLED display according to an embodiment of the present invention.
FIG. 2 is a plan view showing the first pixel and the second pixel in detail in part A of FIG.
3 is a cross-sectional view taken along line I-I 'of Fig.
4 is a circuit diagram of an OLED display according to an example of the present application.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein, but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, To fully disclose the scope of the invention to those skilled in the art, and this application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

The terms " first horizontal axis direction ", " second horizontal axis direction ", and " vertical axis direction " should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term " at least one " includes all possible combinations from one or more related items. For example, the meaning of " at least one of the first item, the second item and the third item " means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, preferred embodiments of the organic light emitting display according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the constituent elements of the drawings, the same constituent elements may have the same sign as possible even if they are displayed on different drawings

1 is a schematic plan view of an OLED display according to an embodiment of the present invention.

FIG. 1 shows a unit pixel UP composed of a first pixel P1, a second pixel P2, a third pixel P3 and a fourth pixel P4.

Referring to FIG. 1, an OLED display according to an exemplary embodiment of the present invention includes first and second data lines DL1 and D12, first and second scan lines SCL1 and SCL2, Lines VDD1 and VDD2, a sensing line SEL, a reference line Ref, a light blocking film LS, and first to fourth driving units.

The first pixel P1 is located between the first power line VDD1 and the first data line DL1 and the second pixel P2 is located between the first data line DL1 and the reference line Ref. The third pixel P3 is located between the reference line Ref and the second data line DL2 and the fourth pixel P4 is located between the second data line DL2 and the second power line VDD2 .

The first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4 may be pixels that emit red, white, blue, and green, respectively, But the present invention is not limited thereto. Hereinafter, each configuration will be described in detail.

The first data line DL1 and the second data line DL2 are arranged on a substrate in a second direction, for example, a longitudinal direction. The first data line DL1 transfers data signals to the first pixel P1 and the second pixel P2. The second data line DL2 transfers the data signal to the third pixel P3 and the fourth pixel P4. Specifically, the first data line DL1 is connected to the switching transistor Tsw provided in the first pixel P1 and the second pixel P2, the second data line DL2 is connected to the third pixel P3, And is connected to the switching transistor Tsw provided in the fourth pixel P4. The first data line DL1 and the second data line DL2 include a data line hole DH.

The data line hole DH may be defined as a contact hole formed in the first data line DL1 and the second data line DL2 to supply a data voltage to each pixel. The first data line DL1 supplies data signals to the first pixel P1 and the second pixel P2 and supplies data signals to the first pixel P1 and the second pixel P2 through the data line hole DH. And the second data line DL2 supplies a data signal to the third pixel P3 and the fourth pixel P4 and is connected to the third pixel P3 through the data line hole DH. And the switching transistor Tsw included in the third pixel P3 and the fourth pixel P4.

The organic light emitting display according to the present application can supply the data voltages of the same polarity to the two pixels. That is, since two pixels can be controlled through one data line, the number of drive ICs can be reduced, and manufacturing cost can be reduced.

The first scan line SCL1 and the second scan line SCL2 are arranged in a first direction, for example, a horizontal direction on the substrate. The first scan line SCL1 transfers a scan signal to the second pixel P2 and the third pixel P3. The second scan line SCL2 transfers the scan signals to the first pixel P1 and the fourth pixel P4. Specifically, the first scan line SCL1 is connected to the switching transistor Tsw included in the second pixel P2 and the third pixel P3, the second scan line SCL2 is connected to the first pixel P1, And is connected to the switching transistor Tsw provided in the fourth pixel P4.

The organic light emitting display according to the present application has a double rate driving (DRD) structure for supplying data voltages of the same polarity to two pixels, so that one unit pixel UP includes two scan lines. That is, since one data line supplies data signals to two pixels, two scan lines must be provided to turn on / off the switching transistor Tsw for each pixel. In the DRD structure, since two scan lines are provided, the switching transistors Tsw of each pixel can be individually turned on / off.

For example, when a high signal is applied to the first scan line SCL1 and the first data line DL1 in the first period and a low signal is applied to the second scan line SCL2 and the second data line DL2 do. At this time, the switching transistor Tsw of the second pixel P2 is turned on. A high signal is applied to the second scan line SCL2 and the first data line DL1 in the second period and a low signal is applied to the first scan line SCL1 and the second data line DL2. At this time, the switching transistor Tsw of the first pixel P1 is turned on.

As described above, the OLED display according to the present invention drives pixels by a DRD scheme sharing a data line, and has two scan lines, so that each pixel can be individually adjusted.

The first power supply line VDD1 and the second power supply line VDD2 are arranged on a substrate in a second direction, for example, a longitudinal direction. First and second data lines DL1 and DL2 and a reference line Ref are arranged between the first power supply line VDD1 and the second power supply line VDD2. Data lines of neighboring unit pixels are arranged on the left side of the first power supply line VDD1 and on the right side of the second power supply line VDD2, though not shown.

The first power supply line VDD1 according to an example supplies driving power to the first pixel P1 and the second pixel P2. Specifically, the first power supply line VDD1 is connected to the driving transistor Tdr included in the first pixel P1 and the second pixel P2, the second power supply line VDD2 is coupled to the third pixel P3, And the driving transistor Tdr included in the fourth pixel P4.

The sensing line SEL is connected to the sensing transistor Tse provided in the first to fourth pixels P1, P2, P3 and P4, respectively. The sensing line SEL generates a sensing signal and supplies it to the sensing transistor Tse. The sensing transistor Tse responds to the sensing signal and supplies the current of the driving transistor Tdr to the reference line Ref.

The reference lines Ref are arranged on a substrate in a second direction, for example, a longitudinal direction. The reference line Ref is arranged between the second data line DL2 and the third data line DL3.

The reference line Ref according to an example is connected to the sensing transistor Tse provided in the first to fourth pixels P1, P2, P3 and P4, respectively. The reference line Ref can be supplied with the current of the driving transistor Tdr by the sensing line SEL and the sensing transistor Tse.

The organic light emitting diode display according to an exemplary embodiment of the present invention may have a compensation circuit for generating a compensation voltage based on sensing results generated through a sensing line SEL, a reference line Ref, and a sensing transistor Tse have. Therefore, reliability deterioration due to deterioration of the driving transistor Tdr can be prevented, and the lifetime of the driving transistor Tdr is extended.

The light-shielding film LS is formed to cover the regions of the driving transistor Tdr and the switching transistor Tsw provided in the first to fourth pixels P1, P2, P3 and P4, Layer and the active layer of the switching transistor Tsw. The light shielding film LS is not necessarily formed in the illustrated pattern, and may be variously changed if it can cover the active layer of the driving transistor Tdr and the active layer of the switching transistor Tsw.

The light-shielding film LS according to an exemplary embodiment is separately pattern-formed on each of the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4. That is, the light blocking film LS formed by patterning the first pixel P1, the light blocking film LS formed by patterning the second pixel P2, the light blocking film LS formed by patterning the third pixel P3, and the fourth pixel P4 Are electrically insulated from each other. This is because the light blocking film LS is connected to the driving transistor Tdr formed in the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4, respectively. Therefore, it is possible to prevent the data mixing phenomenon in which charge is charged in the light-shielding film LS when the driving transistor Tdr of one pixel operates and the charged charge affects the driving transistor Tdr of the other pixel.

The light-blocking film LS according to an example is formed in the first layer between the substrate and the active layer of the driving transistor Tdr and is made of a conductive material. The first layer may be defined as a layer on which the light blocking film LS is formed, and a specific structure thereof will be described later. Since the light-shielding film LS is made of a conductive material, the same material as the light-shielding film LS can be used as the wiring. Therefore, the light shielding film LS may be formed to shield the external light, and the same material as the light shielding film LS may be arranged in the second direction of the substrate, for example, in the longitudinal direction. That is, the first and second data lines DL1 and DL2, the first and second power supply lines VDD1 and VDD2, and the reference line Ref are formed of the same material as the light-shielding film LS, do. Similarly, the first and second data lines DL1 and DL2, the first and second power supply lines VDD1 and VDD2, and the reference line Ref are separately pattern-formed.

By forming the first and second data lines DL1 and DL2, the first and second power supply lines VDD1 and VDD2 and the reference line Ref in the first layer as described above, the aperture ratio of the organic light emitting display device can be secured . The detailed configuration will be described later.

Each of the first to fourth driving units includes a driving transistor Tdr, a switching transistor Tsw, a sensing transistor Tse, and a storage capacitor Cst. A specific configuration for this will be described later.

2 is a plan view specifically showing the first pixel and the second pixel on the enlarged view of the portion A in Fig. In FIG. 1, the third pixel P3 and the fourth pixel P4 are symmetrical with respect to the first pixel P1 and the second pixel P2, and thus a duplicate description thereof will be omitted.

Referring to FIG. 2, first and second scan lines SCL1 and SCL2 are formed in a first direction and intersect the first and second scan lines SCL1 and SCL2. (VDD1), a first data line DL1, and a reference line Ref are arranged. The first pixel P1 is formed between the first power supply line VDD1 and the first data line DL1 and the second pixel P2 is formed between the first data line DL1 and the reference line Ref do.

A first driver and a light blocking film LS are formed on the first pixel P1. The first driver includes a driving transistor Tdr, a switching transistor Tsw, a sensing transistor Tse, and a storage capacitor Cst.

The driving transistor Tdr includes a first gate electrode G1, a first source electrode S1, a first drain electrode D1, and a first active layer A1.

The first gate electrode G1 is connected to the second drain electrode D2 of the switching transistor Tsw through the first contact hole CH1.

The first source electrode S1 is connected to the first power line VDD1 through a second contact hole CH2.

The first drain electrode D1 faces the first source electrode S1. Although not shown, the first drain electrode D1 is connected to the first electrode (anode electrode) of the organic light emitting element.

The first active layer A1 is connected to the first source electrode S1 and the first drain electrode D1 through a third contact hole CH3 and a fourth contact hole CH4, .

The switching transistor Tsw includes a second gate electrode G2, a second source electrode S2, a second drain electrode D2, and a second active layer A2.

The second gate electrode G2 is connected to the second scan line SCL2 through a fifth contact hole CH5.

The second source electrode S2 is connected to the first data line DL1 through a sixth contact hole CH6. Here, the sixth contact hole CH6 can be viewed as a data line hole DH. The sixth contact hole CH6 corresponds to the same hole as the data line hole DH and is provided with reference numerals for convenience. The second drain electrode D2 faces the second source electrode S2. The second drain electrode D2 is connected to the first gate electrode G1 of the driving transistor Tdr through the first contact hole CH1 as described above.

The second active layer A2 is connected to the second source electrode S2 and the second drain electrode D2 through a seventh contact hole CH7 and an eighth contact hole CH8, do. The second active layer A2 is formed to have a relatively large area, thereby improving the capacity of the storage capacitor Cst.

The sensing transistor Tse includes a third gate electrode G3, a third source electrode S3, a third drain electrode D3, and a third active layer A3.

The third gate electrode G3 is connected to the sensing line SEL through a ninth contact hole CH9.

The third source electrode S3 is connected to the first drain electrode D1. Since the third source electrode S3 is formed on the same layer as the first drain electrode D1, the third source electrode S3 can be connected without a separate contact hole.

The third drain electrode D3 is connected to the reference line Ref through a tenth contact hole CH10.

The third active layer A3 is connected to the third source electrode S3 and the third drain electrode D3 through the eleventh contact hole CH11 and the twelfth contact hole CH12 to function as an electron transfer channel do.

The light-shielding film LS is formed so as to cover the first active layer A1 of the driving transistor Tdr and the second active layer A2 of the switching transistor Tsw.

The light-shielding film LS according to an example has a region overlapping the second active layer A2 of the switching transistor Tsw and the drain electrode D1 of the driving transistor Tdr. The overlapping region at this time is defined as the capacitor region CA. The capacitor region CA corresponds to a region where the storage capacitor Cst is provided.

The storage capacitor Cst is provided in the capacitor region CA. The storage capacitor Cst holds the data voltage supplied to the driving transistor Tdr for one frame and is connected to the gate electrode G1 and the drain electrode D1 of the driving thin film transistor Tdr.

A second driver and a light blocking film LS are formed on the second pixel P2. The second driver includes a driving transistor Tdr, a switching transistor Tsw, a sensing transistor Tse, and a storage capacitor Cst. Here, the detailed configuration included in the second pixel P2 is the same as the detailed configuration included in the first pixel P1, and the same reference numerals are given to only the differences in configuration. Hereinafter, the redundant description of the first pixel P1 will be omitted, and only the modified structure will be described.

The driving transistor Tdr includes a first gate electrode G1, a first source electrode S1, a first drain electrode D1, and a first active layer A1. Here, the overlapping description of the first source electrode S1 and the first drain electrode D1 is omitted.

The first gate electrode G1 is connected to the second drain electrode D2 of the switching transistor Tsw through the thirteenth contact hole CH13.

The first active layer A1 is connected to the first source electrode S1 and the first drain electrode D1 through the fourteenth contact hole CH14 and the fifteenth contact hole CH15, .

 The switching transistor Tsw includes a second gate electrode G2, a second source electrode S2, a second drain electrode D2, and a second active layer A2. Here, the overlapping description of the second source electrode S2 is omitted.

The second gate electrode G2 is connected to the first scan line SCL1 through the sixteenth contact hole CH16.

The second drain electrode D2 faces the second source electrode S2. The second drain electrode D2 is connected to the first gate electrode G1 of the driving transistor Tdr through the thirteenth contact hole CH13 as described above.

The second active layer A2 is connected to the second source electrode S2 and the second drain electrode D2 through the seventeenth contact hole CH17 and the eighteenth contact hole CH18, do. The second active layer A2 is formed to have a relatively large area, thereby improving the capacity of the storage capacitor Cst.

The sensing transistor Tse includes a third gate electrode G3, a third source electrode S3, a third drain electrode D3, and a third active layer A3. Here, the overlapping description of the third source electrode S3 is omitted.

The third gate electrode G3 is connected to the sensing line SEL through a 19th contact hole CH19.

The third drain electrode D3 is connected to the reference line Ref through a twentieth contact hole CH20.

The third active layer A3 is connected to the third source electrode S3 and the third drain electrode D3 through the twenty-first contact hole CH21 and the twenty-second contact hole CH22, do.

Here, the first to third source electrodes S1, S2, and S3, and the first to third data electrodes D1, D2, and D3 are formed in the third layer and formed of the same material. Alternatively, the first to third gate electrodes G1, G2 and G3 are formed in the second layer. The second layer may be defined as a layer in which a gate electrode is formed, and the third layer may be defined as a layer in which a source and a data electrode are formed. A specific structure for this will be described later.

Also, the first and second scan lines SCL1 and SCL2 and the sensing line SEL are formed in the third layer. That is, the organic light emitting diode display according to the present invention includes the first and second scan lines SCL1 and SCL2, the sensing line SEL, the first to third source electrodes S1, S2 and S3, The three data electrodes D1, D2 and D3 are formed of the same material in the same layer. Therefore, when the source electrode and the drain electrode are connected through the active layer, they do not form a separate channel even if they pass through the scan line or the sensing line.

At this time, if the gate electrode formed in the second layer is connected to the scan line or the sensing line through the contact hole, a separate channel can be formed at a portion where the gate electrode is connected through the contact hole.

Specifically, in the first pixel P1, the second gate electrode G2 is connected to the second scan line SCL2 through the third contact hole CH3, and the second active layer A2 is connected to the second scan line SC2 through the third contact hole CH3. The second gate electrode G2 of the second pixel P2 forms a channel with the first scan line SCL1 and the eighth contact hole CH8 And the second active layer A2 overlaps the first scan line SCL1 to form a channel with the second gate electrode G2 connected to the first scan line SCL1. Therefore, even if the first and second scan lines SCL1 and SCL2 are arranged so as to be adjacent to each other, the first pixel P1 forms a channel only when passing the second scan line SCL2, The channel is formed only when it passes the first scan line SCL1.

Conventionally, since a data line, a power supply line, and a reference line are formed in the source / drain electrode layer and a scan line is formed in the gate electrode layer, there is a problem that two channels are formed while passing through two scan lines. The bridge had to be formed. However, in order to provide a contact hole between the scan lines and bridge formation, the scan lines must be spaced apart from each other, and the area occupied by the pixel circuits increases by a predetermined gap, thereby reducing the aperture ratio. Here, as the aperture ratio decreases, the density of the current increases, and the density of the current is an important factor that affects the lifetime of the organic light emitting display. As the density of the current increases, the lifetime of the organic light emitting display decreases.

For example, a data line hole DH for supplying a data signal from the first data line DL1 to the first pixel P1 or a data line DL for supplying a data signal from the first data line DL1 to the second pixel P2 Since the data line hole DH for supplying data is formed between the first scan line SCL1 and the second scan line SCL2 so as to be positioned between the first scan line SCL1 and the second scan line SCL2, The data line holes DH may be formed and the aperture ratio may be reduced by the gap that is opened.

Alternatively, the organic light emitting display according to the present invention may include first and second power supply lines VDD1 and VDD2, first and second data lines DL1 and DL2, Since the reference line Ref is formed, the first and second scan lines SCL1 and SCL2 and the sensing line SEL can be formed in the third layer in which the source electrode and the drain electrode are formed, Since the gate electrode can be connected to the scan line or the sensing line through the contact hole, one channel can be formed without a separate bridge, and the aperture ratio can be prevented from being reduced.

A data line hole DH for supplying a data signal to the first pixel P1 and the second pixel P2 in the first data line DL1 is formed at the same position, And the second scan line SCL2 are positioned between the data line hole DH and the capacitor area CA so that the first scan line SCL1 and the second scan line SCL2 can be formed adjacent to each other , The interval between the first scan line (SCL1) and the second scan line (SCL2) can be reduced, so that the aperture ratio does not decrease.

Similarly, a data line hole DH for supplying a data signal to the third pixel P3 and the fourth pixel P4 in the second data line DL2 is formed at the same position, and the first scan line SCL1, And the second scan line SCL2 are positioned between the data line hole DH and the capacitor area CA so that the first scan line SCL1 and the second scan line SCL2 can be formed adjacent to each other , The interval between the first scan line (SCL1) and the second scan line (SCL2) can be reduced, so that the aperture ratio does not decrease.

Therefore, the organic light emitting diode display according to the present invention has a DRD structure, which can reduce the number of drive ICs and reduce the manufacturing cost, and the lifetime can be extended by a structure in which the aperture ratio is optimized in the DRD structure.

3 is a cross-sectional view taken along line I-I 'of Fig.

3, the OLED display according to the present application includes a substrate 100, a light-shielding film LS, a first power line VDD1, a buffer layer 110, a driving transistor Tdr, a gate insulating layer 120, A first scan line SCL1, a second scan line SCL2, an interlayer insulating layer 130, a planarization layer 140, and a first electrode E1.

The substrate 100 is a thin film transistor array substrate, and may be made of glass or plastic. On one side of the substrate 100, scan lines, data lines and pixels are formed.

The light-shielding film LS is formed on the substrate 100. The light shielding film LS serves to shield external light incident on the active layer A1 of the driving transistor Tdr and may be formed of a metallic material. As described above, the light blocking film LS is formed in the first layer. Where the first layer can be seen as a layer located between the substrate 100 and the buffer layer 110.

The first power supply line VDD1 is formed on the substrate 100. [ The first power supply line VDD1 is formed of the same material as the light-shielding film LS and is formed on the first layer together with the light-shielding film LS.

The buffer layer 110 is provided on the substrate 100 so as to cover the light-shielding film LS and the first power source line VDD1. The buffer layer 110 functions to prevent moisture from penetrating into the pixel. The buffer layer 110 may be formed of an inorganic insulating material, for example, silicon dioxide (SiNx), silicon nitride (SiNx), or a multilayer thereof, but is not limited thereto.

The driving transistor Tdr is provided on the buffer layer 110. The driving transistor Tdr controls the amount of current flowing to the organic light emitting element. The driving transistor Tdr includes a first active layer A1, a first gate electrode G1, a first drain electrode D1, and a first source electrode S1.

The first active layer (A1) is provided on the buffer layer (110). The first active layer A1 may be composed of a semiconductor material composed of any one of amorphous silicon, polycrystalline silicon, oxide and organic material, but is not limited thereto.

The first gate electrode G1 is formed on the semiconductor insulating layer. The first gate electrode G1 is covered by the gate insulating layer 120. [ As described above, the first gate electrode G1 is formed in the second layer. Here, the second layer can be regarded as a layer located between the semiconductor insulating layer and the gate insulating layer 120.

The first source electrode S1 is connected to one side of the first active layer A1 through a contact hole. The first source electrode S1 may be connected to the first power line VDD1 formed in the first layer through the contact hole.

The first drain electrode D1 is connected to the other side of the first active layer A1 through a contact hole and is spaced apart from the first source electrode S1.

As described above, the first source electrode S1 and the first drain electrode D1 are formed in the third layer. Here, the third layer can be regarded as a layer positioned between the gate insulating layer 120 and the interlayer insulating layer 130.

The gate insulating layer 120 is formed to cover the first gate electrode G1. The gate insulating layer 120 isolates the driving transistor Tdr from the outside and protects it from chemicals, moisture and air during the process. The gate insulating layer 120 is generally formed of an inorganic material having low electrical and ductile characteristics or an inorganic material containing silicon (Si).

The first and second scan lines SCL1 and SCL2 are formed on the gate insulating layer 120. [ The first and second scan lines SCL1 and SCL2 are formed in the third layer and formed of the same material as the first source electrode S1 and the first drain electrode D1.

The interlayer insulating layer 130 is formed on the first source electrode S1, the first drain electrode D1, the first scan line SCL1, and the second scan line SCL2. This interlayer insulating layer 130 isolates the driving transistor Tdr from the outside and protects it from chemicals, moisture and air during the process. The interlayer insulating layer 130 is generally formed of an inorganic material having low electrical and ductile characteristics or an inorganic material containing silicon (Si).

The planarization layer 140 is provided on the substrate 100 so as to cover the driving transistor Tdr. The planarization layer 140 protects the driving transistor Tdr and provides a flat surface on the driving transistor Tdr. The planarization layer 140 may be formed of an organic material such as photo acryl or benzocyclobutene. However, the planarization layer 140 is preferably made of a photo-acrylic material for convenience of processing.

The first electrode E1 is an anode electrode and is provided on the planarization layer 140 in the form of a pattern. The first electrode E1 is electrically connected to the drain electrode D1 of the driving transistor Tdr through a contact hole provided in the planarization layer 140 to receive a data current output from the driving transistor Tdr. The first electrode E1 may be made of a metal having a high reflectance and may be made of a material such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), or magnesium (Mg) Or alloys thereof, but are not limited thereto.

 The organic light emitting display according to the present application is characterized in that the light shielding film LS and the first power supply line VDD1 are formed in the same first layer and the first and second scan lines SCL1 and SCL2 and the first source electrode S1 And the first drain electrode D1 are formed in the same third layer. Although not shown, since the second power supply line VDD2, the reference line Ref, the first data line DL1, and the second data line DL2 are formed in the first layer, the substrate 100 and the buffer layer 110 are formed, As shown in FIG. Since the sensing line SEL is formed in the third layer, it can be seen that the sensing line SEL is located between the gate insulating layer 120 and the interlayer insulating layer 130. In addition, since the gate electrode of the switching transistor is formed in the second layer and jumped like the first gate electrode G1, one channel can be formed without decreasing the aperture ratio as described above.

FIG. 4 is a circuit diagram of an OLED display according to an embodiment of the present application, which is a circuit diagram of each of the pixels P1, P2, P3, and P4 constituting the OLED display of FIG.

Referring to FIG. 4, the organic light emitting diode display according to an exemplary embodiment of the present invention includes first and second scan lines SCL1 and SCL2, first and second data lines DL1 and DL2, And includes a plurality of lines VDD1 and VDD2, a reference line Ref, a driving transistor Tdr, a switching transistor Tsw, a sensing transistor Tse, a storage capacitor Cst and an organic light emitting diode OLED.

The driving transistor Tdr is switched in accordance with a data voltage supplied from the switching thin film transistor Tsw to generate a data current from a power source supplied from the first or second power source line VDD1 or VDD2, .

The switching transistor Tsw is switched according to a gate signal supplied to the first or second scan lines SCL1 and SCL2 to apply a data voltage supplied from the first or second data line DL1 or DL2 to the driving thin film transistor Tdr.

The sensing transistor Tse senses a threshold voltage deviation of the driving transistor Tdr that causes a deterioration in image quality. The sensing of the threshold voltage deviation is performed in the sensing mode. The sensing transistor Tse supplies the current of the driving transistor Tdr to the reference line Ref in response to a sensing control signal supplied from the sensing line SEL.

The storage capacitor Cst holds a data voltage supplied to the driving transistor Tdr for one frame, and is connected to the gate terminal and the drain terminal of the driving transistor Tdr, respectively.

The organic light emitting diode OLED emits a predetermined light according to a data current supplied from the driving transistor Tdr. The organic light emitting diode OLED includes a first electrode (anode electrode) connected to a drain electrode of the driving transistor Tdr, and an organic light emitting layer and a second electrode (cathode electrode) sequentially formed on the first electrode. And the second electrode of the organic light emitting diode OLED is connected to the low power line VSS.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the scope of the present application is to be defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present application.

100: substrate 110: buffer layer
120: gate insulating layer 130: interlayer insulating layer
140: planarization layer

Claims (8)

First to fourth pixels provided on the substrate and including a capacitor region;
A first data line for transmitting a data signal to the first and second pixels;
A second data line for transmitting a data signal to the third and fourth pixels;
A first scan line for transmitting a scan signal to the second and third pixels; And
And a second scan line for transmitting a scan signal to the first and fourth pixels,
Wherein the first and second data lines include data line holes formed to supply data signals to respective pixels,
And the first and second scan lines are located between the data line hole and the capacitor region. The method according to claim 1,
A first power line located on the left side of the first data line and supplying driving power to the first and second pixels;
A second power line located on the right side of the second data line and supplying driving power to the third and fourth pixels; And
And a reference line disposed between the first data line and the second data line to sense deterioration of the first through fourth pixels. 3. The method of claim 2,
Further comprising first through fourth drivers provided in the first through fourth pixels, respectively,
Wherein each of the first to fourth drive units comprises:
A first source electrode connected to the first or second power source line, a first drain electrode connected to the organic light emitting element, and a first gate electrode receiving a signal from the first or second data line, A driving transistor for emitting light;
A second source electrode connected to the first or second data line, a second drain electrode connected to the first gate electrode, and a second gate electrode connected to the first or second scan line, A switching transistor for controlling light emission of the device;
A storage capacitor provided in the capacitor region and storing a signal from the first or second data line; And
A third source electrode connected to the storage capacitor, a third drain electrode connected to the reference line, and a third gate electrode connected to the sensing line, wherein a threshold voltage of the organic light emitting device is adjusted according to a signal from the sensing line And a sensing transistor for controlling the sensing transistor. The method of claim 3,
Further comprising a light shielding film provided on the first layer for protecting the active layer of the driving transistor and the active layer of the switching transistor from external light,
Wherein the first and second power supply lines, the first and second data lines, and the reference line are provided in the first layer. 5. The method of claim 4,
Further comprising a second layer which is a layer different from the first layer,
And the first to third gate electrodes are provided in the second layer. 6. The method of claim 5,
Further comprising a third layer which is a layer different from the first and second layers,
And the first to third source electrodes and the first to third drain electrodes are provided in the third layer. The method according to claim 6,
The first and second scan lines, and the sensing line are provided in the third layer. 8. The method according to any one of claims 1 to 7,
Wherein the first to fourth pixels are grouped together to form a unit pixel.

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