KR20190046120A - RECEIVER FRAME DETECTION APPARATUS AND METHOD FOR DVB-S2x SUPER-FRAME SYSTEMS BASED ON BURST TRANSMISSION MODE - Google Patents

Abstract

Disclosed are a device to detect a receiver frame for a DVB-S2x super-frame transmission system based on burst transmission and a method thereof. The method to detect a receiver includes: a step of inputting input data by delay line by compensating for carrier frequency offsets (CFO) of different ranges; a step enabling accumulators forming each delay line to accumulate symbols included in the input data; a step of calculating the sum of phase differences between the symbols accumulated by the accumulators; a step of detecting a frame from a time axis of the input data by using a time axis threshold value set for the largest value among the sums of the phase differences; and a step of detecting a frame from a frequency axis of the input data by using the sum of the phase differences, which has a value no less than the time axis threshold value, among the sums of the phase differences.

Description

TECHNICAL FIELD [0001] The present invention relates to a receiver frame detection apparatus and method for a DVB-S2x super frame transmission system based on a burst transmission scheme, and a receiver frame detection apparatus and method for a DVB-S2x super frame transmission system based on a burst transmission scheme.

The present invention relates to an apparatus and a method for detecting a frame in a receiver when a signal is transmitted in a burst transmission scheme in a DVB-S2x superframe standard scheme, which is a forward link transmission technique in a digital satellite broadcasting communication system.

DVB-S2x technology is based on DVB-S2 technology and adds new roll-off factor, constellation and negative efficiency, channel bonding, and VL (Very Low) -SNR (Signal to Noise Ratio) Technologies.

Eutelsat, France's satellite operator, will launch the world's first geostationary communications satellite called "Quantum" and launch it in 2019. The Quantum satellite will use beam-hopping technology to change the shape of fixed coverage in real time. Beam-Hopping technology adopts the DVB-S2x superframe structure suitable for burst transmission in transmission frame format as a technique to adjust the coverage by changing continuously many independent beams to any position continuously.

The SOSF of the DVB-S2x superframe is padded with 14 bits to a 256-bit Walsh-Hadamard (WH) sequence, and 270 bits are modulated by a differential BPSK (binary phase shift keying) scheme. The SFFI also encodes 4 bits of B_SFFI into 15 bits and repeats 30 times in sequence using a spreading technique to form a total of 450 bits. These 450 bits are modulated and transmitted in a differential BPSK scheme.

The SOSF in the DVB-S2x superframe is a known symbol between 270 transceivers and requires up to 269 complex multipliers to be implemented using only a differential correlator, It corresponds to complexity. In addition, the SFFI must be known between the transmitting and receiving systems or be detected by the receiver without knowing it, while the SFFI has the structural characteristic of applying the spreading technique.

The SOSF in the superframe is 270 symbols. In order to detect a frame using the full correlation method, a complexity of 1,076 (269 x 4, complex multiplication operation) multipliers is required, .

Therefore, a method of increasing frame detection accuracy at a low signal-to-noise ratio (SNR) while reducing hardware complexity is being demanded.

The present invention detects a superframe in a signal by using a simple differential detector that includes a plurality of delay lines and compensates for different ranges of CFOs in input data for each delay line, thereby detecting a frame accurately while lowering hardware complexity The present invention is not limited thereto.

A method of detecting a frame according to an exemplary embodiment of the present invention includes: inputting carrier frequency offset (CFO) of different ranges in input data for each delay line; Accumulating the symbols included in the input data by accumulators constituting each of the delay lines; Calculating a sum of phase differences of symbols accumulated in the accumulators for each delay line; Detecting a frame on a time axis of the input data using a time axis threshold value set for a maximum value among a sum of the phase differences; And detecting a frame in a frequency axis of the input data using a sum of phase differences having a value equal to or greater than the time axis threshold value among the sum of the phase differences.

The phase difference of the accumulated symbols in each of the accumulators of the frame detection method according to an embodiment of the present invention is determined according to the difference between the CFO and the CFO compensated for each delay line and the period of the symbols accumulated in the accumulators .

The sum of the phase differences in the frame detection method according to an exemplary embodiment of the present invention may be determined by a number of accumulators, a period of a symbol accumulated in each of the accumulators, an additive white Gaussian noise (AWGN) And the difference between CFOs compensated for each delay line.

A frame detection method according to an embodiment of the present invention includes estimating SPO using a sum of the phase differences; And setting the time base threshold value according to the AWGN, the CFO, and the estimated SPO according to the reception target.

The step of detecting a frame in the frequency axis of the frame detection method according to an exemplary embodiment of the present invention includes a step of detecting an SFFIVect including a phase-transformed SOSF value and an SSFI symbol value modulated by BPSK (Binary Phase Shift Keying) Determining a sum of a constant and a CFO using a sum of phase differences having a value greater than a predetermined value; Performing zero-padding on the sum of the predetermined constant and the CFO, and performing an FFT operation; And

If the maximum value of the frequency component determined according to the CFO interval of each of the delay lines among the values obtained by performing the FFT operation exceeds the frequency axis threshold value, it is determined that the frame is detected at the N-multiple sampling frequency of the input data Step < / RTI >

The CFO of the frame detection method according to an embodiment of the present invention is determined by normalizing the N-multiple sampling frequency of the input data, and N may be an integer of 2 or more.

The frame detection apparatus according to an embodiment of the present invention compensates for different ranges of CFOs in the input data for each delay line and inputs the compensated CFOs to the phase difference of the symbols of the input data accumulated in the accumulators constituting each of the delay lines A simple differential detector for calculating the sum of the two outputs; A time axis frame detector for detecting a frame on a time axis of the input data using a time axis threshold value set for a maximum value among a sum of the phase differences; And a frequency axis frame detector for detecting a frame in the frequency axis of the input data by using a sum of the phase differences having a value equal to or greater than the time axis threshold value among the sum of the phase differences.

The phase difference of the accumulated symbols in each of the accumulators of the frame detection apparatus according to an embodiment of the present invention can be determined according to the difference between the CFO and the CFO compensated for each delay line and the period of the symbols accumulated in the accumulators have.

The sum of the phase differences of the frame detection apparatus according to an embodiment of the present invention may be at least one of the differences between the number of accumulators, the period of symbols accumulated in each of the accumulators, the AWGN, ≪ / RTI >

The time axis threshold value of the frame detection apparatus according to an embodiment of the present invention can be set according to the AWGN, the CFO, and the estimated SPO according to the reception target.

The frame detection apparatus according to an exemplary embodiment of the present invention performs zero padding on a sum of SFFIVect including a phase-converted SOSF value and an SSFI symbol value modulated with BPSK, and a phase difference having a value equal to or greater than the time- Wherein the maximum frequency component of the frequency component determined according to the CFO interval of each of the delay lines among the values obtained by performing the FFT operation is greater than a frequency- Value, it can be determined that the frame is detected at the N-multiple sampling frequency of the input data.

The CFO of the frame detection apparatus according to an embodiment of the present invention is determined by normalizing the N-multiple sampling frequency of the input data, and N may be an integer of 2 or more.

According to an embodiment of the present invention, a superframe is detected in a signal by using a simple differential detector that includes a plurality of delay lines and compensates for different ranges of CFOs in input data for each delay line, It is possible to accurately detect a frame at a low signal-to-noise ratio (SNR).

1 is a diagram illustrating a superframe transmission system including a frame detection apparatus according to an embodiment of the present invention.
2 is a diagram showing a structure of a frame detecting apparatus according to an embodiment of the present invention.
3 is an example of a simple differential detector included in the frame detection apparatus according to an embodiment of the present invention.
4 is a characteristic of SOSF & SFFI symbols used in an embodiment of the present invention.
5 is an example of a process of calculating a sum of phase differences of accumulated symbols in accumulators according to an embodiment of the present invention.
6 is an example of a process of detecting a frame on the time axis using the result of FIG.
7 is an example of a process of detecting a frame on the frequency axis according to an embodiment of the present invention.
8 is an example of a process of calculating a value input to the FFT processor.
9 is a flowchart showing a frame detection method according to an embodiment of the present invention.
10 is a flowchart illustrating a process of detecting a frame on the frequency axis of the frame detection method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. A frame detection method according to an embodiment of the present invention can be performed by a frame detection apparatus.

1 is a diagram illustrating a superframe transmission system including a frame detection apparatus according to an embodiment of the present invention.

The transmitter 101 may transmit a signal including the super frame to the receiver 102. [ Further, the communicator 103 included in the receiver 102 can receive a signal including the superframe from the transmitter 101. [ Then, the frame detection apparatus 100 included in the receiver 102 can extract a super frame from the signal received by the communicator 103. At this time, the frame detection apparatus 100 may be a processor performing a frame detection method. Further, the frame detection apparatus 100 can detect a superframe on the time and frequency axes of signals received by the communicator 103 on a per-input-sample basis using two-multiplied received samples.

The superframe may comprise a Start of Super-Frame (SOSF) field, a Super Frame Format Index (SSFI), and a payload.

At this time, the SOSF field is a field indicating a start position of a super frame included in a signal transmitted by the transmitter 101, and the SSFI may include format information of a super frame. For example, the SSFI may be composed of 4 bits of data. The payload unit may be data whose structure is changed according to the format of the super frame. For example, the SOSF may be composed of 270 symbols, and the SFFI may be composed of 450 symbols. Also, the payload unit may be composed of 611,820 data symbols.

For example, receiver 102 may be a burst transmission based DVB-S2x superframe receiver. The frame detection apparatus 100 can detect a frame with a low hardware complexity and robustness using SOSF & SFFI symbols corresponding to a total of 720 symbols. A concrete configuration and a method for the frame detection apparatus 100 to detect a frame using SOSF & SFFI symbols will be described in detail with reference to FIG.

2 is a diagram showing a structure of a frame detecting apparatus according to an embodiment of the present invention.

The frame detection apparatus 100 includes a reverse randomizer 210, a simple differential detector 220, a time axis frame detector 230, an FFT performer 240 and a frequency axis frame detector 250 as shown in FIG. can do. At this time, the Randomizer 210, the Simple Differential Detector 220, the Time Axis Frame Detector 230, the FFT Performer 240 and the Frequency Axis Frame Detector 250 perform different processes or programs included in one process And may be a respective module for performing.

The signal received from the transmitter 110 may be a randomized signal such that 0 or 1 is not consecutive. Accordingly, the de-randomizer 210 can restore the signal including the super-frame by reverse-randomizing the signal received from the transmitter 110. [

The simple differential detector 220 includes a plurality of delay lines and can calculate a phase difference by inputting compensation for carrier frequency offset (CFO) in different ranges in input data for each delay line. At this time, the CFO is determined by normalizing the N-multiple sampling frequency of the input data, and N may be an integer of 2 or more.

At this time, the accumulators constituting each of the delay lines can accumulate the symbols included in the input data. In this case, the phase difference of the accumulated symbols in each of the accumulators may be determined according to the difference between the CFO and the CFO compensated for each delay line, and the period of the symbols accumulated in the accumulators.

The simple differential detector 220 may then calculate the sum of the phase differences of the accumulated symbols in the accumulators on a per-delay-line basis. At this time, the sum of the phase differences is at least one of the differences between the cumulative number of accumulators, the cumulative cumulative number of symbols in each accumulator, additive white Gaussian noise (AWGN), software pattern ontology (SPO) Can be determined accordingly.

Next, the simple differential detector 220 can estimate the SPO using the sum of the phase differences. Then, the simple differential detector 220 can set the time axis threshold value according to the AWGN, the CFO, and the estimated SPO according to the reception target.

The detailed configuration and operation of the simple differential detector 220 will be described in detail with reference to FIGS. 3 to 5 below.

The time base frame detector 230 may detect the frame in the time axis of the input data using the time base threshold value set for the maximum value among the sum of the phase differences calculated by the simple differential detector 220. [

Detailed operation of the time base frame detector 230 will be described in detail below with reference to FIG.

The frame detection apparatus 100 detects a frame on the time axis and then detects a frame on the frequency axis using the FFT performer 240 and the frequency axis frame detector 250 so as to perform erroneous detection by AWGN, CFO, and SPO It is possible to reduce the False Alarm Probability.

An FFT (Fast Fourier Transform) multiplier 240 performs zero padding on the sum of the constant and the CFO, and performs an FFT operation. In this case, the sum of the constant constant and the CFO may be a value determined by using SFFIVect and a sum of phase differences having a value equal to or greater than a time axis threshold value. In addition, SFFIVect may include a phase-converted SOSF value and an SSFI symbol value modulated by BPSK (Binary Phase Shift Keying).

The frequency axis frame detector 250 may detect the frame in the frequency axis of the input data using the sum of the phase differences having a value equal to or greater than the time axis threshold value in the sum of the phase differences calculated by the simple differential detector 220. In this case, when the maximum value of the frequency components determined according to the CFO interval of each of the delay lines among the values obtained by performing the FFT operation by the FFT performer 240 exceeds the frequency axis threshold value, the frequency axis frame detector 250 It can be determined that a frame is detected at the N-multiple sampling frequency of the input data.

Detailed operation of the frequency axis frame detector 250 will be described in detail with reference to FIGS. 7 and 8. FIG.

The frame detection apparatus 100 of the present invention detects a superframe in a signal by using a simple differential detector that includes a plurality of delay lines and compensates for different ranges of CFOs in input data for each delay line, (SNR), and can accurately detect a frame at a low signal-to-noise ratio (SNR).

3 is an example of a simple differential detector included in the frame detection apparatus according to an embodiment of the present invention.

The simple differential detector 220 may include n DL delay lines. 3 is an example of the structure of a simple differential detector 220 having nDL = 7. At this time, the simple differential detector 220 has a delay line of iDL = 0, a delay line of iDL = 1, a delay line of iDL = 2, a delay line of iDL = 3, a delay line of iDL = 4, , And iDL = 6.

The simple differential detector 220 can input a Numerically Controlled Oscillator (NCO) 301, which is a compensation for CFOs of different ranges for each delay line at regular intervals. At this time, the constant interval may be 0.45%.

For example, as shown in FIG. 3, the simple differential detector 220 may input an NCO 301, which is a compensation for a CFO in the -1.35% range, to a delay line with iDL = 0. In addition, the simple differential detector 220 also includes an NCO 301, which is a compensation for the CFO in the range of -0.9%, and a compensation for the CFO in the range of -0.45%, to the delay line iDL = 1 and the delay line iDL = NCO < RTI ID = 0.0 > 301 < / RTI > Then, the simple differential detector 220 may input the NCO 301, which is a compensation for the CFO in the 0% range, to the delay line of iDL = 3. In addition, the simple differential detector 220 has NCO 301, which is a compensation for the CFO in the range of 0.45% for the delay line of iDL = 4, a delay line of iDL = 5, and a delay line of iDL = An NCO 301 as a compensation for CFO, and an NCO 301 as a compensation for CFO in the range of 1.35%.

For example, when the input data is r (n), data r _l [n] input to each of the delay lines by applying different NCOs to r (n) can be calculated by Equation (1).

Where n is the sample index of the input data and l may be the index of the delay line. Also, the delay lines can operate at 2x speed and the length of the delay lines can be 1440, which is twice the 720.

In addition, each delay line is made up of 48 accumulators, and each accumulator can accumulate 15 symbols 1x. Since the signal input to the delay line is a 2-multiplied sample, the accumulators may accumulate symbols on a symbol (1x) domain using a means of performing an operation of skipping one sample, such as a counter. At this time, the number of symbols accumulated by the accumulators may be determined according to the characteristics of the SOSF & SFFI symbols used in the frame detection apparatus.

For example, the accumulated symbol A _l [k] [n] in the accumulator can be calculated by Equation (2).

Here, k is an index of an accumulator, and C [i] may be a de-scrambling and a phase rotation sequence.

In addition, since the simple differential detector 220 calculates the phase difference between consecutive accumulators in the delay line, the accumulators that calculate the phase difference are referred to herein as the first accumulator and the second accumulator, Respectively. However, since the first accumulator and the second accumulator are defined to explain whether or not to calculate the phase difference between the accumulators, the first accumulator and the second accumulator may have the same hardware or software configuration. Then, the simple differential detector 220 can calculate the phase difference between the first accumulator and the second accumulator.

4 is a characteristic of SOSF & SFFI symbols used in an embodiment of the present invention.

로 변환된 SOSF & SFFI 복소 심벌의 동상(in-phase) 신호(410) 및 직각 위상(quadrature phase) 신호(420)는 도 4에 도시된 바와 같을 수 있다.If the SFFI index is 2,

The in-phase signal 410 and the quadrature phase signal 420 of the SOSF & SFFI complex symbol converted into the quadrature phase signal 420 may be as shown in FIG.

로 위치하도록 위상을 변환시킬 수 있다. 또한, SFFI는 15개의 심벌이 30번씩 반복되어 전송이 되므로 30 심벌 동안 위상이 동일할 수 있다. 또한, 입력 데이터의 N 체배 샘플링 주파수를 사용하는 경우, SFFI는 30* N 심벌 동안 위상이 동일할 수 있다. 그리고, 오프셋(offset)이 없는 경우, SOSF & SFFI 심벌에서 누적값 블록(400)들은 항상 동일한 위상을 가질 수 있다.Since the SOSF is a promised symbol between the transmitter 101 and the receiver 102, the receiver 102 may determine that all SOSF symbols

As shown in FIG. In addition, the SFFI is transmitted by repeating 15 symbols 30 times, so that the phase can be the same during 30 symbols. Also, if an N-multiplication sampling frequency of the input data is used, the SFFI may have the same phase during a 30 * N symbol. And, if there is no offset, the accumulation blocks 400 in the SOSF & SFFI symbols can always have the same phase.

5 is an example of a process of calculating a sum of phase differences of accumulated symbols in accumulators according to an embodiment of the present invention.

The simple differential detector 220 performs complex conjugate multiplication on the values of symbol units accumulated in fifteen symbol units in the first accumulator 510 and the second accumulator 520 to generate a first accumulator 510 ) And the second accumulator 520. In this case, For example, if the SOSF & SFFI 500 is located exactly on a symbol basis in the delay line and there is no Additive White Gaussian Noise (AWGN), SPO, and CFO, the first accumulator 510 and the second accumulator 520, There is no phase difference 530 between them. At this time, if n is the last transmitted sample of SFFI, R ₃ [n] may be 5400.

However, the above condition is limited to the case where an ideal situation occurs, and in reality, an error occurs in the position of the SOSF & SFFI 500 and AWGN, SPO, and CFO also occur. A phase difference 530 between the two accumulators 520 also occurs.

Accuval (i), which is the phase difference 530 between the values of the symbol units accumulated in the first accumulator 510 and the values of the symbol units accumulated in the second accumulator 520, is 15 (Accu_period ) x 2 x CFO '. In this case, Accu_period is the period of the symbols accumulated in the first accumulator 510 and the second accumulator 520, and thus may be 15 in the embodiment of FIG. Also, CFO '= (CFO - CFO_compen_Delay_line). At this time, CFO_compen_Delay_line may be a CFO compensating in each of the delay lines. For example, CFO_compen_Delay_line may be the NCO shown in FIG.

6 is an example of a process of detecting a frame on the time axis using the result of FIG.

Since the 48 accumulators constituting each of the delay lines are classified into 24 first accumulators 510 and 24 second accumulators 520, the values of the symbol units accumulated in the first accumulator 510, Accuval (i), which is the phase difference 530 between the values of the symbol units accumulated in the accumulator 520, may be calculated by 24 in each of the delay lines.

At this time, the simple differential detector 220 may calculate R _l [n], which is the sum of the phase differences 530 of the accumulated symbols in the accumulators for each delay line. In this case, R _l [n] may be the absolute value of the consensus 24 Accuval (i). For example, the simple differential detector 220 may calculate R _l [n] as shown in equation (3).

Here, * may be a conjugate complex operator.

Then, the simple differential detector Scorebuf (220) is a D flip-flop (flip-flop) buffer for two body fold behavior of R _l [n] of the delay line, which is calculated each time a second multiplying the received samples of the input data input [ iDL] [3]. At this time, the simple differential detector 220 can estimate SPO using R _l [n] of each delay line stored in Scorebuf [iDL] [3].

Further, the simple differential detector 220 generates output data second multiplier receiving the time base for the R _{l, max} [n] the maximum value (MaxScore) among the R _l [n], each delay line is calculated each time the sample is input to the You can set a threshold. At this time, the time-base threshold value may be determined according to the AWGN, CFO, and SPO as the reception target in the receiver 102.

The time-base frame detector 230 may detect a frame on the time axis of the input data using a time-base threshold.

7 is an example of a process of detecting a frame on the frequency axis according to an embodiment of the present invention.

7, the FFT implementer 240 performs a complex conjugate multiplication operation between the values 710 of accumulators of the delay line having R _l [n] equal to or greater than the time axis threshold value and the SFFIVect values 720 A 256 FFT operation 730 can be performed by performing zero padding.

At this time, the SFFIVect value 720 may be the phase-converted SOSF value and the SFFI symbol value that is repeated twice and modulated with BPSK. Since the SFFI is defined 0 to 4 times in the DVB-S2x Annex-E [1] standard, five SSFIVect values (720) must be used to detect superframe frames having all SFFI values. Only one SFFIVect value 720 can be used to detect a frame having a frame.

As shown in FIG. 7, the FFT processor 240 performs a complex conjugate multiplication operation 710 between the SFFIVect value 720 and the accumulator values 710 of the delay line having R _l [n] Lt; RTI ID = 0.0 > FFT < / RTI >

That is, the number of FFT operators 240 included in the frame detection apparatus 100 can be determined according to the number of SFF frames used by the frame detection apparatus 100. [

Also, since the number of accumulators included in the delay line having R _l [n] equal to or greater than the time axis threshold value is 48, the value 710 of the accumulators may be the values of the symbol units accumulated in each of the 48 accumulators. Therefore, the FFT processor 240 performs 256 FFT operations on the values of the symbol units accumulated in each of the 48 accumulators by performing (256-48) = 208 zero padding on the values of the symbol units, thereby obtaining 2.6e-4 = 1 / (256 * AccuPeriod) frequency resolution.

The frequency axis frame detector 250 can detect a frame on the frequency axis by applying a coherent detection method to the values of the FFT operation.

In FIG. 3, since the CFO interval of each of the delay lines is 0.45%, the CFO estimated by each of the delay lines is within 0.45%. The frequency axis frame detector 250 performs an FFT operation on the absolute values of the 0th to 17th frequency components and the 239th to 255th frequency components of the FFT-performed values. It is possible to check whether the maximum value (best FFT score) of one result exceeds the frequency axis threshold value. At this time, the frequency threshold value may be set in consideration of AWGN and sampling timing offset (STO).

If the maximum value of the FFT operation results exceeds the frequency axis threshold value, the frequency axis frame detector 250 may determine that the frame is detected at the N-multiple sampling frequency of the input data.

For example, the frequency axis frame detector 250 can detect a frame in the frequency axis using the coherent detection method as shown in Equations (4) to (6).

Here, P [m] is locally generated SOSF & SFFI, and l may be an index of R _{l, max} [n] which is the maximum value (MaxScore) among R _l [n] of the delay lines.

인 P [m]에 대하여

일 수 있다. 또한, 디스크램블된 15 SFFI 심벌들은 모두

인 P [m]에 대하여 2회 반복될 수 있다.The descrambled and phase rotated SOSF symbols are all

About P [m]

Lt; / RTI > Further, the 15 descrambled SFFI symbols are all

Can be repeated twice for P [m].

8 is an example of a process of calculating a value input to the FFT processor.

The value input to the FFT performer 240 may be the result of a complex conjugate multiplication operation between the values 810 of accumulators of the delay line and the SFFIVect values 820 of the delay line having R _l [n] .

At this time, the value 810 of the accumulators of the delay line is calculated by multiplying the values of the symbol units accumulated in the first accumulator 510 and the values of the symbol units accumulated in the second accumulator 520, .

로 변환된 SOSF 값과 2번 반복되고 BPSK로 변조된 SFFI 심벌 값일 수 있다.Also, the SFFIVect value 820 indicates that the phase is < RTI ID = 0.0 >

Lt; / RTI > and SFFI symbol values that are repeated twice and modulated with BPSK.

Then, when SOSF & SFFI is correctly located in the accumulator of the delay line, the result of the complex conjugate multiplication operation between the SFFIVect value 820 and the accumulator value 810 of the delay line having Score [iDL] It can be a constant constant such as a DC value and the sum of CFOs.

9 is a flowchart showing a frame detection method according to an embodiment of the present invention.

In step 910, the frame detection apparatus 100 may compensate for different ranges of CFOs in the input data for each delay line.

The accumulators constituting each of the delay lines included in the frame detection apparatus 100 in step 920 may accumulate the symbols included in the input data received in step 910,

In step 930, the frame detection apparatus 100 may calculate the sum of the phase differences of the symbols accumulated in step 920 for each delay line. At this time, the sum of the phase differences may be determined according to at least one of the number of accumulators, the period of the symbols accumulated in each of the accumulators, and the difference between AWGN, SPO, and CFO compensated for each delay line.

In step 940, the frame detection apparatus 100 may detect the frame on the time axis of the input data using the time base threshold value set for the maximum value among the sum of the phase differences calculated in step 930. At this time, the time base threshold value may be set according to the AWGN, the CFO and the estimated SPO according to the reception target.

In step 950, the frame detection apparatus 100 may detect the frame in the frequency axis of the input data using the sum of the phase differences having a value equal to or greater than the time axis threshold value in the sum of the phase differences calculated in step 930 .

10 is a flowchart illustrating a process of detecting a frame on the frequency axis of the frame detection method according to an embodiment of the present invention. Steps 1010 to 1040 of FIG. 10 may be included in step 950 of FIG.

In step 1010, the frame detection apparatus 100 may perform a complex conjugate multiplication operation on the values of the accumulator of the delay line having Score [iDL] equal to or greater than the SFFIVect value and the time axis threshold value. At this time, the result of the complex conjugate multiplication operation may be a constant constant and a sum of CFOs.

In step 1020, the frame detection apparatus 100 may perform 256 FFT operations by zero padding the sum of the constant and the CFO determined in step 1010. [

In step 1030, the frame detection apparatus 100 may check whether the maximum value of the results of performing the FFT operation of step 1020 exceeds a frequency axis threshold value.

If the maximum value of the result of performing the FFT operation of step 1020 exceeds the frequency axis threshold value, the frequency axis frame detector 250 detects the frame at the N-multiple sampling frequency of the input data in step 1040 .

If the maximum value among the values obtained by performing the FFT operation of step 1020 is less than or equal to the frequency axis threshold value, the frequency axis frame detector 250 determines that the maximum value of the results obtained by performing the FFT operation of step 1020 is & Step 1030 may be repeatedly performed until the axial threshold is exceeded.

The present invention detects a superframe in a signal by using a simple differential detector that includes a plurality of delay lines and compensates for CFOs of different ranges in input data for each delay line to thereby reduce hardware complexity and provide a low signal- It is possible to accurately detect the frame at the SNR.

Meanwhile, the method according to the present invention may be embodied as a program that can be executed by a computer, and may be embodied as various recording media such as a magnetic storage medium, an optical reading medium, and a digital storage medium.

Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or combinations thereof. Implementations may be implemented in a computer program product, such as an information carrier, e.g., a machine readable storage device, such as a computer readable storage medium, for example, for processing by a data processing apparatus, Apparatus (computer readable medium) or as a computer program tangibly embodied in a propagation signal. A computer program, such as the computer program (s) described above, may be written in any form of programming language, including compiled or interpreted languages, and may be stored as a stand-alone program or in a module, component, subroutine, As other units suitable for use in the present invention. A computer program may be deployed to be processed on one computer or multiple computers at one site or distributed across multiple sites and interconnected by a communications network.

Processors suitable for processing a computer program include, by way of example, both general purpose and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer may include one or more mass storage devices for storing data, such as magnetic, magneto-optical disks, or optical disks, or may receive data from them, transmit data to them, . ≪ / RTI > Information carriers suitable for embodying computer program instructions and data include, for example, semiconductor memory devices, for example, magnetic media such as hard disks, floppy disks and magnetic tape, compact disk read only memory A magneto-optical medium such as a floppy disk, an optical disk such as a DVD (Digital Video Disk), a ROM (Read Only Memory), a RAM , Random Access Memory), a flash memory, an EPROM (Erasable Programmable ROM), an EEPROM (Electrically Erasable Programmable ROM), and the like. The processor and memory may be supplemented or included by special purpose logic circuitry.

In addition, the computer-readable medium can be any available media that can be accessed by a computer, and can include both computer storage media and transmission media.

While the specification contains a number of specific implementation details, it should be understood that they are not to be construed as limitations on the scope of any invention or claim, but rather on the description of features that may be specific to a particular embodiment of a particular invention Should be understood. Certain features described herein in the context of separate embodiments may be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, either individually or in any suitable subcombination. Further, although the features may operate in a particular combination and may be initially described as so claimed, one or more features from the claimed combination may in some cases be excluded from the combination, Or a variant of a subcombination.

Likewise, although the operations are depicted in the drawings in a particular order, it should be understood that such operations must be performed in that particular order or sequential order shown to achieve the desired result, or that all illustrated operations should be performed. In certain cases, multitasking and parallel processing may be advantageous. Also, the separation of the various device components of the above-described embodiments should not be understood as requiring such separation in all embodiments, and the described program components and devices will generally be integrated together into a single software product or packaged into multiple software products It should be understood.

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100: frame detection device
220: Simple differential detector
230: Time base frame detector
240: FFT implementer
250: Frequency axis frame detector

Claims (12)

Compensating the carrier frequency offset (CFO) of different ranges in the input data for each delay line;
Accumulating the symbols included in the input data by accumulators constituting each of the delay lines;
Calculating a sum of phase differences of symbols accumulated in the accumulators for each delay line;
Detecting a frame on a time axis of the input data using a time axis threshold value set for a maximum value among a sum of the phase differences; And
Detecting a frame in a frequency axis of the input data using a sum of phase differences having a value equal to or greater than the time axis threshold value among the sum of the phase differences;
/ RTI > The method according to claim 1,
The phase difference of the accumulated symbols in each of the accumulators may be expressed as:
A difference between a CFO and a CFO compensated for each delay line and a period of a symbol accumulated in the accumulators. The method according to claim 1,
The sum of the phase differences
A frame determined according to at least one of a difference between the number of accumulators, a period of a symbol accumulated in each of the accumulators, an additive white Gaussian noise (AWGN), a software pattern ontology (SPO) Detection method. The method according to claim 1,
Estimating SPO using the sum of the phase differences; And
Setting the time base threshold value according to AWGN, CFO and estimated SPO according to a reception target
Further comprising: The method according to claim 1,
Wherein the step of detecting a frame on the frequency axis comprises:
Determining the sum of the constant constant and the CFO using the SFFIVect including the phase-converted SOSF value and the SSFI symbol value modulated by BPSK (Binary Phase Shift Keying) and the sum of the phase differences having a value equal to or greater than the time axis threshold value; ;
Performing zero-padding on the sum of the predetermined constant and the CFO, and performing an FFT operation; And
If the maximum value of the frequency component determined according to the CFO interval of each of the delay lines among the values obtained by performing the FFT operation exceeds the frequency axis threshold value, it is determined that the frame is detected at the N-multiple sampling frequency of the input data step
/ RTI > The method according to claim 1,
The CFO includes:
Wherein N is an integer greater than or equal to 2, the normalized N-th sampling frequency of the input data. A simple differential detector for compensating for different ranges of CFOs in the input data for each delay line and calculating the sum of the phase differences of the symbols of the input data accumulated in the accumulators constituting each of the delay lines;
A time axis frame detector for detecting a frame on a time axis of the input data using a time axis threshold value set for a maximum value among a sum of the phase differences; And
A frequency axis frame detector for detecting a frame in the frequency axis of the input data using a sum of the phase differences having a value equal to or greater than the time axis threshold value among the sums of the phase differences;
And a frame detector. 8. The method of claim 7,
The phase difference of the accumulated symbols in each of the accumulators may be expressed as:
The difference between the CFO and the CFO compensated for each delay line and the period of the symbols accumulated in the accumulators. 8. The method of claim 7,
The sum of the phase differences
A difference between the number of accumulators, a period of a symbol accumulated in each of the accumulators, an AWGN, and a CFO compensated for each delay line. 8. The method of claim 7,
The time-
The frame detection apparatus is set according to AWGN, CFO, and estimated SPO according to a reception target. 8. The method of claim 7,
An SFFIVect including a phase-converted SOSF value and an SSFI symbol value modulated with BPSK, and an FFT operator for performing zero-padding on the sum of phase differences having a value equal to or greater than the time axis threshold value and performing an FFT operation
Further comprising:
Wherein the frequency axis frame detector comprises:
If the maximum value of the frequency component determined according to the CFO interval of each of the delay lines among the values obtained by performing the FFT operation exceeds the frequency axis threshold value, it is determined that the frame is detected at the N-multiple sampling frequency of the input data Frame detection device. 8. The method of claim 7,
The CFO includes:
Wherein N is an integer greater than or equal to 2, the normalization being determined by normalizing the N-multiple sampling frequency of the input data.

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