KR20190037008A - Circuit for static random access memory and display apparatus comprising the same - Google Patents

Abstract

Disclosed is a static random-access memory (SRAM) circuit and a display device including the same. According to the present invention, the SRAM circuit includes: a control unit which is connected to a first power supply node (low) supplying a first voltage and generates row signals and column signals at the first voltage; a level shifter which shifts the magnitude of row selection signals generated by the control unit from the first voltage to a second voltage having a greater magnitude compared to the first voltage; one or more switching units which are connected to a second power supply node (high) for supplying the second voltage, row selection signal lines, and column signal lines; and a memory cell which applies at least one of a third voltage, the column signals of the first voltage, and the row selection signals of the second voltage converted by the level shifter to the switching units to drive a display device at the second voltage supplied from the second power supply node. According to the present invention, data values can be stored in the memory cell at a high voltage while at least one of the row selection signals and column signals is applied at a low voltage, and thus the speed of the display device can be increased and power consumption can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an SRAM circuit and a display device including the SRAM circuit.

The present invention relates to an SRAM circuit and a display device including the same, and more particularly, to a SRAM circuit having a high data value stored in a memory cell and a display device including the same.

2. Description of the Related Art Generally, a display device is an apparatus for displaying an image on a display panel using electrical and optical characteristics, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED) . Such a display device has a structure in which a plurality of pixels are arranged in the form of a two-dimensional matrix of rows and columns.

In the case of a display device that drives pixels in a digital manner, each pixel includes an N-bit memory, and the color of the screen is determined according to the value of the memory. A method of storing data values in the pixel memory will be described with reference to FIG.

FIG. 1 is a view for explaining a digital pixel driving method of a conventional display device, and FIG. 2 is a circuit diagram of a memory cell of a conventional display device.

Referring to FIG. 1, a conventional display device has a structure in which a plurality of pixels (pixels) are arranged in R rows and C columns. In the conventional method of driving a digital pixel of a display device, an N bit memory is included in each pixel, and the color of the screen is determined according to each memory value. In many cases, N = 1. Although the description below is limited to the case of N = 1, a conceptual similar explanation is possible even when N has a different value.

A method of storing a value in a memory included in each pixel is based on a row select signal (e.g., a scan line select signal) (Fig. 1A), and a row line sequentially turns from ROW_1 to ROW_R The desired data value (0 or 1) can be applied to each of the column lines COL_1 to COL_C (Fig. 1 (b)). In this case, the application time (T _ON ) of the row selection signal of each row means a time obtained by dividing the unit time slot by the total number of rows R, and can be sequentially turned on for each Ton time. That is, by turning on ROW_1 by a row select signal and applying a desired data value to COL_1 through COL_C, data values can be stored in each pixel crossing ROW_1 and COL_1 through COL_C, respectively. Next, after turning off ROW_1, it is possible to store data values in each pixel crossing ROW_2 and COL_1 to COL_C, respectively, by turning on ROW_2 and applying desired data values to COL_1 to COL_C.

Referring to FIG. 2, the memory cell of the conventional display device includes a plurality of transistors M1 to M6. The first and fourth transistors M1 and M6 are turned on and off according to a row select signal ROW and a column signal COL / , M4 may switch and apply a data value to the display device.

In this manner, the brightness of the entire display panel can be adjusted by the difference in time occupancy ratio of '0' and '1' stored in the memory cell or occupied area ratio. When a small-sized transistor operating at a low voltage is used to generate a signal of a row line and a column line, the power consumption can be reduced and the operation speed can be increased. have. However, a liquid crystal or OLED (Organic Light Emitting Device) is mainly used as a material of the display device, and a data value driving a pixel is often applied at a high voltage in view of the material characteristics of the display device. The transistors M1 to M6 constituting the cell must be driven with a high voltage to display an accurate pixel value.

In order to drive the transistors M1 to M6 at a high voltage in this manner, a level shifter array is provided in a row line and a column line, respectively, as shown in FIG. 1 (b) Voltage low select signal / column signal to a high voltage low select signal / column signal. However, if the entire display pixel is driven at a high voltage by using a level shifter array, the operation speed is remarkably slowed due to the characteristics of the high voltage transistor used in the driving circuit, and the total power consumption is greatly increased.

In order to solve the above problems, an object of the present invention is to provide an SRAM circuit for driving a row line and a column line at a low voltage while driving a memory cell at a high voltage, and a display device including the same will be.

In order to achieve the above object, the SRAM circuit includes a control unit connected to a first power supply node low to supply a first voltage and generating a row signal and a column signal with the first voltage, A level shifter for changing a magnitude of the row select signal generated by the controller to a second voltage greater than the first voltage, and a second power supply node for supplying a second voltage, a row select signal line, And at least one of a row select signal of the second voltage, a column signal of the first voltage, or a third voltage, which is converted in the level shifter, is applied to the at least one switching unit And a memory cell for driving the display device to a second voltage supplied from the second power supply node.

Wherein the at least one switching unit includes first switching units M1 and M4 that are switched according to a row selection signal of the second voltage, second switching units M2, M3, and M5 that switch according to a column signal of the first voltage, And M6), and a third switching unit (M7, M8) that is switched to the third voltage or a row selection signal of the second voltage.

The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit is composed of seventh and eighth transistors M7 and M8. The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line, The source terminals of the first and second transistors M1 and M4 are respectively connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8, The source terminals of the sixth transistors M5 and M6 are connected to the second power source node and the drain terminals thereof are connected to the source terminals of the seventh and eighth transistors M7 and M8, And M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the first and fourth transistors M1 and M4 are connected to the source terminal of the first transistor M1 according to a row select signal of the second voltage applied to the gate terminal, The first transistor M1 transmits the first voltage column signal applied to one end of the first transistor M1 to the gate terminals of the third and sixth transistors M3 and M6, And the fifth and sixth transistors M5 and M6 transfer the column signal of the first voltage applied to the gate terminal and the column signal of the first voltage applied to the gate terminal of the fifth transistor M2, The second voltage of the second power source is applied to the gate terminal of the seventh and eighth transistors M7 and M8 according to an inverting column signal, The fifth transistor M5, The connection of the first transistor M1 may be cut off and the connection of the sixth transistor M6 and the fourth transistor M4 may be disconnected.

The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit is composed of seventh and eighth transistors M7 and M8. The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line, The source terminals of the first and second transistors M1 and M4 are respectively connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8, The source terminals of the sixth transistors M5 and M6 are connected to the second power source node and the drain terminals thereof are connected to the source terminals of the seventh and eighth transistors M7 and M8, And M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the first and fourth transistors M1 and M4 are connected to the source terminal of the first transistor M1 according to a row select signal of the second voltage applied to the gate terminal, The first transistor M1 transmits the first voltage column signal applied to one end of the first transistor M1 to the gate terminals of the third and sixth transistors M3 and M6, And the fifth and sixth transistors M5 and M6 transfer the column signal of the first voltage applied to the gate terminal and the column signal of the first voltage applied to the gate terminal of the fifth transistor M2, Wherein the first voltage is applied to the gate terminal of the seventh and eighth transistors M7 and M8 in accordance with an inverting column signal to transfer the second voltage of the second power supply node to the display device, The transistor M1 and the fourth transistor M4 The current flow can be interrupted.

Here, the third voltage may be a voltage having a magnitude relatively lower than a value obtained by subtracting a large absolute value of a threshold voltage of the seventh and eighth transistors M7 and M8 from the second voltage.

The row select signal may be a scan line select signal or a word line select signal, and the column signal may be a data signal or a bit signal.

According to another aspect of the present invention, there is provided a display apparatus including a controller coupled to a first power supply node low to supply a first voltage to generate a scan line select signal and a data signal with the first voltage, A level shifter array for changing the level of the scan line selection signal to a second voltage greater than the first voltage, a second power supply node for supplying a second voltage, at least one switching unit connected to the scan line and the data signal line, And supplying at least one of the scan line selection signal of the second voltage, the data signal of the first voltage, or the third voltage, which is converted in the level shifter, to the at least one switching unit, And a memory cell array for driving each of the display elements with a second voltage applied thereto, and in accordance with the scanning line selection signal, So that the data signal can be sequentially stored.

According to another aspect of the present invention, there is provided an SRAM circuit including a controller coupled to a first power supply node supplying a first voltage to generate a row signal and a column signal with the first voltage, And a second power supply node (high) for supplying a second voltage having a magnitude greater than the first voltage, a row select signal line, and at least one switching unit connected to the column signal line, A column select signal, a row select signal, a column signal of the first voltage, or a third voltage to the at least one switching unit to drive the display device to a second voltage supplied from the second power supply node can do.

The at least one switching unit includes a first switching unit (M1, M4) for switching in response to a row selection signal of the first voltage, a second switching unit (M2, M3, M5) for switching in accordance with a column signal of the first voltage, And M6, and third switching units M7 and M8 that are switched according to the row selection signal of the first voltage or the third voltage.

The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit is composed of seventh and eighth transistors M7 and M8. The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line, The source terminals of the first and second transistors M1 and M4 are respectively connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8, The source terminals of the sixth transistors M5 and M6 are connected to the second power source node and the drain terminals thereof are connected to the source terminals of the seventh and eighth transistors M7 and M8, And M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the first and fourth transistors M1 and M4 are coupled to the gate terminal of the first transistor M1 according to a row select signal of the first voltage, The first transistor M1 transmits the first voltage column signal applied to one end of the first transistor M1 to the gate terminals of the third and sixth transistors M3 and M6, And the fifth and sixth transistors M5 and M6 transfer the column signal of the first voltage applied to the gate terminal and the column signal of the first voltage applied to the gate terminal of the fifth transistor M2, And the seventh and eighth transistors (M7, M8) and the seventh and eighth transistors (M7, M8) are connected to the display element in accordance with an inverting column signal, Can be satisfied.

(W / L) _{M1, M4} >> (W / L) _{M7, M8}

(Where W represents Weight and L represents Length)

The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit is composed of seventh and eighth transistors M7 and M8. The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line, The source terminals of the first and second transistors M1 and M4 are respectively connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8, The source terminals of the sixth transistors M5 and M6 are connected to the second power source node and the drain terminals thereof are connected to the source terminals of the seventh and eighth transistors M7 and M8, And M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the first and fourth transistors M1 and M4 are coupled to the gate terminal of the first transistor M1 according to a row select signal of the first voltage, The first transistor M1 transmits the first voltage column signal applied to one end of the first transistor M1 to the gate terminals of the third and sixth transistors M3 and M6, And the fifth and sixth transistors M5 and M6 transfer the column signal of the first voltage applied to the gate terminal and the column signal of the first voltage applied to the gate terminal of the fifth transistor M2, Wherein the first voltage is applied to the gate terminal of the seventh and eighth transistors M7 and M8 in accordance with an inverting column signal to transfer the second voltage of the second power supply node to the display device, The transistor M1 and the fourth transistor M4 Current flow is blocked,

Here, the third voltage may be a voltage having a magnitude relatively lower than a value obtained by subtracting a large one of absolute values of threshold voltages of the seventh and eighth transistors M7 and M8 from the second voltage .

The row select signal may be a scan line select signal or a word line select signal, and the column signal may be a data signal or a bit signal.

According to another aspect of the present invention, there is provided a display device including a control unit coupled to a first power supply node low to supply a first voltage to generate a scan line select signal and a data signal with the first voltage, A second power supply node for supplying a second voltage of a greater magnitude, and at least one switching unit connected to a scanning line and a data signal line, the scanning line selection signal of the first voltage generated by the control unit, And a memory cell array for applying at least one of a data signal, a data signal of a voltage, or a third voltage to the at least one switching unit to drive each display device to a second voltage supplied from the second power source node, The data signal may be stored in the memory cell array sequentially according to a signal.

According to the present invention, since the data value can be stored in the memory cell at a high voltage while applying at least one of the row select signal or the column signal to the low voltage, the consumption power can be reduced while increasing the speed of the display device.

1 is a view for explaining a digital pixel driving method of a conventional display device.
2 is a circuit diagram of a memory cell of a conventional display device.
3 is a view for explaining a digital pixel driving method when a low voltage column signal and a high voltage row selection signal are applied to the display device of the present invention.
FIG. 4 is a diagram for explaining a case where the circuit of the memory cell of FIG. 2 is applied to FIG.
5A and 5B are views for explaining the driving principle of the memory cell of FIG.
6 is a circuit diagram for driving a memory cell with a low voltage column signal, a high voltage row select signal according to an embodiment of the present invention.
FIGS. 7A and 7B are views for explaining a driving principle of a memory cell when a low-voltage column signal and a high-voltage row selection signal are applied to the circuit proposed in FIG. 6 according to an embodiment of the present invention.
8 is a circuit diagram proposed to drive a memory cell with a low voltage column signal, a high voltage row select signal according to another embodiment of the present invention.
FIGS. 9A and 9B are diagrams for explaining a driving principle of a memory cell when a low-voltage column signal and a high-voltage row selection signal are applied to the circuit proposed in FIG. 8 according to another embodiment of the present invention.
10 is a view for explaining a digital pixel driving method when a low voltage column signal and a low voltage row selection signal are applied to the display device of the present invention.
FIG. 11 is a diagram for explaining a case where the circuit of the memory cell of FIG. 6 is applied to FIG.
12A to 12B are diagrams for explaining the driving principle of the memory cell of FIG.
13 is a circuit diagram proposed to drive a memory cell with a low voltage column signal, a low voltage row select signal according to an embodiment of the present invention.
FIGS. 14A and 14B are diagrams for explaining a driving principle of a memory cell when a low-voltage column signal and a low-voltage row selection signal are applied to the circuit shown in FIG. 13 according to an embodiment of the present invention.
15 is a circuit diagram proposed to drive a memory cell with a low voltage column signal, a low voltage row select signal according to another embodiment of the present invention.
FIGS. 16A and 16B are diagrams for explaining a driving principle of a memory cell when a low-voltage column signal and a low-voltage row selection signal are applied to the circuit proposed in FIG. 15 according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted. The suffix " part " for the constituent elements used in the following description is to be given or mixed with consideration only for ease of specification, and does not have a meaning or role that distinguishes itself.

In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. , ≪ / RTI > equivalents, and alternatives.

Terms including ordinals, such as first, second, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a component, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

For convenience of explanation, the low voltage signal is indicated in lower case and the high voltage signal is indicated in upper case, and the magnitudes of the low voltage and the high voltage indicate the magnitude of the voltage used for driving the low voltage transistor and the high voltage transistor in the display device. The low voltage and the high voltage are used as a relative concept, and can be changed depending on the performance of the transistor, the performance of the display device, and the like.

3 is a view for explaining a digital pixel driving method when a low voltage column signal and a high voltage row selection signal are applied to the display device of the present invention.

3, the display device of the present invention includes a level shifter array arranged in a column direction through which low voltage row select signals row_1 to row_R pass, and outputs low voltage row select signals row_1 to row_R as a high voltage row select signal ROW_1 To ROW_C), and then the low voltage column signals col_1 to col_C and the high voltage row select signals ROW_1 to ROW_C are applied to the memory cell array to drive the display device.

The display device of the present invention is a structure in which a plurality of pixels are arranged in R rows and C columns, and each pixel includes a 1-bit memory cell. Here, the 1-bit memory can be replaced with an N-bit memory and can be configured as a static random access memory (SRAM) circuit.

Method for driving each memory cell row selection signal based on the (e.g., the scanning line selection signal), the row line (row line) is from ROW_1 a row select signal of the high voltage (V _{DD _high)} which has passed through the level shifter array ROW_R Can be applied sequentially. When a row select signal is applied to each row line, low-voltage column signals col_1 to col_C can be applied to the respective column lines. At this time, a high voltage row select signal is a "V _{DD _high} 'applied for a period of time that the row is selected and a' 0 'is applied for the rest period, low-voltage column signal depending on the data value,' 0 'or' V _{DD_low} Can be granted.

By turning on ROW_1 by a row select signal to apply the desired data values to col_1 to col_C, data values can be stored in each pixel that crosses ROW_1 and col_1 to col_C, respectively. Thus, by sequentially turning on ROW_1 through ROW_2, ..., and ROW_R and applying a desired data value through the column lines col_1 through col_C, data values are sequentially stored in the pixels of each row or stored data You can change the value.

FIG. 4 is a diagram for explaining a case where the circuit of the memory cell of FIG. 2 is applied to FIG. 3, and FIGS. 5A to 5B are views for explaining the driving principle of the memory cell of FIG.

Referring to Figure 4, application of a memory cell circuit of Figure 2 to Figure 3, a memory cell is composed of a plurality of transistors (M1 to M6), a high voltage row select signal (ROW) and a low voltage (V _{DD _high)} ( V _DD, while the first and fourth transistors (M1, M4) according to a column signal (col / colb) _{_low} switching) can be applied to data values to the display device. Hereinafter to describe the operating principle of storing a data value in the memory cell of Figure 4 to the column signal (col / colb) of the row select signal (ROW) and a low voltage (V _{DD _low)} of the high voltage (V _{DD _high).}

Referring to Figure 5a, and when writing a data value to the same data value stored in the display device of the particular memory cell, i.e., = the current display device (X node) data value V _X stored in the V _{DD _ high,} corresponding to the pixels When the row select signal is applied by applying a data value (V _{DD_low)} saved in (rOW = V _{DD _high)} column lines can write the same data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row select signal is applied to the row including the memory cell (ROW = 0), data stored in the display element (X node) value V _X = V _{DD_high} is maintained.

Next, when a row select signal is applied to the row including the memory cell (ROW = V _{DD_high} ), the first and fourth transistors M 1 and M 4 are turned on, and the Y node is turned to 0 The second transistor M2 can be turned off and the fifth transistor M5 can be turned on. In addition, the first, fifth, since the transistors (M1, M5) turned on, the constant current I ₁ is the fifth transistor is caused to flow toward the first transistor (M1) from (M5) side. Therefore, since the voltage values of the X node V _X is V _{DD _low} and V _DD is a value between _{_high,} sixth and turns on the transistor (M6), the peg to completely turn off the third transistor (M3), a sixth transistor ( M6) a fourth transistor (M4) is a constant current I ₂ flows from the side of the side, the sixth constant current I ₃ is the side of the transistor (third transistor (M3) from the M6) side to flow.

When the row select signal is applied to the row including the next memory cell after writing data in the memory cell, the previous memory cell becomes ROW = 0, so that the first and fourth transistors M1 and M4 are turned off again, data values stored in the display device (node X) (voltage value) V _X may be stored in the change in value between V _DD and V _{DD_low _high} to V _{DD _high.}

In this case, accurate data values can be stored in the display device, but the constant currents I ₁ to I ₃ flow when the memory cell is selected, which causes a problem of high power consumption.

5B, when a data value different from the data value stored in the display element of a specific memory cell is written, that is, when the data value V _X = 0 stored in the current display element (X node) When applied to a store (ROW = V _{DD _high)} column lines by applying a data value (V _{DD_low)} can write different data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row select signal is applied to the row including the memory cell (ROW = 0), data stored in the display element (X node) The value V _X = 0 is maintained.

Next, when a row select signal is applied to the row including the memory cell (ROW = V _{DD_high} ), the first and fourth transistors M 1 and M 4 are turned on, and the Y node is turned to 0 The second transistor M2 can be turned off and the fifth transistor M5 can be turned on. In addition, the first, fifth, since the transistors (M1, M5) turned on, the constant current I ₁ is the fifth transistor is caused to flow toward the first transistor (M1) from (M5) side. Therefore, since the voltage values of the X node V _X is V _{DD _low} and V _DD is a value between _{_high,} sixth and turns on the transistor (M6), the peg to completely turn off the third transistor (M3), a sixth transistor ( M6) a fourth transistor (M4) is a constant current I ₂ flows from the side of the side, the sixth constant current I ₃ is the side of the transistor (third transistor (M3) from the M6) side to flow.

When the row select signal is applied to the row including the next memory cell after writing data in the memory cell, the previous memory cell becomes ROW = 0, so that the first and fourth transistors M1 and M4 are turned off again, data values stored in the display device (node X) (voltage value) V _X may be stored in the change in value between V and V _{DD_low DD_high} to V _{DD_high.}

Similarly, although accurate data values can be stored in the display device, there is a problem that power consumption is large because the constant currents I ₁ to I ₃ flow when the memory cell is selected.

Therefore, the leakage current I ₁ flowing from the fifth transistor M 5 side to the first transistor M 1 side and the leakage current I ₁ flowing from the fifth transistor M 5 side to the first transistor M 1 side, while the circuit of the memory cell is being driven by applying the low voltage column signal and the high- There is a need for a circuit capable of storing accurate data values in a display device while preventing leakage currents I ₂ and I ₃ from flowing from the first and second transistors M 3 and M 4 to the third and fourth transistors M 3 and M 4. Hereinafter, the circuit of the memory cell will be described in the same sense as the SRAM circuit.

<Low voltage column  Signal, high voltage low  Proposal Circuit for Applying Selection Signal>

The SRAM circuit for driving a memory cell with a low voltage column signal and a high voltage row select signal according to an embodiment of the present invention includes a control unit (not shown), a level shifter (not shown), and a memory cell (a plurality of transistors, M1 to M8) As shown in FIG. The SRAM circuit may be implemented as an independent memory device, and may be included as a component of a display device.

Specifically, the controller (not shown) is connected to a first power supply node low to supply a first voltage, and generates a row select signal row and a column signal col with the first voltage. When the SRAM circuit is used in a display device, the row select signal indicates a scan line select signal and the column signal indicates a data signal. Further, when the SRAM circuit is used as an independent memory device, the row select signal indicates a word line select signal and the column signal indicates a bit signal.

The level shifter (not shown) may change the magnitude of the row select signal generated by the controller to a second voltage greater than the first voltage to output a row select signal ROW of a high voltage.

The memory cell may include a second power supply node (high) supplying a second voltage, a row select signal line, and at least one switching unit connected to the column signal line. The memory cell applies at least one of the row select signal ROW, the column voltage signal col, or the third voltage V _B of the second voltage converted in the level shifter to at least one switching unit The display device can be driven with the second voltage supplied from the two power supply nodes. Here, driving the display element means storing a data value of the second voltage, which is a high voltage, in the display element.

The display device for driving the memory cells using the low voltage column signal and the high voltage row select signal according to the embodiment of the present invention may include a controller (not shown), a level shifter array (not shown), and a memory cell array have. The display device is a structure in which the SRAM circuits are arranged in an R * C matrix structure, the level shifters are arranged in an array in the column direction, and the memory cells are arranged in an array in the row and column directions. If the functions of the control unit, the level shifter array, and the memory cell array of the display device are the same as those of the SRAM circuit, the data signal (column signal) can be sequentially stored in the memory cell array according to the scanning line selection signal (row selection signal).

- 1st Example

FIG. 6 is a circuit diagram for driving a memory cell with a low voltage column signal, a high voltage row select signal according to an embodiment of the present invention, and FIGS. 7A to 7B are schematic diagrams Voltage column signal and a high-voltage-low select signal are applied to a memory cell.

Referring to FIG. 6, the circuit of the memory cell of FIG. 4 includes at least one switching unit including seventh and eighth transistors M7 and M8, and the seventh and eighth transistors M7 and M8 are turned off to, off the row select signal is applied the moment a high voltage (V _{DD _high)} power supply node side and the display device side to which it is possible to constitute the circuit so that the constant current flows.

At least one switching unit includes first switching units M1 and M4 that are switched according to a row selection signal of a second voltage, second switching units M2, M3, M5, and M6 that switch according to a column signal of a first voltage, And third switching units M7 and M8 that are switched to a row selection signal of a second voltage.

The first switching unit may include first and fourth transistors M1 and M4 and may apply a column signal to the second and third switching units by a row selection signal. Second switching unit display is connected to the second, third, fifth and sixth transistors a second power supply node (V _{DD _high)} that may be composed of (M2, M3, M5, M6), supplying a second voltage A second voltage of a high voltage can be applied to the device. The third switching unit may be composed of seventh and eighth transistors M7 and M8 and the fifth and sixth transistors M5 and M6 of the second switching unit may be constituted by the first switching unit or the second, 3 transistors M2 and M3.

Specifically, the transistor connection relation of each switching unit is as follows.

First, the drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line to transmit the column signal col and the inverting column signal colb to the source terminal. The source terminals of the first and fourth transistors M1 and M4 are connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8. The source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node, and the drain terminal thereof is connected to the source terminals of the seventh and eighth transistors M7 and M8. The drain terminals of the second and third transistors M2 and M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the display element is connected to the source terminal of the first transistor M1.

According to such a connection structure, the first and fourth transistors M1 and M4 are turned on in response to the row select signal ROW of the second voltage applied to the gate terminal, And transmits the column signal col of the voltage to the gate terminals of the third and sixth transistors M3 and M6. Further, the inverting curl signal colb applied to one end of the fourth transistor is transferred to the gate terminals of the second and fifth transistors M2 and M5. Fifth and sixth transistors (M5, M6) along a column signal (col) and the inverting column signal (colb) of the first voltage applied to the second agent terminal, and a second voltage (V _{DD _high} the power supply node ) To the display element. However, when the row selection signal ROW of the second voltage applied to the gate terminals of the seventh and eighth transistors M7 and M8 is applied, the connection between the fifth transistor M5 and the first transistor M1 And the connection of the sixth transistor M6 and the fourth transistor M4 is cut off.

Therefore, according to the first embodiment, when the row select signal is applied to the SRAM circuit, the second switching unit and the first switching unit are turned off, thereby solving the problem that the leakage current occurs. Referring to FIGS. 7A to 7B, the process of storing the same data value or other data values in the display device will be described.

Referring to Figure 7a, and when to write a data value to the same data value stored in the display device of the particular memory cell, i.e., = the current display device (X node) data value V _X stored in the V _{DD _ high,} corresponding to the pixels When the row select signal is applied by applying a data value (V _{DD_low)} saved in (rOW = V _{DD _high)} column lines can write the same data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row select signal is applied to the row including the memory cell (ROW = 0), data stored in the display element (X node) value V _X = V _{DD_high} is maintained.

When the row select signal is applied to the row including the memory cell (ROW = V _{DD_high} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8 are turned off. The Y node becomes zero applied to the colb to turn off the second transistor M2 and turn on the fifth transistor M5. The first and fifth transistors (M1, M5) is turned on, but the seventh and the eighth transistors (M7, M8) is so turned off, the leak current I _1, I _2, and I ₃ flows. At this time, the voltage value V _X of the X node becomes V _{DD - low} .

When the row select signal is applied to the row including the next memory cell after the data is written in the memory cell, the previous memory cell becomes ROW = 0, so that the first and fourth transistors M1 and M4 are turned off again, The seventh and eighth transistors M7 and M8 are turned on, so that the display element is reconnected to the second power node. Therefore, the data value (voltage value) V _X stored in the display element (X node) can be changed from V _{DD - low} to V _DD - high and stored.

7B, when a data value different from the data value stored in the display element of the specific memory cell is written, that is, when the data value V _X = 0 stored in the current display element (X node) When applied to (ROW = V _{DD _high),} save it as a column line to apply a data value (V _{DD_low)} can write different data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row select signal is applied to the row including the memory cell (ROW = 0), data stored in the display element (X node) The value V _X = 0 is maintained.

When the row select signal is applied to the row including the memory cell (ROW = V _{DD_high} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8 are turned off. The Y node becomes zero applied to the colb to turn off the second transistor M2 and turn on the fifth transistor M5. The first and fifth transistors (M1, M5) is turned on, but the seventh and the eighth transistors (M7, M8) is so turned off, the leak current I _1, I _2, and I ₃ flows. At this time, the voltage value V _X of the X node becomes V _{DD - low} .

When the row select signal is applied to the row including the next memory cell after the data is written in the memory cell, the previous memory cell becomes ROW = 0, so that the first and fourth transistors M1 and M4 are turned off again, The seventh and eighth transistors M7 and M8 are turned on, so that the display element is reconnected to the second power node. Therefore, the data value (voltage value) V _X stored in the display element (X node) can be changed from V _{DD - low} to V _DD - high and stored.

- Second Example

8 is a circuit diagram proposed for driving a memory cell with a low-voltage column signal, a high-voltage row select signal according to another embodiment of the present invention, and Figs. 9A to 9B are diagrams Voltage column signal and a high-voltage-low select signal are applied to a memory cell.

Referring to FIG. 8, in the circuit of the memory cell of FIG. 4, at least one switching unit including seventh and eighth transistors M7 and M8 is included, and seventh and eighth transistors M7 and M8 are slightly The third voltage V _B may be applied to the gate terminals of the seventh and eighth transistors M7 and M8 so as to maintain the turned-on state, thereby blocking the leakage current. Here, the third voltage is a constant voltage source (V _{DD_High} ) having a magnitude relatively lower than a value obtained by subtracting a large one of the absolute values of the threshold voltages of the seventh and eighth transistors M7 and M8 from the second voltage V _{DD_high} V _B ). The constant voltage source V _B may be commonly connected to both ends of the third switching unit of each of the plurality of memory cell arrays of the display device. Therefore, since the seventh and eighth transistors M7 and M8 are slightly turned on by the third voltage, the leakage current can not flow.

Specifically, the at least one switching unit includes first switching units M1 and M4 that are switched according to a row selection signal of a second voltage, second switching units M2, M3, M5, and M5 that switch according to a column signal of the first voltage, M6, and third switching units M7 and M8 that are switched to a third voltage.

The first switching unit includes first and fourth transistors M1 and M4, and the column signal may be applied to the second and third switching units by a row select signal. Second switching unit display is connected to the second, third, fifth and sixth transistors a second power supply node (V _{DD _high)} that may be composed of (M2, M3, M5, M6), supplying a second voltage A second voltage of a high voltage can be applied to the device. The third switching unit is composed of the seventh and eighth transistors M7 and M8 connected to the third voltage V _B , and is always kept in a turned-on state. At this time, third voltage (V _B) is V _DD -V _{th _high} a little lower than the constant voltage source _{(M7, M8),} the seventh, the eighth transistor can be maintained so as to operate in a slightly turn-on state (M7, M8).

Specifically, the transistor connection relationship of each switching unit is as follows

First, the drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line to transmit the column signal col and the inverting column signal colb to the source terminal. The source terminals of the first and fourth transistors M1 and M4 are connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8. The source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node, and the drain terminal thereof is connected to the source terminals of the seventh and eighth transistors M7 and M8. The drain terminals of the second and third transistors M2 and M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the display element is connected to the source terminal of the first transistor M1.

According to such a connection structure, the first and fourth transistors M1 and M4 are turned on in response to the row select signal ROW of the second voltage applied to the gate terminal, And transmits the column signal col of the voltage to the gate terminals of the third and sixth transistors M3 and M6. Further, the inverting curl signal colb applied to one end of the fourth transistor is transferred to the gate terminals of the second and fifth transistors M2 and M5. The fifth and sixth transistors M5 and M6 are turned on and off according to the column signal col of the first voltage applied to the gate terminal and the inverting column signal colb, _{DD _high} ) to the display device. At this time, the fifth transistor M5 and the first transistor M1 are disconnected from each other by the third voltage V _B applied to the gate terminals of the seventh and eighth transistors M7 and M8, M6 and the fourth transistor M4 may be cut off.

Thus, the seventh, eighth transistors (M7, M8) are not flow through the tap is turned on state, so the leakage current I _1, I _2, and I _3. Here, the magnitude of the third voltage V _B may be determined according to the threshold voltage V _th of the seventh and eighth transistors and the second voltage magnitude. Referring to FIGS. 9A to 9B, a process of storing the same data value or another data value in the display device will be described.

Referring to Figure 9a, and if write data value and the same data value stored in the display device of the particular memory cell, i.e., = the current display device (X node) data value V _X stored in the V _{DD _ high,} corresponding to the pixels When the row select signal is applied by applying a data value (V _{DD_low)} saved in (rOW = V _{DD _high)} column lines can write the same data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row select signal is applied to the row including the memory cell (ROW = 0), data stored in the display element (X node) The value V _X = V _{DD _high} is maintained.

When the row select signal is applied to the row including the memory cell (ROW = V _{DD_high} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8 are always kept in a slightly on state, so that the Y node becomes 0 applied to the colb to turn off the second transistor M2. The first and fifth transistors (M1, M5) is turned on, but the seventh transistor (M7) is rare ondoen state, so the leakage current I ₁ does not flow. Similarly, the eighth transistor (M8) is also rare ondoen state, so the leakage current I _2, and I ₃ does not flow. Therefore, the voltage value V _X of the X node becomes V _{DD - low} .

When the row select signal is applied to the row including the next memory cell after the data is written in the memory cell, the previous memory cell becomes ROW = 0, so that the first and fourth transistors M1 and M4 are turned off again, seventh, eighth transistors (M7, M8) of the second voltage (V _{DD _high)} because of a little on state, the second power source node is transmitted to the display device. Thus, the data value stored in the display device (node X) (voltage value) V _X may be stored is changed from V _DD to V _{DD _low _ high.}

9B, when a data value different from the data value stored in the display element of a specific memory cell is written, that is, when the data value V _X = 0 stored in the current display element (X node) When applied to (ROW = V _{DD _high),} save it as a column line to apply a data value (V _{DD_low)} can write different data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row select signal is applied to the row including the memory cell (ROW = 0), data stored in the display element (X node) The value V _X = 0 is maintained.

When the row select signal is applied to the row including the memory cell (ROW = V _{DD_high} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8 are kept in a slightly on state, so that the Y node becomes zero applied to the colb to turn off the second transistor M2 and turn on the fifth transistor M5. The first and fifth transistors (M1, M5) is turned on, but the seventh transistor (M7) is rare ondoen state, so the leakage current I ₁ does not flow. Similarly, the eighth transistor (M8) is also rare ondoen state, so the leakage current I _2, and I ₃ does not flow. Therefore, the voltage value V _X of the X node becomes V _{DD - low} .

When the row select signal is applied to the row including the next memory cell after the data is written in the memory cell, the previous memory cell becomes ROW = 0, so that the first and fourth transistors M1 and M4 are turned off again, seventh, eighth transistors (M7, M8) of the second voltage (V _{DD _high)} because of a little on state, the second power source node is transmitted to the display device. Thus, the data value stored in the display device (node X) (voltage value) V _X may be stored is changed from V _DD to V _{DD _low _ high.}

As described above, according to the first and second embodiments of the present invention, no leakage current is generated even when a circuit is driven by using a low-voltage column signal and a high-voltage row selection signal. Therefore, Can be stored.

10 is a view for explaining a digital pixel driving method when a low voltage column signal and a low voltage row selection signal are applied to the display device of the present invention.

Referring to FIG. 10, the display device of the present invention can drive the display device by applying the low voltage row select signals row_1 to row_R and the low voltage column signals col_1 to col_C to the memory cell array.

The display device of the present invention is a structure in which a plurality of pixels are arranged in R rows and C columns, and each pixel includes a 1-bit memory cell. Here, the 1-bit memory can be replaced with an N-bit memory and can be configured as a static random access memory (SRAM) circuit.

Method for driving each memory cell row selection signal based on the (e.g., the scanning line selection signal), the row line (row line) may be applied to row_R the one from row_1 the row select signal with a low voltage (V _{DD _low)} have. When a low-voltage row select signal is applied to each row line, low-voltage column signals col_1 to col_C can be applied to the respective column lines. At this time, 'V _{DD_low} ' is applied and '0' is applied for the remaining time period during the time period in which the corresponding row is selected, and the low voltage column signal is' 0 'or' V _{DD _low} Can be granted.

When a low-voltage row select signal is applied, data values can be stored or changed in each of the intersecting pixels by applying a desired data value to col_1 to col_C in each column.

FIG. 11 is a diagram for explaining a case where the circuit of the memory cell of FIG. 6 is applied to FIG. 10, and FIGS. 12A to 12B are views for explaining the driving principle of the memory cell of FIG.

Referring to Figure 11, application of a memory cell circuit of Fig 10, the memory cell is composed of a plurality of transistors (M1 to M8), the low voltage row select signals (row) and a low voltage (V _{DD _low)} ( The first and fourth transistors M1 and M4 are switched according to the column signal col / colb of the data signal V _{DD_low} to apply a high voltage data value to the display element. Hereinafter to describe the operating principle of storing a data value in the memory cell of Figure 6 to the column signal (col / colb) of the low voltage row select signals (row) of (V _{DD_low)} and low voltage (V _{DD _low).}

See Figure 12a way, when writing a data value to the same data value stored in the display device of the particular memory cell, i.e., the current display device (X node) data value V _X = V _{DD _ high} stored in the pixels corresponding to When the row select signal is applied by applying a data value (V _{DD_low)} to store the (row = V _{DD _low)} column lines can write the same data value.

In this case, since the first and fourth transistors M1 and M4 are off before the low select signal of the low voltage is applied to the row including the memory cell (row = 0), the display element (X node) The stored data value V _X = V _{DD _high} is maintained.

Next, when a row select signal of a low voltage is applied to the row including the memory cell (row = V _{DD - low} ), the first and fourth transistors M 1 and M 4 are turned on and the low voltage Y node in accordance with the column signals _{(col = V DD _low, colb} = 0) is close gapgo the applied zero at colb, X node, since the values close to V _{DD _high} value previously stored off the second transistor (M2) The sixth transistor M6 can be turned on and the third and fifth transistors M3 and M5 can be turned on. However, since the row select signal with a low voltage is applied, the seventh, the eighth does not completely turn off the transistor (M7, M8), a constant current I ₁ is flowing toward the first transistor (M1) from the fifth transistor (M5) side, a sixth constant current I ₂ is the side of the transistor a fourth transistor (M4) from (M6) side flows, the sixth constant current I flows through the _third transistor side of the third transistor (M3) from (M6) side.

When the row select signal is applied to the row including the next memory cell after writing data in the memory cell, the previous memory cell becomes row = 0, so that the first and fourth transistors M1 and M4 are turned off again, The data value (voltage value) V _X stored in the display element (X node) can be changed again to V _{DD -} high.

In this case, accurate data values can be stored in the display device, but the constant currents I ₁ to I ₃ flow when the memory cell is selected, which causes a problem of high power consumption.

12B, when a data value different from the data value stored in the display element of the specific memory cell is written, that is, when the data value V _X = 0 stored in the current display element (X node) applying a selection signal is applied (row = V _{DD _low)} to store the column line of data values (V _{DD_low)} and can write the other data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row selection signal is applied to the row including the memory cell (row = 0), the data stored in the display element (X node) The value V _X = 0 is maintained.

Next, the first and fourth transistors M1 and M4 are slightly turned on when a low select signal of a low voltage is applied to the row including the memory cell (rowOW = V _{DD - low} ), but the seventh and eighth transistors Can not be turned off completely. Also, according to the inverting column signal (colb = 0) of the low voltage, the Y node becomes a value close to 0 applied in the colb to turn off the fifth transistor M5. In addition, the X node may hold the previously stored data value close to 0, so that the sixth transistor M6 may be momentarily turned on. In addition, the first, second, because the transistor (M1, M2) is turned on, the constant current I ₁ is flowing toward the first transistor, the second transistor (M2) from (M1) side. Since the sixth transistor M6, the eighth transistor M8 and the fourth transistor M4 are slightly turned on, the constant current I ₂ flows from the sixth transistor M6 to the fourth transistor M4.

When the row select signal is applied to the row including the next memory cell after writing data in the memory cell, the previous memory cell becomes row = 0, so that the first and fourth transistors M1 and M4 are turned off again, The data value (voltage value) V _X stored in the display element (X node) is stored as zero.

In this case, since accurate data values can not be stored in the display device, and constant currents I ₁ to I ₂ flow when the memory cell is selected, there is a problem that power consumption is large.

Accordingly, the leakage current I ₁ flowing from the fifth transistor M 5 side to the first transistor M 1 side and the leakage current I ₁ flowing from the sixth transistor M 6 side from the fourth transistor circuit that can be stored on the device display the exact data value, while preventing the leakage current I ₂ flowing through the side of occurrence (M4) is required. Hereinafter, the circuit of the memory cell will be described in the same sense as the SRAM circuit.

<Low voltage column  Signal, low voltage low  Proposal Circuit for Applying Selection Signal>

The SRAM circuit for driving a memory cell with a low-voltage column signal and a low-voltage row select signal according to an embodiment of the present invention may include a control unit (not shown) and a memory cell (a plurality of transistors, M1 to M8) . The SRAM circuit may be implemented as an independent memory device, and may be included as a component of a display device.

Specifically, the controller (not shown) is connected to a first power supply node low to supply a first voltage, and generates a row select signal row and a column signal col with the first voltage. When the SRAM circuit is used in a display device, the row select signal indicates a scan line select signal and the column signal indicates a data signal. Further, when the SRAM circuit is used as an independent memory device, the row select signal indicates a word line select signal and the column signal indicates a bit signal.

The memory cell may include a second power supply node (high) supplying a second voltage having a magnitude greater than the first voltage, a row select signal line, and at least one switching unit connected to the column signal line. Memory cell to at least one of the row select the first voltage generated by the control signal (row), the first voltage column signal (col), or a third voltage (V _B) applied to at least one switching unit of claim 2, And the display element can be driven by the second voltage supplied from the power supply node. Here, the meaning sikindaneun driving a display device indicates to store the data value of the high voltage to the display device a second voltage (V _{DD _high).} At least a part of the transistors included in the memory cell may be designed so that a width and a length ratio are specified so that leakage current does not flow.

In addition, a display device for driving a memory cell using a low-voltage column signal and a low-voltage row selection signal according to an embodiment of the present invention may include a controller (not shown) and a memory cell array. The display device is a structure in which the SRAM circuits are arranged in a matrix structure of R * C matrices. If the functions of the control unit and the memory cell array of the display device are the same as those of the SRAM circuit, the data signal (column signal) can be sequentially stored in the memory cell array according to the scan line select signal (row select signal).

- 1st Example

13 is a circuit diagram proposed for driving a memory cell with a low-voltage column signal, a low-voltage row select signal according to an embodiment of the present invention, and Figs. 14A to 14B are schematic diagrams Voltage column signal and a low-voltage-low select signal are applied to the memory cell.

Referring to FIG. 13, in the circuit of the memory cell of FIG. 6, the turn-on resistances of the first and fourth transistors M1 and M4 are relatively smaller than the turn-on resistances of the seventh and eighth transistors M7 and M8 The first, fourth, seventh, and eighth transistors M1, M4, M7, and M8 may be designed so that a large difference in the ratio of W (width) to L (length) occurs.

At least one switching unit includes first switching units M1 and M4 that are switched according to a row selection signal of a first voltage, second switching units M2, M3, M5, and M6 that switch according to a column signal of a first voltage, And third switching units M7 and M8 that are switched according to a row selection signal of a first voltage.

The first switching unit includes first and fourth transistors M1 and M4, and the column signal may be applied to the second and third switching units by a row select signal. The second switching unit is composed of the second, third, fifth and sixth transistors M2, M3, M5 and M6 and is connected to the second power supply node V _{DD_high} for supplying the second voltage, The second voltage can be applied. The third switching unit may be composed of seventh and eighth transistors M7 and M8 and the fifth and sixth transistors M5 and M6 of the second switching unit may be constituted by the first switching unit or the second, 3 transistors M2 and M3.

Specifically, the transistor connection relation of each switching unit is as follows.

The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line and the source terminals of the first and fourth transistors M1 and M4 are connected to the drain terminals of the second and seventh transistors M2 and M7. And the source terminals of the third and eighth transistors M3 and M8, respectively. The source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node and the drain terminal thereof is connected to the source terminals of the seventh and eighth transistors M7 and M8. The drain terminals of the second and third transistors M2 and M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the display element is connected to the source terminal of the first transistor M1. The first and fourth transistors M1 and M4 are turned on and off according to the row selection signal Row of the first voltage applied to the gate terminal of the first transistor M1, And the column signal col to the gate terminals of the third and sixth transistors M3 and M6. In addition, the inverting curl signal colb applied to one end of the fourth transistor can be transmitted to the gate terminals of the second and fifth transistors M2 and M5. The fifth and sixth transistors M5 and M6 generate a second voltage V _{DD_high} of the second power supply node according to the column signal col and the inverting column signal colb of the first voltage applied to the gate terminal, To the display device. However, the seventh and eighth transistors M7 and M8 are slightly turned on according to the row select signal row of the first voltage applied to the gate terminals of the seventh and eighth transistors M7 and M8, When the first and fourth transistors M1 and M4 and the seventh and eighth transistors M7 and M8 satisfy the following formula (1), no leakage current occurs due to the resistance difference of each transistor.

Therefore, according to the first embodiment, since the resistances of the first and fourth transistors M1 and M4 are relatively smaller than the resistances of the seventh and eighth transistors M7 and M8, The leakage current does not flow through the first and fourth transistors M1 and M4 even when the transistors M7 and M8 are lightly turned on. Referring to FIGS. 14A to 14B, a process of storing the same data value or another data value in the display device will be described.

Reference to Figure 14a way, when writing a data value to the same data value stored in the display device of the particular memory cell, i.e., the current display device (X node) data value V _X = V _{DD _ high} stored in the pixels corresponding to When the row select signal is applied by applying a data value (V _{DD_low)} to store the (row = V _{DD _low)} column lines can write the same data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row selection signal is applied to the row including the memory cell (row = 0), the data stored in the display element (X node) The value V _X = V _{DD _high} is maintained.

When the row select signal is applied to the row including the memory cell (row = V _{DD - low} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8) is lightly turned on. The Y node becomes zero applied to the colb to turn off the second transistor M2 and turn on the fifth transistor M5. The first transistor M1 is turned on because the first, fifth, and seventh transistors M1, M5, and M7 are turned on and the seventh transistor M7 has a relatively larger resistance than the first transistor M1. Leakage current I ₁ does not flow to the side On the same principle, the leakage current I ₂ does not flow through the fourth transistor M4, and the voltage value V _X of the X node is stored close to V _{DD_high} .

When a row select signal is applied to a row including the next memory cell after writing data to the memory cell, the previous memory cell becomes row = 0, so that the first and fourth transistors M1 and M4 are turned off again, The seventh and eighth transistors M7 and M8 are turned on, so that the display element is reconnected to the second power node. Therefore, the data value (voltage value) V _X stored in the display element (X node) is V _{DD_high} And stored.

14B, when a data value different from the data value stored in the display element of the specific memory cell is written, that is, when the data value V _X = 0 stored in the current display element (X node) When applied to the (row = V _{DD _low)} stored in the column line to apply a data value (V _{DD_low)} you can write different data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row selection signal is applied to the row including the memory cell (row = 0), the data stored in the display element (X node) The value V _X = 0 is maintained.

When the row select signal is applied to the row including the memory cell (row = V _{DD - low} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8) is lightly turned on. The Y node becomes zero applied to the colb to turn off the second transistor M2 and turn on the fifth transistor M5. The first transistor M1 is turned on because the first, fifth, and seventh transistors M1, M5, and M7 are turned on and the seventh transistor M7 has a relatively larger resistance than the first transistor M1. Leakage current I ₁ does not flow to the side On the same principle, the leakage current I ₂ does not flow through the fourth transistor M4, and the voltage value V _X of the X node is stored close to V _{DD_high} .

When a row select signal is applied to a row including the next memory cell after writing data to the memory cell, the previous memory cell becomes row = 0, so that the first and fourth transistors M1 and M4 are turned off again, The seventh and eighth transistors M7 and M8 are turned on, so that the display element is reconnected to the second power node. Therefore, the data value (voltage value) V _X stored in the display element (X node) can be changed to V _{DD_high} and stored.

- Second Example

15 is a circuit diagram proposed for driving a memory cell with a low-voltage column signal, a low-voltage row select signal according to another embodiment of the present invention, and Figs. 16A to 16B are diagrams Voltage column signal and a low-voltage-low select signal are applied to the memory cell.

Referring to FIG. 15, in the circuit of the memory cell of FIG. 13, the gate terminals of the seventh and eighth transistors M7 and M8 are controlled so that the seventh and eighth transistors M7 and M8 are slightly turned on. 3 voltage (V _B ) may be applied to cut off the leakage current. Here, the third voltage is a constant voltage source (V _{DD_High} ) having a magnitude relatively lower than a value obtained by subtracting a large one of the absolute values of the threshold voltages of the seventh and eighth transistors M7 and M8 from the second voltage V _{DD_high} V _B ). The constant voltage source V _B may be commonly connected to both ends of the third switching unit of each of the plurality of memory cell arrays of the display device. Therefore, since the seventh and eighth transistors M7 and M8 are slightly turned on by the third voltage, the leakage current can not flow.

Specifically, the at least one switching unit includes first switching units M1 and M4 that are switched according to a row selection signal of a second voltage, second switching units M2, M3, M5, and M5 that switch according to a column signal of the first voltage, M6, and third switching units M7 and M8 that are switched to a third voltage.

The first switching unit includes first and fourth transistors M1 and M4, and the column signal may be applied to the second and third switching units by a row select signal. Second switching unit display is connected to the second, third, fifth and sixth transistors a second power supply node (V _{DD _high)} that may be composed of (M2, M3, M5, M6), supplying a second voltage A second voltage of a high voltage can be applied to the device. The third switching unit is composed of the seventh and eighth transistors M7 and M8 connected to the third voltage V _B , and is always kept in a turned-on state. At this time, third voltage (V _B) is V _DD -V _{th _high} a little lower than the constant voltage source _{(M7, M8),} the seventh, the eighth transistor can be maintained so as to operate in a slightly turn-on state (M7, M8).

Specifically, the transistor connection relation of each switching unit is as follows.

First, the drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line to transmit the column signal col and the inverting column signal colb to the source terminal. The source terminals of the first and fourth transistors M1 and M4 are connected to the drain terminals of the second and seventh transistors M2 and M7 and the source terminals of the third and eighth transistors M3 and M8. The source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node, and the drain terminal thereof is connected to the source terminals of the seventh and eighth transistors M7 and M8. The drain terminals of the second and third transistors M2 and M3 are connected to the drain terminals of the seventh and eighth transistors M7 and M8 and the source terminals of the second and third transistors M2 and M3 are connected to the ground And the display element is connected to the source terminal of the first transistor M1.

According to such a connection structure, the first and fourth transistors M1 and M4 are turned on in response to the row select signal ROW of the second voltage applied to the gate terminal, And transmits the column signal col of the voltage to the gate terminals of the third and sixth transistors M3 and M6. Further, the inverting curl signal colb applied to one end of the fourth transistor is transferred to the gate terminals of the second and fifth transistors M2 and M5. The fifth and sixth transistors M5 and M6 are turned on and off according to the column signal col of the first voltage applied to the gate terminal and the inverting column signal colb, _{DD _high} ) to the display device. At this time, current does not flow through the first transistor M1 and the fourth transistor M4 with the third voltage V _B applied to the gate terminals of the seventh and eighth transistors M7 and M8. .

Thus, the seventh, eighth transistors (M7, M8) are not flow through the tap is turned on state, so the leakage current I ₁ and I _2. Here, the magnitude of the third voltage V _B may be determined according to the threshold voltage V _th of the seventh and eighth transistors and the second voltage magnitude. Referring to Figs. 16A to 16B, the process of storing the same data value or other data values in the display device will be described.

Referring to Figure 16a, and when to write a data value to the same data value stored in the display device of the particular memory cell, i.e., = the current display device (X node) data value V _X stored in the V _{DD _ high,} corresponding to the pixels When the row select signal is applied by applying a data value (V _{DD_low)} to store the (row = V _{DD _low)} column lines can write the same data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row selection signal is applied to the row including the memory cell (row = 0), the data stored in the display element (X node) The value V _X = V _{DD _high} is maintained.

When the row select signal is applied to the row including the memory cell (row = V _{DD - low} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8 are always kept in a slightly on state, so that the Y node becomes 0 applied to the colb to turn off the second transistor M2. The first and fifth transistors (M1, M5) is turned on, but the seventh transistor (M7) is rare ondoen state, so the leakage current I ₁ does not flow. Similarly, the eighth transistor (M8) is also rare ondoen state, so the leakage current I ₂ does not flow. Therefore, the voltage value V _X of the X node becomes a value close to V _{DD_high} .

When a row select signal is applied to a row including the next memory cell after writing data to the memory cell, the previous memory cell becomes row = 0, so that the first and fourth transistors M1 and M4 are turned off again, seventh, eighth transistors (M7, M8) of the second voltage (V _{DD _high)} because of a little on state, the second power source node is transmitted to the display device. Therefore, the data value (voltage value) V _X stored in the display element (X node) is V _{DD_high} And stored.

16B, when a data value different from the data value stored in the display element of the specific memory cell is written, that is, when the data value V _X = 0 stored in the current display element (X node) When applied to the (row = V _{DD _low),} save it as a column line to apply a data value (V _{DD_low)} can write different data value.

In this case, since the first and fourth transistors M1 and M4 are off before the row selection signal is applied to the row including the memory cell (row = 0), the data stored in the display element (X node) The value V _X = 0 is maintained.

When the row select signal is applied to the row including the memory cell (row = V _{DD - low} ), the first and fourth transistors M1 and M4 are turned on, and the seventh and eighth transistors M7, M8 are kept in a slightly on state, so that the Y node becomes zero applied to the colb to turn off the second transistor M2 and turn on the fifth transistor M5. The first and fifth transistors (M1, M5) is turned on, but the seventh transistor (M7) is rare ondoen state, so the leakage current I ₁ does not flow. Similarly, the eighth transistor (M8) is also rare ondoen state, so the leakage current I _2, and I ₃ does not flow. Therefore, the voltage value V _X of the X node becomes a value close to V _{DD_high} .

When a row select signal is applied to a row including the next memory cell after writing data to the memory cell, the previous memory cell becomes row = 0, so that the first and fourth transistors M1 and M4 are turned off again, seventh, eighth transistors (M7, M8) of the second voltage (V _{DD _high)} because of a little on state, the second power source node is transmitted to the display device. Thus, the data value stored in the display device (node X) (voltage value) V _X may be stored has been changed from a value close to the V _DD to V _{DD _high _ high.}

As described above, according to the first and second embodiments of the present invention, even when a circuit is driven by using a low-voltage column signal and a low-voltage row select signal, a leakage current is not generated, Can be stored.

Accordingly, when the circuit proposed in the present invention is used, at least one of the column signal and the row selection signal is used as a low voltage, so that accurate data values can be stored in the display device while reducing the overall power consumption.

ROW_1 to ROW_R: Low select signal of high voltage
COL_1 to COL_C: column signals of high voltage
row_1 to row_R: row select signal of low voltage
col_1 to col_C: column signal of low voltage

Claims (14)

A control unit connected to a first power supply node low to supply a first voltage and generating a row signal and a column signal with the first voltage;
A level shifter for changing the magnitude of the row select signal generated by the controller to a second voltage greater than the first voltage; And
A row select signal line, and at least one switching unit connected to a column signal line, wherein the row select signal of the second voltage, which is converted in the level shifter, the first voltage And a memory cell for applying a first voltage or a third voltage to the at least one switching unit to drive the display device to a second voltage supplied from the second power supply node.
SRAM circuit.
The method according to claim 1,
Wherein the at least one switching unit includes first switching units M1 and M4 that are switched according to a row selection signal of the second voltage, second switching units M2, M3, and M5 that switch according to a column signal of the first voltage, And a third switching unit (M7, M8) which is switched to the third voltage or a row select signal of the second voltage.
SRAM circuit.
3. The method of claim 2,
The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit may include seventh and eighth transistors M7 and M8,
The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line and the source terminals of the first and fourth transistors M1 and M4 are connected to the second and seventh transistors M2 and M7 And the source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node and the drain terminals of the third and fourth transistors M3 and M8 are connected to the source terminal of the third and eighth transistors M3 and M8, And the drain terminals of the second and third transistors M2 and M3 are connected to the source terminals of the seventh and eighth transistors M7 and M8, And the source terminal of the second and third transistors M2 and M3 is connected to the ground, the display element is connected to the source terminal of the first transistor M1,
The first and fourth transistors M1 and M4 may be arranged such that the column signal of the first voltage applied to one end of the first transistor M1 is applied to the gate of the first transistor M1 according to the row select signal of the second voltage applied to the gate terminal To the gate terminals of the third and sixth transistors M3 and M6 and transfers the inverting curling signal applied to one end of the fourth transistor to the gate terminals of the second and fifth transistors M2 and M5 ,
The fifth and sixth transistors M5 and M6 transmit the second voltage of the second power source node to the display device according to the column signal of the first voltage applied to the gate terminal and the inverting column signal, The connection between the fifth transistor M5 and the first transistor M1 is interrupted according to the row select signal of the second voltage applied to the gate terminals of the seventh and eighth transistors M7 and M8 , The sixth transistor (M6) and the fourth transistor (M4) are disconnected from each other,
SRAM circuit.
3. The method of claim 2,
The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit may include seventh and eighth transistors M7 and M8,
The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line and the source terminals of the first and fourth transistors M1 and M4 are connected to the second and seventh transistors M2 and M7 And the source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node and the drain terminals of the third and fourth transistors M3 and M8 are connected to the source terminal of the third and eighth transistors M3 and M8, And the drain terminals of the second and third transistors M2 and M3 are connected to the source terminals of the seventh and eighth transistors M7 and M8, And the source terminal of the second and third transistors M2 and M3 is connected to the ground, the display element is connected to the source terminal of the first transistor M1,
The first and fourth transistors M1 and M4 may be arranged such that the column signal of the first voltage applied to one end of the first transistor M1 is applied to the gate of the first transistor M1 according to the row select signal of the second voltage applied to the gate terminal To the gate terminals of the third and sixth transistors M3 and M6 and transfers the inverting curling signal applied to one end of the fourth transistor to the gate terminals of the second and fifth transistors M2 and M5 ,
The fifth and sixth transistors M5 and M6 transmit the second voltage of the second power source node to the display device according to the column signal of the first voltage applied to the gate terminal and the inverting column signal, Wherein a current flow between the first transistor (M1) and the fourth transistor (M4) is interrupted by the third voltage applied to the gate terminals of the seventh and eighth transistors (M7, M8)
SRAM circuit.
5. The method of claim 4,
Wherein the third voltage is a voltage having a magnitude relatively lower than a value obtained by subtracting a large absolute value of a threshold voltage of the seventh and eighth transistors M7 and M8 from the second voltage,
SRAM circuit.
The method of claim 1,
The row select signal is a scan line select signal or a word line select signal,
Wherein the column signal is a data signal or a bit signal,
SRAM circuit.
A control unit connected to a first power supply node low to supply a first voltage to generate a scan line select signal and a data signal with the first voltage;
A level shifter array for changing a magnitude of the scan line select signal generated by the control unit to a second voltage greater than the first voltage; And
A second power supply node for supplying a first voltage, a second power supply node for supplying a second voltage, and at least one switching unit connected to a scanning line and a data signal line, wherein the scanning line selection signal, And a third voltage is applied to the at least one switching unit to drive each display device to a second voltage supplied from the second power supply node,
And the data signal is sequentially stored in the memory cell array according to the scanning line selection signal.
Display device.
A control unit connected to a first power supply node low to supply a first voltage and generating a row signal and a column signal with the first voltage; And
A second power supply node for supplying a second voltage having a magnitude greater than the first voltage, a row select signal line, and at least one switching unit coupled to the column signal line, And a memory cell for applying a selection signal, a column signal of the first voltage, or a third voltage to the at least one switching unit to drive the display device to a second voltage supplied from the second power supply node doing,
SRAM circuit.
9. The method of claim 8,
The at least one switching unit includes a first switching unit (M1, M4) for switching in response to a row selection signal of the first voltage, a second switching unit (M2, M3, M5) for switching in accordance with a column signal of the first voltage, And third switching units M7 and M8 that are switched according to the row selection signal of the first voltage or the third voltage.
SRAM circuit.
10. The method of claim 9,
The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit may include seventh and eighth transistors M7 and M8,
The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line and the source terminals of the first and fourth transistors M1 and M4 are connected to the second and seventh transistors M2 and M7 And the source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node and the drain terminals of the third and fourth transistors M3 and M8 are connected to the source terminal of the third and eighth transistors M3 and M8, And the drain terminals of the second and third transistors M2 and M3 are connected to the source terminals of the seventh and eighth transistors M7 and M8, And the source terminal of the second and third transistors M2 and M3 is connected to the ground, the display element is connected to the source terminal of the first transistor M1,
The first and fourth transistors M1 and M4 may receive the column signal of the first voltage applied to one end of the first transistor M1 according to the row select signal of the first voltage applied to the gate terminal, To the gate terminals of the third and sixth transistors M3 and M6 and transfers the inverting curling signal applied to one end of the fourth transistor to the gate terminals of the second and fifth transistors M2 and M5 ,
The fifth and sixth transistors M5 and M6 transmit the second voltage of the second power source node to the display device according to the column signal of the first voltage applied to the gate terminal and the inverting column signal, Wherein the first and fourth transistors M1 and M4 and the seventh and eighth transistors M7 and M8 satisfy the following equations:
(W / L) _{M1, M4} >> (W / L) _{M7, M8}
(Where W represents Weight and L represents Length)
SRAM circuit.
10. The method of claim 9,
The first switching unit is composed of first and fourth transistors M1 and M4 and the second switching unit is composed of second, third, fifth and sixth transistors M2, M3, M5 and M6, The third switching unit may include seventh and eighth transistors M7 and M8,
The drain terminals of the first and fourth transistors M1 and M4 are connected to the column signal line and the source terminals of the first and fourth transistors M1 and M4 are connected to the second and seventh transistors M2 and M7 And the source terminals of the fifth and sixth transistors M5 and M6 are connected to the second power source node and the drain terminals of the third and fourth transistors M3 and M8 are connected to the source terminal of the third and eighth transistors M3 and M8, And the drain terminals of the second and third transistors M2 and M3 are connected to the source terminals of the seventh and eighth transistors M7 and M8, And the source terminal of the second and third transistors M2 and M3 is connected to the ground, the display element is connected to the source terminal of the first transistor M1,
The first and fourth transistors M1 and M4 may receive the column signal of the first voltage applied to one end of the first transistor M1 according to the row select signal of the first voltage applied to the gate terminal, To the gate terminals of the third and sixth transistors M3 and M6 and transfers the inverting curling signal applied to one end of the fourth transistor to the gate terminals of the second and fifth transistors M2 and M5 ,
The fifth and sixth transistors M5 and M6 transmit the second voltage of the second power source node to the display device according to the column signal of the first voltage applied to the gate terminal and the inverting column signal, Wherein a current flow between the first transistor (M1) and the fourth transistor (M4) is interrupted by the third voltage applied to the gate terminals of the seventh and eighth transistors (M7, M8)
SRAM circuit.
12. The method of claim 11,
Wherein the third voltage is a voltage having a magnitude relatively lower than a value obtained by subtracting a large absolute value of a threshold voltage of the seventh and eighth transistors M7 and M8 from the second voltage,
SRAM circuit.
9. The method of claim 8,
The row select signal is a scan line select signal or a word line select signal,
Wherein the column signal is a data signal or a bit signal,
SRAM circuit.
A control unit connected to a first power supply node low to supply a first voltage to generate a scan line select signal and a data signal with the first voltage; And
A second power supply node for supplying a second voltage having a magnitude greater than the first voltage, at least one switching unit connected to a scanning line and a data signal line, , A data signal of the first voltage, or a third voltage to the at least one switching unit to drive each display element to a second voltage supplied from the second power supply node and,
And the data signal is sequentially stored in the memory cell array according to the scanning line selection signal.
Display device.

Images