KR20190035250A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

Provided are a semiconductor device and a manufacturing method thereof, having improved operational characteristics and process margin. The semiconductor device comprises: a substrate; a trench formed in the substrate; a bit line formed in the trench and having a width narrower than the width of the trench,; a first spacer extending along the trench and at least a part of a sidewall of the bit line, being in contact with the bit line, and including a silicon oxide; and a second spacer formed on the first spacer, and filling the trench.

Description

Technical Field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same,

The present invention relates to a semiconductor device and a manufacturing method thereof.

As semiconductor devices become more and more highly integrated, individual circuit patterns are becoming finer in order to realize more semiconductor devices on the same area.

On the other hand, as semiconductor memory devices become highly integrated, the influence of parasitic capacitance and leakage current increases gradually. Such parasitic capacitance and leakage current deteriorate the operation characteristics of the semiconductor device, and therefore, there is a demand for a semiconductor device capable of minimizing these parasitic capacitance and leakage current.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device with improved operational characteristics and process margin.

It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device with improved operational characteristics and process margin.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a trench in the substrate, a bit line having a width narrower than the width of the trench, A first spacer extending along the trench and in contact with the bit line, the first spacer comprising silicon oxide, and the second spacer filling the trench on the first spacer.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including a first active region, a first bit line on the first active region, A first spacer extending along at least a portion and in contact with the first bit line, the first spacer comprising SiOC, and the second spacer comprising silicon nitride on the first spacer.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a bit line extending along a first direction on the substrate, a bit line extending in a first direction crossing the first direction, A word line extending along a first direction, a word line extending along a second direction, a capping pattern extending along the second direction on the word line, a first trench including a first sub trench in the capping pattern, A first spacer including a silicon oxide film, and a second spacer on the first spacer, the second spacer filling the first sub trench.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: providing a substrate; forming a trench in the substrate; forming a trench in the trench, Forming at least a portion of a sidewall of the bit line and a trench extending along the trench and in contact with the bit line to form a first spacer comprising silicon oxide, And forming a second spacer filling the trench.

The details of other embodiments are included in the detailed description and drawings.

1 is a layout diagram for explaining a semiconductor device according to some embodiments of the technical idea of the present invention.
2 is a cross-sectional view taken along line A-A 'in Fig.
FIGS. 3A-3F are various enlarged views of the area R of FIG.
4 is a cross-sectional view taken along line B-B 'in Fig.
5 is a layout diagram illustrating a semiconductor device according to some embodiments of the technical idea of the present invention.
6 is a cross-sectional view taken along line C-C 'in Fig.
7 is a cross-sectional view taken along the line D-D 'in FIG.
FIGS. 8 to 46 are intermediate plan views illustrating a method of manufacturing a semiconductor device according to some embodiments of the technical idea of the present invention. FIG.

Hereinafter, with reference to Figs. 1 to 4, a semiconductor device according to some embodiments of the technical idea of the present invention will be described.

1 is a layout diagram for explaining a semiconductor device according to some embodiments of the technical idea of the present invention. 2 is a cross-sectional view taken along line A-A 'in Fig. FIGS. 3A-3F are various enlarged views of the area R of FIG. 4 is a cross-sectional view taken along line B-B 'in Fig.

1, 2, 3A, and 4, a semiconductor device according to some embodiments includes a substrate 110, an isolation layer 120, an insulating layer 130, a first trench TR1, BL, a bit line, a spacer structure SP, a word line WL, a direct contact (DC), a fence 170, a buried contact BC, a landing pad LP, An interlayer insulating film 180 and a capacitor 190.

The substrate 110 may have a structure in which a base substrate and an epi layer are stacked, but the technical idea of the present invention is not limited thereto. The substrate 110 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or an SOI (Semiconductor On Insulator) substrate. Illustratively, in the following, the substrate 110 is a silicon substrate.

The substrate 110 may comprise an active region AR. As the design rule of the semiconductor device is reduced, the active region AR may be formed in an oblique bar shape, as shown in FIG.

For example, the active region AR extends in any direction other than the first direction X and the second direction Y in the plane in which the first direction X and the second direction Y extend And may be formed in a bar shape. In addition, the active areas AR may be in the form of a plurality of bars extending in a direction parallel to each other. In addition, the center of the active region AR of one of the plurality of active regions AR may be disposed adjacent to the end of the other active region AR.

The active region AR may contain impurities to form the source and drain regions.

For example, the center of the active area AR may be connected to the bit line BL by a direct contact DC. Accordingly, the center of the active region AR can form one of the source and drain regions. Further, for example, both ends of the active region AR may be connected to the buried contact BC. Accordingly, the center of the active region AR can form another one of the source and drain regions.

The device isolation film 120 may define a plurality of active regions AR. 2 and 4, the sidewalls of the device isolation film 120 are shown as being inclined, but this is only a feature of the process, and the technical idea of the present invention is not limited thereto.

The device isolation film 120 may include an oxide film, a nitride film, or a combination thereof, but the technical idea of the present invention is not limited thereto. The device isolation layer 120 may be a single layer made of one kind of insulating material or a multi-layer made of a combination of various kinds of insulating materials.

The first trench TR1 may be formed in the substrate 110. [ The first trench TR1 may be a trench formed in the substrate 110 to contact the bit line BL with the active region AR. For example, a direct contact DC may be formed in the first trench TR1.

The first trench TR1 may include a first sub trench STR1 and a second sub trench STR2.

The first sub trench STR1 may be formed around the center of the active region AR. For example, as shown in Figs. 1 and 2, the first sub trench STR1 may be formed in the device isolation film 120 adjacent to the center of the active region AR and the center of the active region AR . Thus, the first sub trench STR1 can expose the center of the active region AR.

The second sub trench STR2 may be formed on the word line 160 (WL in FIG. 1). For example, as shown in FIGS. 1 and 4, a second sub-trench STR2 may be formed in the second capping pattern 164 on the word line 160. As shown in FIG.

The depth of the second sub trench STR2 may be shallower than the depth of the first sub trench STR1. However, this is only a feature of the process, and the technical idea of the present invention is not limited thereto.

In some embodiments, the first sub trench STR1 and the second sub trench STR2 may be connected to each other.

The insulating layer 130 may be formed on the substrate 110 and the device isolation layer 120. 2, the insulating film 130 may be formed on the substrate 110 and the device isolation film 120 in the region of the substrate 110 where the direct contact (DC) is not formed.

The insulating film 130 may be a single film but the insulating film 130 may be a multiple film including a first insulating film 131, a second insulating film 132 and a third insulating film 133.

The first insulating film 131 may include, for example, silicon oxide. The second insulating layer 132 may include a material having an etch selectivity different from that of the first insulating layer 131. For example, the second insulating film 132 may include silicon nitride. The third insulating layer 133 may include a material having a dielectric constant lower than that of the second insulating layer 132. For example, the third insulating film 133 may include silicon oxide.

In some embodiments, the width of the third insulating film 133 may be substantially equal to the width of the bit line BL. In the present specification, "same" means not only completely identical but also minute differences that may occur due to process margins and the like.

The word line 160 (WL in FIG. 1) may extend long along the first direction X across the active area AR. The word lines 160 may extend in parallel to one another. In addition, the plurality of word lines 160 may be spaced apart from one another at regular intervals.

In some embodiments, as shown in Figure 4, the word lines 160 may be buried in the substrate 110 and extended. For example, the word line 160 may form a second trench TR2 extending in a first direction X on the substrate 110, a gate dielectric layer 161 within the second trench TR2, The conductive film 162 and the fifth conductive film 163 in this order. Next, a second capping pattern 164 filling the second trench TR2 may be formed on the gate dielectric layer 161, the fourth conductive layer 162, and the fifth conductive layer 163.

4, the word line 160 is shown as a multiple layer including a fourth conductive layer 162 and a fifth conductive layer 163, but the word line 160 may be a single layer.

For example, the fourth conductive layer 162 and the fifth conductive layer 163 may include metal, polysilicon, etc., but the technical idea of the present invention is not limited thereto.

The bit line 140 (BL in FIG. 1) may be disposed on the substrate 110 and the insulating film 130. The bit line 140 may extend along the second direction Y different from the first direction X across the active region AR and the word line 160. For example, the second direction Y may be a direction orthogonal to the first direction X. [ Accordingly, the bit line 140 may obliquely cross the active region AR and may vertically intersect the word line 160. The bit lines 140 may extend in parallel to one another. In addition, the plurality of bit lines 140 may be spaced apart from one another at regular intervals.

The bit line 140 may be a single film but the bit line 140 may include a first conductive film 141, a second conductive film 142, a third conductive film 143, (DC). ≪ / RTI >

For example, the first conductive layer 141, the second conductive layer 142, and the third conductive layer 143 may each comprise polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or combinations thereof . For example, the first conductive layer 141 may include polysilicon, the second conductive layer 142 may include TiSiN, the third conductive layer 143 may include tungsten, The technical idea of the present invention is not limited thereto.

The direct contact DC may be formed in the first sub trench STR1. In addition, the direct contact (DC) can contact the substrate 110. For example, the direct contact DC may contact the center of the active region AR exposed by the first sub trench STR1. The active region AR of the substrate 110 in contact with the direct contact DC can function as a source and a drain region.

The remaining portion of the bit line 140 where the direct contact DC is not formed may be formed on the insulating film 130. [

The direct contact (DC) may comprise a conductive material. Accordingly, a part of the bit line 140 can be electrically connected to the active region AR.

In some embodiments, the direct contact (DC) may comprise the same material as the first conductive film 141. [ For example, a direct contact (DC) may comprise polysilicon. However, the technical idea of the present invention is not limited thereto, and the direct contact (DC) may include a material different from the first conductive film 141 according to the manufacturing process.

The bit line 140 may include a first capping pattern 144 thereon. The first capping pattern 144 may include a silicon nitride film, but the technical idea of the present invention is not limited thereto.

The bit line 140 may include a first bit line 140a and a second bit line 140b.

The first bit line 140a is part of the bit line 140 in contact with the active area AR. The second bit line 140b is part of the bit line 140 that is not in contact with the active area AR. 2, the first bit line 140a may be part of the bit line 140 including the direct contact (DC), and the second bit line 140b may include a direct contact (DC) (Not shown).

In some embodiments, the first bit line 140a may not include the first conductive layer 141. For example, the first conductive layer 141 of the second bit line 140b may be replaced by a direct contact (DC) in the first bit line 140a. However, the technical idea of the present invention is not limited thereto, and a direct contact (DC) of the first bit line 140a may be formed under the first conductive film 141. [

In some embodiments, the width of the bit line 140 may be less than the width of the first sub-trench STR1. The width of the bit line 140 and the first sub trench STR1 means a width in the first direction X intersecting the second direction Y in which the bit line 140 extends do. For example, as shown in FIG. 2, the width of the bit line 140 may be less than the width of the first sub-trench STR1. Accordingly, a part of the bit line 140 can be formed in the first sub trench STR1.

Spacer structure 150 (SP in FIG. 1) may be disposed on the sidewalls of bit line 140. In addition, the spacer structure 150 may be elongated along the second direction Y. [

The spacer structure 150 may be in contact with the substrate 110 and the device isolation film 120 at a portion of the bit line 140 where the direct contact DC is formed. However, in the remaining portion of the bit line 140 where the direct contact (DC) is not formed, the spacer structure 150 may contact the insulating film 130. [ For example, the spacer structure 150 may be in contact with the substrate 110 and the device isolation film 120 on the sidewalls of the first bit line 140a and on the sidewalls of the second bit line 140b with the insulating film 130 ). ≪ / RTI >

The spacer structure 150 may include a first spacer 151, a second spacer 152, a third spacer 153, and a fourth spacer 154.

The first spacers 151 may extend along at least a portion of the sidewalls of the bit line 140 and the first trench TR1. Also, the first spacer 151 may contact the bit line 140.

For example, the first spacers 151 may extend along at least a portion of the sidewalls of the first bit line 140a and the profile of the first trench TR1. At this time, the first spacer 151 may contact at least part of the side wall of the first bit line 140a, the substrate 110, and the device isolation film 120.

As shown in Fig. 3A, the first spacer 151 may include a medial portion 151i and an outer portion 151o. The inner portion 151i of the first spacer 151 contacts the at least a portion of the sidewalls of the first bit line 140a and is spaced apart from the first spacers 151a extending along at least a portion of the sidewalls of the first bit line 140a ). The outer portion 151o of the first spacer 151 is a portion of the first spacer 151 that contacts the substrate 110 and the element isolation film 120 and extends along the profile of the first trench TR1.

2, the first spacer 151 is illustrated as being in contact with the center of the active region AR and the isolation layer 120 adjacent to the center of the active region AR, but the technical idea of the present invention is limited thereto It is not. For example, due to a misalignment that may occur in the process of forming the first sub-trench STR1, the first spacer 151 may be in contact with another adjacent active region AR. For example, the first sub trench STR1 may be formed in one active area AR in contact with the direct contact DC and in the other active area AR in contact with the solder contact BC . Thus, in some embodiments, the outer portion 151o of the first spacer 151 may contact the active region AR in contact with the buried contact BC.

Also, for example, the first spacers 151 may extend along at least a portion of the sidewalls of the second bit line 140b. At this time, the first spacer 151 may contact at least a part of the side wall of the second bit line 140b.

Also, the first spacer 151 may extend on the insulating film 130. [ For example, the first spacers 151 may extend along the upper surface of the second insulating layer 132 from the side walls of the second bit line 140b.

Also, as shown in FIG. 4, a first spacer 151 may be formed on the word line 160. The first spacer 151 extends along the first trench TR1 so that the first spacer 151 can extend along the second sub trench STR2 on the word line 160. [ Accordingly, the first spacers 151 may be formed in the second capping pattern 164 on the word line 160.

The first spacer 151 may comprise silicon oxide. In some embodiments, the first spacers 151 may comprise a material resistant to the wet etch process. For example, the first spacer 151 may comprise a material resistant to a wet etch process using hydrogen fluoride (HF) or phosphoric acid (H ₃ PO ₄ ). The first spacer 151 may comprise, for example, carbon-doped silicon oxide (SiOC).

The second spacers 152 may be formed on the first spacers 151. Also, the second spacer 152 may fill the first trench TR1.

In some embodiments, the uppermost surface of the second spacer 152 may be disposed substantially in the same plane as the upper surface of the first spacer 151 on the second insulating film 132.

4, a second spacer 152 may be formed on the word line 160. In this case, The second spacer 152 fills the second trench TR2 so that the second spacer 152 can fill the second sub trench STR2 on the word line 160. [ Accordingly, a second spacer 152 may be formed in the second capping pattern 164 on the word line 160.

The second spacers 152 may comprise a material resistant to the wet etch process. For example, the first spacer 151 may comprise a material resistant to a wet etch process using hydrogen fluoride (HF) or phosphoric acid (H ₃ PO ₄ ). The second spacers 152 may comprise, for example, silicon nitride.

The third spacer 153 may be formed on the first spacer 151 and the second spacer 152. Also, third spacers 153 may extend along the sidewalls of bit line 140. For example, a third spacer 153 may be formed on the sidewalls of the first spacer 151 and the upper surface of the second spacer 152. The third spacer 153 may be elongated along the second direction Y. [

The third spacer 153 may include a material having a lower dielectric constant than silicon nitride. For example, the third spacer 153 may comprise silicon oxide. However, the technical idea of the present invention is not limited thereto, and the third spacer 153 may include a silicon germanium compound or a polymer.

The fourth spacer 154 may be formed on the second spacer 152 and the third spacer 153. In addition, fourth spacers 154 may extend along the sidewalls of bit line 140. For example, the fourth spacer 154 may be formed on the upper surface of the second spacer 152 and on the side wall of the third spacer 153. The fourth spacers 154 may be elongated along the second direction (Y).

In some embodiments, the fourth spacers 154 may be formed to fill the trenches in the second spacers 152 and the third spacers 153. This will be described later in detail with reference to FIGS. 30 to 33. FIG.

3A, the fourth spacer 154 is shown as not contacting the first spacer 151, but the technical idea of the present invention is not limited thereto. For example, the fourth spacer 154 may contact both the first spacer 151, the second spacer 152, and the third spacer 153 all together.

The fourth spacers 154 may comprise, for example, silicon nitride.

The fence 170 may be formed on the word line 160. Like the word line 160, the fence 170 may extend long along the first direction X. [ The fence 170 may support a buried contact BC formed between the word lines 160.

The fence 170 may include, for example, silicon nitride, but the technical idea of the present invention is not limited thereto.

The buried contacts BC may be disposed on the substrate 110 between the bit lines 140. For example, as shown in FIG. 1, a buried contact BC may be interposed in an area defined by the word line 160 and the bit line 140. In addition, the buried contacts BC can form a plurality of isolated regions which are spaced apart from each other.

In some embodiments, the immersion contact (BC) may be interposed in the region defined by the fourth spacer 154 and the fence 170.

The buried contact (BC) can contact the substrate 110. For example, the immersion contact BC may contact the end of the active region AR of FIG. The active region AR of the substrate 110 in contact with the buried contact BC may function as a source and a drain region.

In some embodiments, the immersion contact BC may be formed to fill the fourth spacer 154 and the trench in the substrate 110. In some embodiments, the immersion contact (BC) may be in contact with the first spacer (151). For example, as shown in FIG. 3A, the buried contact BC can contact the outer portion 151o of the first spacer 151. [ These will be described later in detail with reference to Figs. 38 to 42. Fig.

The investment contact (BC) may include a conductive material. Accordingly, the solder contact BC can be electrically connected to the active region AR. The investment contact (BC) may include, for example, polysilicon, but the technical idea of the present invention is not limited thereto.

The landing pad LP may be disposed on a part of the upper surface of the bit line 140 and on the upper surface of the buried contact BC. In addition, the landing pad LP may contact the buried contact BC. Similar to the buried contacts BC, the landing pads LP can form a plurality of isolated regions that are spaced apart from one another.

The landing pad LP may include a conductive material and be electrically connected to the buried contact BC. For example, the landing pad LP may include tungsten (W), but the technical idea of the present invention is not limited thereto.

The interlayer insulating film 180 may be formed on a part of the upper surface of the landing pad LP and on a part of the bit line 140. Further, the interlayer insulating film 180 can define a region of the landing pad LP that forms a plurality of isolated regions. That is, the interlayer insulating film 180 can separate a plurality of landing pads LP from each other. Further, the interlayer insulating film 180 may be patterned to expose a part of the upper surface of each landing pad LP.

The interlayer insulating film 180 may include an insulating material to electrically isolate the plurality of landing pads LP from each other. For example, the interlayer insulating film 180 may include silicon oxide, but the technical idea of the present invention is not limited thereto.

The capacitor 190 may be disposed on the interlayer insulating film 180 and the landing pad LP. The capacitor 190 may be connected to a part of the upper surface of the landing pad LP exposed by the interlayer insulating film 180. [ As a result, the capacitor 190 can be electrically connected to the source and drain regions connected to the buried contact BC. Accordingly, the capacitor 190 can store charges in a semiconductor memory device or the like.

For example, as shown in FIGS. 2 and 4, the capacitor 190 may include a lower electrode 191, a capacitance dielectric layer 192, and an upper electrode 193. The capacitor 190 can store the charge in the capacitance dielectric layer 192 by the potential difference generated between the lower electrode 191 and the upper electrode 193. [

The lower electrode 191 and the upper electrode 193 may comprise, for example, doped polysilicon, metal or metal nitride. In addition, the capacitance dielectric layer 192 may comprise, for example, silicon oxide or high permittivity material.

As the semiconductor device becomes highly integrated, the influence of parasitic capacitance and leakage current increases gradually. For example, as the spacing between the bit lines of a dynamic random access memory (DRAM) narrows, the parasitic capacitance between the bit line and the bit line, and the bit line and the buried contact can increase.

However, the semiconductor device according to some embodiments can minimize the parasitic capacitance by using silicon oxide. For example, a semiconductor device according to some embodiments may include a first spacer 151 in contact with the bit line 140. The first spacer 151 includes silicon oxide so that the semiconductor device according to some embodiments can maximize the silicon oxide content between the bit line 140 and the buried contact BC.

Since the silicon oxide is lower in dielectric constant than silicon nitride, the semiconductor device according to some embodiments can effectively reduce the parasitic capacitance. For example, compared to a semiconductor device in which spacers in contact with the bit line 140 are formed of silicon nitride, the semiconductor device according to some embodiments can effectively reduce the parasitic capacitance.

Further, the semiconductor device according to some embodiments can effectively reduce the parasitic capacitance, so that the high integration of the semiconductor device can be realized within the permissible parasitic capacitance range.

Further, the semiconductor device according to some embodiments can improve the process margin. There is a problem that silicon nitride is in contact with the depletion region of the substrate 110 to form the interface trap N _it when the spacer in contact with the bit line 140 is formed of silicon nitride. These interface traps cause the leakage current to increase.

However, the semiconductor device according to some embodiments can minimize the leakage current even if the first spacer 151 contacts the depletion region by forming the first spacer 151 with silicon oxide. This is because the silicon oxide can effectively prevent the leakage current due to the interface trap (N _it ) from the silicon nitride.

1, 2, 3B and 4, in a semiconductor device according to some embodiments, the spacer structure 150 further includes a fifth spacer 155. For the sake of convenience of description, those which are the same as those described with reference to Figs. 1, 2, 3A, and 4 will be briefly described or omitted.

The fifth spacer 155 may be interposed between the first spacer 151 and the second spacer 152. The fifth spacer 155 may extend along the profile of the first trench TR1 and at least a portion of the sidewalls of the first bit line 140a on the first spacer 151. [ That is, the fifth spacers 155 may extend along the profile of the first spacers 151 on the first bit line 140a. However, the fifth spacers 155 may not be formed on the second bit line 140b.

In some embodiments, the top surface of the fifth spacer 155 may be disposed substantially flush with the top surface of the second spacer 152. Accordingly, the third spacer 153 can be formed on the sidewall of the first spacer 151, the upper surface of the second spacer 152, and the upper surface of the fifth spacer 155.

1, 2, 3C and 4, in the semiconductor device according to some embodiments, the upper surface of the inner side 151i of the first spacer 151 is lower than the upper surface of the second spacer 152 . For the sake of convenience of description, those which are the same as those described with reference to Figs. 1, 2, 3A, and 4 will be briefly described or omitted.

3C, the upper surface of the inner side 151i of the first spacer 151 is shown as being disposed on the same plane as the upper surface of the second spacer 152, but the upper surface of the inner side 151i of the first spacer 151 The upper surface may be lower. Accordingly, the third spacer 153 can be formed on the upper surface of the first spacer 151 and the upper surface of the second spacer 152.

In some embodiments, the first spacers 151 may not be formed on the second bit line 140b.

1, 2, 3, and 4, in a semiconductor device according to some embodiments, the spacer structure 150 includes an air spacer 153A and a sixth spacer 156. For the sake of convenience of description, those which are the same as those described with reference to Figs. 1, 2, 3A, and 4 will be briefly described or omitted.

The air spacers 153A may be formed by removing the third spacers 153 of Fig. 3A. That is, the air spacer 153A may be an empty space formed in the area where the third spacer 153 of FIG. 3A is removed. This will be described later in detail with reference to FIG. 43B.

The sixth spacer 156 may be formed along the outer circumferential surface of the air spacer 153A. For example, a sixth spacer 156 may be formed on the sidewall of the first spacer 151, the upper surface of the second spacer 152, and the sidewall of the fourth spacer 154.

Since the air spacers 153A have a smaller dielectric constant than silicon oxide, the semiconductor device according to some embodiments can more effectively reduce the parasitic capacitance.

1, 2, 3E and 4, in the semiconductor device according to some embodiments, the upper surface of the inner portion 151i of the first spacer 151 is lower than the upper surface of the second spacer 152 . For the sake of convenience of description, those which are the same as those described with reference to Figs. 1, 2, 3D and 4 will be briefly described or omitted.

The air spacer 153A may be formed by removing a part of the first spacer 151 and the third spacer 153 in Fig. 3A. That is, the air spacer 153A may be an empty space formed in a region where the first spacer 151 and the third spacer 153 are removed in FIG. 3A. Accordingly, the air spacer 153A can be formed on the upper surface of the first spacer 151 and the upper surface of the second spacer 152. [ This will be described later in detail with reference to FIG. 43C.

Referring to FIGS. 1, 2, 3, and 4, in the semiconductor device according to some embodiments, the width of the third insulating film 133 may be smaller than the width of the bit line 140. For the sake of convenience of description, those which are the same as those described with reference to Figs. 1, 2, 3E and 4 will be briefly described or omitted.

For example, the width W2 of the third insulating film 133 may be smaller than the width W1 of the second bit line 140b. This can be caused by a process of removing a part of the first spacer 151 to form the air spacer 153A. This will be described later in detail with reference to FIG. 43C.

In some embodiments, the upper surface of the inner portion 151i of the first spacer 151 may be disposed lower than the upper surface of the second spacer 152. [

Referring to Figs. 5 to 7, the semiconductor device according to some embodiments includes a third trench TR3. 5 to 7, except that the third trench TR3 is formed instead of the first trench TR1 in comparison with the semiconductor device according to Figs. 1 to 4, 4 is substantially the same as the semiconductor device according to Figs. Therefore, the differences are mainly described.

The third trench TR3 may be formed in the substrate 110. [ The third trench TR3 may be a trench formed in the substrate 110 to contact the bit line 140 with the active region AR. For example, a direct contact (DC) may be formed in the third trench TR3.

The third trench TR3 may be formed around the center of the active region AR. For example, as shown in Figs. 5 and 6, the third trench TR3 may be formed in the device isolation film 120 adjacent to the center of the active region AR and the center of the active region AR. Thus, the third trench TR3 can expose the center periphery of the active region AR.

However, unlike the first trench TR1 of FIGS. 1 through 4, the third trench TR3 may not be formed on the word line 160. For example, as shown in Fig. 5, the third trench TR3 may be formed in a circular shape around the center of the active region AR. Accordingly, unlike the semiconductor device according to FIGS. 1 to 4, the first spacer 151 and the second spacer 152 may not be formed on the word line 160.

Hereinafter, with reference to Figs. 1 to 46, a method of manufacturing a semiconductor device according to some embodiments of the technical idea of the present invention will be described. For the sake of convenience of description, those which are the same as those described with reference to Figs. 1 to 7 will be briefly described or omitted.

FIGS. 8 to 46 are intermediate plan views illustrating a method of manufacturing a semiconductor device according to some embodiments of the technical idea of the present invention. FIG.

Referring to FIGS. 8 to 10, a substrate 110, an isolation layer 120, a word line 160, and an insulation layer 130 are provided. 9 is a sectional view taken along line A1-A1 'of FIG. 8, and FIG. 10 is a sectional view taken along line B1-B1' of FIG.

The substrate 110 may comprise an active region AR. As shown in Fig. 8, the active region AR may be formed in the shape of an oblique bar. The active region AR may be formed by implanting impurities into the substrate 110. In this case, implantation of impurities may be performed by an ion implantation process, but the technical idea of the present invention is not limited thereto.

The device isolation film 120 may be formed on the substrate 110. The device isolation film 120 may define a plurality of active regions AR.

The word lines 160 may be formed to be buried in the substrate 110 to extend.

The insulating layer 130 may be formed on the substrate 110, the isolation layer 120, and the word line 160. For example, the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 may be sequentially stacked on the substrate 110, the element isolation layer 120, and the word line 160.

11 to 13, a first conductive film 141 is formed on an insulating film 130, and a mask film 200 is formed on a first conductive film 141. Next, as shown in FIG. 12 is a cross-sectional view taken along line A2-A2 'in Fig. 11, and Fig. 13 is a cross-sectional view taken along line B2-B2' in Fig.

The first conductive layer 141 may be formed on the insulating layer 130. For example, the first conductive layer 141 may be formed to cover the third insulating layer 133.

The mask film 200 may be formed on the first conductive film 141 to expose the center periphery of the active region AR. 11 to 13, the mask film 200 may be formed to expose the device isolation film 120 adjacent to the center of the active region AR and the center of the active region AR have. In addition, the mask film 200 may be formed to expose a part of the word line 160.

11, the mask film 200 is shown as being elliptical, but the technical idea of the present invention is not limited thereto. For example, the mask film 200 may be circular, or may be a polygon such as a rectangle.

The mask film 200 may include silicon oxide, but the technical idea of the present invention is not limited thereto.

14 to 16, a first conductive film 141, an insulating film 130, a substrate 110, an element isolation film 120, and a second capping pattern (not shown) are formed by using the mask film 200 as an etching mask. 164 are patterned. 15 is a cross-sectional view taken along line A3-A3 'in Fig. 14, and Fig. 16 is a cross-sectional view taken along line B3-B3' in Fig.

Accordingly, the first trench TR1 may be formed in the substrate 110. [

The first trench TR1 may include a first sub trench STR1 and a second sub trench STR2.

The first sub trench STR1 may be formed in the device isolation film 120 adjacent to the center of the active region AR and the center of the active region AR. Thus, the first sub trench STR1 can expose the center of the active region AR. The second sub trench STR2 may be formed in the second capping pattern 164 on the word line 160. [

17 to 19, a sixth conductive layer 145 is formed in the first trench TR1. 18 is a cross-sectional view taken along the line A4-A4 'in Fig. 17, and Fig. 19 is a cross-sectional view taken along line B4-B4' in Fig.

The sixth conductive film 145 may be formed to fill the first trench TR1. The upper surface of the sixth conductive layer 145 may be formed to be coplanar with the upper surface of the first conductive layer 141.

A second conductive layer 142, a third conductive layer 143 and a first capping pattern 144 are sequentially formed on the first conductive layer 141 and the sixth conductive layer 145.

20 to 22, the first conductive film 141, the second conductive film 142, the third conductive film 143, the first capping pattern 144, and the sixth conductive film 145 are patterned do. 21 is a cross-sectional view taken along line A5-A5 'in Fig. 20, and Fig. 22 is a cross-sectional view taken along line B5-B5' in Fig.

Thus, a bit line 140 may be formed that extends long in the second direction Y across the active region AR and the word line 160. At this time, the sixth conductive layer 145 may be patterned to form a direct contact DC. In addition, the width of the bit line 140 may be smaller than the width of the first sub trench STR1.

In some embodiments, the third insulating film 133 may also be patterned. The third insulating film 133 may be patterned to have the same width as the width of the bit line 140.

23 and 24, a first spacer 151 is formed on the resultant structure according to FIGS. 21 and 22. As shown in FIG.

The first spacers 151 may be formed to extend along at least a portion of the sidewalls of the bit line 140 and the first trench TR1.

The first spacer 151 may comprise silicon oxide. The first spacer 151 may be formed, for example, through an atomic layer deposition (ALD) process.

In some embodiments, the first spacers 151 may comprise carbon-doped silicon oxide (SiOC).

Referring to Figs. 25 to 27, a second spacer 152 is formed on the first spacer 151 to fill the first trench TR1. 26 is a cross-sectional view taken along line A6-A6 'in Fig. 25, and Fig. 27 is a cross-sectional view taken along line B6-B6' in Fig.

For example, a silicon nitride film can be formed on the resultant structure according to FIGS. Then, a part of the silicon nitride film can be etched by using the first spacers 151 as an etching stopper film. Accordingly, a second spacer 152 filling the first trench TR1 can be formed.

Referring to FIGS. 28 and 29, a third spacer 153 is formed on the first spacer 151 and the second spacer 152.

For example, a third spacer 153 including a silicon oxide film may be formed on the resultant structure according to FIGS. 26 and 27. The third spacer 153 may be formed to extend along the profile of the first spacer 151 and the second spacer 152.

Referring to FIGS. 30 and 31, a fourth trench TR4 is formed between the bit lines 140. FIG.

The fourth trench TR4 may be formed to extend along the sidewall of the bit line 140. [ 30, the fourth trench TR4 is formed by etching a part of the first spacer 151, a part of the second spacer 152 and a part of the third spacer 153, for example, . Accordingly, the fourth trench TR4 can be elongated along the second direction Y. [

32 and 33, a fourth spacer 154 is formed in the fourth trench TR4.

The fourth spacers 154 may be formed to extend along the profile of the fourth trench TR4. That is, the fourth spacers 154 may be formed to extend along the profiles of the second spacers 152 and the third spacers 153.

Referring to FIGS. 34 and 35, a sacrificial layer 170S may be formed on the fourth spacer 154. FIG.

The sacrificial layer 170S may be formed to cover the resultant structure according to FIGS.

Then, the fifth trench TR5 may be formed in the sacrificial layer 170S. As shown in FIG. 35, the fifth trench TR5 may be formed on the word line 160. As shown in FIG. In addition, the fifth trench TR5 may be elongated in a direction in which the word line 160 extends. That is, the fifth trench TR5 may extend along the first direction X in a long direction.

The fifth trench TR5 may be formed within a portion of the first spacer 151 on the word line 160 and a portion of the second spacer 152 on the word line 160. In some embodiments,

Referring to FIGS. 36 and 37, a fence 170 is formed on the word line 160.

For example, the fifth trench TR5 in FIG. 35 may be filled with an insulating material containing silicon nitride. Then, the sacrificial layer 170S can be removed. Thus, a fence 170 may be formed on the word line 160, which extends in a direction in which the word line 160 extends.

Referring to FIGS. 38 and 39, a sixth trench TR6 is formed between the bit line 140 and the word line 160. As shown in FIG.

The sixth trench TR6 may be formed to expose a part of the substrate 110. [

As shown in Fig. 38, the sixth trench TR6 may be etched between the bit lines 140 to expose the substrate 110. [0157] As shown in Fig. For example, a portion of the fourth spacers 154, a portion of the substrate 110, and a portion of the device isolation layer 120 may be etched to expose the substrate 110 between the bit lines 140.

By forming the sixth trench TR6, the spacer structure 150 including the first spacer 151, the second spacer 152, the third spacer 153, and the fourth spacer 154 can be formed .

Further, as shown in Fig. 39, the sixth trench TR6 may be etched between the word lines 160 to expose the substrate 110. For example, a portion of the substrate 110 between the fins 170 and a portion of the device isolation layer 120 may be etched to expose the substrate 110 between the word lines 160.

Referring to Figs. 40 to 42, a buried contact BC is formed in the sixth trench TR6. 41 is a cross-sectional view taken along line A7-A7 'in Fig. 40, and Fig. 42 is a cross-sectional view taken along line B7-B7' in Fig.

The upper surface of the buried contact BC may be formed lower than the upper surface of the spacer structure 150 and the fence 170. [ For example, a polysilicon film can be formed on the resultant in accordance with FIGS. 38 and 39. Then, an etchback process may be performed so that the upper surface of the polysilicon film becomes lower than the upper surface of the spacer structure 150 and the fence 170. [ Accordingly, the immersion contact BC can form a plurality of isolated regions that are spaced apart from each other by the spacer structure 150 and the fence 170. [

The landing pad LP may then be formed on the buried contact BC. The upper surface of the landing pad LP may be formed higher than the upper surface of the spacer structure 150.

Referring to Figs. 43A and 44, a seventh trench TR7 is formed in the landing pad LP.

That is, the landing pad LP may be patterned by the seventh trench TR7. Thus, the landing pad LP can form a plurality of isolated regions which are spaced apart from each other by the seventh trench TR7.

In some embodiments, the seventh trench TR7 may be formed to overlap a portion of the bit line 140 and the spacer structure 150. Accordingly, a part of the first capping pattern 144, the first spacer 151, the third spacer 153, and the fourth spacer 154 can be exposed.

Referring to FIG. 43B, the manufacturing method of the semiconductor device according to some embodiments may further include removing the third spacer 153 to form the air spacer 153A.

For example, after the seventh trench TR7 is formed, a wet etching process can be performed to form the air spacers 153A. For example, by using a wet etching process using hydrogen fluoride (HF) or phosphoric acid (H ₃ PO _4), the third spacer 153 it is exposed by the seventh trench (TR7) to be removed.

Since the third spacer 153 may include a silicon oxide film, the third spacer 153 can be easily removed by a wet etching process. However, in the case where the first spacer 151 includes SiOC, the first spacer 151 may remain unremoved by the wet etching process.

In some embodiments, forming the seventh trench TR7 and forming the air spacers 153A may be performed simultaneously.

43C, the method of manufacturing a semiconductor device according to some embodiments may further include removing the portion of the first spacer 151 and the third spacer 153 to form the air spacer 153A .

For example, after the seventh trench TR7 is formed, a wet etching process can be performed to form the air spacers 153A. For example, hydrogen fluoride (HF) or phosphoric acid (H ₃ PO ₄₎ for using the wet etching process using, part and a third spacer (153 of the first spacer (151) exposed by the seventh trench (TR7) Can be removed.

In the case where the first spacer 151 includes SiOC, the resistance to the wet etching process of the first spacer 151 may be deteriorated. For example, in the case where an annealing process or an ashing process is performed in the manufacturing process of a semiconductor device, the resistance to the wet etching process of the SiOC can be deteriorated. Accordingly, a part of the first spacer 151 including SiOC can be removed by a wet etching process. Since the third spacer 153 may include a silicon oxide film, the third spacer 153 can be easily removed by a wet etching process.

However, in some embodiments, forming the seventh trench TR7 and forming the air spacers 153A may be performed simultaneously.

45 and 46, an interlayer insulating film 180 is formed on the landing pad LP.

The interlayer insulating film 180 may be formed to fill the seventh trench TR7. Accordingly, the landing pad LP can form a plurality of isolated regions which are spaced apart from each other by the interlayer insulating film 180. [

Next, referring to FIGS. 1 to 4, a capacitor 190 is formed on the resultant structure according to FIGS. 45 and 46. Thus, a semiconductor device according to some embodiments can be manufactured.

In the process of forming the interlayer insulating film 180, the sixth spacers 156 of FIGS. 3E to 3F may be formed. For example, the interlayer insulating film 180 may not fill the air spacers 153A while filling the seventh trenches TR7. This can be attributed to the fact that the air spacers 153A are formed thin.

However, in the process of forming the interlayer insulating film 180, the material constituting the interlayer insulating film 180 may be thinly coated along the outer peripheral surface of the air spacer 153A. Thus, as shown in FIGS. 3D, 3E and 3F, a sixth spacer 156 may be formed along the outer circumferential surface of the air spacer 153A. However, in some embodiments, the sixth spacers 156 may not be formed.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

110: substrate 120: element isolation film
AR: active region BL: bit line
WL: word line SP: spacer structure
TR1: 1st trench LP: Landing pad

Claims (10)

Board;
A trench in the substrate;
A bit line within the trench, the bit line having a width narrower than the width of the trench;
A first spacer extending along the trench at least a portion of a sidewall of the bit line and in contact with the bit line, the first spacer comprising silicon oxide; And
And a second spacer on the first spacer, the second spacer filling the trench. The method according to claim 1,
The substrate comprising a first active region,
At least a portion of the trench being formed in the first active region,
Wherein the bit line contacts the first active region. The method according to claim 1,
Wherein the first spacer comprises SiOC. The method according to claim 1,
And a third spacer between the first spacer and the second spacer, the third spacer including silicon oxide. The method according to claim 1,
Wherein the first spacer includes an inner portion extending along at least a portion of a sidewall of the first bit line and an outer portion extending along the trench,
And the upper surface of the inner side portion is disposed lower than or equal to the upper surface of the second spacer. A substrate comprising a first active region;
A first bit line on the first active region;
A first spacer extending along at least a portion of a sidewall of the first bit line and in contact with the first bit line, the first spacer comprising SiOC; And
And a second spacer on said first spacer, said second spacer comprising silicon nitride. The method according to claim 6,
A device isolation layer defining a first active region and a second active region spaced apart from the first active region;
The second active region and the second trench in the device isolation film,
Further comprising a trench contact spaced apart from the first bit line and filling the second trench. The method according to claim 6,
A device isolation layer defining the first active region,
And a second bit line spaced apart from the first bit line on the isolation film,
Wherein the first spacer extends along at least a portion of a sidewall of the first bit line and at least a portion of a sidewall of the second bit line. Board;
A bit line extending on the substrate along a first direction;
A word line extending in the substrate along a second direction intersecting the first direction;
A capping pattern extending along the second direction on the word line;
A first trench including a first sub trench in the capping pattern;
A first spacer extending along the first sub trench and including a silicon oxide film; And
And a second spacer on the first spacer, the second spacer filling the first sub trench. Providing a substrate,
Forming a trench in the substrate,
Forming a bit line in the trench, the bit line having a width narrower than the width of the trench,
At least a portion of a sidewall of the bit line and a trench extending along the trench and in contact with the bit line to form a first spacer comprising silicon oxide,
And forming a second spacer on the first spacer, the second spacer filling the trench.

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