KR20190032104A - Nonvolatile memory device, data storage device including nonvolatile memory device and operating method for the data storage device - Google Patents

Abstract

Provided is a nonvolatile memory device which can efficiently determine a reliability state of a page in performing a write operation of data. To this end, the nonvolatile memory device comprises: a plurality of memory cells; a buffer storing data to be written on a page of the memory cells; a fail bit counter configured to count fail bits from the data stored in the buffer; and a state information determination unit determining a risk of the page based on the number of counted fail bits.

Description

TECHNICAL FIELD [0001] The present invention relates to a nonvolatile memory device, a data storage device including the nonvolatile memory device, and a method of operating the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and more particularly, to a data storage device including a non-volatile memory device.

The data storage device may be configured to store data provided from an external device in response to a write request of the external device. In addition, the data storage device may be configured to provide stored data to an external device in response to a read request of the external device. An external device is an electronic device capable of processing data, and may include a computer, a digital camera, a cellular phone, or the like. The data storage device may be built in an external device or operated in a detachable form and connected to an external device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because it has no mechanical driving part, has very high access speed of information and low power consumption. A data storage device having such advantages includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, a UFS (Universal Flash Storage) device, and a solid state drive (SSD).

An embodiment of the present invention is to provide a nonvolatile memory device, a data storage device, and an operation method thereof that can efficiently determine a reliability state of a page when a data write operation is performed.

A non-volatile memory device according to an embodiment of the present invention includes a plurality of memory cells, a buffer configured to store data to be written to a page of memory cells, a fail bit counter configured to count fail bits of data stored in the buffer, And a status information determination unit configured to determine a risk level of the page based on the number of pages.

A data storage device according to an embodiment of the present invention may include a nonvolatile memory device including a plurality of memory cells and a controller configured to output a write command of data to be written to a page of the first memory cells to a nonvolatile memory device Wherein the non-volatile memory device is capable of performing a write operation and a page risk decision operation in response to a write command and transmits the risk of the page to the controller, wherein the controller, when the risk is above a criterion, A write command can be output to be written to the page of memory cells.

A method of operating a data storage device in accordance with an embodiment of the present invention includes the steps of the controller outputting a first write command, the nonvolatile memory device determining a risk of a page in which the data is written in response to a first write command, The controller may include determining a page to which the data is to be written based on the determined risk.

The data storage device according to the embodiment of the present invention can determine the reliability state of the page by judging the fail bit when the data is written.

Further, the number of fail bits of a chunk within one page can be determined, and the reliability state of the page can be judged more efficiently.

1 is a block diagram illustrating an exemplary non-volatile memory device in accordance with an embodiment of the present invention.
2 is a block diagram illustrating an exemplary data storage device in accordance with an embodiment of the present invention.
FIG. 3A is a table showing an example of setting a chunk unit for counting a fail bit, FIG. 3B is a table illustrating an example of a fail bit number setting as a criterion for determining a state of each chunk, A table for exemplarily showing a setting for judging a risk.
4 and 5 are flowcharts illustrating exemplary operation of a data storage device according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a result of judging the degree of risk for each chunk by way of example.
7 is a flowchart illustrating an exemplary method of operating a data storage device according to an embodiment of the present invention.
8 is an exemplary illustration of a data processing system including a solid state drive (SSD) according to an embodiment of the present invention.
9 is an exemplary illustration of a data processing system including a data storage device in accordance with an embodiment of the present invention.
10 is an exemplary illustration of a data processing system including a data storage device in accordance with an embodiment of the present invention.
11 is a diagram illustrating a network system including a data storage device according to an embodiment of the present invention.
12 is a block diagram illustrating an exemplary non-volatile memory device included in a data storage device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein, It is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation of the scope of the appended claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / coupled " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating an exemplary non-volatile memory device in accordance with an embodiment of the present invention. And Figure 2 is a block diagram illustrating an exemplary data storage device in accordance with an embodiment of the present invention.

The data storage device 100 may be configured to store data provided from an external device in response to a write request of the external device. In addition, the data storage device 100 may be configured to provide stored data to an external device in response to a read request of the external device.

The data storage device 100 may store data accessed by a host device (not shown) such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV, an in- vehicle infotainment system, The data storage device 100 may be referred to as a memory system.

The data storage device 100 may be manufactured in any one of various types of storage devices according to a host interface, which means a transfer protocol with the host device. For example, the data storage device 100 may be a solid state drive (SSD), an MMC, an eMMC, an RS-MMC, a multimedia card in the form of a micro-MMC, A storage device in the form of a personal computer memory card international association (PCMCIA) card, a peripheral component interconnection (PCI) device, A storage device in the form of a card, a storage device in the form of a PCI-E (PCI Express) card, a CF (compact flash) card, a smart media card, a memory stick, It can be composed of one.

The data storage device 100 may be manufactured in any one of various types of package types. For example, the data storage device 100 may be a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi chip package (MCP), a chip on board (COB) level fabricated package, a wafer-level stack package (WSP), and the like.

The data storage device 100 may include a controller 200. The controller 200 may include a control unit 210 and a random access memory 220.

The control unit 210 may include a micro control unit (MCU) and a central processing unit (CPU). The control unit 210 can process the request transmitted from the host apparatus. The control unit 210 drives an instruction or algorithm in the form of a code loaded into the random access memory 220 to process the request, that is, the firmware FW, The memory device 300 can be controlled.

Random access memory 220 may be configured with a random access memory such as dynamic random access memory (DRAM) or static random access memory (SRAM). The random access memory 220 may store firmware FW that is driven by the control unit 210. [ In addition, the random access memory 220 may store data, for example, metadata necessary for driving the firmware FW. That is, the random access memory 220 may operate as a working memory of the control unit 210.

Non-volatile memory device 300 may include memory cell region 310. The memory cell region 310 includes a plurality of memory blocks B1 to Bm and each of the memory blocks B1 to Bm may include a plurality of pages P1 to Pn. The memory cells included in the memory cell region 310 may be configured in a hierarchical memory cell set or a memory cell unit in terms of operation or in terms of physical (or structural) view. For example, memory cells connected to the same word line and being read and written at the same time (or written) can be composed of pages P. Hereinafter, for convenience of explanation, the memory cells constituted by the page P will be referred to as " pages ". Also, the memory cells to be deleted at the same time may be constituted by the memory block (B).

Referring to Figures 1 and 2, a non-volatile memory device 300 according to an embodiment of the present invention includes a plurality of memory cells, a buffer 370 configured to store data to be written to a page of memory cells, a buffer 370, A fail bit counter 380 configured to count fail bits among data stored in the cache memory, and a status information determination unit 390 configured to determine a risk of a page based on the counted number of fail bits.

The data storage device 100 may be configured to store data provided from an external device in response to a write request of the external device. At this time, a write command of the controller 200 can be transferred to the nonvolatile memory device 300, and the data to be written can be temporarily stored in the buffer 370 and then written to the page to be written. The buffer 370 may be located within the non-volatile memory device 300.

On the other hand, the erased memory cell may store, for example, " 1 ". Therefore, among the data temporarily stored in the buffer 370, " 1 " may not be substantially written to the memory cell. The memory cell to which " 1 " is to be written is substantially write inhibited and can maintain the state.

On the other hand, of the data stored in the buffer 370,? 0 "can be substantially written to the memory cell. The memory cell to be written to? 0" can receive the write voltage more than once to store? 0 " stored in the buffer may be changed to " 1 ", so that the write voltage is no longer applied to the memory cell when the memory cell stores " 0 ". At this time, 0 " is not stored until the write voltage is applied a predetermined number of times, for example, until the write voltage is applied a predetermined number of times, the write operation for the memory cell has failed and the buffer 370 maintains & Therefore, in the present invention, even after the write operation is completed, bits remaining as " 0 " in the data stored in the buffer 370 can be defined as fail bits.

FIG. 3A is a table showing an example of setting a chunk unit for counting a fail bit, FIG. 3B is a table illustrating an example of a fail bit number setting as a criterion for determining a state of each chunk, A table for exemplarily showing a setting for judging a risk.

3A to 3C, the fail bit counter 380 according to the embodiment of the present invention can count fail bits in units of chunks. At this time, the status information determination unit 390 counts the number of fail bits The risk of each of the chunks included in the page can be determined. Further, the risk judgment criterion can be set according to the control of the external apparatus, and the criterion for judging the risk can be set or changed in advance.

The chunk unit counted as shown in FIG. 3A may be arbitrarily set so as to correspond to the chunk unit of the ECC engine used in the controller 200. By counting the fail bits in chunks, the number of fail bits in each chunk can be grasped, and the reliability can be improved because the fail bit of the entire page can be quickly identified as a specific chunk.

Referring to FIG. 3B, the controller 200 can set the number of fail bits, that is, the criterion for the risk, which is a criterion for state determination for each chunk. The established risk criteria may be transmitted to the non-volatile memory device 300, and thus the number of fail bits may be counted in the non-volatile memory device 300 to determine the risk.

Referring to FIG. 3C, the risk information determined by the state information determination unit 390 can be set. (N) when the counted fail bit is not present (L) when the counted number of fail bits is less than the risk standard (H) when the number of counted fail bits is more than the risk standard Can be judged.

It is a matter of course that the set values shown in Figs. 3A to 3C are exemplary according to the embodiment of the present invention, and the set values can be changed at any time.

In addition, the status information determination unit 390 according to the embodiment of the present invention can determine and output not only the above-described risk information but also whether or not the page is erased and the page is stored.

Referring again to FIG. 2, a data storage device 100 according to an embodiment of the present invention includes a nonvolatile memory device 300 including a plurality of memory cells and a write command To the non-volatile memory device, wherein the non-volatile memory device is capable of performing a write operation and a page risk determination operation in response to a write command, The controller 200 may output a write command so that the data is written to the page of the second memory cells when the risk is equal to or higher than the criterion.

In addition, the non-volatile memory device 300 according to the embodiment of the present invention may include a buffer 370 configured to store data, The fail bit of the data stored in the back buffer 370 may be counted and the risk of the page may be determined based on the count of the counted fail bits. In addition, the non-volatile memory device 300 according to the embodiment of the present invention can count the fail bits in chunk units and determine the risk of each of the chunks included in the page based on the counted number of fail bits .

As described above, the data storage device 100 according to the embodiment of the present invention can determine the number of fail bits and the risk level for each chunk unit. When counting the fail bits in chunks, the controller 200 can send the address corresponding to the selected chunk to the non-volatile memory device 300 and receive the risk of the selected chunk. The risk of any chunk that is determined by the risk information can be determined by the order in which the risk is transmitted. For example, if the result of the risk assessment is 8 bytes, the first byte may be a value corresponding to the leftmost chunk of the page, and the eighth byte may be a value corresponding to the rightmost chunk of the page, It is possible to change the setting at any time.

In addition, the data storage device 100 according to the embodiment of the present invention can receive the risk of all the chunks of the page, and in this case, only the address corresponding to the chunk (for example, the leftmost chunk) To the non-volatile memory device 300.

FIG. 4 and FIG. 5 are flowcharts illustrating exemplary operation methods of a data storage device according to an embodiment of the present invention.

4 and 5, a method of operating a data storage device according to an exemplary embodiment of the present invention includes a step (S110) in which a controller outputs a first write command, and a nonvolatile memory device responds to a first write command A step S120 of determining a risk of a page on which data is written, and a step S130 of determining a page on which data is to be written based on the risk. The step of determining the risk (S120) may include the step of counting fail bits (S121) in the buffer where the data is temporarily stored and the step of determining the risk (S122) based on the number of counted fail bits .

In the operation method of the data storage device according to the embodiment of the present invention, the step of determining a page to which data is to be written (S130) may be such that when the risk level of the determined page is equal to or greater than a criterion, It is possible to output the second write command, and when the risk of the judged page is less than the judgment standard, the data written in the judged page can be maintained. The step of counting the fail bits may include counting fail bits in chunks (not shown), and determining the risk may include determining a risk of chunks based on the counted number of fail bits can do. In addition, the number of fail bits, which is a criterion of the degree of risk, can be set or changed in advance in the same manner as the operation method of the nonvolatile memory device.

FIG. 6 is a diagram illustrating a result of judging the degree of risk for each chunk by way of example.

The step (S122) of determining the risk of the page among the operation methods of the data storage device according to the embodiment of the present invention includes the step of, when any one of at least one of the chunks included in the page is greater than or equal to the determination reference, The risk of the page may be judged to be more than the criterion.

Referring to FIG. 6, it is assumed that the exemplary chunk unit setting in FIG. 3A is set to 0010. That is, one page can be divided into four chunks. At this time, if only one chunk (the second to the left chunk) of the four chunks included in the page to be written as shown in FIG. 6 has fail bit or more than the risk criterion, the remaining three chunks are the fail bit The page may be judged to be more than the risk judgment criterion. When the above-described judgment information is transmitted to the controller, the controller can output the write command again so that the data to be written is written to a page other than the page to be written. In this case, the above-described risk judgment operation can be performed again on the chunks of the new page.

The method of operating the data storage device according to the embodiment of the present invention may include a step (not shown) in which the controller transmits an address corresponding to a chunk in which the risk judgment is required to the nonvolatile memory device.

7 is a flowchart illustrating an exemplary method of operating a data storage device according to an embodiment of the present invention.

Referring to FIG. 7, a method of operating a data storage device according to an exemplary embodiment of the present invention includes a step S100 of setting a unit of a chunk in which a controller counts fail bits in a non-volatile memory device, (S100), and the number of fail bits, which is a unit of a chunk to which fail bits are to be counted or a risk judgment reference, may be set or changed in advance.

8 is an exemplary illustration of a data processing system including a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 8, the data processing system 1000 may include a host device 1100 and a solid state drive 1200 (hereinafter referred to as SSD).

SSD 1200 may include a controller 1210, a buffer memory device 1220, nonvolatile memory devices 1231 through 123n, a power supply 1240, a signal connector 1250, and a power connector 1260 .

The controller 1210 can control all operations of the SSD 1200. The controller 1210 may include a host interface unit 1211, a control unit 1212, a random access memory 1213, an error correction code (ECC) unit 1214 and a memory interface unit 1215.

The host interface unit 1211 can exchange the signal SGL with the host apparatus 1100 through the signal connector 1250. [ Here, the signal SGL may include a command, an address, data, and the like. The host interface unit 1211 can interface the host device 1100 and the SSD 1200 according to the protocol of the host device 1100. [ For example, the host interface unit 1211 may be a secure digital, universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA) A parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI), a PCI- storage, and the like. < RTI ID = 0.0 > [0035] < / RTI >

The control unit 1212 can analyze and process the signal SGL input from the host apparatus 1100. [ The control unit 1212 may control the operation of the internal functional blocks according to firmware or software for driving the SSD 1200. The random access memory 1213 can be used as an operation memory for driving such firmware or software.

An error correction code (ECC) unit 1214 may generate parity data of the data to be transmitted to the non-volatile memory devices 1231 to 123n. The generated parity data may be stored in the nonvolatile memory devices 1231 to 123n together with the data. An error correction code (ECC) unit 1214 can detect errors in data read from the nonvolatile memory devices 1231 to 123n based on the parity data. If the detected error is within the correction range, the error correction code (ECC) unit 1214 can correct the detected error.

The memory interface unit 1215 can provide a control signal such as a command and an address to the nonvolatile memory devices 1231 to 123n under the control of the control unit 1212. [ The memory interface unit 1215 can exchange data with the nonvolatile memory devices 1231 to 123n under the control of the control unit 1212. [ For example, the memory interface unit 1215 may provide the data stored in the buffer memory device 1220 to the non-volatile memory devices 1231 to 123n, or may read the data read from the non-volatile memory devices 1231 to 123n into the buffer To the memory device 1220.

The buffer memory device 1220 may temporarily store data to be stored in the nonvolatile memory devices 1231 to 123n. In addition, the buffer memory device 1220 may temporarily store data read from the non-volatile memory devices 1231 to 123n. The data temporarily stored in the buffer memory device 1220 can be transferred to the host device 1100 or the nonvolatile memory devices 1231 to 123n under the control of the controller 1210. [

The nonvolatile memory devices 1231 to 123n may be used as a storage medium of the SSD 1200. Each of the nonvolatile memory devices 1231 to 123n may be connected to the controller 1210 through a plurality of channels CH1 to CHn. One channel may be coupled to one or more non-volatile memory devices. Non-volatile memory devices connected to one channel may be connected to the same signal bus and data bus.

The power supply 1240 may provide the power supply PWR input through the power supply connector 1260 to the SSD 1200. Power supply 1240 may include an auxiliary power supply 1241. The auxiliary power supply 1241 can supply power to the SSD 1200 so that the SSD 1200 can be normally terminated when a sudden power off occurs. The auxiliary power supply 1241 may include large-capacity capacitors.

The signal connector 1250 may be formed of various types of connectors according to the interface method of the host device 1100 and the SSD 1200.

The power supply connector 1260 may be formed of various types of connectors according to the power supply method of the host apparatus 1100.

9 is an exemplary diagram illustrating a data processing system including a data storage device in accordance with an embodiment of the present invention. Referring to FIG. 9, the data processing system 2000 may include a host device 2100 and a data storage device 2200.

The host device 2100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 2100 may include internal functional blocks for performing the functions of the host device.

The host device 2100 may include an access terminal 2110 such as a socket, slot, or connector. The data storage device 2200 may be mounted on the connection terminal 2110.

The data storage device 2200 may be configured in the form of a substrate such as a printed circuit board. The data storage device 2200 may be referred to as a memory module or a memory card. Data storage device 2200 may include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 through 2232, a power management integrated circuit (PMIC) 2240, and an access terminal 2250 .

The controller 2210 can control all operations of the data storage device 2200. The controller 2210 may be configured in the same manner as the controller 1210 shown in Fig.

The buffer memory device 2220 may temporarily store data to be stored in the non-volatile memory devices 2231 to 2232. In addition, the buffer memory device 2220 may temporarily store data read from the non-volatile memory devices 2231 to 2232. The data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the nonvolatile memory devices 2231 to 2232 under the control of the controller 2210. [

The non-volatile memory devices 2231 to 2232 can be used as a storage medium of the data storage device 2200.

The PMIC 2240 can provide the power input through the connection terminal 2250 to the inside of the data storage device 2200. The PMIC 2240 can manage the power of the data storage device 2200 under the control of the controller 2210. [

The connection terminal 2250 can be connected to the connection terminal 2110 of the host device. A signal such as a command, an address, data, or the like and power can be transmitted between the host device 2100 and the data storage device 2200 through the connection terminal 2250. [ The connection terminal 2250 may be configured in various forms according to the interface manner of the host device 2100 and the data storage device 2200. The connection terminal 2250 may be located on either side of the data storage device 2200.

10 is an exemplary illustration of a data processing system including a data storage device in accordance with an embodiment of the present invention. Referring to FIG. 10, the data processing system 3000 may include a host device 3100 and a data storage device 3200.

The host device 3100 may be configured in the form of a board such as a printed circuit board. Although not shown, the host device 3100 may include internal functional blocks for performing the functions of the host device.

The data storage device 3200 may be configured as a surface mount package. The data storage device 3200 may be mounted to the host device 3100 via a solder ball 3250. [ The data storage device 3200 may include a controller 3210, a buffer memory device 3220, and a non-volatile memory device 3230.

The controller 3210 can control all operations of the data storage device 3200. The controller 3210 may be configured the same as the controller 1210 shown in Fig.

The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory device 3230. [ In addition, the buffer memory device 3220 may temporarily store data read from the non-volatile memory devices 3230. Data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the nonvolatile memory device 3230 under the control of the controller 3210. [

The non-volatile memory device 3230 may be used as the storage medium of the data storage device 3200. [

11 is an exemplary diagram illustrating a network system including a data storage device according to an embodiment of the present invention. 11, the network system 4000 may include a server system 4300 and a plurality of client systems 4410 to 4430 connected through a network 4500.

The server system 4300 can service data in response to requests from a plurality of client systems 4410-4430. For example, server system 4300 may store data provided from a plurality of client systems 4410-4430. As another example, the server system 4300 may provide data to a plurality of client systems 4410-4430.

The server system 4300 may include a host device 4100 and a data storage device 4200. The data storage device 4200 may be comprised of the data storage device 100 of FIG. 2, the SSD 1200 of FIG. 8, the data storage device 2200 of FIG. 9, and the data storage device 3200 of FIG.

12 is a block diagram exemplarily showing a nonvolatile memory device included in a data storage device according to an embodiment of the present invention. 12, a non-volatile memory device 300 includes a memory cell array 310, a row decoder 320, a data read / write block 330, a column decoder 340, a voltage generator 350, (360).

The memory cell array 310 may include memory cells MC arranged in regions where the word lines WL1 to WLm and the bit lines BL1 to BLn cross each other.

The row decoder 320 may be coupled to the memory cell array 310 via word lines WL1 through WLm. The row decoder 320 may operate under the control of the control logic 360. The row decoder 320 may decode an address provided from an external device (not shown). The row decoder 320 can select and drive the word lines WL1 to WLm based on the decoding result. Illustratively, row decoder 320 may provide the word line voltages provided from voltage generator 350 to word lines WLl through WLm.

The data read / write block 330 may be coupled to the memory cell array 310 through the bit lines BL1 to BLn. The data read / write block 330 may include read / write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn, respectively. The data read / write block 330 may operate under the control of the control logic 360. The data read / write block 330 may operate as a write driver or as a sense amplifier, depending on the mode of operation. For example, the data read / write block 330 may operate as a write driver that stores data provided from an external device in the memory cell array 310 during a write operation. As another example, the data read / write block 330 may operate as a sense amplifier that reads data from the memory cell array 310 during a read operation.

The column decoder 340 may operate under the control of the control logic 360. The column decoder 340 may decode the address provided from the external device. The column decoder 340 decodes the read / write circuits RW1 to RWn of the data read / write block 330 corresponding to the bit lines BL1 to BLn and the data input / output line Buffer) can be connected.

Voltage generator 350 may generate a voltage used for internal operation of non-volatile memory device 300. [ Voltages generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. [ For example, the write voltage generated in the write operation may be applied to the word line of the memory cells in which the write operation is to be performed. As another example, the erase voltage generated in the erase operation may be applied to the well-area of the memory cells where the erase operation is to be performed. As another example, the read voltage generated in the read operation may be applied to the word line of the memory cells in which the read operation is to be performed.

The control logic 360 can control all operations of the nonvolatile memory device 300 based on control signals provided from an external device. For example, control logic 360 may control the read, write, and erase operations of non-volatile memory device 300.

With respect to the method according to the embodiment of the present invention, the contents of the above-described apparatus can be applied. Therefore, the description of the same contents as those of the above-mentioned apparatus has been omitted in connection with the method.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. It will be appreciated that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention.

100: Data storage device
200: controller
210: Control unit
220: Random access memory
300: Nonvolatile memory device
310: memory cell array
370: buffer
380: Fail-over counter
390:

Claims (22)

A plurality of memory cells;
A buffer configured to store data to be written to a page of the memory cells;
A fail bit counter configured to count fail bits of the data stored in the buffer; And
And a status information determination unit configured to determine a risk of the page based on the number of fail bits counted. The method according to claim 1,
Wherein the fail bits are bits remaining at a predetermined value of the data stored in the buffer after a write operation has been performed on the page. The method according to claim 1,
The fail bit counter counts fail bits in chunks,
Wherein the state information determination unit determines a risk of each of the chunks included in the page based on the number of the counted fail bits. The method according to claim 1,
Wherein the state information determination unit sets the criterion for the risk according to the control of the external device. A non-volatile memory device including a plurality of memory cells; And
And a controller configured to output a write command of data to be written to a page of the first memory cells to the nonvolatile memory device,
Wherein the nonvolatile memory device performs a write operation and a risk judgment operation of the page in response to the write command, transmits the risk of the page to the controller,
Wherein the controller outputs a write command such that the data is written to a page of the second memory cells when the risk is equal to or greater than a criterion. 6. The method of claim 5,
Wherein the non-volatile memory device further comprises a buffer configured to store the data, wherein the non-volatile memory device counts fail bits of the data stored in the buffer after a write operation and, based on the number of fail bits, A data storage device for determining the risk. The method according to claim 6,
Wherein the fail bits are bits remaining at a predetermined value of the data stored in the buffer after a write operation is performed on the page. The method according to claim 6,
Wherein the non-volatile memory device counts fail bits in chunks and determines the risk of each of the chunks included in the page based on the number of failed fail bits. 9. The method of claim 8,
The controller comprising:
Transferring an address corresponding to the selected chunk to the non-volatile memory device, and receiving a risk of the selected chunk. 9. The method of claim 8,
Wherein the controller sets the chunk unit in the nonvolatile memory device. 9. The method of claim 8,
Wherein the controller sets the number of fail bits, which is a criterion for determining a risk level, in the non-volatile memory device. The controller outputting a first write command;
Wherein the non-volatile memory device is responsive to the first write command to determine a risk of a page on which data is written; And
And the controller determining a page on which the data is to be written based on the risk. 13. The method of claim 12,
The step of determining the risk includes:
Counting the fail bits in the buffer where the data is temporarily stored; And
And determining the risk based on the number of failing bits counted. 14. The method of claim 13,
Wherein the fail bits are bits remaining in a predetermined value of the data stored in the buffer after a write operation is performed. 13. The method of claim 12,
Further comprising the step of the controller setting the number of fail bits in the non-volatile memory device as a criterion of the risk. 13. The method of claim 12,
The step of determining a page to which the data is to be written,
Outputs a second write command so that the data is written to a page other than the determined page when the risk of the judged page is equal to or greater than a criterion,
And when the risk of the determined page is less than the determination criterion, the data written to the determined page is held. 14. The method of claim 13,
Wherein counting the fail bits comprises counting fail bits in chunks,
Wherein the determining the risk comprises determining a risk of each of the chunks based on the counted number of fail bits. 18. The method of claim 17,
Further comprising the step of the controller setting a criterion for the risk to the non-volatile memory device. 18. The method of claim 17,
The step of determining the risk of the page comprises:
Wherein when the risk of at least one of the chunks included in the page is equal to or greater than a criterion, the risk of the page including the chunk exceeding the criterion is determined to be equal to or greater than a criterion. 18. The method of claim 17,
Further comprising the step of the controller transmitting an address corresponding to a chunk in which the risk judgment is required to the nonvolatile memory device. 18. The method of claim 17,
Wherein the controller is further configured to set a unit of chunks in which the fail bits are to be counted. 18. The method of claim 17,
Further comprising the step of the controller setting a number of fail bits in the non-volatile memory device that is a criterion for determining a risk level.

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