KR20190030463A - Memory system and operating method thereof - Google Patents

Abstract

According to the present invention, disclosed are a memory system and an operation method thereof capable of increasing performance of the memory system. The memory system comprises: a plurality of memory block groups; memory blocks individually included in the memory block groups; a memory block group management unit allocating life cycles different from each other to each of the memory block groups and organizing the memory block groups in a chain in order of the life cycles; a life cycle prediction unit predicting a life cycle of data and selecting any one of the memory block groups based on the prediction; and a recording control unit recording the data in the selected memory block group.

Description

[0001] The present invention relates to a memory system and an operating method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory system and an operation method thereof, and more particularly, to a method for variably controlling a memory block according to a life cycle of data.

Memory devices are classified as volatile memory devices and non-volatile memory devices. In a volatile memory device, data is not retained when power is removed. However, in the nonvolatile memory device, data is retained even if power is removed. Examples of non-volatile memory devices include read only memory (ROM), or electrically erasable programmable read-only memory (EEPROM).

The structure and operation of a flash memory device introduced as a flash EEPROM are different from those of a conventional EEPROM. The flash memory device may perform an electric erase operation on a block basis and perform a program operation on a bit basis.

The flash memory device may perform a garbage collection operation to obtain a free memory block. Such a garbage collection operation may degrade the performance of the flash memory device. Therefore, there is a growing demand for a technique that can efficiently perform the garbage collection operation.

Embodiments of the present invention provide a method of operating a memory system that can improve the performance of a memory system.

A memory system according to an embodiment of the present invention includes: a plurality of memory block groups; Memory blocks included in each of the plurality of memory block groups; A memory block group management unit allocating different life cycles to each of the plurality of memory block groups and configuring the plurality of memory block groups in a chain in the order of the life cycle; A life cycle prediction unit configured to predict a life cycle of data and select one of the plurality of memory block groups based on the prediction; And a write control unit configured to write the data into the selected memory block group.

A method of operating a memory system according to an embodiment of the present invention includes: receiving data; A prediction step of predicting a life cycle through pattern analysis of the data; Selecting a first memory block group corresponding to the predicted life cycle of the data among a plurality of memory block groups; An allocation step of extracting a memory block included in a second memory block group to which a life cycle different from the first memory block group is allocated and assigning the memory block to the first memory block group; And a storing step of storing the data in the memory block.

A memory system according to an embodiment of the present invention includes first to Nth memory block groups to which first to Nth (N is a natural number equal to or more than 3) life cycles are sequentially allocated, respectively; A memory block group management unit configured to sequentially connect the first to Nth memory block groups in a daisy chain; A life cycle prediction unit configured to predict a life cycle of data and to select any one of the first to Nth memory block groups based on the prediction; And a write control unit configured to write the data into the selected memory block group when the erase memory block included in the selected memory block group is exhausted, Period.

This technique can improve the performance of the memory system by variably controlling the memory block according to the life cycle of the data.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.
2 is a diagram for explaining the memory controller of FIG.
3 is a diagram for explaining the memory device of FIG.
FIG. 4 is a diagram for explaining the memory block of FIG. 3. FIG.
5 is a view for explaining a memory block group according to an embodiment of the present invention.
6 is a diagram for explaining a memory controller according to an embodiment of the present invention.
7 is a diagram for explaining a memory block group management method according to an embodiment of the present invention.
8 is a view for explaining a memory block group management method according to another embodiment of the present invention.
9 is a diagram for explaining a memory block group management method according to another embodiment of the present invention.
FIG. 10 is a diagram for explaining a memory block group management method according to another embodiment of the present invention.
11 is a diagram for explaining a method of managing a memory block group according to another embodiment of the present invention.
12 is a flowchart illustrating a method of managing a memory block group according to an embodiment of the present invention.
13 is a flowchart illustrating a method of managing a memory block group according to another embodiment of the present invention.
FIG. 14 is a flowchart illustrating a configuration of group metadata according to an embodiment of the present invention.
15 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.
16 is a diagram for explaining another embodiment of the memory system including the memory controller shown in FIG.
17 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.
18 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.

1, a memory system 1000 includes a memory device 1100 for storing data, a memory controller 1100 for controlling the memory device 1100 under the control of a host 2000, A memory controller 1200, and the like.

The host 2000 may be connected to the memory 2000 using an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA) And can communicate with the system 1000. In addition, the interface protocols between the host 2000 and the memory system 1000 are not limited to the above-described examples. For example, USB (Universal Serial Bus), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI) Drive Electronics) and the like.

The memory controller 1200 controls the overall operation of the memory system 1000 and can control the exchange of data between the host 2000 and the memory device 1100. For example, the memory controller 1200 may control the memory device 1100 in response to a request from the host 2000 to program or read data. In addition, the memory controller 1200 stores information on main memory blocks and sub memory blocks included in the memory device 1100, and performs program operation on a main memory block or a sub memory block according to the amount of data loaded for the program operation The memory device 1100 may be selected to perform. According to an embodiment, the memory device 1100 may be a DDR SDRAM, a Low Power Double Data Rate (SDRAM) SDRAM, a GDDR (Graphics Double Data Rate) SDRAM, a LPDDR (Low Power DDR) A Rambus Dynamic Random Access Memory (RDRAM) or a FLASH memory.

The memory device 1100 may perform a program, read, or erase operation under the control of the memory controller 1200. [

2 is a diagram for explaining the memory controller of FIG.

2, the memory controller 1200 includes a processor 710, a memory buffer 720, an error correcting unit (ECC) 730, a host interface 740, A buffer control circuit 750, a memory interface 760, a data randomizer 770, and a bus 780.

The bus 780 may be configured to provide a channel between components of the memory controller 1200.

The processor unit 710 controls all operations of the memory controller 1200 and can perform logical operations. The processor unit 710 may communicate with the external host 2000 via the host interface 740 and with the memory device 1100 via the memory interface 760. [ The processor unit 710 can communicate with the memory buffer unit 720 through the buffer control unit 750. [ The processor unit 710 may control the operation of the memory system 1000 by using the memory buffer unit 720 as an operation memory, a cache memory, or a buffer memory.

The processor unit 710 may queue a plurality of commands input from the host 2000. This operation is called a multi-queue. At this time, the queued command may be called a tag. The processor unit 710 may sequentially transmit a plurality of queued tags to the memory device 1100. The processor unit 710 may also change the order of the plurality of queued tags and transmit them to the memory device 1100. In other words, the processor unit 710 may utilize various methods such as prioritization or cross-referencing in order to efficiently process a plurality of queued tags.

The memory buffer unit 720 may be used as an operation memory, a cache memory, or a buffer memory of the processor unit 710. The memory buffer unit 720 may store codes and commands executed by the processor unit 710. The memory buffer unit 720 may store data processed by the processor unit 710. The memory buffer unit 720 may include SRAM (Static RAM) or DRAM (Dynamic RAM).

The error correction unit 730 can perform error correction. Error correction unit 730 may perform error correction encoding (ECC encoding) based on data to be written to memory device 1100 via memory interface 760. [ The error correction encoded data may be passed to the memory device 1100 via the memory interface 760. Error correction unit 730 may perform error correction decoding (ECC decoding) on data received from memory device 1100 via memory interface 760. [ Illustratively, error correction 730 may be included in memory interface 760 as a component of memory interface 760.

The host interface 740 is configured to communicate with an external host 2000 under the control of the processor unit 710. The host interface 740 may be any one of a Universal Serial Bus (USB), a Serial AT Attachment (SAS), a Serial Attached SCSI (SAS), a High Speed Interchip (HSIC), a Small Computer System Interface (SCSI), a Peripheral Component Interconnection (PCI Express), Nonvolatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC, Dual In-line Memory Module (DIMM) (DIMM), a Load Reduced DIMM (LRDIMM), and the like.

The buffer control unit 750 is configured to control the memory buffer unit 720 under the control of the processor unit 710.

The memory interface 760 is configured to communicate with the memory device 1100 under the control of the processor unit 710. Memory interface 760 may communicate commands, addresses, and data with memory device 1100 over the channel.

Illustratively, the memory controller 1200 may not include the memory buffer unit 720 and the buffer control unit 750.

Illustratively, the processor unit 710 can control the operation of the memory controller 1200 using codes. The processor unit 710 may load the codes from a non-volatile memory device (e.g., Read Only Memory) provided in the memory controller 1200. As another example, the processor portion 710 may load the codes from the memory device 1100 via the memory interface 760. [

A data randomizer 770 may randomize data or de-randomize the randomized data. Data randomizer 770 may perform a data randomization operation on data to be written to memory device 1100 via memory interface 760. [ The randomized data may be transferred to the memory device 1100 via the memory interface 760. Data randomizer 770 may perform a data de-randomization operation on data received from memory device 1100 via memory interface 760. [ Illustratively, the data renderer 770 may be included in the memory interface 760 as a component of the memory interface 760.

Illustratively, the bus 780 of the memory controller 1200 can be divided into a control bus and a data bus. The data bus may transmit data within the memory controller 1200 and the control bus may be configured to transmit control information, such as commands, addresses, within the memory controller 1200. The data bus and the control bus are separated from each other and may not interfere with each other or affect each other. The data bus may be connected to the host interface 740, the buffer control unit 750, the error correction unit 730 and the memory interface 760. The control bus may be connected to the host interface 740, the processor unit 710, the buffer control unit 750, the memory buffer unit 720 and the memory interface 760.

3 is a diagram for explaining the memory device of FIG.

Referring to FIG. 3, a memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 includes a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data, (Not shown). Memory device 1100 may include control logic 300 that controls peripheral circuits 200 under the control of a memory controller (1200 of FIG. 1).

The memory cell array 100 may include a plurality of memory blocks MB1 to MBk 110 (where k is a positive integer). Local lines LL and bit lines BL1 to BLn (where n is a positive integer) may be connected to each of the memory blocks MB1 to MBk 110. [ For example, the local lines LL may include a first select line, a second select line, a plurality of word lines arranged between the first and second select lines word lines. In addition, the local lines LL may include dummy lines arranged between the first select line and the word lines, and between the second select line and the word lines. Here, the first select line may be a source select line, and the second select line may be a drain select line. For example, local lines LL may include word lines, drain and source select lines, and source lines (SL). For example, the local lines LL may further include dummy lines. For example, the local lines LL may further include pipe lines. The local lines LL may be connected to the memory blocks MB1 to MBk 110 respectively and the bit lines BL1 to BLn may be connected to the memory blocks MB1 to MBk 110 in common. The memory blocks MB1 to MBk 110 may be implemented in a two-dimensional or three-dimensional structure. For example, the memory cells in the two-dimensional structure memory blocks 110 may be arranged in a direction parallel to the substrate. For example, in memory blocks 110 of a three-dimensional structure, memory cells may be stacked in a direction perpendicular to the substrate.

The peripheral circuits 200 may be configured to perform the program, read, and erase operations of the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuits 200 supply the verify voltage and the pass voltages to the first select line, the second select line and the word lines under the control of the control logic 300, Select lines and word lines, and verify memory cells connected to a selected one of the word lines. For example, the peripheral circuits 200 may include a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, An input / output circuit 250, and a sensing circuit 260. The input /

The voltage generation circuit 210 may generate various operating voltages Vop used in program, read, and erase operations in response to the operation signal OP_CMD. In addition, the voltage generation circuit 210 may selectively discharge the local lines LL in response to the operation signal OP_CMD. For example, the voltage generating circuit 210 may generate a program voltage, a verify voltage, pass voltages, a turn-on voltage, a read voltage, an erase voltage, and a source line voltage according to the control of the control logic 300.

The row decoder 220 may transmit the operating voltages Vop to the local lines LL connected to the selected memory block 110 in response to the row address RADD.

The page buffer group 230 may include a plurality of page buffers PB1 to PBn 231 connected to the bit lines BL1 to BLn. The page buffers PB1 to PBn 231 may operate in response to the page buffer control signals PBSIGNALS. For example, the page buffers PB1 to PBn 231 may temporarily store data received via the bit lines BL1 to BLn, or may not store the voltages of the bit lines BL1 to BLn Or the current can be sensed.

The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 may exchange data with the page buffers 231 via the data lines DL, or may exchange data with the input / output circuit 250 through the column lines CL .

The input / output circuit 250 transfers the command CMD and the address ADD received from the memory controller 1200 (FIG. 1) to the control logic 300 or the data DATA to / from the column decoder 240 have.

The sensing circuit 260 generates a reference current in response to a permission bit VRY_BIT <#> at the time of a read operation or a verify operation and outputs a sensing voltage VPB) and the reference voltage generated by the reference current to output the pass signal PASS or the fail signal FAIL.

The control logic 300 outputs the operation signal OP_CMD, the row address RADD, the page buffer control signals PBSIGNALS and the permission bit VRY_BIT <# > in response to the command CMD and the address ADD The peripheral circuits 200 can be controlled. In addition, the control logic 300 may determine whether the verify operation has passed or failed in response to the pass or fail signal (PASS or FAIL).

FIG. 4 is a diagram for explaining the memory block of FIG. 3. FIG.

Referring to FIG. 4, the memory block 110 may be connected to a plurality of word lines arranged in parallel to each other between a first select line and a second select line. Here, the first select line may be a source select line (SSL), and the second select line may be a drain select line (DSL). More specifically, the memory block 110 may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be respectively connected to the strings ST and the source line SL may be connected to the strings ST in common. Since the strings ST can be configured to be identical to each other, a string ST connected to the first bit line BL1 will be described in detail, for example.

The string ST includes a source select transistor SST, a plurality of memory cells F1 to F16 and a drain select transistor DST connected in series between the source line SL and the first bit line BL1 . One string ST may include at least one of the source select transistor SST and the drain select transistor DST and the memory cells F1 to F16 may also include more than the number shown in the figure.

The source of the source select transistor SST may be connected to the source line SL and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells F1 to F16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in the different strings ST may be connected to the source select line SSL and the gates of the drain select transistors DST may be connected to the drain select line DSL. And the gates of the memory cells F1 to F16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page (PPG). Accordingly, the memory block 110 may include physical pages PPG as many as the number of the word lines WL1 to WL16.

One memory cell MC can store one bit of data. This is commonly referred to as a single level cell (SLC). In this case, one physical page (PPG) can store one logical page (LPG) data. One logical page (LPG) data may contain as many data bits as the number of cells included in one physical page (PPG). Also, one memory cell MC can store two or more bits of data. This is commonly referred to as a multi-level cell (MLC). In this case, one physical page (PPG) may store two or more logical page (LPG) data.

5 is a view for explaining a memory block group according to an embodiment of the present invention.

Referring to FIG. 5, the memory system 1000 may include first through fourth memory block groups 120, 130, 140, and 150. Each of the memory block groups 120, 130, 140, and 150 may include a plurality of memory blocks 110. The memory block groups 120, 130, 140, and 150 in the memory system 1000 may be less or more than four as shown in FIG. The first to fourth memory block groups 120, 130, 140, and 150 may have the same configuration. However, it shall be named separately for convenience of explanation. Hereinafter, the memory block group may be any one of the first to fourth memory block groups 120, 130, 140, and 150.

Each of the first to fourth memory block groups 120 to 150 may include a plurality of memory blocks 110. 5 is an example in which each of the memory block groups 120, 130, 140, and 150 includes first to fourth memory blocks 110, that is, four memory blocks 110. FIG. The memory blocks 110 in the memory block group are not limited to four as shown in FIG. 5, and may be smaller or more.

The memory controller 1200 may allocate different life times to the first to fourth memory block groups 120 to 150, respectively. In other words, the memory system 1000 allocates the first life cycle to the first memory block group 120, allocates the second life cycle to the second memory block group 130, allocates the second life cycle to the third memory block group 130, And allocate a fourth life cycle to the fourth memory block group 140. In this case, The first to fourth life periods may be different from each other, and may be sequentially increasing values. In other words, a relationship such as "the fourth life cycle> the third life cycle> the second life cycle> the first life cycle" can be established. The life cycle of the memory block 110 may be the life cycle of data stored in the memory block 110. [

The life cycle of the memory block 110 may be the length of time the data stored in the memory block 110 is held. In other words, data that is frequently updated can have a short life cycle, and data that has little update can have a long life cycle. Also, long-lived data may have a long life cycle, and data that is erased after a short period of time may have a short life-cycle. The garbage collection operation can be performed at about the same time for data having a similar life cycle. Therefore, when data having a similar life cycle is stored in the same memory block 110, the garbage collection operation can be efficiently performed.

The memory system 1000 may previously allocate a specific life cycle to each of the memory block groups 120, 130, 140, In other words, the first to fourth memory block groups 120 to 150 may have a predetermined life cycle, and the first to fourth memory block groups 120 to 150 may store data corresponding to each life cycle Can be stored. In addition, the life cycle pre-assigned to each of the first to fourth memory block groups 120 to 150 may be varied during operation of the memory system 1000. This will be described in detail below.

Each of the first to fourth memory block groups 120 to 150 may include first to fourth memory blocks 110. The memory system 1000 may previously allocate a plurality of memory blocks 110 to each of the memory block groups 120, 130, 140, Also, the memory blocks 110 previously allocated to each of the first to fourth memory block groups 120 to 150 may be varied during operation of the memory system 1000. This will be described in detail below.

The first to fourth memory blocks 110 included in each of the first to fourth memory block groups 120 to 150 may have a continuous block number. In other words, the first to fourth memory blocks 110 included in the first memory block group 120 may have block numbers sequentially increasing or decreasing. In addition, the first to fourth memory blocks 110 included in the second memory block group 120 may have block numbers sequentially increasing or decreasing. In this case, the fourth memory block 110 included in the first memory block group 120 and the first memory block 110 included in the second memory block group 130 may have consecutive block numbers. In other words, the first to fourth memory blocks 110 included in the first to fourth memory block groups 120 to 150 may have consecutive block numbers, and the first to fourth memory block groups The sixteen memory blocks 110 included in the memory blocks 120 to 150 may have a continuous block number as a whole.

6 is a diagram for explaining a memory controller according to an embodiment of the present invention.

6, the processor unit 710 of the memory controller 1200 may include a memory block group management unit 721, a life cycle predicting unit 722, a write control unit 723, and a garbage collection control unit 724. [ have. The memory block group management unit 721 may include a group meta management unit 7211. [

The memory block group management unit 721 may be configured to manage the plurality of memory block groups 120, 130, 140, and 150 described with reference to FIG. The memory block group management unit 721 constitutes a plurality of memory block groups 120, 130, 140 and 150 and allocates predetermined different life cycles to the respective memory block groups 120, 130, 140 and 150 can do. In addition, the memory block group management unit 721 can vary the life cycle assigned to each of the memory block groups 120, 130, 140, and 150. In other words, the memory block group management unit 721 allocates the first life cycle to the first memory block group 120, allocates the second life cycle to the second memory block group 130, 140 and assign a fourth life cycle to the fourth memory block group 150. [ Each life cycle may be a range defined by a minimum life cycle value or a maximum life cycle value. Illustratively, the second life cycle may be a life cycle range defined by a first minimum life cycle value and a first maximum life cycle value. The memory block group management unit 721 can manage the first to fourth memory block groups 120 to 150 by connecting them in a chain form. Illustratively, the memory block group management unit 721 can manage the first to fourth memory block groups 120 to 150 by connecting them in a daisy chain form. In other words, the memory block group management unit 721 stores the first memory block group 120, the second memory block group 130, the third memory block group 140, and the fourth memory block group 150, You can assign a period. The memory block group management unit 721 may assign the shortest life cycle to the first memory block group 120 and the longest life cycle to the fourth memory block group 150. [ The life cycles allocated to the first memory block group 120, the second memory block group 130, the third memory block group 140 and the fourth memory block group 150 may be consecutive values. Illustratively, the first life cycle has a range less than the first life cycle value, and the second life cycle can range from the first life cycle value to less than the second life cycle value. Also, the third life cycle may range from the second life cycle value to less than the third life cycle value, and the fourth life cycle may have a range beyond the third life cycle value.

The memory block group management unit 721 may vary the life cycle assigned to each of the memory block groups 120, 130, 140, and 150. In other words, the memory block group management unit 721 can assign a life cycle different from the life cycle previously allocated to each of the memory block groups 120, 130, 140, and 150. The memory block group management unit 721 assigns a first life cycle to the first memory block group 120 and a second life cycle to the second memory block group 130, A third life cycle may be assigned to the group 140, and a fourth life cycle may be assigned to the fourth memory block group 150. [ Then, the memory block group management unit 721 allocates a fourth life cycle to the first memory block group 120, allocates a first life cycle to the second memory block group 130, Assign a second life cycle to the group 140, and assign a third life cycle to the fourth memory block group 150. [ This dynamic lifetime allocation operation of the memory block group management unit 721 allows the garbage collection operation and the wear leveling operation of the memory system 1000 to be performed efficiently. This will be described in detail below.

The memory block group management unit 721 may allocate a plurality of memory blocks 110 to each of the memory block groups 120, 130, 140, The memory block group management unit 721 may dynamically change the memory blocks 110 allocated to the respective memory block groups 120, 130, 140, and 150. This will be described in detail below.

The memory block group management unit 721 may include a group meta management unit 7211. [ The group meta-management unit 7211 may manage group meta data for each of the memory block groups 120, 130, 140, and 150. Illustratively, the group meta data includes a group number of each of the plurality of memory block groups 120, 130, 140 and 150, an erased block count of the erased memory blocks 110, A start block number of the start memory block 110, and a block count of the entire memory blocks 110. This will be described in detail below.

The life cycle prediction unit 722 can be configured to predict the life cycle of the data through pattern analysis of the data. The life cycle of the data may be the update period of the data. In other words, data having a short update period can have a short life period, and data having a long update period can have a long life period. As another example, the life cycle of the data may be the retention period of the data. In other words, data with a long retention period can have a long life cycle, and data with a short retention period can have a short life cycle. Hot data, which is typically accessed frequently, can have a short life cycle, and cold data that has little access can have a long life cycle. A garbage collection operation may be performed at a time similar to that of the memory blocks 110 storing data having a similar life cycle. Therefore, when data having a similar life cycle is stored in the same memory block 110, the garbage collection operation can be efficiently performed.

When the data is received from the host 2000, the life-period predicting unit 722 can perform an operation of predicting a life cycle of the received data. The life cycle prediction unit 722 transfers the life cycle prediction result of the data to the memory block group management unit 721. The memory block group management unit 721 receives the life cycle prediction result from the life cycle prediction unit 722, 130, 140, and 150 based on a plurality of memory block groups. In other words, when the life-period predicting unit 722 predicts that the data received from the host 2000 has a first life-period, the life-period predicting unit 722 determines, based on the life- The memory block group management unit 721 can select the first memory block group 120 to which the first life cycle is allocated.

The write control section 723 can control the data write operation. The write control unit 723 may be configured to write the data received from the host 2000 to the memory block groups 120, 130, 140, and 150 selected by the memory block group management unit 721. [ The write controller 723 controls the write operation of the memory block groups 120, 130, 140 and 150 selected from the memory block group management unit 721 and the selected memory blocks 110 in the selected memory block groups 120, 130, 140, Information can be received. The write control unit 723 can write data to the selected memory block 110 in the selected memory block group 120, 130, 140, 150 based on the information received from the memory block group management unit 721. [

The garbage collection control unit 724 may control a garbage collection operation of the memory system 1000. The garbage collection operation is a process of reading data stored in a plurality of memory blocks 110 and storing the read data in another memory block 110 and erasing the plurality of memory blocks 110 to make new data available for storage Lt; / RTI &gt; In other words, the garbage collection operation is a process of collecting data scattered in N memory blocks 110, copying the data to M memory blocks 110, erasing the N memory blocks 110, , That is, the free memory block 110. Where N and M are natural numbers, and N is a natural number greater than M. The garbage collection control unit 724 may perform a garbage collection operation in units of the memory block groups 120, 130, 140, and 150. In other words, the memory blocks 110 included in the first memory block group 120 are simultaneously subjected to the garbage collection operation, and the memory blocks 110 included in the first memory block group 120 and the second memory The memory blocks 110 included in the block group 130 may not perform the garbage collection operation together. This may be due to the fact that each memory block group 120, 130, 140, 150 has a different life cycle. The update cycle may be more efficient when the garbage collection operation is performed together with similar data. In other words, the operation in which the memory system 1000 stores data having a similar life cycle in the same memory block group 120, 130, 140, 150 can improve the efficiency of the garbage collection operation.

7 is a diagram for explaining a memory block group management method according to an embodiment of the present invention.

Referring to FIG. 7, the processor unit 710 may variably perform a write operation according to a life cycle of data.

The first to fourth life cycles may be assigned to the first to fourth memory block groups 120 to 150 by the memory block group management unit 721. [ In other words, the first to fourth memory block groups 120 to 150 sequentially store data W1 having a first life cycle, data W2 having a second life cycle, data W3 having a third life cycle And data W4 having the fourth life cycle. In this case, the first to fourth life cycles may be sequentially increasing life cycles, the first life cycle may be the shortest life cycle, and the fourth life cycle may be the longest life cycle. Each of the memory block groups 120, 130, 140, and 150 may include four memory blocks 110. The four memory blocks 110 included in each memory block group may have consecutive block numbers. In other words, the four memory blocks 110 of the first memory block group 120, that is, the first memory block 110, the second memory block 110, the third memory block 110, 110 may have the first to fourth block numbers, and the second memory block group 130, the third memory block group 140, and the fourth memory block group 150 may also be the same. At this time, the memory blocks 110 included in the first to fourth memory block groups 120 to 150 may all be in the erased state. In other words, it may be possible to store new data.

Data corresponding to one memory block 110 may be input from the host 2000 in step-1. The life cycle predicting unit 722 performs an operation of predicting the life cycle of the data, and can predict, for example, the data W1 having the first life cycle. The life cycle prediction unit 722 transfers the life cycle prediction result to the memory block group management unit 721. The memory block group management unit 721 receives the prediction result of the first memory block group 120 and the first The first memory block 110 in the memory block group 120 can be selected and the selection result can be transmitted to the write control unit 723. [ The write controller 723 can write the data to the first memory block 110 in the first memory block group 120 (W1) based on the received selection result.

Data corresponding to three memory blocks 110 may be input from the host 2000 in step-2. The life-period predicting unit 722 performs an operation of predicting a life cycle of the data, and can predict, for example, data W2 having a second life cycle. The life cycle prediction unit 722 transfers the life cycle prediction result to the memory block group management unit 721. The memory block group management unit 721 transfers the life cycle prediction result to the second memory block group 130 and the second memory block group management unit 721 based on the prediction result. The first to third memory blocks 110 in the memory block group 130 may be selected and the selection result may be transmitted to the write control unit 723. [ The write controller 723 may write (W2) the data to the first to third memory blocks 110 in the second memory block group 130 based on the received selection result.

8 is a view for explaining a memory block group management method according to another embodiment of the present invention.

Referring to FIG. 8, the memory block group management unit 721 may vary the life cycles allocated to the first to fourth memory block groups 120 to 150. [0064] FIG.

Data corresponding to the three memory blocks 110 may be input from the host 2000 in step-3. The life cycle prediction unit 722 performs an operation of predicting the life cycle of the data and predicts the data with the data W1 having the first life cycle as an example. The life cycle prediction unit 722 transfers the life cycle prediction result to the memory block group management unit 721. The memory block group management unit 721 receives the prediction result of the first memory block group 120 and the first The second to fourth memory blocks 110 in the memory block group 120 may be selected and the selection result may be transmitted to the write control unit 723. [ The write controller 723 may write (W1) data to the second to fourth memory blocks 110 in the first memory block group 120 based on the received selection result.

(W1) operation is performed to all the memory blocks 110 in the first memory block group 120 and the first memory block group 120 is no longer written to the erase (E) memory block 110 ). &Lt; / RTI &gt; When the memory block group management unit 721 determines that the erase (E) memory block 110 in the first memory block group 120 has been exhausted, the memory block groups 120, 130, 140, The order of the chain of the &lt; / RTI &gt; In other words, the memory block group management unit 721 allocates the fourth life cycle by moving the first memory block group 120 and allocates the fourth life cycle to each of the second to fourth memory block groups 130, 140, As a result, a first life cycle is allocated to the second memory block group 130, a second life cycle is allocated to the third memory block group 140, A first life cycle may be assigned to the first memory block 150 and a fourth life cycle may be assigned to the first memory block group 120. [

The memory block group management unit 721 stores the sequence of chains when data write (W) is performed on all the memory blocks 110 included in any one of the plurality of memory block groups 120, 130, 140, and 150 Can be varied. The memory block group management unit 721 also performs a write operation on all the memory blocks 110 of the first memory block group 120 among the plurality of memory block groups 120, The longest life cycle may be allocated to the first memory block group 120 and the life cycles allocated to the remaining memory block groups 130, 140, and 150 may be shifted by one.

9 is a diagram for explaining a memory block group management method according to another embodiment of the present invention.

Referring to FIG. 9, the garbage collection control unit 724 may perform a garbage collection operation on the memory block groups 120, 130, 140, and 150.

A garbage collection operation or an erase operation may be performed on the first memory block group 120 in step-5. The garbage collection control unit 724 can control the garbage collection operation to preferentially perform the garbage collection operation on the memory block groups 120, 130, 140, and 150 having a long lifetime. In FIG. 9, the memory block group having the longest life cycle is the first memory block group 120. Accordingly, the garbage collection control unit 724 may control the first memory block group 120 to perform the garbage collection operation first. As a result of the garbage collection operation, the first memory block group 120 copies the data stored in the second to fourth memory blocks 110 to another memory block 110, and writes the data stored in the second to fourth memory blocks 110 It is possible to perform an erase (E) operation. As a result, the memory block group management unit 721 can select the first memory block group 120 when new data is input.

In other words, the garbage collection control unit 724 may determine the order of garbage collection operations of the memory block groups 120, 130, 140, and 150 based on the length of the life cycle. In other words, the memory block groups 120, 130, 140 and 150 having a long life cycle are controlled so that the garbage collection operations are performed first, and the memory block groups 120, 130, 140, You can control the collection behavior to be performed. In addition, the garbage collection controller 724 may control the memory blocks 110 included in one memory block group 120, 130, 140, and 150 to perform garbage collection operations together. This is because the memory blocks included in one memory block group 120, 130, 140, and 150 store data having a similar life cycle to each other, so that the time at which the garbage collection operation is performed may be similar.

FIG. 10 is a diagram for explaining a memory block group management method according to another embodiment of the present invention.

Referring to FIG. 10, the number of memory blocks 110 included in each of the memory block groups 120, 130, 140, and 150 may be variably controlled.

Data corresponding to four memory blocks 110 may be input from the host 2000 in step -6. The life cycle prediction unit 722 performs an operation of predicting a life cycle of the data, and can predict the data W3 having the third life cycle as an example. The life cycle prediction unit 722 transfers the life cycle prediction result to the memory block group management unit 721. The memory block group management unit 721 transfers the life cycle prediction result to the memory block group management unit 721, The first to fourth memory blocks 110 in the memory block group 150 may be selected and the selection result may be transmitted to the write control unit 723. [ The write controller 723 may write (W3) the data to the first to fourth memory blocks 110 in the fourth memory block group 150 based on the received selection result.

(W3) operation is performed on all the memory blocks 110 in the fourth memory block group 150 and the fourth memory block group 150 no longer includes the erase (E) memory block I can not. If the memory block group management unit 721 determines in step 7 that the erase E block in the fourth memory block group 150 has been exhausted, The order can be varied. In other words, the memory block group management unit 721 may move the fourth memory block group 150 to allocate a fourth life cycle, and may shift the life cycle of the first memory block group 120 by one time. A third life cycle is assigned to one memory block group 120, a first life cycle is assigned to the second memory block group 130, a second life cycle is assigned to the third memory block group 140, The fourth memory block group 150 may be allocated a fourth life cycle.

Data corresponding to the two memory blocks 110 may be input from the host 2000 in step -8. The life cycle prediction unit 722 performs an operation of predicting the life cycle of the data, and can predict, for example, the data W4 having the fourth life cycle. The life cycle prediction unit 722 transfers the life cycle prediction result to the memory block group management unit 721 and the memory block group management unit 721 can select the fourth memory block group 150 based on the prediction result have. At this time, the fourth memory block group 150 may be in a state where the erase (E) memory block 110 is exhausted. The memory block group management unit 721 deletes the erase (E) memory block 110 in the adjacent memory block groups 120, 130, 140 and 150 when the erase (E) memory block 110 is exhausted to the memory block groups 120, E) memory block 110 may be extracted and allocated to the exhausted memory block groups 120, 130, 140, and 150 by the erase (E) memory block 110. The memory block group management unit 721 verifies that the erase E block 110 has been exhausted to the fourth memory block group 150 and the adjacent memory block group, that is, the first memory block group 120, The third to fourth memory blocks 110 may be extracted and allocated to the fourth memory block group 150. [ The memory block group management unit 721 then reads out and allocates the third to fourth memory blocks 150 extracted from the first memory block group 120 included in the fourth memory block group 150 and the fourth memory block group 150, And may transmit the selection result to the write control unit 723. [ The write controller 723 extracts the data from the first memory block group 120 in the fourth memory block group 150 and writes the data in the third to fourth memory blocks 110 (W4).

In other words, the memory block group management unit 721 determines whether the erase (E) memory block 110 is present in the other memory block groups 120, 130, 140, and 150 when the selected memory block group 120, The E memory block 110 may be extracted and allocated to the selected memory block group 120, 130, 140, 150. Specifically, in other words, the memory block group management unit 721 stores the memory block groups 120, 130, 140 and 150 having the adjacent life periods when there is no erase (E) memory block 110 in the selected memory block groups 120, 130, 140, and 150, and may allocate the erase memory block 110 to the selected memory block group 120, 130, 140,

11 is a diagram for explaining a method of managing a memory block group according to another embodiment of the present invention.

11, the garbage collection controller 724 may sequentially perform a garbage collection operation on a plurality of memory blocks 110 included in one memory block group 120, 130, 140, and 150 .

A garbage collection operation or an erase operation may be performed on the fourth memory block group 150 in step -9. The garbage collection control unit 724 can control the garbage collection operation to preferentially perform the garbage collection operation on the memory block groups 120, 130, 140, and 150 having a long lifetime. In FIG. 11, the memory block groups 120, 130, 140, and 150 having the longest life cycle are the fourth memory block group 150. Accordingly, the garbage collection control unit 724 may control the fourth memory block group 150 to perform the garbage collection operation first. At this time, the garbage collection controller 724 controls the first to fourth memory blocks 110 included in the fourth memory block group 150 to perform a garbage collection operation (first garbage collection operation) first .

An additional garbage collection operation or erase operation may be performed for the fourth memory block group 150 in step -10. The garbage collection controller 724 controls the third to fourth memory blocks 110 (memory blocks in the dotted line) extracted from the first memory block group 120 in the fourth memory block group 150 and allocated to the garbage collection controller 724, To perform a collection operation (a second garbage collection operation).

By the above operation, write (W) operation and erase (E) operations can be performed evenly on the entire plurality of memory blocks 110 included in the memory system 1000. As a result, a wear leveling operation for a plurality of memory blocks 110 included in the memory system 1000 can be easily performed.

12 is a flowchart illustrating a method of managing a memory block group according to an embodiment of the present invention.

12, the memory system 1000 can receive data from the host 2000 (step S1201). Then, a prediction step of predicting the life cycle may be performed through pattern analysis on the data (step S1202). Step S1202 may be performed by the life cycle predicting unit 722. [ (N is a natural number) memory block group 120, 130, 140, 150 corresponding to the predicted life cycle of the data among a plurality of memory block groups 120, 130, 140, 150 after step S1202 is performed, 150) may be performed (step S1203). Step S1203 may be performed by the memory block group management unit 721. [

After step S1203 is performed, the memory block group management unit 721 may determine whether the data can be written to the Nth memory block group 120, 130, 140, and 150 (step S1204) . The memory block group management unit 721 determines whether or not the data can be written to the Nth memory block group 120, 130, 140 and 150 by referring to the Nth memory block group 120, 130, 140, 150 ) To determine whether the erase memory block 110 remains. If it is determined that the data can be written to the Nth memory block group 120, 130, 140, or 150 (corresponding to Yes in FIG. 12), the data is transferred to the Nth memory block group 120 , 140, 150) to the memory block 110 (step S1205). In step S1205, the memory block group management unit 721 writes information on the selected memory block groups 120, 130, 140, and 150 and the selected memory blocks 110 in the selected memory block groups 120, 130, 140, And the write control unit 723 writes the data to the selected memory block 110 included in the Nth memory block group 120, 130, 140, 150 based on the above information .

If it is determined that the data can not be written to the Nth memory block groups 120, 130, 140 and 150 (corresponding to 'NO' in FIG. 12), the Nth memory block groups 120, 130, 140 and 150 Extracting the erase memory block 110 from the (N-1) th memory block group 120, 130, 140, 150 adjacent to the N th memory block group 120, 130, 140, (Step S1206). Step S1206 may be performed by the memory block group management unit 721. [ At this time, the life cycles allocated to the Nth memory block groups 120, 130, 140 and 150 and the life cycles allocated to the (N-1) th memory block groups 120, 130, 140 and 150 may be adjacent to each other . After step S1206 is performed, a step of writing the data to the erase memory block 110 newly allocated to the Nth memory block group 120, 130, 140, and 150 may be performed (step S1207). In step S1207, the memory block group management unit 721 writes information on the selected memory block groups 120, 130, 140, and 150 and the selected memory blocks 110 in the selected memory block groups 120, 130, 140, And the write control unit 723 transfers the data to the newly allocated memory block 110 included in the Nth memory block group 120, 130, 140, 150 based on the above information Can be performed.

13 is a flowchart illustrating a method of managing a memory block group according to another embodiment of the present invention.

Referring to FIG. 13, the memory system 1000 can receive data from the host 2000 (step S1301). Then, a prediction step for predicting a life cycle may be performed through an update period prediction on the data (step S1302). Step S1302 may be performed by the life cycle predicting unit 722. [ The step of selecting the first memory block group 120 corresponding to the predicted life cycle of the data among the plurality of memory block groups 120, 130, 140, 150 after the step S1302 is performed may be performed (Step S1303). Step S1303 may be performed by the memory block group management unit 721. [ After step S1303 is performed, a step of writing data into the first memory block group 120 may be performed (step S1304). The step S1304 transfers the information on the selected first memory block group 120 and the selected memory block 110 in the selected first memory block group 120 to the write control unit 723 by the memory block group management unit 721, The write controller 723 may write the data to the selected memory block 110 included in the first memory block group 120 based on the information.

The memory block group management unit 721 can determine whether the erased memory block 110 exists in the first memory block group 120 (step S1305). If it is determined that there is no erase memory block 110 in the first memory block group 120 (i.e., NO in FIG. 13), the step of moving the first memory block group 120 to the end of the chain (Step S1306). Step S1306 may be performed by the memory block group management unit 721. [ Step S1306 may be the operation of assigning the longest life cycle to the first memory block group 120. [ After step S1306 is performed, a step of shifting the lifetime of the other memory block groups 130, 140, and 150 except for the first memory block group 120 may be performed (step S1307). Step S1307 may be performed by the memory block group management unit 721. [

If it is determined that the erased memory block 110 is present in the first memory block group 120 (i.e., YES in FIG. 13), steps S1306 and S1307 may not be performed.

FIG. 14 is a flowchart illustrating a configuration of group metadata according to an embodiment of the present invention.

Referring to FIG. 14, the group meta-manager 721 may be configured to manage group meta data for a plurality of memory block groups 120, 130, 140, and 150, A group number of each of the plurality of memory block groups 120, 130, 140 and 150, an erased block count of the erase memory blocks 110, a start block of the start memory block 110, number, and the number of all memory blocks 110 (block count).

15 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

15, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device . The memory system 30000 can include a memory device 1100 and a memory controller 1200 that can control the operation of the memory device 1100. The memory controller 1200 may control the data access operation of the memory device 1100 such as a program operation, an erase operation or a read operation under the control of the processor 3100. [

The data programmed into the memory device 1100 may be output through a display (Display) 3200 under the control of the memory controller 1200.

The radio transceiver 3300 can transmit and receive radio signals through the antenna ANT. For example, the wireless transceiver 3300 may change the wireless signal received via the antenna ANT to a signal that can be processed by the processor 3100. Thus, the processor 3100 can process the signal output from the wireless transceiver 3300 and transmit the processed signal to the memory controller 1200 or display 3200. The memory controller 1200 may program the signal processed by the processor 3100 to the semiconductor memory device 1100. [ In addition, the wireless transceiver 3300 may convert the signal output from the processor 3100 into a wireless signal, and output the modified wireless signal to an external device through the antenna ANT. An input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100 and includes a touch pad, A pointing device such as a computer mouse, a keypad, or a keyboard. The processor 3100 is connected to the display 3200 so that data output from the memory controller 1200, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output via the display 3200. [ Can be controlled.

According to an embodiment, a memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as part of the processor 3100 and may also be implemented as a separate chip from the processor 3100.

16 is a diagram for explaining another embodiment of the memory system including the memory controller shown in FIG.

16, the memory system 40000 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant ), A portable multimedia player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling data processing operations of the memory device 1100.

A processor 4100 may output data stored in the memory device 1100 through a display 4300 according to data input through an input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200. [ The memory controller 1200 capable of controlling the operation of the memory device 1100 according to an embodiment may be implemented as part of the processor 4100 or in a separate chip from the processor 4100. [

17 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

17, the memory system 50000 can be implemented as an image processing apparatus, such as a digital camera, a mobile phone with a digital camera, a smart phone with a digital camera, or a tablet PC with a digital camera.

The memory system 50000 includes a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 and the memory device 1100, for example, a program operation, an erase operation, or a read operation.

The image sensor 5200 of the memory system 50000 can convert the optical image into digital signals and the converted digital signals can be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signals may be output via a display 5300 or stored in the semiconductor memory device 1100 through the memory controller 1200. The data stored in the memory device 1100 may also be output via the display 5300 under the control of the processor 5100 or the memory controller 1200. [

The memory controller 1200 capable of controlling the operation of the memory device 1100 according to an embodiment may be implemented as a part of the processor 5100 or in a chip separate from the processor 5100. [

18 is a diagram for explaining another embodiment of the memory system including the memory controller shown in Fig.

Referring to FIG. 18, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

The memory controller 1200 can control the exchange of data between the semiconductor memory device 1100 and the card interface 7100. [ According to an embodiment, the card interface 7100 may be an SD (secure digital) card interface or a multi-media card (MMC) interface, but is not limited thereto.

The card interface 7100 can interface data exchange between the host 2000 and the memory controller 1200 according to the protocol of the host 2000. [ According to the embodiment, the card interface 7100 can support USB (Universal Serial Bus) protocol and IC (InterChip) -USB protocol. Here, the card interface may mean hardware that can support the protocol used by the host 60000, software installed on the hardware, or a signal transmission method.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

1000: memory system 1100: memory device
1200: memory controller 100: memory cell array
200: peripheral circuits 300: control logic

Claims (20)

A plurality of memory block groups;
Memory blocks included in each of the plurality of memory block groups;
A memory block group management unit allocating different life cycles to each of the plurality of memory block groups and configuring the plurality of memory block groups in a chain in the order of the length of the life cycle;
A life cycle prediction unit configured to predict a life cycle of data and select one of the plurality of memory block groups based on the prediction; And
And a write control unit configured to write the data into the selected memory block group.
The method according to claim 1,
Wherein the memory block group management unit is configured to vary the order of the chains when data writing is performed on all of the memory blocks included in any one of the plurality of memory block groups.
The method according to claim 1,
The memory block group management unit is configured to allocate the longest life cycle to the first memory block group when data is written to all the memory blocks of the first memory block group among the plurality of memory block groups &Lt; / RTI &gt;
The method according to claim 1,
Wherein when there is no erase memory block in the selected memory block group, the memory block group manager extracts an erase memory block included in another memory block group and allocates the erase memory block to the selected memory block group.
5. The method of claim 4,
Wherein the life cycle assigned to the other memory block group is a value adjacent to the life cycle assigned to the selected memory block group.
The method according to claim 1,
Wherein the life cycle prediction unit is configured to predict the life cycle through a pattern analysis of the data.
The method according to claim 1,
Wherein the life cycle prediction unit is configured to predict the life cycle based on an update period of the data.
The method according to claim 1,
Wherein the chain has the form of a daisy chain.
The method according to claim 1,
Further comprising a garbage collection controller configured to determine an order of a garbage collection operation of the memory block groups based on the life cycle.
10. The method of claim 9,
Further comprising a group meta-manager configured to manage group metadata for the plurality of memory block groups,
Wherein the group metadata includes at least one of a group number of each of the plurality of memory block groups, a number of erased memory blocks, a block number of the starting memory block, and information on the total number of memory blocks. .
A receiving step of receiving data;
A prediction step of predicting a life cycle of the data through a pattern analysis of the data;
Selecting a first memory block group to which the predicted life cycle of the data is allocated among the plurality of memory block groups;
An allocation step of extracting a memory block included in a second memory block group to which a life cycle different from the first memory block group is allocated and assigning the memory block to the first memory block group; And
And storing the data in the memory block.
12. The method of claim 11,
Wherein the predicting step comprises analyzing an update period of the data.
12. The method of claim 11,
Wherein the allocating step is performed when there is no erase memory block in the first memory block.
14. The method of claim 13,
Wherein among the plurality of memory block groups, the life cycles allocated to the first memory block group and the second memory block group are most similar to each other.
12. The method of claim 11,
Wherein the first memory block group is allocated a longer life cycle than the remaining memory block groups.
12. The method of claim 11,
Performing a garbage collection operation on the memory blocks included in the first memory block group,
Wherein a garbage collection operation is performed on two or more memory blocks among the memory blocks included in the first memory block group.
First to Nth memory block groups to which first to Nth (N is a natural number equal to or more than 3) life cycles are sequentially allocated;
A memory block group management unit configured to sequentially connect the first to Nth memory block groups in a daisy chain;
A life cycle prediction unit configured to predict a life cycle of data and to select any one of the first to Nth memory block groups based on the prediction; And
And a write control unit configured to write the data into the selected memory block group,
And when the erase memory block included in the selected memory block group is exhausted, the memory block group management unit is configured to allocate an Nth life cycle to the selected memory block group.
18. The method of claim 17,
Wherein when the selected memory block group is the first memory block group, the memory block group management unit is configured to shift the life cycles allocated to the second to Nth memory block groups one by one. system.
18. The method of claim 17,
Wherein the life cycle prediction unit is configured to predict the life cycle based on an update period of the data.
18. The method of claim 17,
And a garbage collection controller configured to determine an order of a garbage collection operation for the first to Nth memory block groups based on the length of the life cycle.

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