KR20190024579A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device comprises: a wiring structure; a laminated material located on the wiring structure; channel structures passing through the laminated material; contact plugs electrically connected to the wiring structure through the laminated material; and insulating spacers surrounding the side walls of each of the contact plugs and including loop patterns laminated along the side walls of the contact plugs.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

The present invention relates to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the same.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a two-dimensional non-volatile memory device that forms a memory cell in a single layer on a substrate has reached a limit, a three-dimensional non-volatile memory device that vertically stacks memory cells on a substrate has been proposed.

The three-dimensional nonvolatile memory device includes alternately stacked interlayer insulating films and gate electrodes, channel films passing therethrough, and memory cells are stacked along the channel films. Various structures and fabrication methods have been developed to improve the operational reliability of such a non-volatile memory device having a three-dimensional structure.

An embodiment of the present invention provides a semiconductor device having a structure that is easy to manufacture, stable, and improved, and a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention includes a wiring structure; A stack disposed on the wiring structure; Channel structures passing through the stack; Contact plugs electrically connected to the wiring structure through the laminate; And insulating spacers surrounding the sidewalls of each of the contact plugs and including loop patterns stacked along the sidewalls of the contact plugs.

A semiconductor device according to an embodiment of the present invention includes: a laminate; A plug penetrating the laminate in a lamination direction; And spacers each enclosing the plugs and including loop patterns stacked along the sidewalls of the plugs, wherein neighboring spacers can be interconnected.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a wiring structure; Forming a laminate including the first material layers and the second material layers which are alternately stacked on the wiring structure; Forming first openings through the laminate; Etching a part of the first material films exposed through the first openings to form second openings; Forming insulating spacers including loop patterns located within the second openings, respectively; And forming contact plugs electrically connected to the wiring structure in the first openings.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a laminate; Forming first openings through the laminate; Forming second openings protruding from side walls of the first openings; Forming spacers including loop patterns filling the second openings; And forming plugs in the first openings, wherein the second openings of the neighboring first openings can be interconnected.

A semiconductor device having a stable structure and improved reliability can be provided. Further, in manufacturing the semiconductor device, it is possible to lower the degree of difficulty of the process, simplify the procedure, and reduce the cost.

1A to 1C are views showing a structure of a semiconductor device according to an embodiment of the present invention.
2A to 2D are diagrams showing a structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 2A is a layout and FIGS. 2B to 2D are sectional views taken along line AA 'in FIG. 2A.
3A to 3D are diagrams showing the structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A is a layout and FIGS. 3B to 3D are sectional views taken along AA 'of FIG. 3A.
4A and 4B are views showing a structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 4A is a layout and FIG. 4B is a cross-sectional view taken along line CC 'of FIG. 4A.
5 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.
6 and 7 are layouts showing a structure of a semiconductor device according to an embodiment of the present invention.
8A to 8C are cross-sectional views illustrating a structure of a semiconductor device according to an embodiment of the present invention.
FIGS. 9A to 13A and FIGS. 9B to 13B are layouts and cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
14A to 14C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
15A to 15C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
16 and 17 are block diagrams showing a configuration of a memory system according to an embodiment of the present invention.
18 and 19 are block diagrams showing a configuration of a computing system according to an embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of each drawing, the same constituent elements have the same number as possible even if they are displayed on different drawings.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1A to 1C are views showing a structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a layout, FIG. 1B is a cross-sectional view taken along line A-A 'of FIG. 1A, and FIG. 1C is a cross-sectional view taken along a line B-B' of FIG.

1A to 1C, a semiconductor device according to an embodiment of the present invention includes a stacked body ST, a plurality of plugs and plugs passing through the stacked body ST in the stacking direction, RTI ID = 0.0 > loop patterns. ≪ / RTI > The spacers may further include a connection pattern that surrounds the sidewalls of the plugs and interconnects the connection patterns. Here, the plugs refer to a through structure that partially or entirely passes through the stacked body ST, and may include a semiconductor material, a conductive material, and the like. In one example, the plugs may be contact plugs 13, and the spacers may be insulating spacers 14. The semiconductor device may further include channel structures CH, dummy channel structures D_CH, isolation patterns 18, slit insulating films 19, and the like.

The stacked body ST may include the conductive films 11 and the insulating films 12 alternately stacked. Here, the conductive films 11 may be gate electrodes of memory cells, selection transistors, and the like, and may include a metal such as tungsten. The insulating films 12 are for insulating the stacked conductive films 11 from each other and may include an insulating material such as an oxide.

In one example, the topmost at least one conductive film 11 is an upper select line, the lowermost at least one conductive film 11 is a lower select line, and the remaining conductive films 11 may be a word line. In this case, at least one lower select transistor, a plurality of memory cells and at least one upper select transistor may be connected in series to form a vertical memory string. Here, the upper select transistor may be a drain select transistor, and the lower select transistor may be a source select transistor. Further, a substructure such as a source line, a wiring structure, a peripheral circuit, and the like may be positioned below the laminate ST.

As another example, the topmost at least one conductive film 11 may be a select line, and the lowermost at least one conductive film 11 may be a pipe gate and the remaining conductive films 11 may be a word line. Further, a lower structure such as a wiring structure, a peripheral circuit, and the like may be positioned below the stacked product ST. In this case, at least one first select transistor, a plurality of memory cells, at least one pipe transistor, a plurality of memory cells, and at least one second select transistor may be connected in series to form a memory string arranged in U- . Here, the first selection transistor may be a drain selection transistor and the second selection transistor may be a source selection transistor.

The plurality of channel structures CH may be arranged in a second direction II-II 'intersecting with the first direction I-I' and the first direction I-I '. In addition, the channel structures CH adjacent in the first direction I-I 'may be staggered so that the centers are offset.

The plurality of channel structures CH are for providing a current path of a selection transistor, a memory cell, and the like, and may include semiconductor patterns such as silicon (Si) and germanium (Ge). Each of the channel structures CH includes a channel film 15A and a memory film 16A surrounding the channel film 15A. Here, the channel film 15A has a structure completely filled up to the central region, or has a structure in which the central region is open. When the channel film 15A has an open central region, the channel structure CH may further include a gap fill insulating film 17A formed in the channel film 15A.

The memory film 16A may include at least one of a tunnel insulating film, a data storage film, and a charge blocking film. The data storage film may include a floating gate, a charge trap film, a nano dot, a phase change material film, and the like. In addition, the semiconductor device may further include a memory film 16A 'that surrounds the conductive films 11, respectively. The memory film 16A 'may include at least one of a tunnel insulating film, a data storage film, and a charge blocking film, and may be a charge blocking film containing a high precolumn material.

The dummy channel structures D_CH may be located between the channel structures CH and may be arranged in a line along the second direction II-II '. Further, the dummy channel structures D_CH may have a structure similar to the channel structures CH. For example, each of the dummy channel structures D_CH includes a dummy channel film 15B and a dummy memory film 16B surrounding the dummy channel film 15B. Here, the dummy channel film 15B may include a dummy gap filler insulating film 17B.

The separation pattern 18 is for separating the conductive films 11 of the same level from each other and may have a line shape extended along the second direction II-II '. In addition, the separation pattern 18 may include an insulating material such as an oxide.

The separation pattern 18 may have a depth penetrating partly through the laminate ST. For example, the separation pattern 18 may penetrate at least one conductive film 11 at the top, and the remaining conductive films 11 may have a depth that does not penetrate. Here, the topmost at least one conductive film 11 may be a selected line. Thus, the isolation pattern 18 can penetrate the upper select line, the first select line, the second select line, the source select line, or the drain select line and have a depth that does not penetrate the word line.

The separation pattern 18 may overlap the dummy channel structures D_CH. For example, the isolation pattern 18 may penetrate some depths of the dummy channel structures D_CH.

The slit insulating film 19 is for separating neighboring memory blocks MB from each other and may be located at the boundary of neighboring memory blocks MB. For example, the slit insulating film 19 may have a line shape extending in the second direction (II-II '). In addition, the slit insulating film 19 may include an insulating material such as an oxide film.

The contact plugs 13 penetrate the laminate ST and can be electrically connected to the lower structure located under the laminate ST. For example, the contact plugs 13 are electrically connected to a wiring structure located under the stacked structure ST. In addition, the contact plugs 13 may comprise a conductive material such as polysilicon, metal, or the like.

The contact plugs 13 may be arranged along the second direction II-II '. For example, contact plugs 13 may be located between channel structures CH and aligned to be centered with dummy channel structures D_CH. Further, the contact plugs 13 may be arranged at regular intervals or may be arranged at different intervals. In this figure, the contact plugs 13 are arranged at regular intervals.

In addition, the contact plugs 13 may have cross-sectional shapes similar to or different from the channel structures CH and the dummy channel structures D_CH. For example, the contact plugs 13 may have a circular, elliptical, rectangular, polygonal, or other cross-section. In addition, the contact plugs 13 can have a wider width than the channel structure CH or the dummy channel structure D_CH.

The insulating spacers 14 have a structure that surrounds the contact plugs 13, respectively. Each of the insulating spacers 14 may include loop patterns 14B that surround the sidewalls of the contact plugs 13 and are stacked along the sidewalls of the contact plugs 13. The loop patterns 14B may be located at a level corresponding to the conductive films 11. Each of the insulating spacers 14 may also include a connection pattern 14A that surrounds the sidewalls of the contact plugs 13 and interconnects the loop patterns 14B. The connection pattern 14A can extend in the longitudinal direction of the contact plug 13 or in the stacking direction of the stacked body ST. Here, one insulating spacer 14 may include a plurality of loop patterns 14B, and the loop patterns 14B may be interconnected by a connecting pattern 14A. Therefore, each of the insulating spacers 14 can have a structure in which the loop patterns 14B protrude from the connecting pattern 14A. In addition, the insulating films 12 may be interposed between the stacked loop patterns 14B.

The insulating spacers 14 are for insulating the contact plugs 13 from the conductive films 11 and may include insulating materials such as oxides. In addition, the insulating function of the insulating spacers 14 can be adjusted according to the thickness T2 of the loop patterns 14B.

Each of the insulating spacers 14 includes a first region corresponding to the conductive films 11 and a second region corresponding to the insulating films 12. Here, since the first region directly contacts the conductive films 11, it is necessary to increase the thickness of the first region in order to improve the insulating function. Thus, each of the insulating spacers 14 has loop patterns 14B in a first region in direct contact with the conductive films 11. In this case, the distance between the insulating films 12 and the contact plug 13 is "T1" in the second region but the distance between the conductive films 11 and the contact plug 13 is " . That is, the distance increases by the thickness T2 of the loop pattern 14B. Therefore, the function of the insulating spacers 14 can be improved without increasing the area. For example, the thickness T1 of the connection pattern 14A may be equal to or larger than a half of the thickness of each conductive film 11. [

Here, the loop patterns 14B of neighboring insulating spacers 14 can be interconnected. For example, loop patterns 14B located at the same level can be interconnected. In this case, there are no conductive films 11 between neighboring contact plugs 13, and only insulating films 12 and insulating spacers 14 are present. Therefore, in the region defined between the adjacent contact plugs 13, the loop patterns 14B and the insulating films 12 can be alternately stacked.

In addition, insulating spacers 14 may overlap some of the surrounding films. In one example, the insulating spacers 14 may overlap the dummy channel structures D_CH. In this case, the insulating spacers 14 and the dummy memory film 16B are in contact with each other, the insulating spacers 14 and the dummy channel film 15B are in contact with each other, or the insulating spacers 14 and the dummy gap- . As another example, the insulating spacers 14 may be connected to the separation pattern 18. [ In this case, the insulating spacers 14 mutually insulate the conductive films 11 of the same level together with the separation pattern 18 from each other. That is, the conductive films 11 on both sides can be mutually insulated based on the insulating spacers 14 and the separation pattern 18. Thus, the insulating spacers 14 not only isolate the contact plugs 13 and the conductive films 11 from each other, but also can be used as a slit insulating film.

In addition, the loop patterns 14B in contact with the separation pattern 18 may have a thickness different from that of the remaining loop patterns 14B. For example, the first loop patterns 14B corresponding to the separation patterns 18 have a relatively thin thickness T3, and the second loop patterns 14B corresponding to the conductive films 11 And may have a relatively thick thickness T2. In this case, the second loop patterns 14B have a structure more protruded than the first loop patterns 14B (see FIG. 1B).

2A to 2D are views showing a structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 2A is a layout and FIGS. 2B to 2D are cross-sectional views taken along the line A-A 'in FIG. 2A. Hereinafter, duplicated description will be omitted.

Referring to FIGS. 2A and 2B, the contact plugs 13_1 to 13_4 may be arranged at different intervals. In addition, the insulating spacers 14_1 to 14_4 may be interconnected or separated according to the distance between the contact plugs 13_1 to 13_4.

In one example, the insulation spacers 14_1 / 14_2, 14_3 / 14_4 of the contact plugs 13_1 / 13_2, 13_3 / 13_4 arranged in a relatively narrow space D1 are interconnected, The insulation spacers 14_2 / 14_3 of the contact plugs 13_2 / 13_3 arranged in a matrix can be separated from each other.

As another example, the contact plugs include first to second n contact plugs 13_1 to 13_4, the first to nth insulating spacers 14_1 / 14_2 of the first to nth contact plugs are interconnected, the nth insulating spacer 14_2 of the n contact plug 13_2 and the n + 1 insulating spacer 14_3 of the (n + 1) th contact plug 13_3 are separated from each other and the Th to (2n + 1) th insulating spacers 14_3 / 14_4 of the first through 13_3 / 13_4 may be interconnected. Here, n may be an integer of 2 or more.

A second separation pattern 18B may be additionally disposed between the mutually separated insulating spacers 14_2 / 14_3. In one example, the second separation pattern 18B is located between the contact plugs 13_2 / 13_3 arranged in a relatively wide space D2. As another example, the second separation pattern 18B is positioned between the n-th insulation spacer 14_2 and the (n + 1) -th insulation spacer 14_3. In this case, the first separating pattern 18A, the insulating spacers 14_1 and 14_2, the second separating pattern 18B, and the insulating spacers 14_3 and 14_4 are interconnected to connect the conductive films 11 on both sides to each other It can be insulated.

Also, at least one dummy channel structure (D_CH) may be additionally located between the mutually isolated insulating spacers 14_2 / 14_3. In this case, the dummy channel structure D_CH may overlap with the second separation pattern 18B.

Figs. 2C and 2D show a modification of Fig. 2B. Referring to FIG. 2C, the insulating spacers 14 'include loop patterns 14B that surround the sidewalls of the contact plugs 13, and do not include a connection pattern. The loop patterns 14B are located at the same level as the conductive films 11 and include an insulating material. Therefore, the conductive films 11 and the contact plugs 13 can be mutually insulated by the loop patterns 14B.

2D, the loop patterns 14B have a multilayer structure. The loop patterns 14B may have a structure in which materials having a large mutual etching selectivity are stacked, and at least one of the stacked films may be an insulating film. For example, each of the loop patterns 14B includes a first insulation pattern 14BA and a second insulation pattern 14BB formed in the first insulation pattern 14BA. Here, the second insulation pattern 14BB may include a material having a large etching selection ratio with respect to the first insulation pattern 14BA. For example, the first insulating pattern 14BA may be an oxide film and the second insulating pattern 14BB may be a nitride film.

3A to 3D are views showing a structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A is a layout and FIGS. 3B to 3D are sectional views taken along the line A-A 'of FIG. 3A. Hereinafter, duplicated description will be omitted.

Referring to FIGS. 3A and 3B, the contact plugs 13 are arranged at relatively wide intervals, and the insulating spacers 14 of neighboring contact plugs 13 can be separated from each other. In this case, the conductive film 11 may be interposed between the loop patterns 14B of the insulating spacers 14 separated from each other.

It is also possible that the dielectric films D are interposed between the loop patterns 14B of the insulating spacers 14 separated from each other instead of the conductive film 11. [ Here, the dielectric films D may be a material having a high etching selection ratio with respect to the insulating films 12. For example, the dielectric films D may include a nitride and the insulating films 12 may include an oxide. For reference, the dielectric films (D) may be those in which the sacrificial films used in the manufacturing process remain.

Fig. 3C and Fig. 3D show a modification of Fig. 3B. Referring to FIG. 3C, the insulating spacers 14 'include loop patterns 14B that surround the sidewalls of the contact plugs 13, and do not include a connection pattern. Referring to FIG. 3D, the loop patterns 14B have a multilayer structure. Each of the loop patterns 14B includes a first insulation pattern 14BA and a second insulation pattern 14BB formed in the first insulation pattern 14BA.

4A and 4B are views showing a structure of a semiconductor device according to an embodiment of the present invention, wherein FIG. 4A is a layout and FIG. 4B is a cross-sectional view taken along line C-C 'of FIG. 4A. Hereinafter, duplicated description will be omitted.

4A and 4B, the contact plugs 13 and the insulating spacers 14 may be positioned so as to overlap with the slit insulating film 19. For example, the contact plugs 13 and the insulating spacers 14 may be located at the boundaries of neighboring memory blocks MB and may be located at the boundary of neighboring memory blocks MB, 19). In this case, the insulating spacers 14 are connected to the slit insulating film 19 and may serve to separate the memory blocks MB adjacent to the slit insulating film 19 with each other.

On the other hand, the laminate ST may include a cell region CR and a contact region CT. Here, the cell region CR is a region where memory strings are located, and the contact region CT is an area where an interconnection for driving a select transistor, a memory cell, a pipe transistor, and the like included in the memory string is located. According to this structure, the channel structures CH, dummy channel structures D_CH, and the like described above can be placed in the cell region CR. A contact plug, a wiring, or the like may be placed in the contact area CT of the laminate ST. In addition, the contact area CT of the laminate ST has a structure in which the conductive films 11 can be respectively exposed, and can have a stepped shape.

In addition, the contact region CT includes a first contact region CT1 in which the interconnection of at least one conductive film 11 is located and a second contact region CT2 in which the interconnection of the remaining conductive films 11 is located, ). For example, the pads of the upper select lines may be located in the first contact area CT1 and the pads of the word lines may be located in the second contact area CT2.

According to this structure, the contact plugs 13 and the insulating spacers 14 are located at the boundaries of the neighboring memory blocks MB and are positioned to correspond to the cell regions CR of the stack ST, May be positioned to correspond to the area CT. For example, the contact plugs 13 and the insulating spacers 14 may be positioned corresponding to the first contact area CT1 of the stack ST.

For reference, it is also possible that the contact plugs 13 and the insulating spacers 14 are located inside the memory block MB, as described with reference to Figs. 1A to 3D. In this case, the contact plugs 13 and the insulating spacers 14 may be located in the cell region CR of the stack ST or may be located in the contact region CT of the stack ST.

Although the present embodiment has been described with reference to the case where the contact plugs 13 and the insulating spacers 14 are arranged according to the embodiment described above with reference to Figs. 1A and 1B, the contact plugs 13 and the insulation The arrangement and structure of the spacers 14 can be changed with reference to the embodiments described above with reference to FIGS. 2A to 3D.

5 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention. Hereinafter, duplicated description will be omitted.

Referring to FIG. 5, the contact plugs 13 may be electrically connected to the wiring structures 35 and 36 located under the stacked structure ST. Further, a peripheral circuit is located under the stacked body ST, and the contact plugs 13 can be connected to the peripheral circuit through the wiring structures 35 and 36 through the stacked body ST.

The semiconductor device may include a first substrate 20 located underneath the laminate ST. The first substrate 20 may be a semiconductor substrate and may include pads 21 for electrically connecting the contact plugs 13 with the underlying wiring structures 35 and 36. An insulating film 22 may be interposed between the pad 21 and the first substrate 20 and the pad 21 and the first substrate 20 may be electrically separated from each other by the insulating film 22. [ . It is also possible that the first substrate 20 does not include the pads 21 and the contact plugs 13 penetrate the insulating film 22 and are directly connected to the wiring structures 35 and 36.

The second substrate 30 may be positioned below the first substrate 20. The second substrate 30 may be a semiconductor substrate and the peripheral circuitry may be located on the second substrate 30. The peripheral circuits are circuits for driving the cell array, and may include transistors, switches, resistors, amplifiers, and the like. For example, the transistor TR may include a gate electrode 32, a gate insulating film 31, and a junction 33. In addition, a device isolation film 34 may be disposed in the second substrate 30. [

An interlayer insulating film 37 is positioned between the first substrate 20 and the second substrate 30 and wiring structures 35 and 36 may be located in the interlayer insulating film 37. The wiring structures 35 and 36 may include a wiring 35, a contact plug 36 connected to the wiring 35, and the like. Here, the wirings 35 may be arranged in multiple layers, connected to the gate electrode 32 of the transistor TR, or connected to the junction 33. The contact plugs 36 may interconnect the wirings 35 or may electrically connect the wirings 35 to the junction 33, the gate electrode 32, the pad 21, and the like.

Although the present embodiment has been described with reference to the case where the contact plugs 13 and the insulating spacers 14 have the structure according to the embodiment described with reference to FIGS. 1A and 1B, the contact plugs 13 and The arrangement, structure and the like of the insulating spacers 14 may be changed with reference to the embodiment described above with reference to FIGS. 2A to 3D.

Further, the layout of the contact plugs 13 can be changed according to the layout of the peripheral circuits. For example, the positions, intervals, etc. of the contact plugs 13 can be changed according to the layout of peripheral circuits.

6 and 7 are layouts showing a structure of a semiconductor device according to an embodiment of the present invention.

6 and 7, a semiconductor device according to an embodiment of the present invention includes channel structures CH, dummy channel structures D_CH, first contact plugs 13, insulating spacers 14, The support plugs 41, the support spacers 42, the second contact plugs 43, the separation pattern 18, and the slit insulating film 19.

Here, the channel structures CH, the dummy channel structures D_CH, and the separation pattern 18 may be located in the cell region CR. In addition, the first contact plugs 13, the insulating spacers 14, the support plugs 41, the support spacers 42 and the second contact plugs 43 can be located in the contact area CT And may be dispersedly disposed in the first contact region CT1 and the second contact region CT2.

The support plugs 41 and support spacers 42 serve to support the laminate ST in order to prevent the laminate ST from tilting or collapsing during the manufacturing process. Further, the support spacers 42 located in the first contact region CT1 may be connected to the isolation pattern 18. [ In this case, the conductive films 11 on both sides can be separated from each other by the interconnecting separation pattern 18 and the support spacers 42.

The second contact plugs 43 are for respectively applying a bias to the conductive films 11 included in the laminate ST and can be electrically connected to the conductive films 11, respectively. The second contact plugs 43 can be located in the empty space between the support plugs 41 and the first contact plugs 13. [ For example, the second contact plugs 43 may be located between the insulating spacers 14 and the support spacers 42, or may be located in the recesses of the interconnect spacers 14, (Not shown).

Meanwhile, the arrangement of the support plugs 41 located in the contact area CT, the number of the support spacers 42 connected to each other, and the like can be variously changed.

8A to 8C are cross-sectional views showing the structure of a semiconductor device according to an embodiment of the present invention, and are cross-sectional views showing the structures of the support plugs 41 and support spacers 42. FIG. Hereinafter, duplicated description will be omitted.

8A, the support plugs 41 may have a structure similar to that of the first contact plugs 13, and the support spacers 42 may have a structure similar to the insulating spacers 14. In other words, the support plugs 41 may have a material and structure corresponding to the first contact plugs 13, and the support spacers 42 may have a material and structure corresponding to the insulating spacers 14 . For example, the support plugs 41 may comprise a conductive material such as tungsten, polysilicon, or the like. Further, the support plugs 41 may be a single film or may include a multilayer film.

Each of the support spacers 42 may include loop patterns 42B that surround the support plug 41 and are stacked along the side wall of the support plug 41. [ In addition, each of the support spacers 42 may include a connection pattern 42A that surrounds the side wall of the support plug 41 and connects the loop patterns 42B. Accordingly, each of the support spacers 42 may have a shape in which a plurality of loop pads 42B protrude from the connection pattern 42A. Here, the loop patterns 42B may be located at a level corresponding to the conductive films 11. In addition, neighboring support spacers 42 may be interconnected. For example, loop patterns 42B of neighboring support spacers 42 may be interconnected.

In addition, the loop patterns 42B of the support spacers 42 can be located at the same level as the loop patterns 14B of the insulating spacers 14. [ It is therefore possible for the loop patterns 42B of the support spacers 42 and the loop patterns 14B of the insulating spacers 14 to be interconnected.

The support plugs 41 may have the same height as the first contact plugs 13 or may have different heights. Also, the support plugs 41 and the first contact plugs 13 can be connected to different substructures, respectively. As described above with reference to FIG. 5, the first contact plugs 13 may be connected to a wiring structure located under the stacked structure ST. To this end, the first contact plugs 13 may be electrically connected to the pads 21 of the first substrate 20 or may be directly connected to the wiring structure through the first substrate 20. On the other hand, the support plugs 41 may not penetrate the substrate 20, or may not be connected to the pads 21. It is also possible that the support plugs 41 are connected to the first substrate 20. In this case, no bias may be applied to the support plugs 41, and the support plugs 41 may be used only as a support without an electric role.

Referring to FIG. 8B, the support plugs 41 'and support spacers 42' may have a structure similar to the channel structures CH. For example, each of the support plugs 41 'may include a semiconductor film 41A corresponding to the channel film 15A and an insulating film 41B corresponding to the gap filler insulating film 17A. In addition, each of the support spacers 42 'may have a material and structure corresponding to the memory film 16A. Here, the support plugs 41 'may have a structure not connected to wiring such as a bit line, or may have a structure connected to the first substrate 20.

Although the semiconductor film 41A and the support spacer 42 'are not formed on the bottom surface of the insulating film 41B in the figure, the structure of the semiconductor film 41A and the support spacer 42' It is possible. For example, the semiconductor film 41A may be formed so as to surround the bottom surface of the insulating film 41B, or the support spacer 42 'may be formed to surround the bottom surface of the insulating film 41B, or the semiconductor film 41A and the support spacer 42 'may be formed to surround the bottom surface of the insulating film 41B.

Referring to Fig. 8C, it is also possible that the semiconductor device does not include the support plugs but only the support spacers 42 ". For example, when the opening for the support is narrower than the opening for the contact plug (W2 < W1), the opening is completely filled with the support spacers 42 ". Here, the support spacers 42 " may be formed of a single film or may be formed of a multilayer film.

FIGS. 9A to 13A and FIGS. 9B to 13B are layouts and cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. The a of each number is the layout and the b of each number is a D-D 'cross-sectional view of a degree. Hereinafter, duplicated description will be omitted.

Referring to FIGS. 9A and 9B, a laminate ST including alternately stacked first material films 51 and second material films 52 is formed. Here, the first material films 51 may be for forming gate electrodes of memory cells, selection transistors and the like, and the second material films 52 may be for insulating the stacked gate electrodes from each other.

The first material films 51 are formed of a material having a high etch selectivity with respect to the second material films 52. For example, the first material films 51 may be a sacrifice film including nitride and the like, and the second material films 52 may be an insulating film including an oxide and the like. As another example, the first material films 51 may be a conductive film including polysilicon, tungsten, or the like, and the second material films 52 may be an insulating film including an oxide or the like. As another example, the first material films 51 may be a conductive film including doped polysilicon or the like, and the second material films 52 may be a sacrificial film including undoped polysilicon or the like.

For reference, although not shown in this drawing, a substructure can be formed before forming the laminate ST. For example, the wiring structure described above with reference to FIG. 5B can be formed.

Then, channel structures CH through the stacked body ST are formed. Here, each of the channel structures CH may have the structure described above with reference to FIG. 1C. For example, after forming the channel holes passing through the stacked body ST, the channel structures CH are formed by sequentially forming the memory film, the channel film, and the gap fill insulating film in the channel holes. At this time, it is also possible to form the plug in the recessed region after recessing the cap filler insulating film to some thickness. It is also possible to form the dummy channel structures D_CH together when the channel structures CH are formed.

The channel structures CH are arranged in a first direction I-I 'and a second direction II-II', and dummy channel structures D_CH can be located between the channel structures CH have. At this time, the arrangement of the channel structures CH and the dummy channel structures D_CH can be determined in consideration of the position of the structure to be formed in the subsequent process. For example, in subsequent processes, the channel structures CH and dummy channel structures D_CH may not be formed in the region R where the contact plugs and insulating spacers are to be formed (see FIG. 9A). Of course, the present invention is not limited thereto, and it is also possible to form the channel structures CH and the dummy channel structures D_CH in the region R. [ In this case, the insulating spacers are brought into contact with the channel structures CH or the dummy channel structures D_CH.

For reference, the support plugs 41 and support spacers 42 described above with reference to Figs. 5 and 6 can also be formed together with the channel structures CH. In this case, the support plugs 41 and support spacers 42 may have the structure described with reference to Fig. 8B.

Then, first openings OP1 penetrating the stacked body ST are formed. Here, the first openings OP1 may have a circular, elliptical, quadrangular, or polygonal cross-section, and may have a hole shape. The first openings OP1 are located in the region R and can be arranged with a predetermined distance therebetween. For example, the first openings OP1 may be located between the adjacent channel structures CH in the first direction I-I 'and may be arranged in the second direction II-II' .

In the present embodiment, the first openings OP1 are located in the cell region. However, it is also possible that the first openings OP1 are located in the contact region. Alternatively, it is also possible that the first openings OP1 are located at the boundary between neighboring memory blocks.

Referring to FIGS. 10A and 10B, the first material films 51 exposed through the first openings OP1 are partially etched to form the second openings OP2. At this time, since the first material films 51 are selectively etched, the second openings OP2 are formed so as to protrude from the first openings OP1.

At this time, the second openings OP2 of the neighboring first openings OP1 may be mutually connected or separated according to the etching depth of the first material films 51 or the gap between the first openings OP1 have. For example, the etch depth of the first material films 51 can be adjusted so that the second openings OP2 of the neighboring first openings OP1 are interconnected. In this case, the first material films 51 are relatively etched to interconnect the second openings OP2 located at the same level. As another example, the etching depth of the first material films 51 can be adjusted so that the second openings OP2 of the neighboring first openings OP1 are separated from each other. In this case, the first material films 51 are relatively less etched to separate the second openings OP2 located at the same level from each other. As another example, the distance between the first openings OP1 may be relatively narrowed to interconnect the second openings OP2, or the distance between the first openings OP1 may be relatively broadened, OP2 can be separated from each other.

11A and 11B, insulating spacers 53 are formed to enclose contact plugs 54 and contact plugs 54, respectively. First, an insulating film for a spacer is formed in the first openings OP1 and the second openings OP2. Here, the insulating film for a spacer may be formed along the inner surface of the first openings OP1, filling the second openings OP2. Subsequently, the region formed on the bottom surface of the first openings OP1 in the insulating film for spacers is removed to form the loop patterns 53B in the connection pattern 53A and the second openings OP2 in the first opening OP1 To form insulating spacers (53). Then, contact plugs 54 are formed in the first openings OP1.

For reference, in forming the contact plugs 54 and the insulating spacers 53, the support plugs 41 and the support spacers 42 described above with reference to FIGS. 6 and 7 can be formed together . In this case, the support plugs 41 and support spacers 42 may have the structure described with reference to Fig. 8A.

Referring to Figs. 12A and 12B, a separation pattern 55 partially passing through the laminate ST is formed. For example, a separation pattern 55 is formed at a depth penetrating the topmost at least one first material film 51. The separation pattern 55 may have a line shape extending in the second direction II-II '. Further, the separation pattern 55 may be overlapped with the preformed contact plugs 54 and the insulating spacers 53.

For reference, the case of forming the separation pattern 55 after forming the contact plugs 54 and the insulating spacers 53 has been described in this embodiment, but the process order can be changed. For example, it is also possible to form the contact plugs 54 and the insulating spacers 53 after the separation pattern 55 is formed.

13A and 13B, after the slit SL passing through the stacked body ST is formed, the first material films 51 exposed through the slit SL are removed. At this time, a part of the first material films 51 may remain depending on the distance from the slit SL. For example, the first material films 51 may be removed in a region close to the slit SL, and the first material films 51 may remain in a region far from the slit SL. Therefore, as in the embodiment described with reference to FIG. 3B, the first material films 51 interposed between the loop patterns 53B can be left without being removed.

The first material films 51 may be selectively etched, and the second material films 52 may remain unetched. Thus, the remaining second material films 52 are supported by the preformed vertical structures. The remaining second material layers (e.g., via channel structures CH, dummy channel structures D_CH, support plugs, support spacers, contact plugs 54, insulation spacers 53, etc.) 52 are supported.

Here, in the case of the insulating spacers 53, the loop patterns 53B including the loop patterns 53B are protruded between the remaining second material films 52. Therefore, the loop patterns 53B are interposed between the stacked second material films 52, so that the second material films 52 can be more stably supported.

Then, the conductive films 56 are formed in the regions where the first material films 51 are removed. At this time, it is also possible to further form a memory film in the region from which the first material films 51 are removed, before the conductive films 56 are formed. Then, a slit insulating film 57 is formed in the slit SL.

The process of replacing the first material films 51 with the conductive films 56 may be changed depending on the materials of the first material films 51 and the second material films 52. [ For example, when the first material films 51 are conductive films and the second material films 52 are insulating films, the first material films 51 may be silicided. As another example, when the first material films 51 are the conductive film and the second material films 52 are the sacrificial film, the second material films 52 may be replaced with insulating films.

Meanwhile, in this embodiment, the method of forming the contact plugs and the insulating spacers according to the embodiment described above with reference to FIGS. 1A and 1B has been described. However, the manufacturing method may be variously changed with reference to other embodiments have.

14A to 14C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, duplicated description will be omitted.

Referring to FIG. 14A, a laminate ST including alternately stacked first material films 61 and second material films 62 is formed. Subsequently, after the first openings OP1 penetrating the stacked body ST are formed, the first material films 61 exposed through the first openings OP1 are partially etched to form the second openings OP1, (OP2). At this time, the second openings OP2 of the neighboring first openings OP1 may be mutually connected or mutually separated depending on the etching depth of the first material films 61 or the gap between the first openings OP1 have.

Then, insulating films 63 for spacers are formed in the first openings OP1 and OP2. Here, the insulating films 63 for spacers may be formed along the inner surface of the first openings OP1, filling the second openings OP2. In addition, each insulating film 63 for spacers may include a first region formed in the first opening OP1 and a second region formed in the second openings OP2.

Referring to FIG. 14B, a region formed on the bottom surface of the first openings OP1 of the spacer insulating film 63 is removed. For example, the insulating film 63 for a spacer is etched using a cleaning process and a dry cleaning process. In this case, not only the area formed on the bottom surface of the first openings OP1 but also the area formed along the inner wall of the first openings OP1 can be removed. That is, the first region of the spacer insulating films 63 can be completely removed, and only the second region can be left. Thus, the loop patterns 63A positioned in the second openings OP2 can be formed, respectively.

When the first region of the spacer insulating film 63 is completely removed, the second material films 62 of the stacked body ST2 are exposed. In the process of etching the insulating film 63 for a spacer, 2 material films 62 may also be etched to some thickness. In this case, the thickness T4 of the loop patterns 63A can be reduced.

Referring to FIG. 14C, contact plugs 64 are formed in the first openings OP1. Next, although not shown in the figure, the above-described separation pattern, slit, conductive film, and the like can be formed.

Meanwhile, in this embodiment, the method of forming the contact plugs and the insulating spacers according to the embodiment described with reference to FIGS. 2C and 3C has been described. The manufacturing method may be variously changed with reference to other embodiments have.

15A to 15C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, duplicated description will be omitted.

Referring to FIG. 15A, a laminate ST including alternately stacked first material films 71 and second material films 72 is formed. After the first openings OP1 penetrating the stacked body ST are formed, the first material films 71 exposed through the first openings OP1 are partially etched to form the second openings OP1, (OP2). At this time, the second openings OP2 of the neighboring first openings OP1 may be mutually connected or mutually separated depending on the etching depth of the first material films 71 or the interval between the first openings OP1 have.

Subsequently, first insulating films 73 are formed in the first openings OP1 and OP2. Here, the first insulating films 73 are formed along the inner surfaces of the first openings OP1 and the second openings 73, and are formed to a thickness that does not completely fill the second openings OP2.

Subsequently, second insulating films 74 are formed on the first insulating films 73. Here, the second insulating films 74 are formed in the first openings OP1 and OP2, and may be formed to have a thickness that completely fills the second openings OP2. The second insulating films 74 include a material having a large etch selectivity with respect to the first insulating films 73. For example, the first insulating films 73 may be an oxide film and the second insulating films 74 may be a nitride film.

Referring to FIG. 15B, the second insulating layers 74 are selectively etched to form second insulating patterns 74A. For example, the dry etching process is used to etch regions of the second insulating films 74 formed in the first openings OP1. Through this, second insulating patterns 74B located in the second openings OP2 are formed, respectively.

Referring to FIG. 15C, the first insulating films 73 are etched using the second insulating patterns 74B as an etching barrier. For example, the first insulating films 73 are selectively etched using a wet etching process, a dry cleaning process, or the like. At this time, the regions of the first insulating films 73 formed in the second openings OP2 are protected by the second insulating patterns 74B, and thus remain unetched. Therefore, the first insulation patterns 73A positioned in the second openings OP2 can be formed, respectively. Here, the first insulation patterns 73A each have a shape that surrounds the second insulation patterns 74A. The first insulation pattern 73A and the second insulation pattern 74A formed in the same second opening OP2 constitute one loop pattern 75. [

Then, contact plugs 76 are formed in the first openings OP1. Next, although not shown in the figure, the above-described separation pattern, slit, conductive film, and the like can be formed.

On the other hand, in the present embodiment, the case where the loop pattern 75 is formed of a double film has been described, but it is also possible that the loop pattern has a multilayer structure of a triple film or more. In addition, in this embodiment, a method of forming contact plugs and insulating spacers according to the embodiment described above with reference to FIGS. 2D and 3D has been described. The manufacturing method can be variously changed with reference to other embodiments have.

16 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention.

Referring to FIG. 16, a memory system 1000 according to an embodiment of the present invention includes a memory device 1200 and a controller 1100.

The memory device 1200 is used to store data information having various data types such as text, graphics, software code, and the like. Memory device 1200 may be a non-volatile memory. In addition, the memory device 1200 may have the structure described above with reference to Figs. 1A to 15C, and may be manufactured according to the manufacturing method described with reference to Figs. 1A to 15C. As an example, the memory device 1200 may include a wiring structure; A stack disposed on the wiring structure; Channel structures passing through the stack; Contact plugs electrically connected to the wiring structure through the laminate; And insulating spacers comprising loop patterns of a ring structure surrounding the sidewalls of each of the contact plugs. Since the structure and manufacturing method of the memory device 1200 are the same as those described above, a detailed description thereof will be omitted.

Controller 1100 is coupled to host and memory device 1200 and is configured to access memory device 1200 in response to a request from the host. For example, the controller 1100 is configured to control the reading, writing, erasing, background operation, etc. of the memory device 1200.

The controller 1100 includes a random access memory (RAM) 1110, a central processing unit (CPU) 1120, a host interface 1130, an error correction code circuit 1140, a memory interface 1150 ) And the like.

Here, the RAM 1110 can be used as an operation memory of the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, and the like. For reference, the RAM 1110 may be replaced with a static random access memory (SRAM), a read only memory (ROM), or the like.

The CPU 1120 is configured to control the overall operation of the controller 1100. For example, the CPU 1120 is configured to operate firmware such as a Flash Translation Layer (FTL) stored in the RAM 1110.

The host interface 1130 is configured to perform interfacing with the host. For example, the controller 1100 may be implemented as a Universal Serial Bus (USB) protocol, a MultiMedia Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI- At least one of various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Communicates with the host via one.

The ECC circuit 1140 is configured to detect and correct errors contained in the data read from the memory device 1200 using an error correction code (ECC).

The memory interface 1150 is configured to perform interfacing with the memory device 1200. For example, the memory interface 1150 includes a NAND interface or a NOR interface.

For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. Here, the buffer memory may be used to temporarily store data transferred to the outside via the host interface 1130, or to temporarily store data transferred from the memory device 1200 through the memory interface 1150. Further, the controller 1100 may further include a ROM for storing code data for interfacing with a host.

As such, the memory system 1000 according to an embodiment of the present invention includes the memory device 1200 with improved integration and improved characteristics, so that the integration and characteristics of the memory system 1000 can also be improved.

17 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention. Hereinafter, duplicated description will be omitted.

Referring to FIG. 17, a memory system 1000 'according to an embodiment of the present invention includes a memory device 1200' and a controller 1100. The controller 1100 includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

The memory device 1200 'may be a non-volatile memory. Further, the memory device 1200 'may have the structure described above with reference to Figs. 1A to 15C and may be manufactured according to the manufacturing method described with reference to Figs. 1A to 15C. As an example, the memory device 1200 'may include a wiring structure; A stack disposed on the wiring structure; Channel structures passing through the stack; Contact plugs electrically connected to the wiring structure through the laminate; And insulating spacers comprising loop patterns of a ring structure surrounding the sidewalls of each of the contact plugs. The structure and manufacturing method of the memory device 1200 'are the same as those described above, so that a detailed description thereof will be omitted.

Further, the memory device 1200 'may be a multi-chip package composed of a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups, and the plurality of groups are configured to communicate with the controller 1100 through the first to k-th channels CH1 to CHk. Also, the memory chips belonging to one group are configured to communicate with the controller 1100 over a common channel. For reference, it is also possible that the memory system 1000 'is modified such that one memory chip is connected to one channel.

As such, the memory system 1000 'according to an embodiment of the present invention includes a memory device 1200' with improved integration and improved characteristics, so that the integration and characteristics of the memory system 1000 ' have. In particular, by configuring the memory device 1200 'in a multi-chip package, the data storage capacity of the memory system 1000' can be increased and the driving speed can be improved.

18 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention. Hereinafter, duplicated description will be omitted.

18, a computing system 2000 according to an embodiment of the present invention includes a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus (not shown) 2600).

The memory device 2100 stores data provided through the user interface 2400, data processed by the CPU 2200, and the like. The memory device 2100 is also electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like via the system bus 2600. For example, the memory device 2100 may be connected to the system bus 2600 via a controller (not shown) or may be directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the functions of the controller can be performed by the CPU 2200, the RAM 2300, and the like.

Here, the memory device 2100 may be a non-volatile memory. Further, the memory device 2100 may have the structure described above with reference to Figs. 1A to 15C, and may be manufactured according to the manufacturing method described with reference to Figs. 1A to 15C. As an example, the memory device 2100 may include a wiring structure; A stack disposed on the wiring structure; Channel structures passing through the stack; Contact plugs electrically connected to the wiring structure through the laminate; And insulating spacers comprising loop patterns of a ring structure surrounding the sidewalls of each of the contact plugs. Since the structure and manufacturing method of the memory device 2100 are the same as those described above, a detailed description thereof will be omitted.

Also, the memory device 2100 may be a multi-chip package composed of a plurality of memory chips as described with reference to Fig.

The computing system 2000 having such a configuration may be a computer, an UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box a digital audio recorder, a digital picture recorder, a digital video recorder, a digital video recorder, a digital video recorder, a digital video recorder, a digital video recorder, a picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, One of various electronic devices constituting a work, one of various electronic devices constituting a telematics network, an RFID device, and the like.

As such, the computing system 2000 according to an embodiment of the present invention includes the memory device 2100 with improved integration and improved characteristics, so that the characteristics of the computing system 2000 can also be improved.

19 is a block diagram illustrating a computing system in accordance with one embodiment of the present invention.

19, a computing system 3000 according to an embodiment of the present invention includes a software layer including an operating system 3200, an application 3100, a file system 3300, a transformation layer 3400, and the like. do. In addition, computing system 3000 includes a hardware layer, such as memory device 3500. [

The operating system 3200 is for managing software, hardware resources, and the like of the computing system 3000, and can control program execution of the central processing unit. The application 3100 may be a utility that is executed by the operating system 3200, with various application programs running on the computing system 3000.

The file system 3300 refers to a logical structure for managing data, files, and the like existing in the computing system 3000, and organizes files or data to be stored in the memory device 3500 or the like according to a rule. The file system 3300 may be determined according to the operating system 3200 used in the computing system 3000. For example, if the operating system 3200 is a Microsoft Windows family, the file system 3300 may be a file allocation table (FAT), an NT file system (NTFS), or the like. If the operating system 3200 is a Unix / Linux family, the file system 3300 may be an extended file system (EXT), a unix file system (UFS), a journaling file system (JFS), or the like.

Although the operating system 3200, the application 3100 and the file system 3300 are shown as separate blocks in this figure, the application 3100 and the file system 3300 may be included in the operating system 3200.

The translation layer (3400) translates the address in a form suitable for the memory device (3500) in response to a request from the file system (3300). For example, the translation layer 3400 translates the logical address generated by the file system 3300 into the physical address of the memory device 3500. Here, the mapping information of the logical address and the physical address can be stored in an address translation table. For example, the translation layer 3400 may be a Flash Translation Layer (FTL), a Universal Flash Storage Link Layer (ULL), or the like.

The memory device 3500 may be a non-volatile memory. Further, the memory device 3500 may have the structure described above with reference to Figs. 1A to 15C, and may be manufactured according to the manufacturing method described above with reference to Figs. 1A to 15C. As an example, the memory device 3500 may include a wiring structure; A stack disposed on the wiring structure; Channel structures passing through the stack; Contact plugs electrically connected to the wiring structure through the laminate; And insulating spacers comprising loop patterns of a ring structure surrounding the sidewalls of each of the contact plugs. Since the structure and manufacturing method of the memory device 3500 are the same as those described above, a detailed description thereof will be omitted.

The computing system 3000 having such a configuration can be divided into an operating system layer that is performed in a higher level region and a controller layer that is executed in a lower level region. Here, the application 3100, the operating system 3200 and the file system 3300 are included in the operating system layer and can be driven by the operating memory of the computing system 3000. In addition, the transformation layer 3400 may be included in the operating system layer or may be included in the controller layer.

As such, the computing system 3000 according to an embodiment of the present invention includes the memory device 3500 with improved integration and improved characteristics, so that the characteristics of the computing system 3000 can also be improved.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the embodiments, but it should be noted that the above-described embodiments are for explanation purposes only and not for the purpose of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the technical scope of the present invention.

11: conductive film 12: insulating film
13: contact plug 14: insulated spacer
14a: Connection pattern 14b: Loop pattern
15a: channel film 15b: dummy channel film
16a: memory film 16b: dummy memory film
17a: Gap fill insulator film 17b: Dummy gap fill insulator film
18: Separation pattern 19: Slit insulating film
20: first substrate 21: pad
30: second substrate 31: gate insulating film
32: gate electrode 33: junction
34: Element isolation film 35: Wiring
36: contact plug 41: support plug
42: support spacer 42A: connection pattern
42B: Loop pattern 51: First material film
52: second material film 53: insulating spacer
54: contact plug 55: separation pattern
56: conductive film

Claims (38)

Wiring structure;
A stack disposed on the wiring structure;
Channel structures passing through the stack;
Contact plugs electrically connected to the wiring structure through the laminate; And
An insulating spacers surrounding the sidewalls of the contact plugs and including loop patterns stacked along the sidewalls of the contact plugs,
≪ / RTI >
The method according to claim 1,
Wherein each of the insulating spacers includes a connection pattern that surrounds the sidewalls of the contact plugs and connects the loop patterns
A semiconductor device.
The method according to claim 1,
Each of the loop patterns has a multilayer structure
A semiconductor device.
The method according to claim 1,
Each of the loop patterns comprising:
A first insulation pattern;
And a second insulation pattern formed in the first insulation pattern, the second insulation pattern including a material having a high etching selection ratio with respect to the first insulation pattern
A semiconductor device.
The method according to claim 1,
The loop patterns of neighboring insulating spacers are interconnected
A semiconductor device.
6. The method of claim 5,
The interconnecting loop patterns and the insulating films are alternately stacked between neighboring contact plugs
A semiconductor device.
The method according to claim 1,
The stacked structure includes alternately stacked conductive films and insulating films, and the loop patterns are formed at positions corresponding to the conductive films
A semiconductor device.
The method according to claim 1,
The contact plugs are arranged at different spacings, the insulating spacers of the relatively narrowly arranged contact plugs are interconnected, and the insulating spacers of the relatively wide arrayed contact plugs are mutually isolated
A semiconductor device.
The method according to claim 1,
The contact plugs include first to second contact plugs, and the first to n-th insulating spacers of the first to the n-th contact plugs are interconnected, and the n-th insulating spacer of the n-th contact plug and the The n + 1 th insulating spacers of the plug are mutually separated, the n + 1 th to the 2n th insulating spacers of the n + 1 th to the 2n th contact plugs are interconnected, and the n is an integer of 2 or more
A semiconductor device.
The method according to claim 1,
Further comprising dummy channel structures through said stack,
The dummy channel structures may be formed in a < RTI ID = 0.0 >
A semiconductor device.
The method according to claim 1,
Dummy channel structures passing through the stack; And
A plurality of dummy channel structures and a superimposed separation pattern
Further comprising:
Wherein the insulating spacers and the separation pattern are interconnected
A semiconductor device.
12. The method of claim 11,
And an insulation spacer directly connected to the isolation pattern of the insulation spacers,
First loop patterns in contact with the separation pattern; And
And second loop patterns in contact with the stack,
Wherein the second loop patterns are more protruded than the first loop patterns
A semiconductor device.
The method according to claim 1,
Wherein the channel structures are located in a cell region of the stack and the contact plugs are located between the channel structures
A semiconductor device.
The method according to claim 1,
Wherein the channel structures are located in a cell region of the stack and the contact plugs are located in a contact region of the stack
A semiconductor device.
The method according to claim 1,
Further comprising slit insulating films extending in one direction through the laminate,
Wherein the insulating spacers are formed to overlap with the slit insulating films
A semiconductor device.
The method according to claim 1,
Support plugs passing through the stack; And
A support pattern including a connection pattern surrounding the side wall of each of the support plugs and loop patterns protruding from the connection pattern,
Further comprising:
Laminate;
A plug penetrating the laminate in a lamination direction; And
Spacers each enclosing the plugs and including loop patterns stacked along the sidewalls of the plugs,
Loop patterns of neighboring spacers are interconnected
A semiconductor device.
18. The method of claim 17,
Each of said spacers including a connection pattern that surrounds the sidewalls of said plugs and connects said loop patterns
A semiconductor device.
18. The method of claim 17,
A peripheral circuit located at a lower portion of the stack and electrically connected to the plugs,
Further comprising:
Forming a wiring structure;
Forming a laminate including the first material layers and the second material layers which are alternately stacked on the wiring structure;
Forming first openings through the laminate;
Etching a part of the first material films exposed through the first openings to form second openings;
Forming insulating spacers including loop patterns located within the second openings, respectively; And
Forming, in the first openings, contact plugs electrically connected to the interconnect structure
Wherein the semiconductor device is a semiconductor device.
21. The method of claim 20,
Wherein forming the insulating spacers comprises:
And forming insulating spacers including the loop patterns filling the second openings and the connection pattern in the first openings
A method of manufacturing a semiconductor device.
21. The method of claim 20,
Wherein forming the insulating spacers comprises:
Forming an insulating film in the first and second openings; And
Etching the insulating film by a dry cleaning process to form the loop patterns to fill the second openings, respectively
A method of manufacturing a semiconductor device.
21. The method of claim 20,
Wherein forming the insulating spacers comprises:
Forming a first insulating film in the first and second openings;
Forming second insulating patterns located within the second openings, respectively; And
And etching the first insulating film with the second insulating patterns with an etching barrier to form first insulating patterns respectively positioned in the second openings
A method of manufacturing a semiconductor device.

21. The method of claim 20,
Wherein forming the second openings comprises:
The etch depth of the first material layers is adjusted so that the neighboring first openings are interconnected
A method of manufacturing a semiconductor device.
21. The method of claim 20,
Wherein forming the second openings comprises:
The etch depth of the first material layers is adjusted so that the neighboring first openings are separated from each other
A method of manufacturing a semiconductor device.
21. The method of claim 20,
Further comprising the step of penetrating the laminate to some extent and forming a separation pattern extending in one direction,
The separation pattern is connected to the insulation spacers
A method of manufacturing a semiconductor device.
21. The method of claim 20,
Forming channel structures through the stack;
Forming dummy channel structures through the stack; And
Forming a separation pattern extending in one direction and partially overlapping the laminate and overlapping the inter-dummy channel structures
Further comprising the steps of:
28. The method of claim 27,
The dummy channel structures may be formed in a < RTI ID = 0.0 >
Wherein the method comprises the steps of:
21. The method of claim 20,
Forming support plugs through the stack; And
Forming support spacers that each wrap the support plugs
Further comprising:
The support plugs are formed together in the formation of the contact plugs, and the support spacers are formed together in the formation of the insulating spacers
A method of manufacturing a semiconductor device.
30. The method of claim 29,
Each of the support spacers,
A connection pattern surrounding the sidewalls of each of the support plugs and loop patterns protruding from the connection pattern,
A method of manufacturing a semiconductor device.
21. The method of claim 20,
Forming slit insulating films extending in one direction through the laminate
Further comprising:
Wherein the insulating spacers are formed to overlap with the slit insulating films
A method of manufacturing a semiconductor device.
Forming a laminate;
Forming first openings through the laminate;
Forming second openings protruding from side walls of the first openings;
Forming spacers including loop patterns filling the second openings; And
Forming plugs in the first openings
Lt; / RTI >
The second openings of the neighboring first openings are interconnected
A method of manufacturing a semiconductor device.
33. The method of claim 32,
Wherein forming the spacers comprises:
And forming insulating spacers including the loop patterns filling the second openings and the connection pattern in the first openings
A method of manufacturing a semiconductor device.
33. The method of claim 32,
Wherein forming the spacers comprises:
Forming an insulating film in the first and second openings; And
Etching the insulating film by a dry cleaning process to form the loop patterns to fill the second openings, respectively
A method of manufacturing a semiconductor device.
33. The method of claim 32,
Wherein forming the spacers comprises:
Forming a first insulating film in the first and second openings;
Forming second insulating patterns located within the second openings, respectively; And
And etching the first insulating film with the second insulating patterns with an etching barrier to form first insulating patterns respectively positioned in the second openings
A method of manufacturing a semiconductor device.
33. The method of claim 32,
The laminate includes first material layers and second material layers which are alternately stacked, and the second openings are formed by selectively etching the first material layers exposed through the first openings
A method of manufacturing a semiconductor device.
33. The method of claim 32,
Before forming the laminate, a step of forming a wiring structure
Further comprising:
The plugs are contact plugs electrically connected to the wiring structure
A method of manufacturing a semiconductor device.
33. The method of claim 32,
The loop patterns of neighboring spacers are interconnected
A method of manufacturing a semiconductor device.

Images