KR20190013151A - Multi-thread Based Big Image Display Acceleration Method - Google Patents

Abstract

According to an embodiment, the present invention relates to a large-capacity display acceleration system using multiple threads, which comprises: a chip image storage unit storing an image of a chip; a memory including a hash table indicating the position of the chip image, which is divided in a lattice structure based on the size of resolution of the screen, with a matrix number and a file pointer, and a visible image buffer storing image data of a part to be displayed on the screen by a user from the chip image; and a control unit including a display coordinate determination module determining the position of the part to be displayed on the screen by the user from the chip image, based on the hash table, and a buffer process control module controlling the image data, which corresponds to the position of the part to be displayed on the screen determined by the display coordinate determination module, to be stored in the visible image buffer. Therefore, the large-capacity display acceleration system can quickly display a large-capacity chip image.

Description

[0001] Multi-thread Based Big Image Display Acceleration Method [

The present invention relates to a large capacity image display acceleration system, and more particularly, to a large capacity image display acceleration system and method for processing a large capacity chip image.

The CAD software that supports the design while exchanging data with the user interactively provides a graphical user interface by default. Generally, the data used in the semiconductor design are C code, Verilog code, EDIF format file, GDSII format file, and the like, which are pure text data or coordinate data represented by pictures. In addition, CAD tools that directly use large amounts of image data are used only by reverse engineering CAD software.

However, since the reverse engineering CAD software is used only as a special purpose to monitor technology abuse of other companies, only a few countries have only a few products developed with their own technology. As a result, only the reverse engineering CAD software itself is provided, only the reverse engineering design service is provided, and only the service that leases the reverse engineering CAD software with the expensive license exists, and the implementation technology of the reverse engineering CAD software is a small number It is not exposed to the outside as assets.

In the prior art, when the reverse engineering CAD software is used in the process of extracting an electronic circuit from a large-capacity chip image obtained by attaching images obtained by enlarging a surface image of a chip, which is obtained by decapsulating a package, by a microscope, Therefore, not only can not all be put in the computer memory, but the processing speed is slow and it is impossible for the user to manually extract the circuit.

The present invention has been devised in order to meet the above-mentioned demand, and the present invention is a patent relating to chip image processing of CAD software for reverse engineering, which extracts electronic circuits in the background of a multi-layer large capacity chip image. In particular, the present invention is a technology applied to reverse engineering CAD software for extracting electronic circuits from a large-capacity chip image obtained by attaching images obtained by enlarging a surface image of a chip, which is obtained by decapsulating a package, by a microscope. Since the chip image is large in size, it is impossible to mount the entire chip image in the computer memory. If it is inconvenient for the user to extract the electronic circuit in real time because the image processing speed deteriorates even if it is possible, a hidden image buffer, a hash table, We propose a new algorithm to accelerate image display processing.

According to the present invention, since only a necessary portion of image data is read without dividing a large chip image into a matrix grid and scanning a whole chip image through a hash table mapping a grid matrix number, a file pointer and image coordinates, It can speed up.

According to an embodiment of the present invention, there is provided a system for accelerating a large image display using a multithread, comprising: a chip image storage unit for storing a chip image; A hash table in which a position on the chip image when the chip image is divided into a grid structure based on a resolution size of a screen is represented by a matrix number and a file pointer, and a hash table in which a user wants to display an image A memory including a visible image buffer for storing data; And a display coordinate determination module that determines a position of a portion of the chip image that the user intends to display on the screen based on the hash table and a display coordinate determination module that determines image coordinates of the image data corresponding to the position of the portion to be displayed on the screen determined by the display coordinate determination module And a buffer process control module for controlling to store the image data in the visible image buffer.

In this case, the memory further includes an invisible image buffer storing image data of an area adjacent to the visible image buffer, and a predicted image buffer storing image data of an area neighboring the invisible image buffer, Further comprising a user movement prediction module for predicting a direction in which the user moves in accordance with the statistical recording of the screen movement direction of the user, wherein the image data of the area neighboring the visible image buffer is stored in the invisible image buffer , And control to store the invisible image buffer and the image data arranged adjacent to the moving direction in the predictive image buffer.

Also, the control unit controls the multi-threaded image processing system to perform parallel processing, and the multithreaded processor copies the image data of the invisible image buffer into the visible image buffer, or the image of the predictive image buffer A buffer copy process of copying data into the invisible image buffer or copying the image data of the visible image buffer into the invisible image buffer; And a buffer reading process of reading image data at a position determined based on the hash table and storing the image data in either the visible image buffer, the invisible image buffer, or the predicted image buffer.

Also, the multithread may be configured such that the buffer copy process has priority over the buffer read process.

In addition, the buffer reading process may further include, when reading image data corresponding to an area neighboring the moving direction of the user most recently executed in the visible image buffer, the invisible image buffer, or the predictive image buffer, . ≪ / RTI >

In addition, the total number of threads executed in parallel in the multithread may be configured to be determined by the number of cores that can be operated on by the processor.

In addition, the number of matrix numbers mapped according to the enlargement or reduction ratio of the area to be displayed among the chip images may be changed.

Meanwhile, a method for accelerating a large-capacity image display using multithread according to the present invention is a method for accelerating a large-capacity image display using a multithread, wherein a position on the chip image when a chip image is divided into a grid structure based on a resolution size of a screen is represented by a hash Storing as a table; Determining a position of a portion of the chip image that the user wants to display on the screen based on the hash table; Storing image data corresponding to a position of a portion to be displayed on a screen determined in the determining step in a visible image buffer; And displaying the image stored in the visible image buffer.

In this case, a method for accelerating a large image display using a multithread includes storing image data of an area neighboring the visible image buffer in an invisible image buffer; Estimating a direction in which the user moves according to the statistical recording of the screen movement direction of the user; And storing the image data of the area neighboring in the moving direction predicted in the predicting step in the invisible image buffer in the predictive image buffer.

Also, a method for accelerating a large image display using a multithread may include copying the image data of the invisible image buffer to the visible image buffer, copying the image data of the predictive image buffer to the invisible image buffer, A buffer copy step of copying the image data of the image data into the invisible image buffer; And a buffer reading step of reading image data at a position determined based on the hash table and storing the image data in either the visible image buffer, the invisible image buffer, or the predicted image buffer, The read phase can be handled in parallel through multiple threads.

In addition, the buffer copying step may have priority over the multithreading step than the buffer reading step.

In addition, the buffer reading step may include, when reading image data corresponding to a region neighboring the moving direction of the user most recently executed in the visible image buffer, the invisible image buffer, or the predictive image buffer, . ≪ / RTI >

Also, the total number of threads in the multithread may be determined by the number of cores that can be operated on by the processor.

In the hash table, the number of matrix numbers mapped according to the enlargement or reduction ratio of the area to be displayed among the chip images may be changed.

The large-capacity image display acceleration system using the multithread according to the present invention divides a large-capacity chip image into a matrix grid, and through a hash table mapping a grid matrix number, a file pointer and an image coordinate of the entire chip image, The memory capacity is limited so that the entire chip image can not be mounted in the computer memory or the image processing speed is greatly reduced.

Further, the function of displaying an image can be normally executed irrespective of the performance of the computer or the performance of the image processing of the user is slowed down. Of course, the scope of the present invention is not limited by these effects.

1 is a block diagram of a multi-threaded large image display acceleration system in accordance with an embodiment of the present invention.
2 is a view for explaining a large-capacity image display acceleration system using a multithread according to an embodiment of the present invention.
3 is a block diagram of a process performed in a multi-thread according to an embodiment of the present invention.
4 is a flow diagram of multi-threaded process priority according to an embodiment of the present invention.
5 is a flowchart illustrating a method of accelerating a large-capacity image display using a multithread according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, Is provided to fully inform the user. In addition, for convenience of explanation, components may be exaggerated or reduced in size.

However, it should be understood that the following embodiments are provided so that those skilled in the art will be able to fully understand the present invention, and that various modifications may be made without departing from the scope of the present invention. It is not.

1 is a block diagram of a multi-threaded large image display acceleration system in accordance with an embodiment of the present invention.

Referring to FIG. 1, a large-capacity image display acceleration system 100 according to the present invention may include a control unit 110, a memory 130, and a chip image storage unit 140.

In this case, the control unit 110 may include a display coordinate determination module 113, a user movement prediction module 115, and a buffer process control module 117.

The control unit and the module according to the present invention may be implemented in various forms such as a software program executed on the processor or a hardware module using the dedicated logic circuit.

The display coordinate determination module 113 divides the large-capacity chip image into a grid structure based on the display screen size, acquires the grid matrix number, maps pointers of image data corresponding to the obtained matrix number, (230) in the hash table. In this case, the storage of the hash table 230 may be performed only once in the initial execution.

In addition, when the user tries to display at least a part of the chip image on the screen, the portion to be displayed of the entire chip image is determined based on the hash table 230 and the virtual image buffer, the non-virtual image buffers, And determines the image data to be stored in the buffer.

The user movement prediction module 115 predicts in advance whether the user wants to move the chip image 200 viewed from the computer screen in the left or right direction or the up and down direction and determines whether or not the portion adjacent to the image data stored in the invisible image buffer 215 on the chip image Can be prepared as predicted image data.

For example, the user movement prediction module 115 controls the upper portion of the chip image stored in the invisible image upper buffer on the chip image to be stored in the prediction image buffer as an image on the chip when the user is predicted to move to the top .

In this case, the user movement prediction module 115 can determine the number of prediction image buffers 218 according to the extra memory capacity.

In addition, the user movement prediction module 115 can predict the movement of the user based on the movement record statistics of the user. For example, if the user moves statistically to the right, the right portion of the chip image stored in the non-hypothetical image right buffer can be stored as the predicted image in the predicted image buffer 118. Therefore, the moving speed can be increased when the user actually moves the chip image to the right side as expected.

Or the user movement prediction module 115 may predict the moving direction of the user based on the direction in which the user has recently moved.

In addition, when the user moves the chip image 100 on the computer screen evenly, the image buffer 118 can evenly store upper, lower, left, and right images of the chip image stored in the invisible image buffer.

Buffer process control module 117 may control the process associated with the buffer to be performed in multithreaded 220 on the processor. For example, the process associated with the buffer may include a buffer read process 223 and a buffer copy process 225. On the other hand, the memory 130 may be a device that displays the chip image, for example, Volatile memory. In addition, the chip image storage module 140 may be a non-volatile memory such as a hard disk, for example, a large-capacity storage device capable of storing the entire chip image 200. [

2 is a view for explaining the operation of the multi-threaded large image display acceleration apparatus according to the embodiment of the present invention.

Referring to FIG. 2, the display coordinate determination module 113 divides the entire chip image 200 into a grid structure composed of rows and columns, with the screen resolution size of the display as a basic unit. Here, the display coordinate determination module 113 does not actually divide the entire chip image 200 into a grid size, but divides it into a grid structure in order to obtain information necessary for constructing the hash table 230.

In this case, the hash table 230 is a table in which the position information of the corresponding area is stored on the entire chip image when the size of the resolution of the screen on which the entire chip image is displayed is divided by the basic unit. In this case, the hash table 230 may store the pointer of the chip image data corresponding to the matrix number of the above-mentioned lattice matrix.

In the present invention, the visible image buffer and the non-visible image buffer store image data based on the corresponding hash table 230.

For example, the chip image 200 is stored as a file, and according to the prior art, the image data corresponding to an arbitrary grid has to be scanned from the beginning to be read. However, if the entire chip image 200 is divided into the matrix lattice structure and the position information of the corresponding matrix lattice is stored in the hash table 230 as in the present invention, the chip image data of the corresponding lattice position And can be read independently, which can significantly increase the speed of reading data.

The image buffer 210 may include a visible image buffer 213, an invisible image buffer 215, and a predicted image buffer 218. In this case, the image buffer 210 may store a plurality of pieces of image data having the same size as the computer screen resolution.

Here, the visible image buffer 213 may store image data displayed on a computer screen, and the data stored in the visible image buffer 113 may be directly displayed on a computer screen.

The invisible image buffer 115 may store images that can be placed immediately adjacent to the top, bottom, left, and right of the visual image buffer 113. [ For example, the invisible image buffer 215 can read and store the chip image 200 data, utilizing the available computing resources while the user proceeds on circuit extraction operations on the current image. Because of this, the use of the invisible image buffer 215 is handled in the background, and the user's circuit extraction manipulation does not utilize a large amount of computing resources and may not interfere with the user's work.

In addition, although the invisible image buffer 215 is stored in the memory and hidden, the invisible image buffer 215 may be displayed on the computer screen when moving to the visible image buffer 213. Thus, in preparation for movement of the chip image 200 displayed on the computer screen You can prepare in advance.

The predictive image buffer 218 predicts the screen movement of the user and can generate predictive image data corresponding to the direction in which the user moves.

The predictive image buffer 218 predicts the case where the user moves the chip image 200 viewed from the computer screen in the horizontal direction or the vertical direction and predicts the predicted image data adjacent to the invisible image buffer 215 can do.

For example, the predictive image buffer 218 may include a predictive image buffer 218, which may be located at the right side of the invisible image right buffer, the left side of the invisible image left buffer, the upper side of the invisible image upper buffer , It can be placed underneath the invisible image lower buffer. In this specification, the term " buffer " is interpreted to mean that the buffer stores the image data corresponding to the position of the corresponding grid on the hash table 230 corresponding to the position designated by the user on the entire chip image do.

The term " neighboring region " in this specification means an area corresponding to image data to be displayed next when a user selects a direction.

In addition, the number of prediction image buffers 218 may be determined by computer memory capacity, e.g., the location at which the prediction image buffer 218 is located may be determined by the user's movement history statistics.

Another aspect of the present invention is that it is possible to parallelize the buffer read process and the buffer copy process occurring in the buffer using the multithread 220. [

For example, the multithread 220 can process the entire chip image 200 by reading the image data of the area to be displayed by the user, converting the size and position information, and then storing the size and position information in the image buffer 210 have. At this time, the total number of threads executed in parallel in the multi-thread 220 can generate the same number of threads as the number of multi-cores existing in the processor.

The buffer copy process 223 is a process of copying image data between image buffers.

For example, when the chip image 200 on the computer screen moves to the right, the buffer copy process 223 copies the data stored in the image buffer 200 adjacent to the left side as image data stored in the image buffer 110 as it is Thus, the copying of the data existing in the memory can be performed without reading the data from the file, thereby speeding up the processing speed.

The buffer read process 225 may read the image data stored in the partial grid mapped by the hash table 230 in the entire chip image 200 and store the image data in the image buffer 210.

The buffer read process 225 may also read data from the file, determine the image interval using the hash table 230, and perform image reduction or enlargement calculations.

In addition, the buffer read process 225 can process the image buffer 210 corresponding to the moving direction of the most recently executed computer screen chip image 200 with the highest priority.

The buffer copy process 223 may have priority over the buffer read process 225 in the process of parallel processing by the thread among the buffer copy process 223 and the buffer read process 225. In the process of the multithread 220 The description of the priority will be described in detail later with reference to FIG.

The hash table 230 may extract and store the respective grid image data location and size attributes of the chip image 200. More specifically, the hash table 230 can map the relationship between the lattice matrix values of the entire chip image 100 and the position coordinate values and file pointer values on the image, The data retrieval speed can be improved by directly accessing the image.

In addition, the hash table 230 can provide information so that the image data to be stored in the image buffer 210 can be quickly accessed and accessed from the entire chip image 200.

Meanwhile, the hash table 230 may not correspond to the one-to-one correspondence between the one image buffer 210 and the grid image data of one chip image 200. For example, when the chip image 200 is displayed on the computer screen, Can be mapped to one-to-many according to the reduction ratio.

For example, when the chip image 200 and the image buffer 210 are mapped to one-to-many, the position coordinate value on the image can be changed.

Also, the correspondence between the image buffer 200 and the grid can be handled and processed by the processor that processes the image. For example, the hash table 230 can be calculated only once and then rescued.

In the meantime, the present invention is limited in the capacity of a computer memory in which CAD software for reverse engineering, which extracts electronic circuits from a plurality of layers of large-capacity chip images, is executed, so that the entire chip image 200 can not be mounted in a computer memory, The disadvantage that the processing speed is largely lowered can be solved. In addition, when the performance of the computer used by the user is insufficient and the chip image 200 is large, image processing speed may be slowed down, but the function of displaying an image can be normally executed. In addition, the present invention can be applied to general software that processes images in an interactive manner with a user.

4 is a flow diagram of process priority of a multi-thread.

First, the multi-thread 220 checks whether the buffer copy processor 223 or the buffer read processor 225 is executing at the same time. (Step S300)

If it is concurrently executing, the buffer copy processor 223 is executed first. (Step S310)

For example, the buffer copy process 223 may have a high execution priority because the task processing speed of copying image data is fast.

After executing the buffer copy processor 223, the buffer read processor 225 is executed. (Step S320)

For example, the task of generating new image data in the buffer read process 225 may be low in priority because of the slow processing speed.

As described above, the buffer copy process 223 may have priority over the buffer read process 225 in the process of parallel processing by the thread among the buffer copy process 223 and the buffer read process 225.

On the other hand, when only the buffer copy processor 223 is executed, the buffer copy process 223 is executed irrespective of the priority. When only the buffer read processor 225 is executed, 225). (Step S330)

5 is a flowchart illustrating a method of accelerating a large-capacity image display using a multithread according to an exemplary embodiment of the present invention.

First, the entire chip image 200 is divided into a grid structure composed of rows and columns, and the position information of each grid on the chip image is mapped to the hash table 230 and stored have. (Step S400) In this case, the relation between the lattice matrix value of the entire chip image 200, the position coordinate value on the image, and the file pointer value may be mapped and stored in the hash table.

In the prior art, the chip image 200 is stored as a file. In order to read image data corresponding to an arbitrary grid, the chip image 200 must be scanned from the beginning. However, when the hash table described above is used, the hash table 230 can be used to directly access the image data corresponding to the grid and read it independently, thereby increasing the speed of retrieving and reading data.

On the other hand, the controller 110 reads image data corresponding to a portion of the entire chip image 200 to be displayed on the screen based on the hash table, converts the size and position information, and stores the size and position information in the image buffer 210 . (Step S410)

In this case, the size and position are determined according to the screen magnification and position designated by the user. The user can specify a direction through a direction key or the like to move from a currently specified position to another position. The image buffer 210 may be divided into a visible image buffer, an invisible image buffer, and a predicted image buffer. If the position is changed by the user, the image buffer 210 may update the image data based on the changed position . (Step S420)

The image buffer 210 stores the image data appearing on the computer screen in the visible image buffer 213, and the image data adjacent to the upper, lower, left, and right sides are stored in the invisible image buffer 215.

At this time, the moving direction of the user may be predicted according to the statistical recording of the screen moving direction of the user, and the prediction image buffer may be further allocated in the up, down, left, and right directions. (Step S430)

Therefore, according to the present invention, by using the hash table 230, the data retrieval speed can be improved by the software directly searching for and accessing the image corresponding to the grid at the desired position, and the image data to be stored in the image buffer 210 Information can be provided to quickly locate and access the entire chip image.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Various substitutions, modifications, and variations are possible without departing from the scope of the invention. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

200: chip image
210: image buffer
213: Visible image buffer
215: Invisible image buffer
220: Multithreaded
223: Buffer copy process
225: Buffer Reading Process
230: Hash table

Claims (14)

A chip image storage unit for storing a chip image;
A hash table in which a position on the chip image when the chip image is divided into a grid structure based on a resolution size of a screen is represented by a matrix number and a file pointer, and a hash table in which a user wants to display an image A memory including a visible image buffer for storing data; And
A display coordinate determination module that determines a position of a portion of the chip image that the user wants to display on the screen based on the hash table and a display coordinate determination module that determines image data corresponding to a position of a portion to be displayed on the screen determined by the display coordinate determination module And a buffer process control module for controlling the image buffer to store the image data in the visible image buffer.
Large Image Display Acceleration System using Multi - thread.
The method according to claim 1,
Wherein the memory further comprises an invisible image buffer storing image data of an area neighboring the visible image buffer and a predicted image buffer storing image data of an area neighboring the invisible image buffer,
Wherein the control unit further includes a user movement prediction module for predicting a direction in which the user moves in accordance with the statistical recording of the screen movement direction of the user, wherein the control unit controls the invisible image buffer to store the image data of the area neighboring the visible image buffer And stores the image data arranged in the invisible image buffer and the moving direction in the predictive image buffer,
Large Image Display Acceleration System using Multi - thread.
3. The method of claim 2,
The control unit controls the large-capacity image display acceleration system to perform parallel processing through the multithread,
Wherein the multithread is configured to copy the image data of the invisible image buffer to the visible image buffer, copy the image data of the predictive image buffer to the invisible image buffer, or copy the image data of the invisible image buffer to the non- Buffer copy process to copy to buffer; And
And a buffer reading process of reading image data at a position determined based on the hash table and storing the image data in either the visible image buffer, the invisible image buffer, or the predicted image buffer.
Large Image Display Acceleration System using Multi - thread.
The method of claim 3,
Wherein the multithread is configured such that the buffer copy process has priority over the buffer read process.
Large Image Display Acceleration System using Multi - thread.
The method of claim 3,
Wherein the buffer read process is adapted to have priority in the multithread when reading image data corresponding to an area neighboring the moving direction of the most recently executed user in the visible image buffer, the invisible image buffer, or the predictive image buffer Configured,
Large Image Display Acceleration System using Multi - thread.
The method of claim 3,
Wherein the total number of threads executing in parallel in the multithreaded processor is configured to be determined by the number of cores that are operable in the processor,
Large Image Display Acceleration System using Multi - thread.
The method according to claim 1,
Wherein a number of matrix numbers mapped according to an enlargement or reduction ratio of an area to be displayed among the chip images is varied,
Large Image Display Acceleration System using Multi - thread.
Storing a position on the chip image as a hash table including a matrix number and a file pointer when a chip image is divided into a lattice structure based on a resolution size of a screen;
Determining a position of a portion of the chip image that the user wants to display on the screen based on the hash table;
Storing image data corresponding to a position of a portion to be displayed on a screen determined in the determining step in a visible image buffer; And
And displaying an image stored in the visible image buffer.
A method for accelerating large image display using multithreading.
9. The method of claim 8,
Storing image data of an area neighboring the visible image buffer in an invisible image buffer;
Estimating a direction in which the user moves according to the statistical recording of the screen movement direction of the user; And
And storing the image data of the area neighboring in the moving direction predicted in the predicting step in the invisible image buffer in the predictive image buffer.
A method for accelerating large image display using multithreading.
9. The method of claim 8,
Copying the image data of the invisible image buffer to the invisible image buffer, copying the image data of the predictive image buffer to the invisible image buffer, or copying the image data of the invisible image buffer to the invisible image buffer Buffer copying step; And
Further comprising a buffer reading step of reading image data at a position determined based on the hash table and storing the image data in either the visible image buffer, the invisible image buffer, or the predicted image buffer,
Wherein the buffer copy step and the buffer read step are performed in parallel through multiple threads,
A method for accelerating large image display using multithreading.
11. The method of claim 10,
Wherein the buffer copying step has a priority in the multi-
A method for accelerating large image display using multithreading.
11. The method of claim 10,
Wherein the buffer reading step includes a step of reading the image data corresponding to the area neighboring the moving direction of the most recently executed user in the visible image buffer, the invisible image buffer, or the predictive image buffer so as to have priority in the multithread Configured,
A method for accelerating large image display using multithreading.
11. The method of claim 10,
Wherein the total number of threads in the multithread is determined by the number of cores available for operation in the processor,
A method for accelerating large image display using multithreading.
9. The method of claim 8,
Wherein the hash table has a number of matrix numbers mapped according to an enlargement or reduction ratio of an area to be displayed among the chip images,
A method for accelerating large image display using multithreading.

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