KR20190013063A - Method for controlling accelerator of heterogeneous system, and heterogeneous system for performing the same - Google Patents

Abstract

Provided is a heterogeneous system to increase power efficiency and communication performance. The heterogeneous system comprises: a plurality of calculation devices for executing an application; and a host processor connected to the calculation devices and controlling power supplied to the calculation devices. The host processor confirms one or more calculation devices used for execution of the application among the calculation devices and controls idle power of the remaining calculation devices except for the confirmed calculation device to be minimized during execution of the application.

Description

TECHNICAL FIELD The present invention relates to an accelerator control method for a heterogeneous system and a heterogeneous system for performing the same,

The embodiments disclosed herein relate to a method for controlling a plurality of accelerators included in a heterogeneous system and a heterogeneous system for performing the same.

A heterogeneous system is a system that includes a CPU and a plurality of accelerators.

When running an application in a heterogeneous system, only some of the accelerators, which typically achieve the highest performance among a plurality of accelerators included in a heterogeneous system, are used. However, unused accelerators can occupy a significant portion of the total power consumption by consuming about several to several tens of watts of idle power.

In addition, accelerators are usually connected to the CPU via a PCI-E bus. The number of PCI-E lanes supported by the CPU is limited. To connect multiple accelerators at one time, a PCI-E switch It is necessary to divide the bandwidth into two parts, thereby reducing the speed and quality of communication and increasing power consumption. Especially, in the situation where only some of the accelerators included in the heterogeneous system are used to execute the application, maintaining the connection with the CPU through the PCI-E switch to the unused accelerators causes unnecessary time delay, power consumption, There is a problem that interference occurs.

All of these problems arise because accelerators that are not used by the application consume system hardware resources.

Related Prior Art U.S. Patent No. 9,672,046, which is incorporated herein by reference in its entirety, includes a power plane associated with one of a plurality of processor components for performing a plurality of processor functions, wherein each of the power planes, based on workload characteristics and power constraints, And the power is dynamically adjusted.

On the other hand, the background art described above is technical information acquired by the inventor for the derivation of the present invention or obtained in the derivation process of the present invention, and can not necessarily be a known technology disclosed to the general public before the application of the present invention .

The embodiments disclosed herein relate to a method of controlling a plurality of accelerators included in a heterogeneous system so as to increase power efficiency and communication performance and to a heterogeneous system for performing the same.

As a technical means for achieving the above-mentioned technical object, according to an embodiment, a heterogeneous system includes a plurality of calculation devices for executing an application and a plurality of calculation devices connected to the plurality of calculation devices, Wherein the host processor identifies at least one computing device to be used for execution of the application from among the plurality of computing devices, and during execution of the application, the identified at least one So that the idle power of the remaining calculation devices except for the calculation device of the first calculation device can be minimized.

According to another embodiment, a method of controlling a computing device of a heterogeneous system comprises the steps of: identifying at least one computing device to be used for execution of an application among a plurality of computing devices included in the heterogeneous system; And controlling the idle power of the remaining calculation devices except the identified at least one calculation device to be minimum.

According to yet another embodiment, there is provided a computer program for performing a computing device control method of a heterogeneous system, the computing device control method of a heterogeneous system comprising at least one of a plurality of computing devices included in the heterogeneous system, Checking one computing device and controlling the idle power of the remaining computing devices except for the at least one computing device to be minimized during execution of the application.

According to another embodiment, a computer-readable recording medium on which a program for performing a computing device control method of a heterogeneous system is recorded, the computing device control method of a heterogeneous system comprising: Determining at least one computing device to be used in execution of the application and controlling the idle power of the remaining computing devices except for the at least one computing device to be minimized during execution of the application.

According to any one of the above-mentioned means for solving the problems, it is possible to reduce the average power consumption of the heterogeneous system by controlling the idle power of the accelerators not used for execution of the application to be the smallest among the plurality of accelerators included in the heterogeneous system Can be expected.

In addition, among the plurality of accelerators included in the heterogeneous system, only the accelerators used in the execution of the application maintain the connection with the CPU, so that the mutual interference, the time delay, and the like which may occur in switching the connection between the CPU and the accelerators An effect of reducing power consumption can be expected.

Also, not all of the power budget of the entire system and the number of PCI-E lanes provided by the CPU (or PCI-E controller), after installing multiple accelerators into the system, only the accelerators actually used by the application And the PCI-E lanes are assigned to each of the different types of accelerators, so that various applications requiring different accelerators can be executed in one heterogeneous system.

The effects obtained in the disclosed embodiments are not limited to the effects mentioned above, and other effects not mentioned are obvious to those skilled in the art to which the embodiments disclosed from the following description belong It can be understood.

FIG. 1 is a diagram illustrating a configuration of a heterogeneous system according to an embodiment.
2 is a flow chart for explaining an accelerator control method of a heterogeneous system according to an embodiment.
3 is a diagram illustrating a state in which idle power of some accelerators included in a heterogeneous system is minimally controlled according to an exemplary embodiment.
4 is a flowchart illustrating a method of controlling a connection between a CPU and accelerators in a heterogeneous system according to an exemplary embodiment of the present invention.
5 is a view showing a state in which only accelerators used in execution of an application in a heterogeneous system according to an embodiment are controlled to maintain a connection with a CPU.

Various embodiments are described in detail below with reference to the accompanying drawings. The embodiments described below may be modified and implemented in various different forms. In order to more clearly describe the features of the embodiments, detailed descriptions of known matters to those skilled in the art are omitted. In the drawings, parts not relating to the description of the embodiments are omitted, and like parts are denoted by similar reference numerals throughout the specification.

Throughout the specification, when a configuration is referred to as being "connected" to another configuration, it includes not only a case of being directly connected, but also a case of being connected with another configuration in between. In addition, when a configuration is referred to as "including ", it means that other configurations may be included, as well as other configurations, as long as there is no specially contradicted description.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a configuration of a heterogeneous system according to an embodiment. 1, a disparate system 100 according to one embodiment includes a CPU 110, a PCI-E controller 120, a PCI-E switch 130, and a plurality of accelerators 141, 142, 143, 144 ). Although FIG. 1 illustrates the heterogeneous system 100 as including four accelerators 141, 142, 143, and 144, it is apparent that the present invention is not limited thereto and may include various numbers of calculation devices.

The CPU 110 controls the overall operation of the heterogeneous system 100 as a general purpose processor, and is also referred to as a " host processor ". The operating system of the heterogeneous system 100 can be executed in the CPU 110. [ The CPU 110 may control the operation of the accelerators 141, 142, 143 and 144. A main memory (not shown) may be connected to the CPU 110.

The PCI-E controller 120 is an interface for providing a connection between the CPU 110 and the accelerators 141, 142, 143 and 144. The PCI-E controller 120 may be separately provided outside the CPU 110, or may be integrated into the CPU 110. That is, although the PCI-E controller 120 is illustrated as being separate from the CPU 110 in FIG. 1, the CPU 110 may directly perform the role of the PCI-E controller 120. The PCI-E controller 120 provides a predetermined number of PCI-E lanes.

The PCI-E switch 130 is a configuration for relaying communication between the CPU 100 and the accelerators 141, 142, 143, and 144. 1, the PCI-E controller 120 and the PCI-E switch 130 are connected through a first lane, and the PCI-E switch 130 and the accelerators 141, 142, 143, 144 are connected through a second lane, and the PCI-E switch 130 relays between the first lane and the second lane.

The reason for using the PCI-E switch 130 is that the number of PCI-E lanes (the number of PCI-E lanes included in the second lane) required by the accelerators 141, 142, 143, -E is greater than the number of PCI-E lanes provided by the controller 120 (the number of PCI-E lanes included in the first lane). That is, when all of the accelerators 141, 142, 143, and 144 can not be connected by only the PCI-E lanes provided by the PCI-E controller 120, the PCI- And the PCI-E switch 130 is again connected to the accelerators 141, 142, 143, and 144. The PCI-

The accelerators 141, 142, 143, and 144 are also referred to as 'computing devices' and, unlike general-purpose CPUs, For example, a GPU, an Intel Xeon Phi coprocessor, or an FPGA can be an accelerator.

Accelerators 141, 142, 143, and 144 perform operations specific to each of them under the control of CPU 110. In other words, when the application is executed in the heterogeneous system 100, each of the accelerators 141, 142, 143, and 144 performs an operation of a specific pattern specific thereto, and the remaining operations and I / ). ≪ / RTI > In addition, a device memory (not shown) may be connected to each of the accelerators 141, 142, 143, and 144.

The accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 may operate in different ways, have the same operation method, but may have different detailed architectures, It is possible. Therefore, by selecting and executing the best accelerator according to the application, the efficiency of the entire system can be maximized.

When only some of the accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 are selected and used, the remaining accelerators are idle and consume idle power continuously . Thus, in one embodiment described below, a method for reducing the average power consumption of the heterogeneous system 100 by minimizing the idle power of the accelerator not used in the execution of the application is presented.

When only some of the accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 are selected and used, the remaining unaccelerated accelerators are connected to the CPU 110 , The overhead of the PCI-E switch 130 is increased because the PCI-E switch 130 must perform the routing operation between the CPU 110 and the accelerators 141, 142, 143, and 144, , Inter-communication interference occurs, time delay due to routing operation, and additional power consumption may occur. Therefore, in the embodiment described below, only the accelerator used for executing the application maintains the connection with the CPU 110, thereby suggesting a method of improving communication performance and power efficiency.

Hereinafter, a method of controlling the accelerators 141, 142, 143, and 144 included in the heterogeneous system 100 according to an exemplary embodiment will be described in detail with reference to FIGS. 2 to 5. FIG. In the embodiment described below, it is assumed that only the first accelerator 141 and the third accelerator 143 are used when the application is executed in the heterogeneous system 100. [

2 is a flow chart for explaining an accelerator control method of a heterogeneous system according to an embodiment. Referring to FIG. 2, in step 201, the CPU 110 determines at least one accelerator used by an application among a plurality of accelerators 141, 142, 143, and 144 included in the heterogeneous system 100. That is, the CPU 110 confirms that only the first accelerator 141 and the third accelerator 143 are used among the plurality of accelerators 141, 142, 143, 144 when the application is executed in the heterogeneous system 100.

At this time, the CPU 110 can confirm whether or not the accelerator is used before or during execution of the application in the heterogeneous system 100. Which accelerator to use may be specified by the application, by a runtime system that executes the application, or by a user of the heterogeneous system 100.

In step 202, the CPU 100 controls the idle power of the remaining accelerators 142 and 144 other than the determined accelerators 141 and 143 to be the minimum. For example, the CPU 110 can control the power supplied to the accelerators 141, 142, 143, and 144 according to the ACPI (Advanced Configuration and Power Interface) standard.

At this time, ACPI is a standard that allows software to manage power of hardware components constituting a computer, and includes a power management standard for each individual device installed in a computer, such as an accelerator. ACPI defines four power states of the device (D0, D1, D2, D3). D0 means that the device is on and in operation, and D3 means that the device is off and inoperative. D1 and D2 mean the intermediate state between D0 and D3. That is, the power consumed by the device decreases from D0 to D3.

The CPU 110 can control the power state of the accelerators 141, 142, 143 and 144 to any one of D0 to D3 by transmitting a command to the device drivers of the accelerators 141, 142, 143 and 144.

Accordingly, in step 202, the CPU 110 transmits a command to the first accelerator 141 and the third accelerator 143 to switch to the D0 state, while the second accelerator 142 and the fourth accelerator 144 send the D3 state To < / RTI > Alternatively, if the CPU 110 requires a higher power state than D3 at the unused second accelerator 142 and the fourth accelerator 144, the second accelerator 142 and / To the fourth accelerator 144. That is, the CPU 110 can control the accelerators 142 and 144, which are not used, to consume only the minimum power required by the unused accelerators 142 and 144 as idle power.

FIG. 3 illustrates a state in which the CPU 110 controls the idle power of some of the accelerators 142 and 144 to the minimum according to an embodiment. 3, it can be seen that the first accelerator 141 and the third accelerator 143 are controlled to the D0 state and the second accelerator 142 and the fourth accelerator 144 are controlled to the D3 state.

In the above embodiment, the power supply of the accelerators 141, 142, 143 and 144 is controlled according to the ACPI standard. However, this is merely an example, and the CPU 110 may use the accelerators 142 , 144 can be controlled to be the minimum.

In step 203, the PCI-E switch 130 can control only the accelerators 141 and 143, which are determined to be used when the application is executed, to maintain a connection with the CPU 110. [ A specific method by which the PCI-E switch 130 controls the connection between the CPU 110 and the accelerators 141, 142, 143, and 144 will be described with reference to FIGS.

FIG. 4 is a flowchart for explaining a method of controlling connection between a CPU and accelerators in a heterogeneous system according to an embodiment, and includes the detailed steps of step 203 of FIG. 5 is a view showing a state in which only accelerators used in execution of an application in a heterogeneous system according to an embodiment are controlled to maintain a connection with a CPU.

4, in step 401, the PCI-E switch 130 transmits the number (M) of PCI-E lanes required by the accelerators 141 and 143 used by the application to the PCI-E controller 120, To the number of PCI-E lanes (N) provided by the PCI-E lanes.

Referring to FIG. 5, since the first accelerator 141 and the third accelerator 143 each require 16 PCI-E lanes, M becomes 32. In FIG. 5, the number of PCI-E lanes provided by the PCI-E controller 120 is 32, so that N becomes 32. Thus, according to the embodiment shown in FIG. 5, the PCI-E switch 130 determines that M is less than or equal to N. FIG.

In step 402, the PCI-E switch 130 determines whether M is equal to or less than N, and proceeds to step 403 if M is less than N. [

In step 403, the PCI-E switch 130 transmits the PCI-E lanes connected to the accelerators 141 and 143 used by the application among the PCI-E lanes included in the second lane to the PCI- One-to-one correspondence with E lanes.

In step 404, the PCI-E switch 130 can relay the data transfer between the CPU and the accelerators according to the one-to-one correspondence between the first lane and the second lane. For example, the PCI-E switch 130 may store a routing table that includes a one-to-one correspondence between the first and second lanes, and may relay the data transmission according to the stored routing table. Alternatively, if the PCI-E switch 130 supports a function of establishing a one-to-one correspondence relationship between PCI-E lanes, data transfer may be relayed using the function.

On the other hand, if it is determined in step 402 that M is greater than N, the PCI-E switch 130 switches between the first line and the second line in step 405 and relays data transmission .

In this manner, the PCI-E switch 130 can minimize the overhead of the PCI-E switch 130 by allowing only the accelerators 141 and 143 used in the execution of the application to maintain the connection with the CPU 110 , And can utilize the limited PCI-E lane of the CPU 110 efficiently. As a result, an effect of reducing power consumption, time delay, and mutual interference due to the routing operation of the PCI-E switch 130 can be expected.

The term " part " used in the above embodiments means a hardware component such as a software or a field programmable gate array (FPGA) or an ASIC, and the 'part' performs certain roles. However, 'part' is not meant to be limited to software or hardware. &Quot; to " may be configured to reside on an addressable storage medium and may be configured to play one or more processors. Thus, by way of example, 'parts' may refer to components such as software components, object-oriented software components, class components and task components, and processes, functions, , Subroutines, segments of program patent code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.

The functions provided within the components and components may be combined with a smaller number of components and components or separated from additional components and components.

In addition, the components and components may be implemented to play back one or more CPUs in a device or a secure multimedia card.

The accelerator control method of the heterogeneous system according to the embodiment described with reference to Figs. 2 to 5 may also be embodied in the form of a computer-readable medium for storing instructions and data executable by a computer. At this time, the command and data may be stored in the form of program code, and when executed by the processor, a predetermined program module may be generated to perform a predetermined operation. In addition, the computer-readable medium can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. The computer-readable medium can also be a computer storage medium, which can be volatile and non-volatile, implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, Volatile, removable and non-removable media. For example, the computer recording medium may be a magnetic storage medium such as an HDD and an SSD, an optical recording medium such as a CD, a DVD and a Blu-ray Disc, or a memory included in a server accessible via a network.

The accelerator control method of the heterogeneous system according to the embodiment described with reference to FIGS. 2 to 5 may also be implemented as a computer program (or a computer program product) including instructions executable by the computer. A computer program includes programmable machine instructions that are processed by a processor and can be implemented in a high-level programming language, an object-oriented programming language, an assembly language, or a machine language . The computer program may also be recorded on a computer readable recording medium of a type (e.g., memory, hard disk, magnetic / optical medium or solid-state drive).

Therefore, the accelerator control method of the heterogeneous system according to the embodiment described with reference to Figs. 2 to 5 can be implemented by the computer program as described above being executed by the computing device. The computing device may include a processor, a memory, a storage device, a high-speed interface connected to the memory and a high-speed expansion port, and a low-speed interface connected to the low-speed bus and the storage device. Each of these components is connected to each other using a variety of buses and can be mounted on a common motherboard or mounted in any other suitable manner.

Where the processor may process instructions within the computing device, such as to display graphical information to provide a graphical user interface (GUI) on an external input, output device, such as a display connected to a high speed interface And commands stored in memory or storage devices. As another example, multiple processors and / or multiple busses may be used with multiple memory and memory types as appropriate. The processor may also be implemented as a chipset comprised of chips comprising multiple independent analog and / or digital processors.

The memory also stores information within the computing device. In one example, the memory may comprise volatile memory units or a collection thereof. In another example, the memory may be comprised of non-volatile memory units or a collection thereof. The memory may also be another type of computer readable medium such as, for example, a magnetic or optical disk.

And the storage device can provide a large amount of storage space to the computing device. The storage device may be a computer readable medium or a configuration including such a medium and may include, for example, devices in a SAN (Storage Area Network) or other configurations, and may be a floppy disk device, a hard disk device, Or a tape device, flash memory, or other similar semiconductor memory device or device array.

It will be apparent to those skilled in the art that the above-described embodiments are for illustrative purposes only and that those skilled in the art will readily understand that various changes and modifications can be made without departing from the spirit and scope of the present invention. You will understand. It is therefore to be understood that the above-described embodiments are to be considered in all respects only as illustrative and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

It is to be understood that the scope of the present invention is defined by the appended claims rather than the foregoing description and should be construed as including all changes and modifications that come within the meaning and range of equivalency of the claims, .

100: heterogeneous system 110: CPU
120: PCI-E controller 130: PCI-E switch
141, 142, 143, 144: Accelerators

Claims (15)

In a heterogeneous system,
A plurality of computing devices for executing an application; And
And a host processor coupled to the plurality of computing devices and controlling power supplied to the plurality of computing devices,
Wherein the host processor identifies at least one computing device to be used for execution of the application from among the plurality of computing devices and during execution of the application the idle power of the computing device excluding the at least one computing device identified A heterogeneous system that is controlled to be minimal. The method according to claim 1,
Further comprising a connection switch for controlling connection between the host processor and the plurality of computing devices,
Wherein the connection switch controls, during execution of the application, that only the identified at least one computing device maintains a connection with the host processor. The method according to claim 1,
The host processor,
Wherein the power supplied to the computing devices is controlled through a power management standard that defines three or more power states of the computing devices. The method of claim 3,
The host processor,
Wherein the control unit transmits a command to switch to a power supply state having the lowest power consumption among three or more power supply states defined by the power management standard for the remaining calculation devices except for the checked at least one calculation device. . 3. The method of claim 2,
Wherein the connection switch comprises:
Wherein at least one lane connected between the at least one computing device and the connection switch is associated with at least one lane connected between the connection switch and the host processor. 6. The method of claim 5,
Wherein a routing table containing a one-to-one correspondence between the lanes is stored in the connection switch, and the connection switch relays data communication between the host processor and the plurality of computing devices in accordance with the stored routing table. system. 6. The method of claim 5,
Wherein the connection switch supports a function of setting a one-to-one correspondence between the lanes. A method for controlling a computing device of a heterogeneous system,
Identifying at least one computing device to be used for execution of an application among a plurality of computing devices included in the heterogeneous system; And
During execution of the application, controlling the idle power of the remaining computing devices except for the identified at least one computing device to be at a minimum. 9. The method of claim 8,
Further comprising, during execution of the application, controlling only the identified at least one computing device to maintain a connection with a host processor included in the heterogeneous system. 9. The method of claim 8,
Wherein the controlling comprises:
Wherein the power supplied to the computing devices is controlled through a power management standard that defines three or more power states of the computing devices. 11. The method of claim 10,
Wherein the controlling comprises:
Wherein the command for switching to the power state having the lowest power consumption among the three or more power states defined by the power management standard is transmitted to the remaining calculation devices except the checked at least one calculation device. 10. The method of claim 9,
The step of controlling to maintain the connection comprises:
Wherein at least one lane connected between the at least one computing device and the connection switch is associated with at least one lane connected between the connection switch and the host processor. 13. The method of claim 12,
The step of controlling to maintain the connection comprises:
Storing a routing table including a one-to-one correspondence between the lanes; And
And relaying data communication between the host processor and the plurality of computing devices in accordance with the stored routing table. A computer-readable recording medium on which a program for performing the method according to claim 8 is recorded. A computer program stored in a medium for performing the method of claim 8, which is performed by a heterogeneous system.

Images