KR20190010403A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor device capable of reducing an area of a cell array region may comprise: first and second channel films individually extending from the lower side to the upper side; word lines spaced apart from each other, stacked from the lower side to the upper side, and individually extending to surround the first and second channel films; a first lower select group surrounding a part of the first channel film protruding further toward the lower side than the word lines; and a second lower select group surrounding a part of the second channel film protruding further toward the lower side than the word lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a three-dimensional semiconductor device and a manufacturing method thereof.

A semiconductor device includes memory cell transistors capable of storing data. The three-dimensional semiconductor device may include memory cell transistors arranged in different first to third directions. The three-dimensional semiconductor device includes wirings such as select lines and word lines to access memory cell transistors.

An embodiment of the present invention provides a semiconductor device capable of reducing the area of a cell array region and a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention includes first channel films and second channel films connected between a source region and bit lines; Word lines extending between the source region and the bit lines and spaced apart from each other and extending to surround the first and second channel films, respectively; A first source select line surrounding the first channel layers between the word lines and the source region; A second source select line surrounding the second channel films between the word lines and the source region and spaced apart from the first source select line; And a drain select line disposed between the bit lines and the word lines and extending to overlap the first and second source select lines.

The semiconductor device according to an embodiment of the present invention includes a first channel layer and a second channel layer, each of the first channel layer and the second channel layer having an inverted trapezoidal longitudinal sectional structure extending from a lower portion to an upper portion and having a width narrower toward the lower portion; Word lines stacked from the bottom toward the top and spaced apart from each other and extending to surround the first channel film and the second channel film, respectively; A first lower select group surrounding a portion of the first channel film protruding from the word lines toward the lower portion; And a second lower select group surrounding a part of the second channel film protruding downward from the word lines.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first laminate; Forming separation insulating films for separating the first laminate into first patterns; Forming a second laminate on the first patterns and the isolation insulating films; And one of the first insulating layers, the second insulating layer, and the second insulating layer, the second laminate being divided into second patterns and each of the first patterns being divided into third patterns, And forming slits which face each other with a gap therebetween.

According to the present invention, the select lines can be stably separated without increasing the horizontal area by designing the isolation region of the select lines in consideration of the profile of the channel film. Thus, the present invention can reduce the area of the cell array region of the three-dimensional semiconductor device.

1 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present invention.
2 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.
3A to 3C are cross-sectional views illustrating various structures of a multi-layer memory pattern.
4 is a flowchart for schematically explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
5A to 11 are views for explaining a step-by-step description of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
12A to 12C are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.
13A to 13D are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.
14 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention.
15 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in adding reference numerals to the constituent elements of each drawing, only the same constituent elements have the same number as possible even if they are displayed on different drawings.

1 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG. 1 illustrates an exemplary circuit diagram of a NAND flash memory device.

Referring to FIG. 1, a semiconductor device according to an embodiment of the present invention includes a memory cell array having a three-dimensional structure including a plurality of memory cells arranged along first through third directions I through III 100). The memory cell array 100 includes a plurality of memory strings SR11, SR12, SR21, and SR22. The memory strings SR11, SR12, SR21 and SR22 may be connected between the bit lines BL1 and BL2 and the source region SA. Although FIG. 1 illustrates four memory strings SR11, SR12, SR21, and SR22 connected to a specific gate group GL, the present invention is not limited thereto. For example, a plurality of gate groups may be disposed in a second direction (II) spaced apart, and each of the gate groups may control operation of four or more memory strings.

The memory strings SR11, SR12, SR21 and SR22 may be divided into bit groups BG connected to different bit lines BL1 and BL2. The memory strings constituting each of the bit groups BG are controlled by the same bit line.

The bit lines BL1 and BL2 extend along the second direction II and can be arranged in parallel with each other. The bit lines BL1 and BL2 may include a first bit line BL1 and a second bit line BL2 arranged alternately along the third direction III. 1 illustrates a pair of the first bit line BL1 and the second bit line BL2, the present invention is not limited thereto. For example, a plurality of first bit lines and a plurality of second bit lines may be alternately arranged one by one along the third direction (III).

The memory strings SR11, SR12, SR21, and SR22 may be arranged in a zigzag fashion for improved integration. For example, a bit group BG connected to the first bit line BL1 and a bit group BG connected to the second bit line BL2 can be arranged in a zigzag manner.

Each of the memory strings SR11, SR12, SR21 and SR22 includes a source select transistor SSTa or SSTb connected in series, a plurality of memory cell transistors MC1 through MCn (n is a natural number of 2 or more), and a drain select transistor DSTa Or DSTb). Each of the memory strings SR11, SR12, SR21 and SR22 may include one source select transistor SSTa or two or more source select transistors SSTa and SSTb connected in series. Each of the memory strings SR11, SR12, SR21 and SR22 may include one drain select transistor DSTa or two or more drain select transistors DSTa and DSTb connected in series. 1 shows a case where each of the memory strings SR11, SR12, SR21 and SR22 includes two source select transistors SSTa and SSTb and two drain select transistors DSTa and DSTb, Are not limited thereto. Hereinafter, for convenience of description, one of the two source select transistors is referred to as a lower source select transistor (SSTa), and the other one adjacent to the lower source select transistor (SSTa) in the first direction (I) Select transistor SSTb. Likewise, one of the two drain select transistors is referred to as a lower drain select transistor DSTb, and the other one adjacent to the lower drain select transistor DSTb in the first direction I is an upper drain select transistor DSTa .

The lower and upper source select transistors SSTa and SSTb, the plurality of memory cell transistors MC1 to MCn, and the lower and upper drain select transistors DSTb and DSTa are connected to a channel extending along the first direction I, Can be connected in series by a membrane to form one memory string SR11, SR12, SR21 or SR22. One channel film may be connected to one bit line corresponding to one of the first and second bit lines BL1 and BL2 and the source region SA.

The memory strings SR11, SR12, SR21, and SR22 may be connected to the gate group GL. The gate group GL may include an upper select group USG, word lines WL1 to WLn, a first lower select group LSG1, and a second lower select group LSG2. Each of the word lines WL1 to WLn may extend in the horizontal direction. The horizontal direction is perpendicular to the first direction I and parallel to the second direction II and the third direction III. The word lines WL1 to WLn are connected to the gates of the memory cell transistors MC1 to MCn, respectively.

1 shows memory strings SR11, SR12, SR21 and SR22 of first to fourth rows connected in common to word lines WL1 to WLn, respectively. Although FIG. 1 illustrates only one memory string constituting each row, each row includes a plurality of memory strings. The memory strings constituting each row are connected to the first bit lines and the second bit lines alternately arranged along the third direction (III), and are arranged in a line along the third direction (III). The memory strings SR11, SR12, SR21, SR22 of the first to fourth rows may be arranged in a zigzag manner. The memory strings SR11 and SR21 of the first and third rows are connected to the first bit line BL1 and the memory strings SR12 and SR22 of the second and fourth rows are connected to the second bit line BL2, Lt; / RTI >

The memory strings SR11, SR12, SR21, SR22 of the first to fourth rows may be connected in common to the horizontally extending upper select group USG. The upper select group USG may include one or more drain select lines DSLa and DSLb. For example, the upper select group USG may include an upper drain select line DSLa and a lower drain select line DSLb. The upper drain select line DSLa and the lower drain select line DSLb extend in parallel with each other. The upper drain select line DSLa is connected to the gate of the upper drain select transistor DSTa included in each of the memory strings SR11, SR12, SR21 and SR22 of the first to fourth rows. The lower drain select line DSLb is connected to the gate of the lower drain select transistor DSTb included in each of the memory strings SR11, SR12, SR21, SR22 of the first to fourth rows.

The first lower select group LSG1 and the second lower select group LSG2 may be electrically and structurally separated from each other and disposed on the same layer. The memory strings SR11, SR12, SR21 and SR22 of the first to fourth rows may be connected to the first lower select group LSG1 or may be connected to the second lower select group LSG2. More specifically, the memory strings SR11 and SR12 of the first and second rows are connected to the first lower select group LSG1, and the memory strings SR21 and SR22 of the third and fourth rows are connected to the second And can be connected to the lower select group LSG2.

The first lower select group LSG1 may include more than one source select lines SSL1a and SSL1b. For example, the first lower select group LSG1 may include a first lower source select line SSL1a and a first upper source select select line SSL1b. Likewise, the second lower select group LSG2 may include more than one source select line SSL2a, SSL2b. For example, the second lower select group LSG2 may include a second lower source select select line SSL2a and a second upper source select line SSL2b.

The first lower source select line SSL1a is connected to the gate of the lower source select transistor SSTa included in each of the memory strings SR11 and SR12 of the first and second rows. The first upper source select line SSL1b is connected to the gate of the upper source select transistor SSTb included in each of the memory strings SR11 and SR12 of the first and second rows. The second lower source select line SSL2a is connected to the gate of the lower source select transistor SSTa included in each of the memory strings SR21 and SR22 of the third and fourth rows. The second upper source select line SSL2b is connected to the gate of the upper source select transistor SSTb included in each of the memory strings SR21 and SR22 of the third and fourth rows.

According to the circuit described above, the upper select group USG has an electrical connection between the first to fourth row memory strings SR11, SR12, SR21, SR22 and the first and second bit lines BL1, BL2 Can be controlled. The first lower select group LSG1 may control the electrical connection between the memory strings SR11, SR12 of the first and second rows and the source region SA. The second lower select group LSG2 can control the electrical connection between the memory strings SR21, SR22 of the third and fourth rows and the source region SA. Thus, the memory strings SR11, SR12, SR21 and SR22 of the first to fourth rows can be individually controlled. For example, when one upper select group is selected, one bit line is selected, and one of the first and second lower select groups is selected, the memory strings SR11 and SR12 of the first to fourth rows , SR21, SR22) can be selected.

The above-described gate group GL may be disposed between neighboring slits, and two gate groups may constitute one memory block. Hereinafter, with reference to FIG. 2, a structure of a memory block including two gate groups will be described.

2 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention. 2 is a perspective view for explaining a structure of a semiconductor device constituting the circuit shown in FIG.

Referring to FIG. 2, the memory strings SR11, SR12, SR21 and SR22 of the first to fourth rows shown in FIG. 1 are connected through the first gate stacked structure GST1 and the channel films CH1 and CH2 Or may be constituted through the second gate stacked structure GST2 and the channel films CH1 and CH2. The first gate stacked structure GST1 and the second gate stacked structure GST2 can constitute one memory block. The first gate stacked structure GST1 and the second gate stacked structure GST2 can be separated from each other by one of the slits SI. Although FIG. 2 illustrates a memory block including a pair of first gate stacks GST1 and a second gate stack GST2, a plurality of memory blocks may be arranged along a second direction II . Some of the slits SI may be arranged to separate between the gate stacks adjacent to the boundary between the memory blocks.

The first and second gate stacks GST1 and GST2 are disposed between the source region SA and the first and second bit lines BL1 and BL2. The source region SA may extend along the second direction II and the third direction III. The source region SA may be formed of at least one doped silicon film containing an impurity of the first conductivity type. The impurity of the first conductivity type may be an n-type impurity. The slits SI can extend to the source region SA. The source region SA is connected to the source contact lines SCL. Source contact lines SCL are disposed within the slits SI, respectively.

Each of the first and second gate stacks GST1 and GST2 is disposed between neighboring source contact lines SCL. Each of the first and second gate stacks GST1 and GST2 may be penetrated by the cell plugs PL. Each of the cell plugs PL may include a channel film CH1 or CH2, a multilayer memory pattern ML, and a capping pattern CAP. The cell plugs PL may be divided into a first group GR1 and a second group GR2. The first group GR1 includes cell plugs PL surrounded by the first lower select group LSG1. The second group GR2 includes the cell plugs PL surrounded by the second lower select group LSG2.

The channel films CH1 and CH2 are divided into a first channel layer CH1 constituting the first group GR1 and a second channel layer CH2 constituting the second group GR2. Each of the first and second channel films CH1 and CH2 is in contact with the source region SA through the first gate stacked structure GST or the second gate stacked structure GST2. Each of the first and second channel films CH1 and CH2 may be formed of a semiconductor film. For example, each of the first and second channel films CH1 and CH2 may be formed of a silicon film.

Each of the first and second channel films CH1 and CH2 is disposed in a hole H penetrating the first gate stacked structure GST or the second gate stacked structure GST2. Each of the first and second channel films CH1 and CH2 may be a thin film deposited along the surface of the hole H so as to surround the core insulating film CO. The core insulating film CO may be formed to have a height lower than that of each of the first and second channel films CH1 and CH2. In this case, each of the cell plugs PL may further include a capping pattern CAP. The capping pattern CAP may be formed on the core insulating film CO so as to fill the top central portion of the hole defined by the top of each of the core insulating film CO and the first and second channel films CH1 and CH2. The capping pattern CAP may be directly in contact with one of the corresponding first and second channel films CH1 and CH2. The capping pattern CAP may be formed of a semiconductor film doped with an impurity of the first conductivity type. The impurity of the first conductivity type may be an n-type impurity. More specifically, the capping pattern (CAP) may be a doped silicon film doped with an n-type impurity. The capping pattern CAP can be used as a drain junction.

On the other hand, although not shown in the figure, the capping pattern (CAP) and the core insulating film (CO) may be omitted. In this case, each of the first and second channel films CH1 and CH2 may be formed to completely fill the central region of the hole H defined by the multi-layer memory pattern ML.

The multilayer memory pattern ML surrounds the sidewalls of each of the first and second channel films CH1 and CH2. The multilayer memory pattern ML may extend along the interface between any one of the first and second channel films CH1 and CH2 and the first or second gate stack GST1 or GST2 corresponding thereto. Each of the first and second channel films CH1 and CH2 may protrude toward the source region SA rather than the multilayer memory pattern ML and directly contact the source region SA.

A part of each multilayer memory pattern ML disposed between the upper select group USG and the first and second channel films CH1 and CH2 and the first lower select group LSG1 and the first channel films CH1 And a part of each of the multilayer memory patterns ML disposed between the second lower select group LSG1 and the second channel films CH2 is used as a gate insulating film .

Each of the first and second channel films CH1 and CH2 has an inverted trapezoidal longitudinal sectional structure in which the width becomes narrower toward the lower portion adjacent to the source region SA due to the characteristics of the manufacturing process. In other words, the lower end width W1 of each of the first and second channel films CH1 and CH2 is narrower than the upper end width W2. As a result, the distance between the adjacent first and second channel films CH1 and CH2 gets larger toward the source region SA.

Each of the first and second gate stacks GST1 and GST2 includes the word lines WL1 to WLn which are stacked and isolated from each other in the first direction I. Each of the word lines WL1 to WLn may extend in the horizontal direction along the second and third directions II and III so as to commonly surround the first and second channel films CH1 and CH2. The first and second channel films CH1 and CH2 are protruded toward the bottom where the source region SA is disposed than the word lines WL1 to WLn. The first and second channel films CH1 and CH2 protrude from the word lines WL1 to WLn toward the upper direction in which the first and second bit lines BL1 and BL2 are disposed.

Each of the first and second gate stacks GST1 and GST2 includes an upper select group USG disposed between the word lines WL1 to WLn and the first and second bit lines BL1 and BL2. do. The upper select group USG includes second and third directions II and III to commonly surround portions of the first and second channel films CH1 and CH2 protruding from the word lines WL1 to WLn, In the horizontal direction.

Each of the first and second gate stacks GST1 and GST2 includes a first lower select group LSG1 and a second lower select group LSG2 disposed between the word lines WL1 to WLn and the source region SA, ). The first lower select group LSG1 and the second lower select group LSG2 are disposed on the same layer. More specifically, the first lower source select line SSL1a of the first lower select group LSG1 and the second lower source select line SSL2a of the second lower select group LSG2 are arranged in the same layer, The first upper source select line SSL1b of the first lower select group LSG1 and the second upper source select line SSL2b of the second lower select group LSG2 are disposed on the same layer. The first lower select group LSG1 surrounds portions of the first channel films CH1 protruding downward from the word lines WL1 to WLn and the second lower select group LSG2 surrounds the word lines WL1 To WLn) of the second channel films (CH2) projecting downward.

The upper drain select line DSLa and the lower drain select line DSLb of the upper select group USG extend to overlap the first and second lower select groups LSG1 and LSG2. The word lines WL1 to WLn are extended to overlap the first and second lower select groups LSG1 and LSG2.

Each of the first and second gate stacks GST1 and GST2 may further include a gate insulating film GI disposed between the first and second lower select groups LSG1 and LSG2 and the source region SA . Each of the first and second gate stacks GST1 and GST2 includes an upper drain select line DSLa, a lower drain select line DSLb, word lines WL1 to WLn, upper source select lines SSL1b and SSL2b And interlayer insulating films ILD disposed between the lower source select lines SSL1a and SSL1b.

Each of the gate insulating film GI and the interlayer insulating films ILD may extend in the horizontal direction. The gate insulating film GI and the interlayer insulating films ILD may be formed of an oxide film.

Each of the first and second gate stacks GST1 and GST2 may further include an isolation insulating film SID disposed between the first lower select group LSG1 and the second lower select group LSG2. The first lower select group LSG1 and the second lower select group LSG2 can be separated from each other by the isolation insulating film SID. The isolation insulating film SID may penetrate the interlayer insulating film ILD between the upper source select lines SSL1b and SSL2b and the lower source select lines SSL1a and SSL1b. The isolation insulating film SID is covered with the word lines WL1 to WLn and the upper select group USG.

The isolation insulating film SID does not penetrate the word lines WL1 to WLn and the upper select group USG between the adjacent slits SI but the first lower select between the adjacent slits SI Group LSG1 and the second lower select group LSG2. Thus, the widths of the first lower select group LSG1 and the second lower select group LSG2 are each narrower than the widths of the word lines WL1 to WLn and the upper select group USG, respectively.

As described above, the first and second channel films CH1 and CH2 have an inverted trapezoidal shape due to the nature of the manufacturing process. As a result, the distance between the first and second channel films CH1 and CH2 adjacent to each other becomes narrower toward the upper side. Conversely, as the distance between the first and second channel films CH1 and CH2 increases toward the bottom, the distance between the first and second channel films CH1 and CH2 increases.

According to the embodiment of the present invention, the spacing space between the upper ends of the relatively narrow first and second channel films (CH1, CH2) is not separated into two spaces by the separating insulating film (SID) (USG). That is, the upper select group USG is formed so as to extend so as to commonly surround the first and second channel films CH1 and CH2 without separating between the slits SI. Therefore, in order to secure a space for separating the upper select group (USG) into two groups among the slits SI, the present invention is characterized in that the separation distance between the first and second channel films (CH1, CH2) You do not have to expand. As a result, the present invention can increase the degree of integration of the semiconductor device.

The bottom spacing space between the lower ends of the first and second channel films CH1 and CH2 is relatively wide and thus has an area capable of disposing the isolation insulating film SID. According to the embodiment of the present invention, the isolation insulating film (SID) is disposed in the lower spacing space having the arrangement area of the isolation insulating film (SID) without expanding the horizontal space. Thus, the present invention can increase the degree of integration of the semiconductor device. The isolation insulating film SID electrically isolates the first lower select group LSG1 surrounding the first channel films CH1 and the second lower select group LSG2 surrounding the second channel films CH2. Thus, the present invention selects a memory string of any one of the memory strings defined by the first or second gate stacked structure (GST1, GST2) and the first and second channel films (CH1, CH2) Can be performed.

The first channel films CH1 and the second channel films CH2 can be structurally contacted to the source region SA in common. According to the embodiment of the present invention, the signals applied to the first lower select group LSG1 and the second lower select group LSG2 that are electrically separated are controlled so that the first and second channel films CH1, CH2) may be electrically connected to the source region SA in a divided group. Thus, the present invention can improve the reliability of the semiconductor device by improving the disturbance.

The word lines WL1 to WLn and the upper select group USG surround the same first and second channel films CH1 and CH2 so that the first and second word lines WL1 to WLn, The total number of channel films CH1 and CH2 is equal to the total number of the first and second channel films CH1 and CH2 wrapped by the upper select group USG. The total number of the first channel films CH1 wrapped by the first lower select group LSG1 may be the same as the total number of the second channel films CH2 wrapped by the second lower select group LSG2. Accordingly, the total number of the first and second channel films CH1 and CH2 surrounded by the word lines WL1 to WLn is greater than the total number of the first channel films CH1 to which the first lower select group LSG1 wraps The second lower select group LSG2 may be twice the total number of the first lower select group LSG2 or twice the total number of the second channel films CH2 wrapped by the second lower select group LSG2.

Each of the first and second bit lines BL1 and BL2 is commonly connected to at least one of the first channel films CH1 and the second channel films CH2.

The gate group including the word lines WL1 to WLn, the drain select lines DSLa and DSLb and the source select lines SSL1a, SSL2a, SSL1b and SSL2b is a gate group including at least either a doped silicon, a silicide, Can be formed. For low resistance wiring, the gate group may include a low resistance metal such as tungsten. Although not shown in the figure, the interface between the word lines WL1 to WLn, the drain select lines DSLa and DSLb, and the source select lines SSL1a, SSL2a, SSL1b, and SSL2b and the multi- A barrier film may be further formed to prevent direct contact of the barrier ribs. The barrier film may include a titanium nitride film, a tungsten nitride film, a tantalum nitride film, and the like.

The spacer insulating films SPD are disposed between the first and second gate stacks GST1 and GST2 and the source contact lines SCL so that the first and second gate stacks GST1 and GST2 are connected to the source contact Can be electrically isolated from the lines SCL. The slits SI, the spacer insulating films SPD and the source contact lines SCL may extend along the third direction III.

The source contact lines SCL are formed of a conductive material so as to transmit a common source voltage applied from a peripheral circuit not shown in the figure to the source region SA.

The first and second gate stacks GST1 and GST2 may be covered with an upper insulating film UD. The slits SI, the spacer insulating films SPD, and the source contact lines SCL may further penetrate the upper insulating film UD.

The first and second channel films CH1 and CH2 may be electrically connected to the first and second bit lines BL1 and BL2 via the first and second contact plugs CT1 and CT2. The first and second contact plugs CT1 are connected to the first contact plugs CT1 connected to the first bit lines BL1 and the second contact plugs CT2 connected to the second bit lines BL2 Can be distinguished. The first and second contact plugs CT1 and CT2 may be in contact with the capping pattern CAP through the upper insulating film UD. The capping pattern CAP can reduce the contact resistance between the first and second contact plugs CT1 and CT2 and the first and second channel films CH1 and CH2.

3A to 3C are cross-sectional views illustrating various structures of a multi-layer memory pattern. FIG. 3A is an enlarged cross-sectional view of the region A shown in FIG. 2, and FIGS. 3B and 3C are modifications of the embodiment shown in FIG. 3A.

3A to 3C, the multilayer memory pattern ML includes a tunnel insulating film TI surrounding the channel film CH1, a data storage film DL surrounding the tunnel insulating film TI, and a data storage film DL. (BI or BI1). The data storage layer DL may store data that is changed using Fowler node height tunneling caused by a voltage difference between the word lines (WL1 to WLn in FIG. 2) and the channel layer CH1. For this, the data storage layer (DL) may be formed of various materials, for example, a nitride film capable of charge trapping. In addition, the data storage layer (DL) may include silicon, phase change materials, nanodots, and the like. The blocking insulating film BI or BI1 may include an oxide film capable of charge blocking. The tunnel insulating film TI may be formed of a silicon oxide film capable of charge tunneling.

Referring to FIGS. 3A and 3B, the multi-layer memory pattern ML may extend along the surface of the hole H through the gate stack GST1.

Referring to FIG. 3B, the semiconductor device may further include a second blocking insulating film BI2. The second blocking insulating film BI2 may be formed of a material different from the first blocking insulating film BI1 included in the multi-layer memory pattern ML. The second blocking insulating film BI2 may be formed of an insulating material having a dielectric constant larger than that of the first blocking insulating film BI1. For example, the first blocking insulating film BI1 may be formed of a silicon oxide film, and the second blocking insulating film BI2 may be formed of a metal oxide film. Al ₂ O ₃ may be used as the metal oxide for the second blocking insulating film BI ₂ . The second blocking insulating film BI2 is formed on the interfacial surfaces between the interlayer insulating films ILD and the conductive pattern (for example, DSLa) of the gate group GL and the conductive pattern of the gate group GL (for example, DSLa ) And the multi-layer memory pattern ML.

Referring to FIG. 3C, the multilayer memory pattern ML has a structure in which the interface between the channel film CH1 and the conductive pattern (for example, DSLa) of the gate group GL, the interlayer insulating films ILD and the gate group GL, Of the conductive pattern (e. G., DSLa). ≪ / RTI >

4 is a flowchart for schematically explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 5A to 11 are views for explaining a step-by-step description of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, the semiconductor device may be formed by sequentially performing ST1 to ST11. Steps ST1 to ST11 may be performed on a substrate including a driving circuit for driving a semiconductor device. Hereinafter, with reference to FIGS. 5A to 11, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in more detail.

Referring to FIG. 4, after the source region and the gate insulating layer are sequentially formed on the substrate on which the driver circuit is formed, the ST1 step of separating the first stacked body into the first patterns may be performed. 5A and 5B are cross-sectional views for explaining the ST1 step shown in FIG.

Referring to FIG. 5A, the source region 101 may be a doped silicon film containing a first conductive impurity. The impurity of the first conductivity type may be an n-type impurity. The source region 101 may be formed on a well structure (not shown) including an impurity of a second conductivity type different from that of the first conductivity type. Although not shown in the drawings, a well structure may be formed on a substrate (not shown). Between the substrate and the well structure, transistors constituting the driving circuit and an insulating film covering the driving circuit, contact plugs connected to the driving circuit, and routing wiring may be disposed. The impurity of the second conductivity type may be a p-type impurity.

The gate insulating film 103 is disposed on the source region 101 and may be formed of a silicon oxide film.

The first stacked body PST1 is formed on the gate insulating film 103. [ The first layered product PST1 may include at least one layer of a first material film 111 and at least one layer of a second material film 113. [ The first material film 111 and the second material film 113 are alternately stacked. When the first and second lower select groups are to be formed in a structure including the upper source select line and the lower source select line as illustrated in FIG. 2, the first stack body PST1 is formed of the first And a second material film 113 disposed between the material films 111 and the first material films 111. The structure of the first layered product PST1 of the present invention is not limited thereto and may include a plurality of first material layers 111 and a plurality of second material layers 113 alternately stacked one upon the other .

The first material film 111 is formed of a material different from that of the second material film 113. In the first case, the first material film 111 may be formed of an insulating material for sacrifice, and the second material film 113 may be formed of an insulating material for an interlayer insulating film. More specifically, the first material films 111 may be formed of a silicon nitride film, and the second material films 113 may be formed of a silicon oxide film. In the second case, the first material film 111 may be formed of a conductive material for a gate group, and the second material film 113 may be an insulating material for an interlayer insulating film. More specifically, the first material film 111 may include at least one of a doped silicon film, a metal silicide film, and a metal film, and the second material film 113 may be formed of a silicon oxide film. In the third case, the first material film 111 may be formed of a conductive material for a gate group, and the second material film 113 may be formed of a sacrificial conductive material. More specifically, the first material film 111 may be formed of a doped silicon film, and the second material film 113 may be formed of an undoped silicon film.

Step ST1 is a step of forming the first stacked body PST1 in the first patterns P1 by forming the mask pattern 115 on the first stacked body PST1 and the etching process using the mask pattern 115 as an etching barrier, As shown in FIG.

The mask pattern 115 may be formed using a photolithography process. The first slits 117 are formed by etching the first stacked body PST1 through the etching process using the mask pattern 115 as an etching barrier. The first slits 117 penetrate the first stacked body PST1 and separate the first stacked body PST1 into the first patterns P1.

Referring to FIG. 5B, step ST1 includes forming isolation insulating films 119 filling the first slits 117. FIG. The step of forming the isolation insulating films 119 may include forming an insulating film so that the first slits 117 are completely filled, and planarizing the insulating film to define the isolation insulating films 119. The mask pattern 115 may be removed during the planarization process for forming the isolation insulating films 119, or may be removed through a separate removal process. Thereby, the first patterns P1 can be exposed.

Referring to FIG. 4, after step ST1, step ST3 of forming a second laminate may be performed. 6 is a cross-sectional view for explaining the step ST3 shown in FIG.

Referring to FIG. 6, a second stacked body PST2 is formed on the first patterns P1 and the isolation insulating films 119. As shown in FIG. The second stacked body PST2 extends to cover the first patterns P1 and the isolation insulating films 119. And third material films 121 and fourth material films 123 stacked alternately one by one. The fourth material film 123 is formed of a material different from that of the third material film 121. The third material film 121 may be formed of the same material as the second material film 113 and the fourth material film 123 may be formed of the same material as the first material film 111.

Referring to FIG. 4, after step ST3, step ST5 of forming a cell plug may be performed. Hereinafter, the step ST5 and the cell plug formed thereby will be described in more detail with reference to FIGS. 7, 8A and 8B.

7 is a plan view for explaining the arrangement of the cell plugs formed through step ST5 shown in FIG.

Referring to FIG. 7, the cell plugs PL may be formed through ST5. Each of the cell plugs PL may include a multi-layered memory pattern 133, a channel layer 135, and a capping pattern 139. The multilayer memory pattern 133 may include a blocking insulating film, a data storage film, and a tunnel insulating film as described above with reference to FIG. 3A. The multi-layer memory pattern 133 may be formed to surround the sidewalls of the channel film 135. The capping pattern 139 may be disposed in the central region defined by the channel film 135. [

The cell plugs PL may be divided into a first large group LGR1 and a second large group LGR2 arranged alternately along the second direction II. The cell plugs PL of the first large group LGR1 and the second large group LGR2 are connected to the first group GR1 and the second group GR2 arranged on both sides of the isolation insulating film 119, GR2).

The first group GR1 of the first large group LGR1 and the first group GR1 of the second large group LGR2 may each include a first cell plug PL1 and a second cell plug PL2 have. The second group GR2 of the second major group LGR2 and the second group GR2 of the second major group LGR2 may each include third cell plugs PL3 and fourth cell plugs PL4 have.

The first cell plugs PL1 may be arranged in a line in the third direction III. And the second cell plugs PL2 may be arranged in a line in the third direction III. The first cell plugs PL1 and the second cell plugs PL2 may be arranged in a staggered manner. And the third cell plugs PL3 may be arranged in a line in the third direction III. And the fourth cell plugs PL4 may be arranged in a line in the third direction III. The third cell plugs PL3 and the fourth cell plugs PL4 may be arranged in a zigzag manner. The second cell plugs PL2 and third cell plugs PL3 are disposed adjacent to the isolation insulating film 119 and are disposed between the first cell plugs PL1 and the fourth cell plugs PL4 .

8A and 8B are process cross-sectional views taken along the line "X-X '" shown in Fig.

Referring to FIG. 8A, the step ST5 may include forming holes 131 through the second stacked body PST2, the first patterns P1, and the gate insulating film 103. Referring to FIG. Holes 131 are formed to expose the source region 101.

The holes 131 define the space in which the cell plugs PL shown in FIG. 7 are to be arranged. Hereinafter, for convenience of explanation, a portion close to the source region 101 in each of the holes 131 is defined as a lower portion, and a portion farther from the source region 101 is defined as an upper portion with respect to the lower portion. Due to the characteristics of the etching process for forming the holes 131, the width W1 of the lower portion in each of the holes 131 is formed narrower than the width W2 of the upper portion. Thus, each of the holes 131 can have an inverted trapezoidal longitudinal sectional structure, and the interval W3 between the lower portions of the holes 131 is larger than the interval W4 between the upper portions. That is, the width W3 of the first pattern P1 remaining between adjacent holes 131 is smaller than the width W4 of the second stacked body PST2 remaining between adjacent holes 131 wide.

The isolation insulating film 119 according to the embodiment of the present invention may be disposed between the lower portions of the holes 131 spaced apart from each other at a relatively large interval as compared with the upper portions of the holes 131. [ Thus, even if the interval between the holes 131 is minimized, a sufficient space for arranging the isolation insulating film 119 can be ensured.

8B, step ST5 includes forming a multi-layer memory film on the surface of each of the holes 131 and etching the multi-layer memory film with an etching process such as an etch-back to form a multi-layer memory pattern 133). ≪ / RTI > The multilayer memory film may be formed by sequentially laminating a blocking insulating film, a data storage film, and a tunnel insulating film.

Step ST5 may include forming a channel film 135 on the multi-layer memory pattern 133. [ A channel film 135 is formed in each of the holes 131. The channel film 135 may be formed so as to completely fill the inside of each of the holes 131 or to open the central region of each of the holes 131.

If the central region of each of the holes 131 is opened by the channel film 135, step ST5 may further include filling the central region of each of the holes 131 with the core insulating film 137.

Step ST5 may further include the step of forming a capping pattern 139 on the core insulating film 137. To this end, the upper end of each of the holes 131 can be opened by recessing the upper end of the core insulating film 137. Thus, the height of the core insulating film 137 may be lower than the height of each of the holes 131 and the channel film 135. Thereafter, a capping pattern 139 filling the upper end of each of the holes 131 may be formed on the core insulating film 137 whose height is lowered. The capping pattern 139 may be formed of a doped silicon film containing an impurity of the first conductivity type.

The cell plugs PL can be formed through the above-described processes. The cell plugs PL may be divided into a first large group LGR1 and a second large group LGR2 as described above with reference to FIG. The channel films 135 of the cell plugs PL can be in direct contact with the source region 101. [ Each of the channel films 135 of the cell plugs PL may include a lower portion penetrating the first patterns P1 and an upper portion penetrating the second stacked body PST2. According to the embodiment of the present invention, the lower portion of each of the channel films 135 may be formed narrower than the upper portion. That is, the interval between the lower portions of the channel films 135 may be larger than the interval between the upper portions of the channel films 135.

Referring to FIG. 4, after step ST5, step ST7 of forming a gate stacked body using the first pattern and the second stacked body may be performed. Then, ST9 may be performed to form a source contact line that is insulated from the gate stack and connected to the source region.

FIGS. 9A to 9C are cross-sectional views illustrating steps ST7 and ST9 shown in FIG. Figs. 9A to 9C are cross-sectional views taken along the line "X-X" "

9A, step ST7 is a step of forming slits 143 passing through the third and fourth material films 121 and 123, the first and second material films 111 and 113 and the gate insulating film 103, . Each of the slits 143 is disposed between the first large group LGR1 and the second large group LGR2. The slit 143 extends along the third direction. The isolation insulating films 119 are disposed between adjacent slits 143.

Although not shown in the drawing, at least one side of the first to fourth material films 111, 113, 121, and 123 may be patterned stepwise before the slits 143 are formed. The first to fourth material films 111, 113, 121 and 123 patterned in a stepwise pattern can be covered with a first upper insulating film 141. The first upper insulating film 141 is penetrated by a slit 143 do.

The second stack including the third and fourth material films 121 and 123 may be separated into the second patterns P2 by the slits 143. [ The first pattern between the neighboring separation insulating films 119 can be separated into the third patterns P3 by the slits 143. [ Each of the third patterns P3 is defined by the first and second material films 111 and 113 remaining between the isolation insulating film 119 and the slit 143. [

The slits 143 can penetrate the gate insulating film 103 and expose the source region 101. [ The side walls of each of the first to fourth material films 111, 113, 121, and 123 are exposed by the slits 143.

In the first case where the first and fourth material films 111 and 123 are formed of an insulating material for sacrificing and the second and third material films 113 and 121 are formed of an interlayer insulating film, And may further include a process described below.

In the second case where the first and fourth material films 111 and 123 are formed of a conductive material for a gate group and the second and third material films 113 and 121 are formed of an interlayer insulating film, The process described later is omitted, and step ST9 described later in FIG. 9C can be carried out.

Although not shown in the drawing, the first and fourth material films 111 and 123 are formed of a conductive material for a gate group, and the second and third material films 113 and 121 are formed of a sacrificial conductive material In the third case, after the step of replacing the second and third material films 113 and 121 with the interlayer insulating films, ST9 step described later in FIG. 9C may be performed.

Referring to FIG. 9B, in the above-described first case, step ST7 may include a replacing step of replacing the first and fourth material films 111 and 123 with the conductive patterns 151 for the gate group have. The replacement step may include selectively removing the first and fourth material films 111 and 123 through the slits 143 to open the horizontal spaces. The horizontal spaces are defined between the insulating films including the second and third material films 113 and 121 and the gate insulating film 103. Subsequently, the replacement step may include forming a conductive film to fill the horizontal spaces, and removing a part of the conductive film formed inside the slits 143 to separate the conductive film into the conductive patterns 151. A second blocking insulating film may be further formed along the surface of each of the horizontal spaces before forming the conductive film.

The first gate stacked structure GST1 and the second gate stacked structure GST2 separated by the slit 143 can be defined by performing various processes as described above. The first gate stack GST1 surrounds the cell plugs of the first large group LGR1 and the second gate stack GST2 surrounds the cell plugs of the second large group LGR2.

Referring to FIG. 9C, step ST9 performed after step ST7 includes steps of forming spacer insulating films 161 on the sidewalls of each slit 143 and filling the inside of the slit 143 between the spacer insulating films 161 And forming the source contact line 163.

The step of forming the spacer insulating films 161 on the sidewalls of the slit 143 includes depositing an insulating film along the surface of the slit 143 and exposing the source region 101 through the bottom surface of the slit 143 And then etching the insulating film so as to make it.

The source contact line 163 may include at least one of a doped silicon film, a metal silicide film, and a metal film. The source contact line 163 may be in direct contact with the source region 101. The source contact line 163 extends along the third direction.

Referring to FIG. 4, after step ST9, step ST11 of forming a bit line connected to the cell plugs may be performed. Hereinafter, the bit lines formed in step ST9 and the bit lines formed in the step ST9 will be described in more detail with reference to FIGS. 10 and 11. FIG.

10 is a plan view for explaining the arrangement of bit lines formed through step ST11 shown in FIG.

10, the slits 143 and the isolation insulating films 119 extend along the third direction III and alternately can be disposed along the second direction II. The first and second bit lines BL1 and BL2 may be formed on the first gate stacked structure GST1 and the second gate stacked structure GST2 separated by the slits 143 through step ST11 .

The first and second bit lines BL1 and BL2 may be alternately arranged along the third direction III. Each of the first and second bit lines BL1 and BL2 may extend along the second direction II.

The first and second bit lines BL1 and BL2 may be connected to the channel films of the cell plugs via the first and second contact plugs CT1 and CT2. The first contact plugs CT1 are connected under the first bit lines BL1 and the second contact plugs CT2 are connected under the second bit lines BL2.

The first and second contact plugs CT1 and CT2 are connected to the first large group connected to the channel films passing through the first gate stacked structure GST1 and the first large group connected to the channel films passing through the second gate stacked structure GST2 And can be divided into a second large group connected.

11 is a process sectional view taken along the line "X-X '" shown in Fig.

11, the step ST11 includes forming a second upper insulating film 171 covering the first upper insulating film 141 penetrated by the source contact line 163, forming first and second upper insulating films 141 And 171 to form the first and second contact plugs CT1 and CT2 connected to the capping pattern 139 and the channel films 135 and forming the first and second contact plugs CT1 and CT2, And forming first and second bit lines BL1 and BL2 on the second upper insulating film 141 connected to the first and second bit lines CT1 and CT2. The first and second contact plugs CT1 and CT2 and the first and second bit lines BL1 and BL2 are patterns for electrical signal transmission and are formed of a conductive material.

The first and second contact plugs CT1 and CT2 are connected to the first large group LGR1 and the second gate stack GST2 associated with the operation of the cell plugs PL connected to the first gate stack GST1 And a second large group LGR2 associated with the operation of the connected cell plugs PL.

Each of the first large group LGR1 and the second large group LGR2 includes first and second contact plugs of a first group GR1 associated with the operation of the cell plugs PL connected to the first lower select group LSG1. And first and second contact plugs of a second group GR2 associated with operation of the cell plugs PL coupled to the second lower select group LSG2.

12A to 12C are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 12A, the protective film 203 and the source sacrificial film 205 may be formed on the source region 201 before the ST1 step shown in FIG. 4 is performed. The source region 201 may be formed of a doped silicon film containing a first conductive impurity. The protective film 203 may be formed of an oxide film. The source sacrificial film 205 may be formed of an undoped silicon film.

Then, ST1 to ST7 described above in Fig. 4 can be performed. Steps ST1 to ST7 may be performed using the processes described above with reference to FIGS. 5A to 9B.

The first gate stacked structure GST1 and the second gate stacked structure GST2, which surround the cell plugs PL and are separated from each other by the slits 243, (Not shown). The first gate stacked structure GST1 and the second gate stacked structure GST2 may be covered with the first upper insulating film 241 penetrated by the slit 243. [

Cell plugs PL are formed within holes 231 extending into the source region 201 through the first gate stack GST1 and the second gate stack GST2. Each of the cell plugs PL1 may include a multilayer memory film 233, a channel film 235, a core insulating film 237, and a capping pattern 239. [ The multilayer memory film 233 may include a sequentially stacked blocking insulating film, a data storage film, and a tunnel insulating film. A multilayer memory film 233 is formed along the surface of each of the holes 231 and extends to cover the exposed source region 201 through the bottoms of the holes 231. A channel film 235 is formed on the surface of the multi-layer memory film 233. The core insulating film 237 fills the central region of each of the holes 231 opened by the channel film 235 and the capping pattern 239 fills the central region of each of the holes 231 opened on the core insulating film 237 .

Next, the spacer insulating films 261 may be formed on the sidewalls of the slit 243.

Referring to FIG. 12B, before the step ST9 shown in FIG. 4 is performed, the sacrificial source film exposed through the slit 243 is removed, and a part of the exposed multi-layer memory film is removed by sacrificial source film removal, 235 may be further exposed. This allows the multilayer memory film to be separated into the first and second multilayer memory patterns 233A and 233B and the horizontal space HSP exposing the sidewalls of the channel film 235 is formed in the first and second gate stacked layers 233A and 233B. Gt; GST1 and < / RTI > GST2 and the source region 201, as shown in FIG. In the process of opening the horizontal space HSP, the protective film may be removed and the source region 201 may be exposed.

Referring to FIG. 12C, a contact source film 262, which is in direct contact with the side wall of the channel film 235 exposed through the horizontal space (HSP) and the source region 201 before the step ST9 shown in FIG. Can be formed inside the horizontal space (HSP). The contact source film 262 may be formed of a silicon film. The contact source film 262 may include an impurity of the first conductivity type diffused from the source region 201. Specifically, the contact source film 262 may be a doped silicon film containing the first conductive impurity.

The contact source film 262 may be formed using a selective growth method (e.g., SEG: Selective Epitaxial Growth) or a non-selective deposition method (e.g., CVD: chemical vapor deposition).

After the contact source film 262 is formed, a source contact line 263 filling the inside of the slit is formed. The source contact line 263 may be in contact with the contact source film 262.

Thereafter, the second upper insulating film 271, the first and second contact plugs CT1 and CT2 and the first and second bit lines BL1 and BL2 ) Can be formed.

13A to 13D are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 13A, a source region 301, a first gate insulating film 303, and a first stacked body PST1 can be formed using the same processes and material films as described above in FIG. 5A. Subsequently, the lower plugs LPC can be formed. The lower plugs (LPC) pass through the first stack (PST1) and contact the source region (301). The side walls of each of the lower plugs LPC are surrounded by a second gate insulating film GI. Each of the lower plugs (LPC) can be used as a channel film of a source select transistor.

The step of forming the lower plugs LPC includes the step of forming the lower holes LH through the first material film 311 and the second material film 313 of the first stacked body PST1 and exposing the source region 301, Forming a second gate insulating film GI on the sidewalls of each of the lower holes LH and filling the inside of the lower holes LH with the first semiconductor film. The first semiconductor film may be formed of a silicon film. The first semiconductor film may include at least one of an undoped silicon film and a doped silicon film. An n-type dopant may be distributed in the doped silicon film. The second gate insulating film GI may be formed of an insulating material such as a silicon oxide film.

5A, the slits 317 are formed and the first stacked body PST1 is separated into the first patterns P1 through the slits 317. Then, as shown in FIG. Thereafter, a separation insulating film 319 is formed in the slit 317 using the same process as described above with reference to FIG. 5B.

The lower holes LH, the second gate insulating film GI and the lower plugs LPC may be formed before the step of forming the slits 317 or may be formed after the step of forming the isolation insulating film 319. The lower holes LH adjacent to each other with the isolation insulating film 319 therebetween may be spaced apart from each other by a first distance D1 in consideration of a space in which the isolation insulating film 319 is to be disposed. The lower plugs (LPC) are disposed inside the lower holes (LH) before forming the second laminate. Since the lower holes LH are formed by etching only the first stacked body PST1 formed at a low height, the width of each of the lower holes LH is not excessively widened during the etching process. Therefore, a space in which the isolation insulating film 319 is disposed between the lower holes LH can be sufficiently secured.

Referring to FIG. 13B, a second stacked body PST2 is formed on the first patterns P1, the lower plugs LPC, and the isolation insulating film 319. Referring to FIG. The second laminate (PST2) may be formed of the same process and the same material films as described above in Fig.

Then, upper holes 331 penetrating the second stacked body PST2 are formed. The upper holes 331 expose the lower plugs LPC. The upper holes 331 define the space in which the cell plugs PL to be formed subsequently are to be disposed. The inner diameter of each of the upper holes 331 may become narrower toward the lower plugs LPC due to the characteristics of the manufacturing process as described above with reference to FIG. 8A. Accordingly, the upper holes 331 may have a vertical cross-sectional structure of an inverted trapezoidal shape. In addition, the second spacing D2 between the upper holes 131 aligned on the isolation insulating films 319 may be narrower than the first spacing D1. According to the embodiment of the present invention, since the isolation insulating films 319 do not have to be disposed within the second gap D2, the fabrication process of the semiconductor device can be made less difficult.

The arrangement of the lower plugs LPC and the arrangement of the upper holes 331 may be the same as the arrangement of the cell plugs PL shown in FIG.

Referring to FIG. 13C, cell plugs PL are formed in the upper holes 331. Each of the cell plugs PL may include a multilayer memory pattern 333, a second semiconductor film 335 used as a channel film, and a capping pattern 339. [

The multi-layer memory pattern 333 may include a blocking insulating layer, a data storage layer, and a tunnel insulating layer, as described above with reference to FIG. 3A. The multilayer memory pattern 333 surrounds the sidewalls of the second semiconductor film 335.

The second semiconductor film 335 surrounds the core insulating film 337 disposed in the central region of the upper holes 331 and penetrates the multilayer memory pattern 333. The second semiconductor film 335 is formed along the surface of the corresponding upper hole 331 and is connected to the corresponding lower plug LPC.

The cell plugs PL may be formed using the same material films and the same process as described above in Fig. 8B. The cell plugs PL and the lower plugs LPC can be divided into a first large group LGR1 and a second large group LGR2 as described above with reference to FIG. The lower plugs LP of each of the first large group LGR1 and the second large group LGR1 may be divided into a first group LG1 and a second group LG2. Each of the isolation insulating films 319 extends along the boundary between the first group LR1 and the second group LG2.

Referring to FIG. 13D, gate stacks GST1 and GST2 separated by a slit 343 are formed using the same process as described above in FIGS. 9A and 9B.

Each of the gate stacks GST1 and GST2 includes the drain select lines DSLa and DSLb, the word lines WL1 to WLn, the first source select lines SSL1a and SSL1b, And second source select lines SSL2a and SSL2b.

The slit 343 is disposed between the first large group LGR1 and the second large group LGR2 and exposes the source region 301. [

9C, a spacer insulating film 361 is formed on the sidewall of the slit 343 and the source contact 301 connected to the source region 301 on the spacer insulating film 361 inside the slit 143. [ Line 163 is formed.

According to the above-described process, the lower plug LPC passing through the first source select lines SSL1a and SSL1b and the word lines WL1 to WLn and the drain select lines DSLa and DSLb connected therewith The second semiconductor film 335 may form the first channel film CH1. Further, a lower plug LPC which penetrates through the second source select lines SSL2a and SSL2b and a second semiconductor which is connected thereto and penetrates the word lines WL1 to WLn and the drain select lines DSLa and DSLb, The film 335 may constitute the second channel film CH2.

After forming the source contact line 163, the processes described above in FIGS. 10 and 11 may be performed.

14 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention.

Referring to FIG. 14, a memory system 1100 according to an embodiment of the present invention includes a memory element 1120 and a memory controller 1110.

The memory element 1120 constitutes the circuit described above in Fig. 1, and may include the structure described above in Fig. Or the memory element 1120 may include the structure shown in Figure 12C. Or memory element 1120 may include the structure shown in Figure 13D. More specifically, the memory device 1120 may include first and second groups of memory strings shared by the upper select group and the word lines. The memory strings of the first group and the memory strings of the second group are controlled by the first lower select group and the second lower select group which are separated from each other. The first lower select group and the second lower select group are formed so as to surround the lower ends of the channel films having a relatively narrow width as compared with the upper ends of the channel films surrounded by the upper select group. The memory element 1120 may be a multi-chip package composed of a plurality of flash memory chips.

The memory controller 1110 is configured to control the memory device 1120 and includes a static random access memory (SRAM) 1111, a CPU 1112, a host interface 1113, an ECC (Error Correction Code) 1114, Interface 1115. < / RTI > The SRAM 1111 is used as an operation memory of the CPU 1112 and the CPU 1112 performs all control operations for data exchange of the memory controller 1110 and the host interface 1113 is connected to the memory system 1100 And a host computer. The ECC 1114 also detects and corrects errors contained in the data read from the memory element 1120 and the memory interface 1115 performs interfacing with the memory element 1120. In addition, the memory controller 1110 may further include a ROM (Read Only Memory) for storing code data for interfacing with the host.

The memory system 1100 may be a memory card or a solid state disk (SSD) combined with the memory element 1120 and the controller 1110. [ For example, if the memory system 1100 is an SSD, the memory controller 1110 may be a Universal Serial Bus (USB), a MultiMedia Card (MMC), a Peripheral Component Interconnection-Express (PCI-E), a Serial Advanced Technology Attachment ), PATA (Parallel Advanced Technology Attachment), SCSI (Small Computer Small Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics) Lt; / RTI >

14 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention.

14, a computing system 1200 according to an embodiment of the present invention includes a CPU 1220 electrically connected to a system bus 1260, a RAM (Random Access Memory) 1230, a user interface 1240, a modem 1250, and a memory system 1210. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile deem, .

The memory system 1210 may be composed of a memory element 1212 and a memory controller 1211, as described with reference to Fig.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the technical scope of the present invention.

SA, 101, 201, 301: source regions BL1, BL2: bit lines
CH1, CH2, 135, 235, LPC, 335: channel film
WL1 to WLn: word line SSL1a, SSL1b: first source select line
SSL2a, SSL2b: second source select line SID, 119, 319:
DSLa, DSLb: drain select line SCL, 163, 263, 363: source contact line
LSG1: first lower select group LSG2: second lower select group
USG: upper select group PST1: first laminate
PST2: second laminate P1: first pattern
P2: second pattern P3: third pattern
SI, 161, 261, 361: Slit
151: conductive patterns GST1 and GST2: gate stacked structure

Claims (22)

First channel films and second channel films connected between the source region and the bit lines;
Word lines extending between the source region and the bit lines and spaced apart from each other and extending to surround the first and second channel films, respectively;
A first source select line surrounding the first channel layers between the word lines and the source region;
A second source select line surrounding the second channel films between the word lines and the source region and spaced apart from the first source select line; And
And a drain select line disposed between the bit lines and the word lines and extending to overlap the first and second source select lines. The method according to claim 1,
Wherein the first source select line and the second source select line are disposed in the same layer. The method according to claim 1,
Wherein a total number of the first and second channel films enclosed by the word lines,
The channel select lines being equal to the total number of the first and second channel films enclosed by the drain select line,
Wherein the second source select line is twice the total number of the first channel films enclosed by the first source select line or twice the total number of the second channel films enclosed by the second source select line. The method according to claim 1,
And the spacing distance between the adjacent first and second channel films increases toward the source region. The method according to claim 1,
And a separation insulating film for separating the first source select line from the second source select line and covering the word line. The method according to claim 1,
Wherein at least one of the first channel films and the second channel films are commonly connected to any one of the bit lines. The method according to claim 1,
Each of the first source select line and the second source select line
And the drain select line has a width narrower than that of each of the word lines and the drain select line. The method according to claim 1,
Further comprising source contact lines coupled to the source region,
Wherein the word lines, the drain select line, and the first and second source select lines are disposed between adjacent source contact lines. The method according to claim 1,
Each of the first channel films and the second channel films
A first semiconductor film filling a lower hole passing through the first source select line or the second source select line; And
And a second semiconductor film formed along the surface of the upper hole, the second semiconductor film being connected to the first semiconductor film, the second semiconductor film penetrating the word lines and becoming closer to the first semiconductor film. A first channel layer and a second channel layer each having an inverted trapezoidal longitudinal sectional structure extending from a lower portion to an upper portion and having a width narrower toward the lower portion;
Word lines stacked from the bottom toward the top and spaced apart from each other and extending to surround the first channel film and the second channel film, respectively;
A first lower select group surrounding a portion of the first channel film protruding from the word lines toward the lower portion; And
And a second lower select group which surrounds a part of the second channel film protruding toward the lower side than the word lines. 11. The method of claim 10,
And an upper select group extending to cover a part of the first channel film protruding upward from the word lines and a part of the second channel film. 11. The method of claim 10,
And a bit line commonly connected to the first channel film and the second channel film. 11. The method of claim 10,
And a source region connected in common to the first channel film and the second channel film. 11. The method of claim 10,
And an isolation insulating film disposed between the first lower select group and the second lower select group and covering the word lines. Forming a first laminate;
Forming separation insulating films for separating the first laminate into first patterns;
Forming a second laminate on the first patterns and the isolation insulating films; And
The second laminate is divided into second patterns and each of the first patterns passes through the first patterns from the second laminate so that each of the first patterns is separated into third patterns, And forming slits which face each other. 16. The method of claim 15,
Wherein the slits and the isolation insulating films are alternately arranged along one direction. 16. The method of claim 15,
Before forming the slits,
And forming channel films through the first patterns from the second laminate. 18. The method of claim 17,
Wherein each of the channel films includes a lower portion passing through any one of the first patterns and an upper portion passing through the second stacked body and having a wider width than the lower portion. 18. The method of claim 17,
Wherein an interval between upper portions of the channel films passing through the first patterns is larger than an interval between lower portions of the channel films passing through the second stack. 16. The method of claim 15,
Wherein each of the first laminate and the second laminate includes a laminated structure of an interlayer insulating film and a sacrificial film,
And replacing the sacrificial film of the first and second stacks with a conductive pattern through the slit. 16. The method of claim 15,
The first laminate is formed on the source region,
And forming a source contact line connected to the source region within the slit. 16. The method of claim 15,
Before the step of forming the second laminate,
Forming lower holes passing through the first laminate; And
Filling each of the lower holes with a first semiconductor film,
After the step of forming the second laminate,
Exposing the first semiconductor film through the second layered body and forming upper holes whose inner diameter becomes narrower toward the first semiconductor film; And
And forming a second semiconductor film connected to the first semiconductor film in each of the upper holes.

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